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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / drivers / net / e1000 / e1000_hw.c
blob9be44699300b8a350041d923917cae5630b724c0
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33
34 #include "e1000_hw.h"
35
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41 static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44 static int32_t e1000_check_downshift(struct e1000_hw *hw);
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86 static void e1000_release_software_flag(struct e1000_hw *hw);
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94 static void e1000_phy_init_script(struct e1000_hw *hw);
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122 static void e1000_release_eeprom(struct e1000_hw *hw);
123 static void e1000_standby_eeprom(struct e1000_hw *hw);
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132
133 /* IGP cable length table */
134 static const
135 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
144
145 static const
146 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
155
156 /******************************************************************************
157 * Set the phy type member in the hw struct.
158 *
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
161 static int32_t
162 e1000_set_phy_type(struct e1000_hw *hw)
163 {
164 DEBUGFUNC("e1000_set_phy_type");
165
166 if (hw->mac_type == e1000_undefined)
167 return -E1000_ERR_PHY_TYPE;
168
169 switch (hw->phy_id) {
170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
173 case M88E1111_I_PHY_ID:
174 hw->phy_type = e1000_phy_m88;
175 break;
176 case IGP01E1000_I_PHY_ID:
177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
181 hw->phy_type = e1000_phy_igp;
182 break;
183 }
184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
186 break;
187 case IFE_E_PHY_ID:
188 case IFE_PLUS_E_PHY_ID:
189 case IFE_C_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
191 break;
192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
195 break;
196 }
197 /* Fall Through */
198 default:
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
202 }
203
204 return E1000_SUCCESS;
205 }
206
207 /******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
209 *
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
212 static void
213 e1000_phy_init_script(struct e1000_hw *hw)
214 {
215 uint32_t ret_val;
216 uint16_t phy_saved_data;
217
218 DEBUGFUNC("e1000_phy_init_script");
219
220 if (hw->phy_init_script) {
221 msleep(20);
222
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
229
230 msleep(20);
231
232 e1000_write_phy_reg(hw,0x0000,0x0140);
233
234 msleep(5);
235
236 switch (hw->mac_type) {
237 case e1000_82541:
238 case e1000_82547:
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
256 break;
257
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
261 break;
262 default:
263 break;
264 }
265
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
267
268 msleep(20);
269
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272
273 if (hw->mac_type == e1000_82547) {
274 uint16_t fused, fine, coarse;
275
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278
279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284
285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
298 }
299 }
300 }
301 }
302
303 /******************************************************************************
304 * Set the mac type member in the hw struct.
305 *
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
308 int32_t
309 e1000_set_mac_type(struct e1000_hw *hw)
310 {
311 DEBUGFUNC("e1000_set_mac_type");
312
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
318 break;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
321 break;
322 default:
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
325 }
326 break;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
330 break;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
336 break;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
343 break;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
347 break;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
352 break;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
357 break;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
364 hw->mac_type = e1000_82546_rev_3;
365 break;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
368 case E1000_DEV_ID_82541ER_LOM:
369 hw->mac_type = e1000_82541;
370 break;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
376 break;
377 case E1000_DEV_ID_82547EI:
378 case E1000_DEV_ID_82547EI_MOBILE:
379 hw->mac_type = e1000_82547;
380 break;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
383 break;
384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
389 hw->mac_type = e1000_82571;
390 break;
391 case E1000_DEV_ID_82572EI_COPPER:
392 case E1000_DEV_ID_82572EI_FIBER:
393 case E1000_DEV_ID_82572EI_SERDES:
394 case E1000_DEV_ID_82572EI:
395 hw->mac_type = e1000_82572;
396 break;
397 case E1000_DEV_ID_82573E:
398 case E1000_DEV_ID_82573E_IAMT:
399 case E1000_DEV_ID_82573L:
400 hw->mac_type = e1000_82573;
401 break;
402 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
403 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
404 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
405 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
406 hw->mac_type = e1000_80003es2lan;
407 break;
408 case E1000_DEV_ID_ICH8_IGP_M_AMT:
409 case E1000_DEV_ID_ICH8_IGP_AMT:
410 case E1000_DEV_ID_ICH8_IGP_C:
411 case E1000_DEV_ID_ICH8_IFE:
412 case E1000_DEV_ID_ICH8_IFE_GT:
413 case E1000_DEV_ID_ICH8_IFE_G:
414 case E1000_DEV_ID_ICH8_IGP_M:
415 hw->mac_type = e1000_ich8lan;
416 break;
417 default:
418 /* Should never have loaded on this device */
419 return -E1000_ERR_MAC_TYPE;
420 }
421
422 switch (hw->mac_type) {
423 case e1000_ich8lan:
424 hw->swfwhw_semaphore_present = TRUE;
425 hw->asf_firmware_present = TRUE;
426 break;
427 case e1000_80003es2lan:
428 hw->swfw_sync_present = TRUE;
429 /* fall through */
430 case e1000_82571:
431 case e1000_82572:
432 case e1000_82573:
433 hw->eeprom_semaphore_present = TRUE;
434 /* fall through */
435 case e1000_82541:
436 case e1000_82547:
437 case e1000_82541_rev_2:
438 case e1000_82547_rev_2:
439 hw->asf_firmware_present = TRUE;
440 break;
441 default:
442 break;
443 }
444
445 /* The 82543 chip does not count tx_carrier_errors properly in
446 * FD mode
447 */
448 if (hw->mac_type == e1000_82543)
449 hw->bad_tx_carr_stats_fd = TRUE;
450
451 /* capable of receiving management packets to the host */
452 if (hw->mac_type >= e1000_82571)
453 hw->has_manc2h = TRUE;
454
455 /* In rare occasions, ESB2 systems would end up started without
456 * the RX unit being turned on.
457 */
458 if (hw->mac_type == e1000_80003es2lan)
459 hw->rx_needs_kicking = TRUE;
460
461 if (hw->mac_type > e1000_82544)
462 hw->has_smbus = TRUE;
463
464 return E1000_SUCCESS;
465 }
466
467 /*****************************************************************************
468 * Set media type and TBI compatibility.
469 *
470 * hw - Struct containing variables accessed by shared code
471 * **************************************************************************/
472 void
473 e1000_set_media_type(struct e1000_hw *hw)
474 {
475 uint32_t status;
476
477 DEBUGFUNC("e1000_set_media_type");
478
479 if (hw->mac_type != e1000_82543) {
480 /* tbi_compatibility is only valid on 82543 */
481 hw->tbi_compatibility_en = FALSE;
482 }
483
484 switch (hw->device_id) {
485 case E1000_DEV_ID_82545GM_SERDES:
486 case E1000_DEV_ID_82546GB_SERDES:
487 case E1000_DEV_ID_82571EB_SERDES:
488 case E1000_DEV_ID_82572EI_SERDES:
489 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
490 hw->media_type = e1000_media_type_internal_serdes;
491 break;
492 default:
493 switch (hw->mac_type) {
494 case e1000_82542_rev2_0:
495 case e1000_82542_rev2_1:
496 hw->media_type = e1000_media_type_fiber;
497 break;
498 case e1000_ich8lan:
499 case e1000_82573:
500 /* The STATUS_TBIMODE bit is reserved or reused for the this
501 * device.
502 */
503 hw->media_type = e1000_media_type_copper;
504 break;
505 default:
506 status = E1000_READ_REG(hw, STATUS);
507 if (status & E1000_STATUS_TBIMODE) {
508 hw->media_type = e1000_media_type_fiber;
509 /* tbi_compatibility not valid on fiber */
510 hw->tbi_compatibility_en = FALSE;
511 } else {
512 hw->media_type = e1000_media_type_copper;
513 }
514 break;
515 }
516 }
517 }
518
519 /******************************************************************************
520 * Reset the transmit and receive units; mask and clear all interrupts.
521 *
522 * hw - Struct containing variables accessed by shared code
523 *****************************************************************************/
524 int32_t
525 e1000_reset_hw(struct e1000_hw *hw)
526 {
527 uint32_t ctrl;
528 uint32_t ctrl_ext;
529 uint32_t icr;
530 uint32_t manc;
531 uint32_t led_ctrl;
532 uint32_t timeout;
533 uint32_t extcnf_ctrl;
534 int32_t ret_val;
535
536 DEBUGFUNC("e1000_reset_hw");
537
538 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
539 if (hw->mac_type == e1000_82542_rev2_0) {
540 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
541 e1000_pci_clear_mwi(hw);
542 }
543
544 if (hw->bus_type == e1000_bus_type_pci_express) {
545 /* Prevent the PCI-E bus from sticking if there is no TLP connection
546 * on the last TLP read/write transaction when MAC is reset.
547 */
548 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
549 DEBUGOUT("PCI-E Master disable polling has failed.\n");
550 }
551 }
552
553 /* Clear interrupt mask to stop board from generating interrupts */
554 DEBUGOUT("Masking off all interrupts\n");
555 E1000_WRITE_REG(hw, IMC, 0xffffffff);
556
557 /* Disable the Transmit and Receive units. Then delay to allow
558 * any pending transactions to complete before we hit the MAC with
559 * the global reset.
560 */
561 E1000_WRITE_REG(hw, RCTL, 0);
562 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
563 E1000_WRITE_FLUSH(hw);
564
565 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
566 hw->tbi_compatibility_on = FALSE;
567
568 /* Delay to allow any outstanding PCI transactions to complete before
569 * resetting the device
570 */
571 msleep(10);
572
573 ctrl = E1000_READ_REG(hw, CTRL);
574
575 /* Must reset the PHY before resetting the MAC */
576 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
577 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
578 msleep(5);
579 }
580
581 /* Must acquire the MDIO ownership before MAC reset.
582 * Ownership defaults to firmware after a reset. */
583 if (hw->mac_type == e1000_82573) {
584 timeout = 10;
585
586 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
587 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
588
589 do {
590 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
591 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
592
593 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
594 break;
595 else
596 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
597
598 msleep(2);
599 timeout--;
600 } while (timeout);
601 }
602
603 /* Workaround for ICH8 bit corruption issue in FIFO memory */
604 if (hw->mac_type == e1000_ich8lan) {
605 /* Set Tx and Rx buffer allocation to 8k apiece. */
606 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
607 /* Set Packet Buffer Size to 16k. */
608 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
609 }
610
611 /* Issue a global reset to the MAC. This will reset the chip's
612 * transmit, receive, DMA, and link units. It will not effect
613 * the current PCI configuration. The global reset bit is self-
614 * clearing, and should clear within a microsecond.
615 */
616 DEBUGOUT("Issuing a global reset to MAC\n");
617
618 switch (hw->mac_type) {
619 case e1000_82544:
620 case e1000_82540:
621 case e1000_82545:
622 case e1000_82546:
623 case e1000_82541:
624 case e1000_82541_rev_2:
625 /* These controllers can't ack the 64-bit write when issuing the
626 * reset, so use IO-mapping as a workaround to issue the reset */
627 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
628 break;
629 case e1000_82545_rev_3:
630 case e1000_82546_rev_3:
631 /* Reset is performed on a shadow of the control register */
632 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
633 break;
634 case e1000_ich8lan:
635 if (!hw->phy_reset_disable &&
636 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
637 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
638 * at the same time to make sure the interface between
639 * MAC and the external PHY is reset.
640 */
641 ctrl |= E1000_CTRL_PHY_RST;
642 }
643
644 e1000_get_software_flag(hw);
645 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
646 msleep(5);
647 break;
648 default:
649 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
650 break;
651 }
652
653 /* After MAC reset, force reload of EEPROM to restore power-on settings to
654 * device. Later controllers reload the EEPROM automatically, so just wait
655 * for reload to complete.
656 */
657 switch (hw->mac_type) {
658 case e1000_82542_rev2_0:
659 case e1000_82542_rev2_1:
660 case e1000_82543:
661 case e1000_82544:
662 /* Wait for reset to complete */
663 udelay(10);
664 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
665 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
666 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
667 E1000_WRITE_FLUSH(hw);
668 /* Wait for EEPROM reload */
669 msleep(2);
670 break;
671 case e1000_82541:
672 case e1000_82541_rev_2:
673 case e1000_82547:
674 case e1000_82547_rev_2:
675 /* Wait for EEPROM reload */
676 msleep(20);
677 break;
678 case e1000_82573:
679 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
680 udelay(10);
681 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
682 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
683 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
684 E1000_WRITE_FLUSH(hw);
685 }
686 /* fall through */
687 default:
688 /* Auto read done will delay 5ms or poll based on mac type */
689 ret_val = e1000_get_auto_rd_done(hw);
690 if (ret_val)
691 return ret_val;
692 break;
693 }
694
695 /* Disable HW ARPs on ASF enabled adapters */
696 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
697 manc = E1000_READ_REG(hw, MANC);
698 manc &= ~(E1000_MANC_ARP_EN);
699 E1000_WRITE_REG(hw, MANC, manc);
700 }
701
702 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
703 e1000_phy_init_script(hw);
704
705 /* Configure activity LED after PHY reset */
706 led_ctrl = E1000_READ_REG(hw, LEDCTL);
707 led_ctrl &= IGP_ACTIVITY_LED_MASK;
708 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
709 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
710 }
711
712 /* Clear interrupt mask to stop board from generating interrupts */
713 DEBUGOUT("Masking off all interrupts\n");
714 E1000_WRITE_REG(hw, IMC, 0xffffffff);
715
716 /* Clear any pending interrupt events. */
717 icr = E1000_READ_REG(hw, ICR);
718
719 /* If MWI was previously enabled, reenable it. */
720 if (hw->mac_type == e1000_82542_rev2_0) {
721 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
722 e1000_pci_set_mwi(hw);
723 }
724
725 if (hw->mac_type == e1000_ich8lan) {
726 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
727 kab |= E1000_KABGTXD_BGSQLBIAS;
728 E1000_WRITE_REG(hw, KABGTXD, kab);
729 }
730
731 return E1000_SUCCESS;
732 }
733
734 /******************************************************************************
735 *
736 * Initialize a number of hardware-dependent bits
737 *
738 * hw: Struct containing variables accessed by shared code
739 *
740 * This function contains hardware limitation workarounds for PCI-E adapters
741 *
742 *****************************************************************************/
743 static void
744 e1000_initialize_hardware_bits(struct e1000_hw *hw)
745 {
746 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
747 /* Settings common to all PCI-express silicon */
748 uint32_t reg_ctrl, reg_ctrl_ext;
749 uint32_t reg_tarc0, reg_tarc1;
750 uint32_t reg_tctl;
751 uint32_t reg_txdctl, reg_txdctl1;
752
753 /* link autonegotiation/sync workarounds */
754 reg_tarc0 = E1000_READ_REG(hw, TARC0);
755 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
756
757 /* Enable not-done TX descriptor counting */
758 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
759 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
760 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
761 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
762 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
763 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
764
765 switch (hw->mac_type) {
766 case e1000_82571:
767 case e1000_82572:
768 /* Clear PHY TX compatible mode bits */
769 reg_tarc1 = E1000_READ_REG(hw, TARC1);
770 reg_tarc1 &= ~((1 << 30)|(1 << 29));
771
772 /* link autonegotiation/sync workarounds */
773 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
774
775 /* TX ring control fixes */
776 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
777
778 /* Multiple read bit is reversed polarity */
779 reg_tctl = E1000_READ_REG(hw, TCTL);
780 if (reg_tctl & E1000_TCTL_MULR)
781 reg_tarc1 &= ~(1 << 28);
782 else
783 reg_tarc1 |= (1 << 28);
784
785 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
786 break;
787 case e1000_82573:
788 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
789 reg_ctrl_ext &= ~(1 << 23);
790 reg_ctrl_ext |= (1 << 22);
791
792 /* TX byte count fix */
793 reg_ctrl = E1000_READ_REG(hw, CTRL);
794 reg_ctrl &= ~(1 << 29);
795
796 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
797 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
798 break;
799 case e1000_80003es2lan:
800 /* improve small packet performace for fiber/serdes */
801 if ((hw->media_type == e1000_media_type_fiber) ||
802 (hw->media_type == e1000_media_type_internal_serdes)) {
803 reg_tarc0 &= ~(1 << 20);
804 }
805
806 /* Multiple read bit is reversed polarity */
807 reg_tctl = E1000_READ_REG(hw, TCTL);
808 reg_tarc1 = E1000_READ_REG(hw, TARC1);
809 if (reg_tctl & E1000_TCTL_MULR)
810 reg_tarc1 &= ~(1 << 28);
811 else
812 reg_tarc1 |= (1 << 28);
813
814 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
815 break;
816 case e1000_ich8lan:
817 /* Reduce concurrent DMA requests to 3 from 4 */
818 if ((hw->revision_id < 3) ||
819 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
820 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
821 reg_tarc0 |= ((1 << 29)|(1 << 28));
822
823 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
824 reg_ctrl_ext |= (1 << 22);
825 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
826
827 /* workaround TX hang with TSO=on */
828 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
829
830 /* Multiple read bit is reversed polarity */
831 reg_tctl = E1000_READ_REG(hw, TCTL);
832 reg_tarc1 = E1000_READ_REG(hw, TARC1);
833 if (reg_tctl & E1000_TCTL_MULR)
834 reg_tarc1 &= ~(1 << 28);
835 else
836 reg_tarc1 |= (1 << 28);
837
838 /* workaround TX hang with TSO=on */
839 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
840
841 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
842 break;
843 default:
844 break;
845 }
846
847 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
848 }
849 }
850
851 /******************************************************************************
852 * Performs basic configuration of the adapter.
853 *
854 * hw - Struct containing variables accessed by shared code
855 *
856 * Assumes that the controller has previously been reset and is in a
857 * post-reset uninitialized state. Initializes the receive address registers,
858 * multicast table, and VLAN filter table. Calls routines to setup link
859 * configuration and flow control settings. Clears all on-chip counters. Leaves
860 * the transmit and receive units disabled and uninitialized.
861 *****************************************************************************/
862 int32_t
863 e1000_init_hw(struct e1000_hw *hw)
864 {
865 uint32_t ctrl;
866 uint32_t i;
867 int32_t ret_val;
868 uint16_t pcix_cmd_word;
869 uint16_t pcix_stat_hi_word;
870 uint16_t cmd_mmrbc;
871 uint16_t stat_mmrbc;
872 uint32_t mta_size;
873 uint32_t reg_data;
874 uint32_t ctrl_ext;
875
876 DEBUGFUNC("e1000_init_hw");
877
878 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
879 if ((hw->mac_type == e1000_ich8lan) &&
880 ((hw->revision_id < 3) ||
881 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
882 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
883 reg_data = E1000_READ_REG(hw, STATUS);
884 reg_data &= ~0x80000000;
885 E1000_WRITE_REG(hw, STATUS, reg_data);
886 }
887
888 /* Initialize Identification LED */
889 ret_val = e1000_id_led_init(hw);
890 if (ret_val) {
891 DEBUGOUT("Error Initializing Identification LED\n");
892 return ret_val;
893 }
894
895 /* Set the media type and TBI compatibility */
896 e1000_set_media_type(hw);
897
898 /* Must be called after e1000_set_media_type because media_type is used */
899 e1000_initialize_hardware_bits(hw);
900
901 /* Disabling VLAN filtering. */
902 DEBUGOUT("Initializing the IEEE VLAN\n");
903 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
904 if (hw->mac_type != e1000_ich8lan) {
905 if (hw->mac_type < e1000_82545_rev_3)
906 E1000_WRITE_REG(hw, VET, 0);
907 e1000_clear_vfta(hw);
908 }
909
910 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
911 if (hw->mac_type == e1000_82542_rev2_0) {
912 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
913 e1000_pci_clear_mwi(hw);
914 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
915 E1000_WRITE_FLUSH(hw);
916 msleep(5);
917 }
918
919 /* Setup the receive address. This involves initializing all of the Receive
920 * Address Registers (RARs 0 - 15).
921 */
922 e1000_init_rx_addrs(hw);
923
924 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
925 if (hw->mac_type == e1000_82542_rev2_0) {
926 E1000_WRITE_REG(hw, RCTL, 0);
927 E1000_WRITE_FLUSH(hw);
928 msleep(1);
929 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
930 e1000_pci_set_mwi(hw);
931 }
932
933 /* Zero out the Multicast HASH table */
934 DEBUGOUT("Zeroing the MTA\n");
935 mta_size = E1000_MC_TBL_SIZE;
936 if (hw->mac_type == e1000_ich8lan)
937 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
938 for (i = 0; i < mta_size; i++) {
939 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
940 /* use write flush to prevent Memory Write Block (MWB) from
941 * occuring when accessing our register space */
942 E1000_WRITE_FLUSH(hw);
943 }
944
945 /* Set the PCI priority bit correctly in the CTRL register. This
946 * determines if the adapter gives priority to receives, or if it
947 * gives equal priority to transmits and receives. Valid only on
948 * 82542 and 82543 silicon.
949 */
950 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
951 ctrl = E1000_READ_REG(hw, CTRL);
952 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
953 }
954
955 switch (hw->mac_type) {
956 case e1000_82545_rev_3:
957 case e1000_82546_rev_3:
958 break;
959 default:
960 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
961 if (hw->bus_type == e1000_bus_type_pcix) {
962 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
963 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
964 &pcix_stat_hi_word);
965 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
966 PCIX_COMMAND_MMRBC_SHIFT;
967 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
968 PCIX_STATUS_HI_MMRBC_SHIFT;
969 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
970 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
971 if (cmd_mmrbc > stat_mmrbc) {
972 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
973 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
974 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
975 &pcix_cmd_word);
976 }
977 }
978 break;
979 }
980
981 /* More time needed for PHY to initialize */
982 if (hw->mac_type == e1000_ich8lan)
983 msleep(15);
984
985 /* Call a subroutine to configure the link and setup flow control. */
986 ret_val = e1000_setup_link(hw);
987
988 /* Set the transmit descriptor write-back policy */
989 if (hw->mac_type > e1000_82544) {
990 ctrl = E1000_READ_REG(hw, TXDCTL);
991 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
992 E1000_WRITE_REG(hw, TXDCTL, ctrl);
993 }
994
995 if (hw->mac_type == e1000_82573) {
996 e1000_enable_tx_pkt_filtering(hw);
997 }
998
999 switch (hw->mac_type) {
1000 default:
1001 break;
1002 case e1000_80003es2lan:
1003 /* Enable retransmit on late collisions */
1004 reg_data = E1000_READ_REG(hw, TCTL);
1005 reg_data |= E1000_TCTL_RTLC;
1006 E1000_WRITE_REG(hw, TCTL, reg_data);
1007
1008 /* Configure Gigabit Carry Extend Padding */
1009 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1010 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1011 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1012 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1013
1014 /* Configure Transmit Inter-Packet Gap */
1015 reg_data = E1000_READ_REG(hw, TIPG);
1016 reg_data &= ~E1000_TIPG_IPGT_MASK;
1017 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1018 E1000_WRITE_REG(hw, TIPG, reg_data);
1019
1020 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1021 reg_data &= ~0x00100000;
1022 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1023 /* Fall through */
1024 case e1000_82571:
1025 case e1000_82572:
1026 case e1000_ich8lan:
1027 ctrl = E1000_READ_REG(hw, TXDCTL1);
1028 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1029 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1030 break;
1031 }
1032
1033
1034 if (hw->mac_type == e1000_82573) {
1035 uint32_t gcr = E1000_READ_REG(hw, GCR);
1036 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1037 E1000_WRITE_REG(hw, GCR, gcr);
1038 }
1039
1040 /* Clear all of the statistics registers (clear on read). It is
1041 * important that we do this after we have tried to establish link
1042 * because the symbol error count will increment wildly if there
1043 * is no link.
1044 */
1045 e1000_clear_hw_cntrs(hw);
1046
1047 /* ICH8 No-snoop bits are opposite polarity.
1048 * Set to snoop by default after reset. */
1049 if (hw->mac_type == e1000_ich8lan)
1050 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1051
1052 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1053 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1054 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1055 /* Relaxed ordering must be disabled to avoid a parity
1056 * error crash in a PCI slot. */
1057 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1058 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1059 }
1060
1061 return ret_val;
1062 }
1063
1064 /******************************************************************************
1065 * Adjust SERDES output amplitude based on EEPROM setting.
1066 *
1067 * hw - Struct containing variables accessed by shared code.
1068 *****************************************************************************/
1069 static int32_t
1070 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1071 {
1072 uint16_t eeprom_data;
1073 int32_t ret_val;
1074
1075 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1076
1077 if (hw->media_type != e1000_media_type_internal_serdes)
1078 return E1000_SUCCESS;
1079
1080 switch (hw->mac_type) {
1081 case e1000_82545_rev_3:
1082 case e1000_82546_rev_3:
1083 break;
1084 default:
1085 return E1000_SUCCESS;
1086 }
1087
1088 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1089 if (ret_val) {
1090 return ret_val;
1091 }
1092
1093 if (eeprom_data != EEPROM_RESERVED_WORD) {
1094 /* Adjust SERDES output amplitude only. */
1095 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1096 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1097 if (ret_val)
1098 return ret_val;
1099 }
1100
1101 return E1000_SUCCESS;
1102 }
1103
1104 /******************************************************************************
1105 * Configures flow control and link settings.
1106 *
1107 * hw - Struct containing variables accessed by shared code
1108 *
1109 * Determines which flow control settings to use. Calls the apropriate media-
1110 * specific link configuration function. Configures the flow control settings.
1111 * Assuming the adapter has a valid link partner, a valid link should be
1112 * established. Assumes the hardware has previously been reset and the
1113 * transmitter and receiver are not enabled.
1114 *****************************************************************************/
1115 int32_t
1116 e1000_setup_link(struct e1000_hw *hw)
1117 {
1118 uint32_t ctrl_ext;
1119 int32_t ret_val;
1120 uint16_t eeprom_data;
1121
1122 DEBUGFUNC("e1000_setup_link");
1123
1124 /* In the case of the phy reset being blocked, we already have a link.
1125 * We do not have to set it up again. */
1126 if (e1000_check_phy_reset_block(hw))
1127 return E1000_SUCCESS;
1128
1129 /* Read and store word 0x0F of the EEPROM. This word contains bits
1130 * that determine the hardware's default PAUSE (flow control) mode,
1131 * a bit that determines whether the HW defaults to enabling or
1132 * disabling auto-negotiation, and the direction of the
1133 * SW defined pins. If there is no SW over-ride of the flow
1134 * control setting, then the variable hw->fc will
1135 * be initialized based on a value in the EEPROM.
1136 */
1137 if (hw->fc == E1000_FC_DEFAULT) {
1138 switch (hw->mac_type) {
1139 case e1000_ich8lan:
1140 case e1000_82573:
1141 hw->fc = E1000_FC_FULL;
1142 break;
1143 default:
1144 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1145 1, &eeprom_data);
1146 if (ret_val) {
1147 DEBUGOUT("EEPROM Read Error\n");
1148 return -E1000_ERR_EEPROM;
1149 }
1150 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1151 hw->fc = E1000_FC_NONE;
1152 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1153 EEPROM_WORD0F_ASM_DIR)
1154 hw->fc = E1000_FC_TX_PAUSE;
1155 else
1156 hw->fc = E1000_FC_FULL;
1157 break;
1158 }
1159 }
1160
1161 /* We want to save off the original Flow Control configuration just
1162 * in case we get disconnected and then reconnected into a different
1163 * hub or switch with different Flow Control capabilities.
1164 */
1165 if (hw->mac_type == e1000_82542_rev2_0)
1166 hw->fc &= (~E1000_FC_TX_PAUSE);
1167
1168 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1169 hw->fc &= (~E1000_FC_RX_PAUSE);
1170
1171 hw->original_fc = hw->fc;
1172
1173 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1174
1175 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1176 * polarity value for the SW controlled pins, and setup the
1177 * Extended Device Control reg with that info.
1178 * This is needed because one of the SW controlled pins is used for
1179 * signal detection. So this should be done before e1000_setup_pcs_link()
1180 * or e1000_phy_setup() is called.
1181 */
1182 if (hw->mac_type == e1000_82543) {
1183 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1184 1, &eeprom_data);
1185 if (ret_val) {
1186 DEBUGOUT("EEPROM Read Error\n");
1187 return -E1000_ERR_EEPROM;
1188 }
1189 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1190 SWDPIO__EXT_SHIFT);
1191 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1192 }
1193
1194 /* Call the necessary subroutine to configure the link. */
1195 ret_val = (hw->media_type == e1000_media_type_copper) ?
1196 e1000_setup_copper_link(hw) :
1197 e1000_setup_fiber_serdes_link(hw);
1198
1199 /* Initialize the flow control address, type, and PAUSE timer
1200 * registers to their default values. This is done even if flow
1201 * control is disabled, because it does not hurt anything to
1202 * initialize these registers.
1203 */
1204 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1205
1206 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1207 if (hw->mac_type != e1000_ich8lan) {
1208 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1209 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1210 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1211 }
1212
1213 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1214
1215 /* Set the flow control receive threshold registers. Normally,
1216 * these registers will be set to a default threshold that may be
1217 * adjusted later by the driver's runtime code. However, if the
1218 * ability to transmit pause frames in not enabled, then these
1219 * registers will be set to 0.
1220 */
1221 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1222 E1000_WRITE_REG(hw, FCRTL, 0);
1223 E1000_WRITE_REG(hw, FCRTH, 0);
1224 } else {
1225 /* We need to set up the Receive Threshold high and low water marks
1226 * as well as (optionally) enabling the transmission of XON frames.
1227 */
1228 if (hw->fc_send_xon) {
1229 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1230 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1231 } else {
1232 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1233 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1234 }
1235 }
1236 return ret_val;
1237 }
1238
1239 /******************************************************************************
1240 * Sets up link for a fiber based or serdes based adapter
1241 *
1242 * hw - Struct containing variables accessed by shared code
1243 *
1244 * Manipulates Physical Coding Sublayer functions in order to configure
1245 * link. Assumes the hardware has been previously reset and the transmitter
1246 * and receiver are not enabled.
1247 *****************************************************************************/
1248 static int32_t
1249 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1250 {
1251 uint32_t ctrl;
1252 uint32_t status;
1253 uint32_t txcw = 0;
1254 uint32_t i;
1255 uint32_t signal = 0;
1256 int32_t ret_val;
1257
1258 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1259
1260 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1261 * until explicitly turned off or a power cycle is performed. A read to
1262 * the register does not indicate its status. Therefore, we ensure
1263 * loopback mode is disabled during initialization.
1264 */
1265 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1266 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1267
1268 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1269 * set when the optics detect a signal. On older adapters, it will be
1270 * cleared when there is a signal. This applies to fiber media only.
1271 * If we're on serdes media, adjust the output amplitude to value
1272 * set in the EEPROM.
1273 */
1274 ctrl = E1000_READ_REG(hw, CTRL);
1275 if (hw->media_type == e1000_media_type_fiber)
1276 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1277
1278 ret_val = e1000_adjust_serdes_amplitude(hw);
1279 if (ret_val)
1280 return ret_val;
1281
1282 /* Take the link out of reset */
1283 ctrl &= ~(E1000_CTRL_LRST);
1284
1285 /* Adjust VCO speed to improve BER performance */
1286 ret_val = e1000_set_vco_speed(hw);
1287 if (ret_val)
1288 return ret_val;
1289
1290 e1000_config_collision_dist(hw);
1291
1292 /* Check for a software override of the flow control settings, and setup
1293 * the device accordingly. If auto-negotiation is enabled, then software
1294 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1295 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1296 * auto-negotiation is disabled, then software will have to manually
1297 * configure the two flow control enable bits in the CTRL register.
1298 *
1299 * The possible values of the "fc" parameter are:
1300 * 0: Flow control is completely disabled
1301 * 1: Rx flow control is enabled (we can receive pause frames, but
1302 * not send pause frames).
1303 * 2: Tx flow control is enabled (we can send pause frames but we do
1304 * not support receiving pause frames).
1305 * 3: Both Rx and TX flow control (symmetric) are enabled.
1306 */
1307 switch (hw->fc) {
1308 case E1000_FC_NONE:
1309 /* Flow control is completely disabled by a software over-ride. */
1310 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1311 break;
1312 case E1000_FC_RX_PAUSE:
1313 /* RX Flow control is enabled and TX Flow control is disabled by a
1314 * software over-ride. Since there really isn't a way to advertise
1315 * that we are capable of RX Pause ONLY, we will advertise that we
1316 * support both symmetric and asymmetric RX PAUSE. Later, we will
1317 * disable the adapter's ability to send PAUSE frames.
1318 */
1319 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1320 break;
1321 case E1000_FC_TX_PAUSE:
1322 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1323 * software over-ride.
1324 */
1325 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1326 break;
1327 case E1000_FC_FULL:
1328 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1329 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1330 break;
1331 default:
1332 DEBUGOUT("Flow control param set incorrectly\n");
1333 return -E1000_ERR_CONFIG;
1334 break;
1335 }
1336
1337 /* Since auto-negotiation is enabled, take the link out of reset (the link
1338 * will be in reset, because we previously reset the chip). This will
1339 * restart auto-negotiation. If auto-neogtiation is successful then the
1340 * link-up status bit will be set and the flow control enable bits (RFCE
1341 * and TFCE) will be set according to their negotiated value.
1342 */
1343 DEBUGOUT("Auto-negotiation enabled\n");
1344
1345 E1000_WRITE_REG(hw, TXCW, txcw);
1346 E1000_WRITE_REG(hw, CTRL, ctrl);
1347 E1000_WRITE_FLUSH(hw);
1348
1349 hw->txcw = txcw;
1350 msleep(1);
1351
1352 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1353 * indication in the Device Status Register. Time-out if a link isn't
1354 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1355 * less than 500 milliseconds even if the other end is doing it in SW).
1356 * For internal serdes, we just assume a signal is present, then poll.
1357 */
1358 if (hw->media_type == e1000_media_type_internal_serdes ||
1359 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1360 DEBUGOUT("Looking for Link\n");
1361 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1362 msleep(10);
1363 status = E1000_READ_REG(hw, STATUS);
1364 if (status & E1000_STATUS_LU) break;
1365 }
1366 if (i == (LINK_UP_TIMEOUT / 10)) {
1367 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1368 hw->autoneg_failed = 1;
1369 /* AutoNeg failed to achieve a link, so we'll call
1370 * e1000_check_for_link. This routine will force the link up if
1371 * we detect a signal. This will allow us to communicate with
1372 * non-autonegotiating link partners.
1373 */
1374 ret_val = e1000_check_for_link(hw);
1375 if (ret_val) {
1376 DEBUGOUT("Error while checking for link\n");
1377 return ret_val;
1378 }
1379 hw->autoneg_failed = 0;
1380 } else {
1381 hw->autoneg_failed = 0;
1382 DEBUGOUT("Valid Link Found\n");
1383 }
1384 } else {
1385 DEBUGOUT("No Signal Detected\n");
1386 }
1387 return E1000_SUCCESS;
1388 }
1389
1390 /******************************************************************************
1391 * Make sure we have a valid PHY and change PHY mode before link setup.
1392 *
1393 * hw - Struct containing variables accessed by shared code
1394 ******************************************************************************/
1395 static int32_t
1396 e1000_copper_link_preconfig(struct e1000_hw *hw)
1397 {
1398 uint32_t ctrl;
1399 int32_t ret_val;
1400 uint16_t phy_data;
1401
1402 DEBUGFUNC("e1000_copper_link_preconfig");
1403
1404 ctrl = E1000_READ_REG(hw, CTRL);
1405 /* With 82543, we need to force speed and duplex on the MAC equal to what
1406 * the PHY speed and duplex configuration is. In addition, we need to
1407 * perform a hardware reset on the PHY to take it out of reset.
1408 */
1409 if (hw->mac_type > e1000_82543) {
1410 ctrl |= E1000_CTRL_SLU;
1411 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1412 E1000_WRITE_REG(hw, CTRL, ctrl);
1413 } else {
1414 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1415 E1000_WRITE_REG(hw, CTRL, ctrl);
1416 ret_val = e1000_phy_hw_reset(hw);
1417 if (ret_val)
1418 return ret_val;
1419 }
1420
1421 /* Make sure we have a valid PHY */
1422 ret_val = e1000_detect_gig_phy(hw);
1423 if (ret_val) {
1424 DEBUGOUT("Error, did not detect valid phy.\n");
1425 return ret_val;
1426 }
1427 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1428
1429 /* Set PHY to class A mode (if necessary) */
1430 ret_val = e1000_set_phy_mode(hw);
1431 if (ret_val)
1432 return ret_val;
1433
1434 if ((hw->mac_type == e1000_82545_rev_3) ||
1435 (hw->mac_type == e1000_82546_rev_3)) {
1436 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1437 phy_data |= 0x00000008;
1438 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1439 }
1440
1441 if (hw->mac_type <= e1000_82543 ||
1442 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1443 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1444 hw->phy_reset_disable = FALSE;
1445
1446 return E1000_SUCCESS;
1447 }
1448
1449
1450 /********************************************************************
1451 * Copper link setup for e1000_phy_igp series.
1452 *
1453 * hw - Struct containing variables accessed by shared code
1454 *********************************************************************/
1455 static int32_t
1456 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1457 {
1458 uint32_t led_ctrl;
1459 int32_t ret_val;
1460 uint16_t phy_data;
1461
1462 DEBUGFUNC("e1000_copper_link_igp_setup");
1463
1464 if (hw->phy_reset_disable)
1465 return E1000_SUCCESS;
1466
1467 ret_val = e1000_phy_reset(hw);
1468 if (ret_val) {
1469 DEBUGOUT("Error Resetting the PHY\n");
1470 return ret_val;
1471 }
1472
1473 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1474 msleep(15);
1475 if (hw->mac_type != e1000_ich8lan) {
1476 /* Configure activity LED after PHY reset */
1477 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1478 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1479 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1480 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1481 }
1482
1483 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1484 if (hw->phy_type == e1000_phy_igp) {
1485 /* disable lplu d3 during driver init */
1486 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1487 if (ret_val) {
1488 DEBUGOUT("Error Disabling LPLU D3\n");
1489 return ret_val;
1490 }
1491 }
1492
1493 /* disable lplu d0 during driver init */
1494 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1495 if (ret_val) {
1496 DEBUGOUT("Error Disabling LPLU D0\n");
1497 return ret_val;
1498 }
1499 /* Configure mdi-mdix settings */
1500 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1501 if (ret_val)
1502 return ret_val;
1503
1504 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1505 hw->dsp_config_state = e1000_dsp_config_disabled;
1506 /* Force MDI for earlier revs of the IGP PHY */
1507 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1508 hw->mdix = 1;
1509
1510 } else {
1511 hw->dsp_config_state = e1000_dsp_config_enabled;
1512 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1513
1514 switch (hw->mdix) {
1515 case 1:
1516 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1517 break;
1518 case 2:
1519 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1520 break;
1521 case 0:
1522 default:
1523 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1524 break;
1525 }
1526 }
1527 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1528 if (ret_val)
1529 return ret_val;
1530
1531 /* set auto-master slave resolution settings */
1532 if (hw->autoneg) {
1533 e1000_ms_type phy_ms_setting = hw->master_slave;
1534
1535 if (hw->ffe_config_state == e1000_ffe_config_active)
1536 hw->ffe_config_state = e1000_ffe_config_enabled;
1537
1538 if (hw->dsp_config_state == e1000_dsp_config_activated)
1539 hw->dsp_config_state = e1000_dsp_config_enabled;
1540
1541 /* when autonegotiation advertisment is only 1000Mbps then we
1542 * should disable SmartSpeed and enable Auto MasterSlave
1543 * resolution as hardware default. */
1544 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1545 /* Disable SmartSpeed */
1546 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1547 &phy_data);
1548 if (ret_val)
1549 return ret_val;
1550 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1551 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1552 phy_data);
1553 if (ret_val)
1554 return ret_val;
1555 /* Set auto Master/Slave resolution process */
1556 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1557 if (ret_val)
1558 return ret_val;
1559 phy_data &= ~CR_1000T_MS_ENABLE;
1560 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1561 if (ret_val)
1562 return ret_val;
1563 }
1564
1565 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1566 if (ret_val)
1567 return ret_val;
1568
1569 /* load defaults for future use */
1570 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1571 ((phy_data & CR_1000T_MS_VALUE) ?
1572 e1000_ms_force_master :
1573 e1000_ms_force_slave) :
1574 e1000_ms_auto;
1575
1576 switch (phy_ms_setting) {
1577 case e1000_ms_force_master:
1578 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1579 break;
1580 case e1000_ms_force_slave:
1581 phy_data |= CR_1000T_MS_ENABLE;
1582 phy_data &= ~(CR_1000T_MS_VALUE);
1583 break;
1584 case e1000_ms_auto:
1585 phy_data &= ~CR_1000T_MS_ENABLE;
1586 default:
1587 break;
1588 }
1589 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1590 if (ret_val)
1591 return ret_val;
1592 }
1593
1594 return E1000_SUCCESS;
1595 }
1596
1597 /********************************************************************
1598 * Copper link setup for e1000_phy_gg82563 series.
1599 *
1600 * hw - Struct containing variables accessed by shared code
1601 *********************************************************************/
1602 static int32_t
1603 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1604 {
1605 int32_t ret_val;
1606 uint16_t phy_data;
1607 uint32_t reg_data;
1608
1609 DEBUGFUNC("e1000_copper_link_ggp_setup");
1610
1611 if (!hw->phy_reset_disable) {
1612
1613 /* Enable CRS on TX for half-duplex operation. */
1614 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1615 &phy_data);
1616 if (ret_val)
1617 return ret_val;
1618
1619 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1620 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1621 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1622
1623 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1624 phy_data);
1625 if (ret_val)
1626 return ret_val;
1627
1628 /* Options:
1629 * MDI/MDI-X = 0 (default)
1630 * 0 - Auto for all speeds
1631 * 1 - MDI mode
1632 * 2 - MDI-X mode
1633 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1634 */
1635 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1636 if (ret_val)
1637 return ret_val;
1638
1639 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1640
1641 switch (hw->mdix) {
1642 case 1:
1643 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1644 break;
1645 case 2:
1646 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1647 break;
1648 case 0:
1649 default:
1650 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1651 break;
1652 }
1653
1654 /* Options:
1655 * disable_polarity_correction = 0 (default)
1656 * Automatic Correction for Reversed Cable Polarity
1657 * 0 - Disabled
1658 * 1 - Enabled
1659 */
1660 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1661 if (hw->disable_polarity_correction == 1)
1662 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1663 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1664
1665 if (ret_val)
1666 return ret_val;
1667
1668 /* SW Reset the PHY so all changes take effect */
1669 ret_val = e1000_phy_reset(hw);
1670 if (ret_val) {
1671 DEBUGOUT("Error Resetting the PHY\n");
1672 return ret_val;
1673 }
1674 } /* phy_reset_disable */
1675
1676 if (hw->mac_type == e1000_80003es2lan) {
1677 /* Bypass RX and TX FIFO's */
1678 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1679 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1680 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1681 if (ret_val)
1682 return ret_val;
1683
1684 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1685 if (ret_val)
1686 return ret_val;
1687
1688 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1689 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1690
1691 if (ret_val)
1692 return ret_val;
1693
1694 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1695 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1696 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1697
1698 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1699 &phy_data);
1700 if (ret_val)
1701 return ret_val;
1702
1703 /* Do not init these registers when the HW is in IAMT mode, since the
1704 * firmware will have already initialized them. We only initialize
1705 * them if the HW is not in IAMT mode.
1706 */
1707 if (e1000_check_mng_mode(hw) == FALSE) {
1708 /* Enable Electrical Idle on the PHY */
1709 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1710 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1711 phy_data);
1712 if (ret_val)
1713 return ret_val;
1714
1715 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1716 &phy_data);
1717 if (ret_val)
1718 return ret_val;
1719
1720 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1721 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1722 phy_data);
1723
1724 if (ret_val)
1725 return ret_val;
1726 }
1727
1728 /* Workaround: Disable padding in Kumeran interface in the MAC
1729 * and in the PHY to avoid CRC errors.
1730 */
1731 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1732 &phy_data);
1733 if (ret_val)
1734 return ret_val;
1735 phy_data |= GG82563_ICR_DIS_PADDING;
1736 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1737 phy_data);
1738 if (ret_val)
1739 return ret_val;
1740 }
1741
1742 return E1000_SUCCESS;
1743 }
1744
1745 /********************************************************************
1746 * Copper link setup for e1000_phy_m88 series.
1747 *
1748 * hw - Struct containing variables accessed by shared code
1749 *********************************************************************/
1750 static int32_t
1751 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1752 {
1753 int32_t ret_val;
1754 uint16_t phy_data;
1755
1756 DEBUGFUNC("e1000_copper_link_mgp_setup");
1757
1758 if (hw->phy_reset_disable)
1759 return E1000_SUCCESS;
1760
1761 /* Enable CRS on TX. This must be set for half-duplex operation. */
1762 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1763 if (ret_val)
1764 return ret_val;
1765
1766 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1767
1768 /* Options:
1769 * MDI/MDI-X = 0 (default)
1770 * 0 - Auto for all speeds
1771 * 1 - MDI mode
1772 * 2 - MDI-X mode
1773 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1774 */
1775 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1776
1777 switch (hw->mdix) {
1778 case 1:
1779 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1780 break;
1781 case 2:
1782 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1783 break;
1784 case 3:
1785 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1786 break;
1787 case 0:
1788 default:
1789 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1790 break;
1791 }
1792
1793 /* Options:
1794 * disable_polarity_correction = 0 (default)
1795 * Automatic Correction for Reversed Cable Polarity
1796 * 0 - Disabled
1797 * 1 - Enabled
1798 */
1799 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1800 if (hw->disable_polarity_correction == 1)
1801 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1802 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1803 if (ret_val)
1804 return ret_val;
1805
1806 if (hw->phy_revision < M88E1011_I_REV_4) {
1807 /* Force TX_CLK in the Extended PHY Specific Control Register
1808 * to 25MHz clock.
1809 */
1810 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1811 if (ret_val)
1812 return ret_val;
1813
1814 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1815
1816 if ((hw->phy_revision == E1000_REVISION_2) &&
1817 (hw->phy_id == M88E1111_I_PHY_ID)) {
1818 /* Vidalia Phy, set the downshift counter to 5x */
1819 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1820 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1821 ret_val = e1000_write_phy_reg(hw,
1822 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1823 if (ret_val)
1824 return ret_val;
1825 } else {
1826 /* Configure Master and Slave downshift values */
1827 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1828 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1829 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1830 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1831 ret_val = e1000_write_phy_reg(hw,
1832 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1833 if (ret_val)
1834 return ret_val;
1835 }
1836 }
1837
1838 /* SW Reset the PHY so all changes take effect */
1839 ret_val = e1000_phy_reset(hw);
1840 if (ret_val) {
1841 DEBUGOUT("Error Resetting the PHY\n");
1842 return ret_val;
1843 }
1844
1845 return E1000_SUCCESS;
1846 }
1847
1848 /********************************************************************
1849 * Setup auto-negotiation and flow control advertisements,
1850 * and then perform auto-negotiation.
1851 *
1852 * hw - Struct containing variables accessed by shared code
1853 *********************************************************************/
1854 static int32_t
1855 e1000_copper_link_autoneg(struct e1000_hw *hw)
1856 {
1857 int32_t ret_val;
1858 uint16_t phy_data;
1859
1860 DEBUGFUNC("e1000_copper_link_autoneg");
1861
1862 /* Perform some bounds checking on the hw->autoneg_advertised
1863 * parameter. If this variable is zero, then set it to the default.
1864 */
1865 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1866
1867 /* If autoneg_advertised is zero, we assume it was not defaulted
1868 * by the calling code so we set to advertise full capability.
1869 */
1870 if (hw->autoneg_advertised == 0)
1871 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1872
1873 /* IFE phy only supports 10/100 */
1874 if (hw->phy_type == e1000_phy_ife)
1875 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1876
1877 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1878 ret_val = e1000_phy_setup_autoneg(hw);
1879 if (ret_val) {
1880 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1881 return ret_val;
1882 }
1883 DEBUGOUT("Restarting Auto-Neg\n");
1884
1885 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1886 * the Auto Neg Restart bit in the PHY control register.
1887 */
1888 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1889 if (ret_val)
1890 return ret_val;
1891
1892 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1893 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1894 if (ret_val)
1895 return ret_val;
1896
1897 /* Does the user want to wait for Auto-Neg to complete here, or
1898 * check at a later time (for example, callback routine).
1899 */
1900 if (hw->wait_autoneg_complete) {
1901 ret_val = e1000_wait_autoneg(hw);
1902 if (ret_val) {
1903 DEBUGOUT("Error while waiting for autoneg to complete\n");
1904 return ret_val;
1905 }
1906 }
1907
1908 hw->get_link_status = TRUE;
1909
1910 return E1000_SUCCESS;
1911 }
1912
1913 /******************************************************************************
1914 * Config the MAC and the PHY after link is up.
1915 * 1) Set up the MAC to the current PHY speed/duplex
1916 * if we are on 82543. If we
1917 * are on newer silicon, we only need to configure
1918 * collision distance in the Transmit Control Register.
1919 * 2) Set up flow control on the MAC to that established with
1920 * the link partner.
1921 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1922 *
1923 * hw - Struct containing variables accessed by shared code
1924 ******************************************************************************/
1925 static int32_t
1926 e1000_copper_link_postconfig(struct e1000_hw *hw)
1927 {
1928 int32_t ret_val;
1929 DEBUGFUNC("e1000_copper_link_postconfig");
1930
1931 if (hw->mac_type >= e1000_82544) {
1932 e1000_config_collision_dist(hw);
1933 } else {
1934 ret_val = e1000_config_mac_to_phy(hw);
1935 if (ret_val) {
1936 DEBUGOUT("Error configuring MAC to PHY settings\n");
1937 return ret_val;
1938 }
1939 }
1940 ret_val = e1000_config_fc_after_link_up(hw);
1941 if (ret_val) {
1942 DEBUGOUT("Error Configuring Flow Control\n");
1943 return ret_val;
1944 }
1945
1946 /* Config DSP to improve Giga link quality */
1947 if (hw->phy_type == e1000_phy_igp) {
1948 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1949 if (ret_val) {
1950 DEBUGOUT("Error Configuring DSP after link up\n");
1951 return ret_val;
1952 }
1953 }
1954
1955 return E1000_SUCCESS;
1956 }
1957
1958 /******************************************************************************
1959 * Detects which PHY is present and setup the speed and duplex
1960 *
1961 * hw - Struct containing variables accessed by shared code
1962 ******************************************************************************/
1963 static int32_t
1964 e1000_setup_copper_link(struct e1000_hw *hw)
1965 {
1966 int32_t ret_val;
1967 uint16_t i;
1968 uint16_t phy_data;
1969 uint16_t reg_data;
1970
1971 DEBUGFUNC("e1000_setup_copper_link");
1972
1973 switch (hw->mac_type) {
1974 case e1000_80003es2lan:
1975 case e1000_ich8lan:
1976 /* Set the mac to wait the maximum time between each
1977 * iteration and increase the max iterations when
1978 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1979 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1980 if (ret_val)
1981 return ret_val;
1982 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1983 if (ret_val)
1984 return ret_val;
1985 reg_data |= 0x3F;
1986 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1987 if (ret_val)
1988 return ret_val;
1989 default:
1990 break;
1991 }
1992
1993 /* Check if it is a valid PHY and set PHY mode if necessary. */
1994 ret_val = e1000_copper_link_preconfig(hw);
1995 if (ret_val)
1996 return ret_val;
1997
1998 switch (hw->mac_type) {
1999 case e1000_80003es2lan:
2000 /* Kumeran registers are written-only */
2001 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2002 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2003 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
2004 reg_data);
2005 if (ret_val)
2006 return ret_val;
2007 break;
2008 default:
2009 break;
2010 }
2011
2012 if (hw->phy_type == e1000_phy_igp ||
2013 hw->phy_type == e1000_phy_igp_3 ||
2014 hw->phy_type == e1000_phy_igp_2) {
2015 ret_val = e1000_copper_link_igp_setup(hw);
2016 if (ret_val)
2017 return ret_val;
2018 } else if (hw->phy_type == e1000_phy_m88) {
2019 ret_val = e1000_copper_link_mgp_setup(hw);
2020 if (ret_val)
2021 return ret_val;
2022 } else if (hw->phy_type == e1000_phy_gg82563) {
2023 ret_val = e1000_copper_link_ggp_setup(hw);
2024 if (ret_val)
2025 return ret_val;
2026 }
2027
2028 if (hw->autoneg) {
2029 /* Setup autoneg and flow control advertisement
2030 * and perform autonegotiation */
2031 ret_val = e1000_copper_link_autoneg(hw);
2032 if (ret_val)
2033 return ret_val;
2034 } else {
2035 /* PHY will be set to 10H, 10F, 100H,or 100F
2036 * depending on value from forced_speed_duplex. */
2037 DEBUGOUT("Forcing speed and duplex\n");
2038 ret_val = e1000_phy_force_speed_duplex(hw);
2039 if (ret_val) {
2040 DEBUGOUT("Error Forcing Speed and Duplex\n");
2041 return ret_val;
2042 }
2043 }
2044
2045 /* Check link status. Wait up to 100 microseconds for link to become
2046 * valid.
2047 */
2048 for (i = 0; i < 10; i++) {
2049 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2050 if (ret_val)
2051 return ret_val;
2052 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2053 if (ret_val)
2054 return ret_val;
2055
2056 if (phy_data & MII_SR_LINK_STATUS) {
2057 /* Config the MAC and PHY after link is up */
2058 ret_val = e1000_copper_link_postconfig(hw);
2059 if (ret_val)
2060 return ret_val;
2061
2062 DEBUGOUT("Valid link established!!!\n");
2063 return E1000_SUCCESS;
2064 }
2065 udelay(10);
2066 }
2067
2068 DEBUGOUT("Unable to establish link!!!\n");
2069 return E1000_SUCCESS;
2070 }
2071
2072 /******************************************************************************
2073 * Configure the MAC-to-PHY interface for 10/100Mbps
2074 *
2075 * hw - Struct containing variables accessed by shared code
2076 ******************************************************************************/
2077 static int32_t
2078 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2079 {
2080 int32_t ret_val = E1000_SUCCESS;
2081 uint32_t tipg;
2082 uint16_t reg_data;
2083
2084 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2085
2086 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2087 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2088 reg_data);
2089 if (ret_val)
2090 return ret_val;
2091
2092 /* Configure Transmit Inter-Packet Gap */
2093 tipg = E1000_READ_REG(hw, TIPG);
2094 tipg &= ~E1000_TIPG_IPGT_MASK;
2095 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2096 E1000_WRITE_REG(hw, TIPG, tipg);
2097
2098 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2099
2100 if (ret_val)
2101 return ret_val;
2102
2103 if (duplex == HALF_DUPLEX)
2104 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2105 else
2106 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2107
2108 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2109
2110 return ret_val;
2111 }
2112
2113 static int32_t
2114 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2115 {
2116 int32_t ret_val = E1000_SUCCESS;
2117 uint16_t reg_data;
2118 uint32_t tipg;
2119
2120 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2121
2122 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2123 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2124 reg_data);
2125 if (ret_val)
2126 return ret_val;
2127
2128 /* Configure Transmit Inter-Packet Gap */
2129 tipg = E1000_READ_REG(hw, TIPG);
2130 tipg &= ~E1000_TIPG_IPGT_MASK;
2131 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2132 E1000_WRITE_REG(hw, TIPG, tipg);
2133
2134 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2135
2136 if (ret_val)
2137 return ret_val;
2138
2139 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2140 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2141
2142 return ret_val;
2143 }
2144
2145 /******************************************************************************
2146 * Configures PHY autoneg and flow control advertisement settings
2147 *
2148 * hw - Struct containing variables accessed by shared code
2149 ******************************************************************************/
2150 int32_t
2151 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2152 {
2153 int32_t ret_val;
2154 uint16_t mii_autoneg_adv_reg;
2155 uint16_t mii_1000t_ctrl_reg;
2156
2157 DEBUGFUNC("e1000_phy_setup_autoneg");
2158
2159 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2160 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2161 if (ret_val)
2162 return ret_val;
2163
2164 if (hw->phy_type != e1000_phy_ife) {
2165 /* Read the MII 1000Base-T Control Register (Address 9). */
2166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2167 if (ret_val)
2168 return ret_val;
2169 } else
2170 mii_1000t_ctrl_reg=0;
2171
2172 /* Need to parse both autoneg_advertised and fc and set up
2173 * the appropriate PHY registers. First we will parse for
2174 * autoneg_advertised software override. Since we can advertise
2175 * a plethora of combinations, we need to check each bit
2176 * individually.
2177 */
2178
2179 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2180 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2181 * the 1000Base-T Control Register (Address 9).
2182 */
2183 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2184 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2185
2186 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2187
2188 /* Do we want to advertise 10 Mb Half Duplex? */
2189 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2190 DEBUGOUT("Advertise 10mb Half duplex\n");
2191 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2192 }
2193
2194 /* Do we want to advertise 10 Mb Full Duplex? */
2195 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2196 DEBUGOUT("Advertise 10mb Full duplex\n");
2197 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2198 }
2199
2200 /* Do we want to advertise 100 Mb Half Duplex? */
2201 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2202 DEBUGOUT("Advertise 100mb Half duplex\n");
2203 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2204 }
2205
2206 /* Do we want to advertise 100 Mb Full Duplex? */
2207 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2208 DEBUGOUT("Advertise 100mb Full duplex\n");
2209 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2210 }
2211
2212 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2213 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2214 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2215 }
2216
2217 /* Do we want to advertise 1000 Mb Full Duplex? */
2218 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2219 DEBUGOUT("Advertise 1000mb Full duplex\n");
2220 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2221 if (hw->phy_type == e1000_phy_ife) {
2222 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2223 }
2224 }
2225
2226 /* Check for a software override of the flow control settings, and
2227 * setup the PHY advertisement registers accordingly. If
2228 * auto-negotiation is enabled, then software will have to set the
2229 * "PAUSE" bits to the correct value in the Auto-Negotiation
2230 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2231 *
2232 * The possible values of the "fc" parameter are:
2233 * 0: Flow control is completely disabled
2234 * 1: Rx flow control is enabled (we can receive pause frames
2235 * but not send pause frames).
2236 * 2: Tx flow control is enabled (we can send pause frames
2237 * but we do not support receiving pause frames).
2238 * 3: Both Rx and TX flow control (symmetric) are enabled.
2239 * other: No software override. The flow control configuration
2240 * in the EEPROM is used.
2241 */
2242 switch (hw->fc) {
2243 case E1000_FC_NONE: /* 0 */
2244 /* Flow control (RX & TX) is completely disabled by a
2245 * software over-ride.
2246 */
2247 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2248 break;
2249 case E1000_FC_RX_PAUSE: /* 1 */
2250 /* RX Flow control is enabled, and TX Flow control is
2251 * disabled, by a software over-ride.
2252 */
2253 /* Since there really isn't a way to advertise that we are
2254 * capable of RX Pause ONLY, we will advertise that we
2255 * support both symmetric and asymmetric RX PAUSE. Later
2256 * (in e1000_config_fc_after_link_up) we will disable the
2257 *hw's ability to send PAUSE frames.
2258 */
2259 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2260 break;
2261 case E1000_FC_TX_PAUSE: /* 2 */
2262 /* TX Flow control is enabled, and RX Flow control is
2263 * disabled, by a software over-ride.
2264 */
2265 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2266 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2267 break;
2268 case E1000_FC_FULL: /* 3 */
2269 /* Flow control (both RX and TX) is enabled by a software
2270 * over-ride.
2271 */
2272 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2273 break;
2274 default:
2275 DEBUGOUT("Flow control param set incorrectly\n");
2276 return -E1000_ERR_CONFIG;
2277 }
2278
2279 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2280 if (ret_val)
2281 return ret_val;
2282
2283 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2284
2285 if (hw->phy_type != e1000_phy_ife) {
2286 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2287 if (ret_val)
2288 return ret_val;
2289 }
2290
2291 return E1000_SUCCESS;
2292 }
2293
2294 /******************************************************************************
2295 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2296 *
2297 * hw - Struct containing variables accessed by shared code
2298 ******************************************************************************/
2299 static int32_t
2300 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2301 {
2302 uint32_t ctrl;
2303 int32_t ret_val;
2304 uint16_t mii_ctrl_reg;
2305 uint16_t mii_status_reg;
2306 uint16_t phy_data;
2307 uint16_t i;
2308
2309 DEBUGFUNC("e1000_phy_force_speed_duplex");
2310
2311 /* Turn off Flow control if we are forcing speed and duplex. */
2312 hw->fc = E1000_FC_NONE;
2313
2314 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2315
2316 /* Read the Device Control Register. */
2317 ctrl = E1000_READ_REG(hw, CTRL);
2318
2319 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2320 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2321 ctrl &= ~(DEVICE_SPEED_MASK);
2322
2323 /* Clear the Auto Speed Detect Enable bit. */
2324 ctrl &= ~E1000_CTRL_ASDE;
2325
2326 /* Read the MII Control Register. */
2327 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2328 if (ret_val)
2329 return ret_val;
2330
2331 /* We need to disable autoneg in order to force link and duplex. */
2332
2333 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2334
2335 /* Are we forcing Full or Half Duplex? */
2336 if (hw->forced_speed_duplex == e1000_100_full ||
2337 hw->forced_speed_duplex == e1000_10_full) {
2338 /* We want to force full duplex so we SET the full duplex bits in the
2339 * Device and MII Control Registers.
2340 */
2341 ctrl |= E1000_CTRL_FD;
2342 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2343 DEBUGOUT("Full Duplex\n");
2344 } else {
2345 /* We want to force half duplex so we CLEAR the full duplex bits in
2346 * the Device and MII Control Registers.
2347 */
2348 ctrl &= ~E1000_CTRL_FD;
2349 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2350 DEBUGOUT("Half Duplex\n");
2351 }
2352
2353 /* Are we forcing 100Mbps??? */
2354 if (hw->forced_speed_duplex == e1000_100_full ||
2355 hw->forced_speed_duplex == e1000_100_half) {
2356 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2357 ctrl |= E1000_CTRL_SPD_100;
2358 mii_ctrl_reg |= MII_CR_SPEED_100;
2359 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2360 DEBUGOUT("Forcing 100mb ");
2361 } else {
2362 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2363 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2364 mii_ctrl_reg |= MII_CR_SPEED_10;
2365 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2366 DEBUGOUT("Forcing 10mb ");
2367 }
2368
2369 e1000_config_collision_dist(hw);
2370
2371 /* Write the configured values back to the Device Control Reg. */
2372 E1000_WRITE_REG(hw, CTRL, ctrl);
2373
2374 if ((hw->phy_type == e1000_phy_m88) ||
2375 (hw->phy_type == e1000_phy_gg82563)) {
2376 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2377 if (ret_val)
2378 return ret_val;
2379
2380 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2381 * forced whenever speed are duplex are forced.
2382 */
2383 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2384 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2385 if (ret_val)
2386 return ret_val;
2387
2388 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2389
2390 /* Need to reset the PHY or these changes will be ignored */
2391 mii_ctrl_reg |= MII_CR_RESET;
2392
2393 /* Disable MDI-X support for 10/100 */
2394 } else if (hw->phy_type == e1000_phy_ife) {
2395 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2396 if (ret_val)
2397 return ret_val;
2398
2399 phy_data &= ~IFE_PMC_AUTO_MDIX;
2400 phy_data &= ~IFE_PMC_FORCE_MDIX;
2401
2402 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2403 if (ret_val)
2404 return ret_val;
2405
2406 } else {
2407 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2408 * forced whenever speed or duplex are forced.
2409 */
2410 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2411 if (ret_val)
2412 return ret_val;
2413
2414 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2415 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2416
2417 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2418 if (ret_val)
2419 return ret_val;
2420 }
2421
2422 /* Write back the modified PHY MII control register. */
2423 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2424 if (ret_val)
2425 return ret_val;
2426
2427 udelay(1);
2428
2429 /* The wait_autoneg_complete flag may be a little misleading here.
2430 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2431 * But we do want to delay for a period while forcing only so we
2432 * don't generate false No Link messages. So we will wait here
2433 * only if the user has set wait_autoneg_complete to 1, which is
2434 * the default.
2435 */
2436 if (hw->wait_autoneg_complete) {
2437 /* We will wait for autoneg to complete. */
2438 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2439 mii_status_reg = 0;
2440
2441 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2442 for (i = PHY_FORCE_TIME; i > 0; i--) {
2443 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2444 * to be set.
2445 */
2446 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2447 if (ret_val)
2448 return ret_val;
2449
2450 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2451 if (ret_val)
2452 return ret_val;
2453
2454 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2455 msleep(100);
2456 }
2457 if ((i == 0) &&
2458 ((hw->phy_type == e1000_phy_m88) ||
2459 (hw->phy_type == e1000_phy_gg82563))) {
2460 /* We didn't get link. Reset the DSP and wait again for link. */
2461 ret_val = e1000_phy_reset_dsp(hw);
2462 if (ret_val) {
2463 DEBUGOUT("Error Resetting PHY DSP\n");
2464 return ret_val;
2465 }
2466 }
2467 /* This loop will early-out if the link condition has been met. */
2468 for (i = PHY_FORCE_TIME; i > 0; i--) {
2469 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2470 msleep(100);
2471 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2472 * to be set.
2473 */
2474 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2475 if (ret_val)
2476 return ret_val;
2477
2478 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2479 if (ret_val)
2480 return ret_val;
2481 }
2482 }
2483
2484 if (hw->phy_type == e1000_phy_m88) {
2485 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2486 * Extended PHY Specific Control Register to 25MHz clock. This value
2487 * defaults back to a 2.5MHz clock when the PHY is reset.
2488 */
2489 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2490 if (ret_val)
2491 return ret_val;
2492
2493 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2494 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2495 if (ret_val)
2496 return ret_val;
2497
2498 /* In addition, because of the s/w reset above, we need to enable CRS on
2499 * TX. This must be set for both full and half duplex operation.
2500 */
2501 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2502 if (ret_val)
2503 return ret_val;
2504
2505 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2506 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2507 if (ret_val)
2508 return ret_val;
2509
2510 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2511 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2512 hw->forced_speed_duplex == e1000_10_half)) {
2513 ret_val = e1000_polarity_reversal_workaround(hw);
2514 if (ret_val)
2515 return ret_val;
2516 }
2517 } else if (hw->phy_type == e1000_phy_gg82563) {
2518 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2519 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2520 * we're not in a forced 10/duplex configuration. */
2521 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2522 if (ret_val)
2523 return ret_val;
2524
2525 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2526 if ((hw->forced_speed_duplex == e1000_10_full) ||
2527 (hw->forced_speed_duplex == e1000_10_half))
2528 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2529 else
2530 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2531
2532 /* Also due to the reset, we need to enable CRS on Tx. */
2533 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2534
2535 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2536 if (ret_val)
2537 return ret_val;
2538 }
2539 return E1000_SUCCESS;
2540 }
2541
2542 /******************************************************************************
2543 * Sets the collision distance in the Transmit Control register
2544 *
2545 * hw - Struct containing variables accessed by shared code
2546 *
2547 * Link should have been established previously. Reads the speed and duplex
2548 * information from the Device Status register.
2549 ******************************************************************************/
2550 void
2551 e1000_config_collision_dist(struct e1000_hw *hw)
2552 {
2553 uint32_t tctl, coll_dist;
2554
2555 DEBUGFUNC("e1000_config_collision_dist");
2556
2557 if (hw->mac_type < e1000_82543)
2558 coll_dist = E1000_COLLISION_DISTANCE_82542;
2559 else
2560 coll_dist = E1000_COLLISION_DISTANCE;
2561
2562 tctl = E1000_READ_REG(hw, TCTL);
2563
2564 tctl &= ~E1000_TCTL_COLD;
2565 tctl |= coll_dist << E1000_COLD_SHIFT;
2566
2567 E1000_WRITE_REG(hw, TCTL, tctl);
2568 E1000_WRITE_FLUSH(hw);
2569 }
2570
2571 /******************************************************************************
2572 * Sets MAC speed and duplex settings to reflect the those in the PHY
2573 *
2574 * hw - Struct containing variables accessed by shared code
2575 * mii_reg - data to write to the MII control register
2576 *
2577 * The contents of the PHY register containing the needed information need to
2578 * be passed in.
2579 ******************************************************************************/
2580 static int32_t
2581 e1000_config_mac_to_phy(struct e1000_hw *hw)
2582 {
2583 uint32_t ctrl;
2584 int32_t ret_val;
2585 uint16_t phy_data;
2586
2587 DEBUGFUNC("e1000_config_mac_to_phy");
2588
2589 /* 82544 or newer MAC, Auto Speed Detection takes care of
2590 * MAC speed/duplex configuration.*/
2591 if (hw->mac_type >= e1000_82544)
2592 return E1000_SUCCESS;
2593
2594 /* Read the Device Control Register and set the bits to Force Speed
2595 * and Duplex.
2596 */
2597 ctrl = E1000_READ_REG(hw, CTRL);
2598 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2599 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2600
2601 /* Set up duplex in the Device Control and Transmit Control
2602 * registers depending on negotiated values.
2603 */
2604 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2605 if (ret_val)
2606 return ret_val;
2607
2608 if (phy_data & M88E1000_PSSR_DPLX)
2609 ctrl |= E1000_CTRL_FD;
2610 else
2611 ctrl &= ~E1000_CTRL_FD;
2612
2613 e1000_config_collision_dist(hw);
2614
2615 /* Set up speed in the Device Control register depending on
2616 * negotiated values.
2617 */
2618 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2619 ctrl |= E1000_CTRL_SPD_1000;
2620 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2621 ctrl |= E1000_CTRL_SPD_100;
2622
2623 /* Write the configured values back to the Device Control Reg. */
2624 E1000_WRITE_REG(hw, CTRL, ctrl);
2625 return E1000_SUCCESS;
2626 }
2627
2628 /******************************************************************************
2629 * Forces the MAC's flow control settings.
2630 *
2631 * hw - Struct containing variables accessed by shared code
2632 *
2633 * Sets the TFCE and RFCE bits in the device control register to reflect
2634 * the adapter settings. TFCE and RFCE need to be explicitly set by
2635 * software when a Copper PHY is used because autonegotiation is managed
2636 * by the PHY rather than the MAC. Software must also configure these
2637 * bits when link is forced on a fiber connection.
2638 *****************************************************************************/
2639 int32_t
2640 e1000_force_mac_fc(struct e1000_hw *hw)
2641 {
2642 uint32_t ctrl;
2643
2644 DEBUGFUNC("e1000_force_mac_fc");
2645
2646 /* Get the current configuration of the Device Control Register */
2647 ctrl = E1000_READ_REG(hw, CTRL);
2648
2649 /* Because we didn't get link via the internal auto-negotiation
2650 * mechanism (we either forced link or we got link via PHY
2651 * auto-neg), we have to manually enable/disable transmit an
2652 * receive flow control.
2653 *
2654 * The "Case" statement below enables/disable flow control
2655 * according to the "hw->fc" parameter.
2656 *
2657 * The possible values of the "fc" parameter are:
2658 * 0: Flow control is completely disabled
2659 * 1: Rx flow control is enabled (we can receive pause
2660 * frames but not send pause frames).
2661 * 2: Tx flow control is enabled (we can send pause frames
2662 * frames but we do not receive pause frames).
2663 * 3: Both Rx and TX flow control (symmetric) is enabled.
2664 * other: No other values should be possible at this point.
2665 */
2666
2667 switch (hw->fc) {
2668 case E1000_FC_NONE:
2669 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2670 break;
2671 case E1000_FC_RX_PAUSE:
2672 ctrl &= (~E1000_CTRL_TFCE);
2673 ctrl |= E1000_CTRL_RFCE;
2674 break;
2675 case E1000_FC_TX_PAUSE:
2676 ctrl &= (~E1000_CTRL_RFCE);
2677 ctrl |= E1000_CTRL_TFCE;
2678 break;
2679 case E1000_FC_FULL:
2680 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2681 break;
2682 default:
2683 DEBUGOUT("Flow control param set incorrectly\n");
2684 return -E1000_ERR_CONFIG;
2685 }
2686
2687 /* Disable TX Flow Control for 82542 (rev 2.0) */
2688 if (hw->mac_type == e1000_82542_rev2_0)
2689 ctrl &= (~E1000_CTRL_TFCE);
2690
2691 E1000_WRITE_REG(hw, CTRL, ctrl);
2692 return E1000_SUCCESS;
2693 }
2694
2695 /******************************************************************************
2696 * Configures flow control settings after link is established
2697 *
2698 * hw - Struct containing variables accessed by shared code
2699 *
2700 * Should be called immediately after a valid link has been established.
2701 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2702 * and autonegotiation is enabled, the MAC flow control settings will be set
2703 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2704 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2705 *****************************************************************************/
2706 static int32_t
2707 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2708 {
2709 int32_t ret_val;
2710 uint16_t mii_status_reg;
2711 uint16_t mii_nway_adv_reg;
2712 uint16_t mii_nway_lp_ability_reg;
2713 uint16_t speed;
2714 uint16_t duplex;
2715
2716 DEBUGFUNC("e1000_config_fc_after_link_up");
2717
2718 /* Check for the case where we have fiber media and auto-neg failed
2719 * so we had to force link. In this case, we need to force the
2720 * configuration of the MAC to match the "fc" parameter.
2721 */
2722 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2723 ((hw->media_type == e1000_media_type_internal_serdes) &&
2724 (hw->autoneg_failed)) ||
2725 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2726 ret_val = e1000_force_mac_fc(hw);
2727 if (ret_val) {
2728 DEBUGOUT("Error forcing flow control settings\n");
2729 return ret_val;
2730 }
2731 }
2732
2733 /* Check for the case where we have copper media and auto-neg is
2734 * enabled. In this case, we need to check and see if Auto-Neg
2735 * has completed, and if so, how the PHY and link partner has
2736 * flow control configured.
2737 */
2738 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2739 /* Read the MII Status Register and check to see if AutoNeg
2740 * has completed. We read this twice because this reg has
2741 * some "sticky" (latched) bits.
2742 */
2743 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2744 if (ret_val)
2745 return ret_val;
2746 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2747 if (ret_val)
2748 return ret_val;
2749
2750 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2751 /* The AutoNeg process has completed, so we now need to
2752 * read both the Auto Negotiation Advertisement Register
2753 * (Address 4) and the Auto_Negotiation Base Page Ability
2754 * Register (Address 5) to determine how flow control was
2755 * negotiated.
2756 */
2757 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2758 &mii_nway_adv_reg);
2759 if (ret_val)
2760 return ret_val;
2761 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2762 &mii_nway_lp_ability_reg);
2763 if (ret_val)
2764 return ret_val;
2765
2766 /* Two bits in the Auto Negotiation Advertisement Register
2767 * (Address 4) and two bits in the Auto Negotiation Base
2768 * Page Ability Register (Address 5) determine flow control
2769 * for both the PHY and the link partner. The following
2770 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2771 * 1999, describes these PAUSE resolution bits and how flow
2772 * control is determined based upon these settings.
2773 * NOTE: DC = Don't Care
2774 *
2775 * LOCAL DEVICE | LINK PARTNER
2776 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2777 *-------|---------|-------|---------|--------------------
2778 * 0 | 0 | DC | DC | E1000_FC_NONE
2779 * 0 | 1 | 0 | DC | E1000_FC_NONE
2780 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2781 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2782 * 1 | 0 | 0 | DC | E1000_FC_NONE
2783 * 1 | DC | 1 | DC | E1000_FC_FULL
2784 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2785 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2786 *
2787 */
2788 /* Are both PAUSE bits set to 1? If so, this implies
2789 * Symmetric Flow Control is enabled at both ends. The
2790 * ASM_DIR bits are irrelevant per the spec.
2791 *
2792 * For Symmetric Flow Control:
2793 *
2794 * LOCAL DEVICE | LINK PARTNER
2795 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2796 *-------|---------|-------|---------|--------------------
2797 * 1 | DC | 1 | DC | E1000_FC_FULL
2798 *
2799 */
2800 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2801 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2802 /* Now we need to check if the user selected RX ONLY
2803 * of pause frames. In this case, we had to advertise
2804 * FULL flow control because we could not advertise RX
2805 * ONLY. Hence, we must now check to see if we need to
2806 * turn OFF the TRANSMISSION of PAUSE frames.
2807 */
2808 if (hw->original_fc == E1000_FC_FULL) {
2809 hw->fc = E1000_FC_FULL;
2810 DEBUGOUT("Flow Control = FULL.\n");
2811 } else {
2812 hw->fc = E1000_FC_RX_PAUSE;
2813 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2814 }
2815 }
2816 /* For receiving PAUSE frames ONLY.
2817 *
2818 * LOCAL DEVICE | LINK PARTNER
2819 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2820 *-------|---------|-------|---------|--------------------
2821 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2822 *
2823 */
2824 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2825 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2826 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2827 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2828 hw->fc = E1000_FC_TX_PAUSE;
2829 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2830 }
2831 /* For transmitting PAUSE frames ONLY.
2832 *
2833 * LOCAL DEVICE | LINK PARTNER
2834 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2835 *-------|---------|-------|---------|--------------------
2836 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2837 *
2838 */
2839 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2840 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2841 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2842 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2843 hw->fc = E1000_FC_RX_PAUSE;
2844 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2845 }
2846 /* Per the IEEE spec, at this point flow control should be
2847 * disabled. However, we want to consider that we could
2848 * be connected to a legacy switch that doesn't advertise
2849 * desired flow control, but can be forced on the link
2850 * partner. So if we advertised no flow control, that is
2851 * what we will resolve to. If we advertised some kind of
2852 * receive capability (Rx Pause Only or Full Flow Control)
2853 * and the link partner advertised none, we will configure
2854 * ourselves to enable Rx Flow Control only. We can do
2855 * this safely for two reasons: If the link partner really
2856 * didn't want flow control enabled, and we enable Rx, no
2857 * harm done since we won't be receiving any PAUSE frames
2858 * anyway. If the intent on the link partner was to have
2859 * flow control enabled, then by us enabling RX only, we
2860 * can at least receive pause frames and process them.
2861 * This is a good idea because in most cases, since we are
2862 * predominantly a server NIC, more times than not we will
2863 * be asked to delay transmission of packets than asking
2864 * our link partner to pause transmission of frames.
2865 */
2866 else if ((hw->original_fc == E1000_FC_NONE ||
2867 hw->original_fc == E1000_FC_TX_PAUSE) ||
2868 hw->fc_strict_ieee) {
2869 hw->fc = E1000_FC_NONE;
2870 DEBUGOUT("Flow Control = NONE.\n");
2871 } else {
2872 hw->fc = E1000_FC_RX_PAUSE;
2873 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2874 }
2875
2876 /* Now we need to do one last check... If we auto-
2877 * negotiated to HALF DUPLEX, flow control should not be
2878 * enabled per IEEE 802.3 spec.
2879 */
2880 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2881 if (ret_val) {
2882 DEBUGOUT("Error getting link speed and duplex\n");
2883 return ret_val;
2884 }
2885
2886 if (duplex == HALF_DUPLEX)
2887 hw->fc = E1000_FC_NONE;
2888
2889 /* Now we call a subroutine to actually force the MAC
2890 * controller to use the correct flow control settings.
2891 */
2892 ret_val = e1000_force_mac_fc(hw);
2893 if (ret_val) {
2894 DEBUGOUT("Error forcing flow control settings\n");
2895 return ret_val;
2896 }
2897 } else {
2898 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2899 }
2900 }
2901 return E1000_SUCCESS;
2902 }
2903
2904 /******************************************************************************
2905 * Checks to see if the link status of the hardware has changed.
2906 *
2907 * hw - Struct containing variables accessed by shared code
2908 *
2909 * Called by any function that needs to check the link status of the adapter.
2910 *****************************************************************************/
2911 int32_t
2912 e1000_check_for_link(struct e1000_hw *hw)
2913 {
2914 uint32_t rxcw = 0;
2915 uint32_t ctrl;
2916 uint32_t status;
2917 uint32_t rctl;
2918 uint32_t icr;
2919 uint32_t signal = 0;
2920 int32_t ret_val;
2921 uint16_t phy_data;
2922
2923 DEBUGFUNC("e1000_check_for_link");
2924
2925 ctrl = E1000_READ_REG(hw, CTRL);
2926 status = E1000_READ_REG(hw, STATUS);
2927
2928 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2929 * set when the optics detect a signal. On older adapters, it will be
2930 * cleared when there is a signal. This applies to fiber media only.
2931 */
2932 if ((hw->media_type == e1000_media_type_fiber) ||
2933 (hw->media_type == e1000_media_type_internal_serdes)) {
2934 rxcw = E1000_READ_REG(hw, RXCW);
2935
2936 if (hw->media_type == e1000_media_type_fiber) {
2937 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2938 if (status & E1000_STATUS_LU)
2939 hw->get_link_status = FALSE;
2940 }
2941 }
2942
2943 /* If we have a copper PHY then we only want to go out to the PHY
2944 * registers to see if Auto-Neg has completed and/or if our link
2945 * status has changed. The get_link_status flag will be set if we
2946 * receive a Link Status Change interrupt or we have Rx Sequence
2947 * Errors.
2948 */
2949 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2950 /* First we want to see if the MII Status Register reports
2951 * link. If so, then we want to get the current speed/duplex
2952 * of the PHY.
2953 * Read the register twice since the link bit is sticky.
2954 */
2955 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2956 if (ret_val)
2957 return ret_val;
2958 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2959 if (ret_val)
2960 return ret_val;
2961
2962 if (phy_data & MII_SR_LINK_STATUS) {
2963 hw->get_link_status = FALSE;
2964 /* Check if there was DownShift, must be checked immediately after
2965 * link-up */
2966 e1000_check_downshift(hw);
2967
2968 /* If we are on 82544 or 82543 silicon and speed/duplex
2969 * are forced to 10H or 10F, then we will implement the polarity
2970 * reversal workaround. We disable interrupts first, and upon
2971 * returning, place the devices interrupt state to its previous
2972 * value except for the link status change interrupt which will
2973 * happen due to the execution of this workaround.
2974 */
2975
2976 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2977 (!hw->autoneg) &&
2978 (hw->forced_speed_duplex == e1000_10_full ||
2979 hw->forced_speed_duplex == e1000_10_half)) {
2980 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2981 ret_val = e1000_polarity_reversal_workaround(hw);
2982 icr = E1000_READ_REG(hw, ICR);
2983 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2984 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2985 }
2986
2987 } else {
2988 /* No link detected */
2989 e1000_config_dsp_after_link_change(hw, FALSE);
2990 return 0;
2991 }
2992
2993 /* If we are forcing speed/duplex, then we simply return since
2994 * we have already determined whether we have link or not.
2995 */
2996 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2997
2998 /* optimize the dsp settings for the igp phy */
2999 e1000_config_dsp_after_link_change(hw, TRUE);
3000
3001 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3002 * have Si on board that is 82544 or newer, Auto
3003 * Speed Detection takes care of MAC speed/duplex
3004 * configuration. So we only need to configure Collision
3005 * Distance in the MAC. Otherwise, we need to force
3006 * speed/duplex on the MAC to the current PHY speed/duplex
3007 * settings.
3008 */
3009 if (hw->mac_type >= e1000_82544)
3010 e1000_config_collision_dist(hw);
3011 else {
3012 ret_val = e1000_config_mac_to_phy(hw);
3013 if (ret_val) {
3014 DEBUGOUT("Error configuring MAC to PHY settings\n");
3015 return ret_val;
3016 }
3017 }
3018
3019 /* Configure Flow Control now that Auto-Neg has completed. First, we
3020 * need to restore the desired flow control settings because we may
3021 * have had to re-autoneg with a different link partner.
3022 */
3023 ret_val = e1000_config_fc_after_link_up(hw);
3024 if (ret_val) {
3025 DEBUGOUT("Error configuring flow control\n");
3026 return ret_val;
3027 }
3028
3029 /* At this point we know that we are on copper and we have
3030 * auto-negotiated link. These are conditions for checking the link
3031 * partner capability register. We use the link speed to determine if
3032 * TBI compatibility needs to be turned on or off. If the link is not
3033 * at gigabit speed, then TBI compatibility is not needed. If we are
3034 * at gigabit speed, we turn on TBI compatibility.
3035 */
3036 if (hw->tbi_compatibility_en) {
3037 uint16_t speed, duplex;
3038 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3039 if (ret_val) {
3040 DEBUGOUT("Error getting link speed and duplex\n");
3041 return ret_val;
3042 }
3043 if (speed != SPEED_1000) {
3044 /* If link speed is not set to gigabit speed, we do not need
3045 * to enable TBI compatibility.
3046 */
3047 if (hw->tbi_compatibility_on) {
3048 /* If we previously were in the mode, turn it off. */
3049 rctl = E1000_READ_REG(hw, RCTL);
3050 rctl &= ~E1000_RCTL_SBP;
3051 E1000_WRITE_REG(hw, RCTL, rctl);
3052 hw->tbi_compatibility_on = FALSE;
3053 }
3054 } else {
3055 /* If TBI compatibility is was previously off, turn it on. For
3056 * compatibility with a TBI link partner, we will store bad
3057 * packets. Some frames have an additional byte on the end and
3058 * will look like CRC errors to to the hardware.
3059 */
3060 if (!hw->tbi_compatibility_on) {
3061 hw->tbi_compatibility_on = TRUE;
3062 rctl = E1000_READ_REG(hw, RCTL);
3063 rctl |= E1000_RCTL_SBP;
3064 E1000_WRITE_REG(hw, RCTL, rctl);
3065 }
3066 }
3067 }
3068 }
3069 /* If we don't have link (auto-negotiation failed or link partner cannot
3070 * auto-negotiate), the cable is plugged in (we have signal), and our
3071 * link partner is not trying to auto-negotiate with us (we are receiving
3072 * idles or data), we need to force link up. We also need to give
3073 * auto-negotiation time to complete, in case the cable was just plugged
3074 * in. The autoneg_failed flag does this.
3075 */
3076 else if ((((hw->media_type == e1000_media_type_fiber) &&
3077 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3078 (hw->media_type == e1000_media_type_internal_serdes)) &&
3079 (!(status & E1000_STATUS_LU)) &&
3080 (!(rxcw & E1000_RXCW_C))) {
3081 if (hw->autoneg_failed == 0) {
3082 hw->autoneg_failed = 1;
3083 return 0;
3084 }
3085 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3086
3087 /* Disable auto-negotiation in the TXCW register */
3088 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3089
3090 /* Force link-up and also force full-duplex. */
3091 ctrl = E1000_READ_REG(hw, CTRL);
3092 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3093 E1000_WRITE_REG(hw, CTRL, ctrl);
3094
3095 /* Configure Flow Control after forcing link up. */
3096 ret_val = e1000_config_fc_after_link_up(hw);
3097 if (ret_val) {
3098 DEBUGOUT("Error configuring flow control\n");
3099 return ret_val;
3100 }
3101 }
3102 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3103 * auto-negotiation in the TXCW register and disable forced link in the
3104 * Device Control register in an attempt to auto-negotiate with our link
3105 * partner.
3106 */
3107 else if (((hw->media_type == e1000_media_type_fiber) ||
3108 (hw->media_type == e1000_media_type_internal_serdes)) &&
3109 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3110 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3111 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3112 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3113
3114 hw->serdes_link_down = FALSE;
3115 }
3116 /* If we force link for non-auto-negotiation switch, check link status
3117 * based on MAC synchronization for internal serdes media type.
3118 */
3119 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3120 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3121 /* SYNCH bit and IV bit are sticky. */
3122 udelay(10);
3123 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3124 if (!(rxcw & E1000_RXCW_IV)) {
3125 hw->serdes_link_down = FALSE;
3126 DEBUGOUT("SERDES: Link is up.\n");
3127 }
3128 } else {
3129 hw->serdes_link_down = TRUE;
3130 DEBUGOUT("SERDES: Link is down.\n");
3131 }
3132 }
3133 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3134 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3135 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3136 }
3137 return E1000_SUCCESS;
3138 }
3139
3140 /******************************************************************************
3141 * Detects the current speed and duplex settings of the hardware.
3142 *
3143 * hw - Struct containing variables accessed by shared code
3144 * speed - Speed of the connection
3145 * duplex - Duplex setting of the connection
3146 *****************************************************************************/
3147 int32_t
3148 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3149 uint16_t *speed,
3150 uint16_t *duplex)
3151 {
3152 uint32_t status;
3153 int32_t ret_val;
3154 uint16_t phy_data;
3155
3156 DEBUGFUNC("e1000_get_speed_and_duplex");
3157
3158 if (hw->mac_type >= e1000_82543) {
3159 status = E1000_READ_REG(hw, STATUS);
3160 if (status & E1000_STATUS_SPEED_1000) {
3161 *speed = SPEED_1000;
3162 DEBUGOUT("1000 Mbs, ");
3163 } else if (status & E1000_STATUS_SPEED_100) {
3164 *speed = SPEED_100;
3165 DEBUGOUT("100 Mbs, ");
3166 } else {
3167 *speed = SPEED_10;
3168 DEBUGOUT("10 Mbs, ");
3169 }
3170
3171 if (status & E1000_STATUS_FD) {
3172 *duplex = FULL_DUPLEX;
3173 DEBUGOUT("Full Duplex\n");
3174 } else {
3175 *duplex = HALF_DUPLEX;
3176 DEBUGOUT(" Half Duplex\n");
3177 }
3178 } else {
3179 DEBUGOUT("1000 Mbs, Full Duplex\n");
3180 *speed = SPEED_1000;
3181 *duplex = FULL_DUPLEX;
3182 }
3183
3184 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3185 * if it is operating at half duplex. Here we set the duplex settings to
3186 * match the duplex in the link partner's capabilities.
3187 */
3188 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3189 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3190 if (ret_val)
3191 return ret_val;
3192
3193 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3194 *duplex = HALF_DUPLEX;
3195 else {
3196 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3197 if (ret_val)
3198 return ret_val;
3199 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3200 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3201 *duplex = HALF_DUPLEX;
3202 }
3203 }
3204
3205 if ((hw->mac_type == e1000_80003es2lan) &&
3206 (hw->media_type == e1000_media_type_copper)) {
3207 if (*speed == SPEED_1000)
3208 ret_val = e1000_configure_kmrn_for_1000(hw);
3209 else
3210 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3211 if (ret_val)
3212 return ret_val;
3213 }
3214
3215 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3216 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3217 if (ret_val)
3218 return ret_val;
3219 }
3220
3221 return E1000_SUCCESS;
3222 }
3223
3224 /******************************************************************************
3225 * Blocks until autoneg completes or times out (~4.5 seconds)
3226 *
3227 * hw - Struct containing variables accessed by shared code
3228 ******************************************************************************/
3229 static int32_t
3230 e1000_wait_autoneg(struct e1000_hw *hw)
3231 {
3232 int32_t ret_val;
3233 uint16_t i;
3234 uint16_t phy_data;
3235
3236 DEBUGFUNC("e1000_wait_autoneg");
3237 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3238
3239 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3240 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3241 /* Read the MII Status Register and wait for Auto-Neg
3242 * Complete bit to be set.
3243 */
3244 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3245 if (ret_val)
3246 return ret_val;
3247 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3248 if (ret_val)
3249 return ret_val;
3250 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3251 return E1000_SUCCESS;
3252 }
3253 msleep(100);
3254 }
3255 return E1000_SUCCESS;
3256 }
3257
3258 /******************************************************************************
3259 * Raises the Management Data Clock
3260 *
3261 * hw - Struct containing variables accessed by shared code
3262 * ctrl - Device control register's current value
3263 ******************************************************************************/
3264 static void
3265 e1000_raise_mdi_clk(struct e1000_hw *hw,
3266 uint32_t *ctrl)
3267 {
3268 /* Raise the clock input to the Management Data Clock (by setting the MDC
3269 * bit), and then delay 10 microseconds.
3270 */
3271 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3272 E1000_WRITE_FLUSH(hw);
3273 udelay(10);
3274 }
3275
3276 /******************************************************************************
3277 * Lowers the Management Data Clock
3278 *
3279 * hw - Struct containing variables accessed by shared code
3280 * ctrl - Device control register's current value
3281 ******************************************************************************/
3282 static void
3283 e1000_lower_mdi_clk(struct e1000_hw *hw,
3284 uint32_t *ctrl)
3285 {
3286 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3287 * bit), and then delay 10 microseconds.
3288 */
3289 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3290 E1000_WRITE_FLUSH(hw);
3291 udelay(10);
3292 }
3293
3294 /******************************************************************************
3295 * Shifts data bits out to the PHY
3296 *
3297 * hw - Struct containing variables accessed by shared code
3298 * data - Data to send out to the PHY
3299 * count - Number of bits to shift out
3300 *
3301 * Bits are shifted out in MSB to LSB order.
3302 ******************************************************************************/
3303 static void
3304 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3305 uint32_t data,
3306 uint16_t count)
3307 {
3308 uint32_t ctrl;
3309 uint32_t mask;
3310
3311 /* We need to shift "count" number of bits out to the PHY. So, the value
3312 * in the "data" parameter will be shifted out to the PHY one bit at a
3313 * time. In order to do this, "data" must be broken down into bits.
3314 */
3315 mask = 0x01;
3316 mask <<= (count - 1);
3317
3318 ctrl = E1000_READ_REG(hw, CTRL);
3319
3320 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3321 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3322
3323 while (mask) {
3324 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3325 * then raising and lowering the Management Data Clock. A "0" is
3326 * shifted out to the PHY by setting the MDIO bit to "0" and then
3327 * raising and lowering the clock.
3328 */
3329 if (data & mask)
3330 ctrl |= E1000_CTRL_MDIO;
3331 else
3332 ctrl &= ~E1000_CTRL_MDIO;
3333
3334 E1000_WRITE_REG(hw, CTRL, ctrl);
3335 E1000_WRITE_FLUSH(hw);
3336
3337 udelay(10);
3338
3339 e1000_raise_mdi_clk(hw, &ctrl);
3340 e1000_lower_mdi_clk(hw, &ctrl);
3341
3342 mask = mask >> 1;
3343 }
3344 }
3345
3346 /******************************************************************************
3347 * Shifts data bits in from the PHY
3348 *
3349 * hw - Struct containing variables accessed by shared code
3350 *
3351 * Bits are shifted in in MSB to LSB order.
3352 ******************************************************************************/
3353 static uint16_t
3354 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3355 {
3356 uint32_t ctrl;
3357 uint16_t data = 0;
3358 uint8_t i;
3359
3360 /* In order to read a register from the PHY, we need to shift in a total
3361 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3362 * to avoid contention on the MDIO pin when a read operation is performed.
3363 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3364 * by raising the input to the Management Data Clock (setting the MDC bit),
3365 * and then reading the value of the MDIO bit.
3366 */
3367 ctrl = E1000_READ_REG(hw, CTRL);
3368
3369 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3370 ctrl &= ~E1000_CTRL_MDIO_DIR;
3371 ctrl &= ~E1000_CTRL_MDIO;
3372
3373 E1000_WRITE_REG(hw, CTRL, ctrl);
3374 E1000_WRITE_FLUSH(hw);
3375
3376 /* Raise and Lower the clock before reading in the data. This accounts for
3377 * the turnaround bits. The first clock occurred when we clocked out the
3378 * last bit of the Register Address.
3379 */
3380 e1000_raise_mdi_clk(hw, &ctrl);
3381 e1000_lower_mdi_clk(hw, &ctrl);
3382
3383 for (data = 0, i = 0; i < 16; i++) {
3384 data = data << 1;
3385 e1000_raise_mdi_clk(hw, &ctrl);
3386 ctrl = E1000_READ_REG(hw, CTRL);
3387 /* Check to see if we shifted in a "1". */
3388 if (ctrl & E1000_CTRL_MDIO)
3389 data |= 1;
3390 e1000_lower_mdi_clk(hw, &ctrl);
3391 }
3392
3393 e1000_raise_mdi_clk(hw, &ctrl);
3394 e1000_lower_mdi_clk(hw, &ctrl);
3395
3396 return data;
3397 }
3398
3399 static int32_t
3400 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3401 {
3402 uint32_t swfw_sync = 0;
3403 uint32_t swmask = mask;
3404 uint32_t fwmask = mask << 16;
3405 int32_t timeout = 200;
3406
3407 DEBUGFUNC("e1000_swfw_sync_acquire");
3408
3409 if (hw->swfwhw_semaphore_present)
3410 return e1000_get_software_flag(hw);
3411
3412 if (!hw->swfw_sync_present)
3413 return e1000_get_hw_eeprom_semaphore(hw);
3414
3415 while (timeout) {
3416 if (e1000_get_hw_eeprom_semaphore(hw))
3417 return -E1000_ERR_SWFW_SYNC;
3418
3419 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3420 if (!(swfw_sync & (fwmask | swmask))) {
3421 break;
3422 }
3423
3424 /* firmware currently using resource (fwmask) */
3425 /* or other software thread currently using resource (swmask) */
3426 e1000_put_hw_eeprom_semaphore(hw);
3427 mdelay(5);
3428 timeout--;
3429 }
3430
3431 if (!timeout) {
3432 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3433 return -E1000_ERR_SWFW_SYNC;
3434 }
3435
3436 swfw_sync |= swmask;
3437 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3438
3439 e1000_put_hw_eeprom_semaphore(hw);
3440 return E1000_SUCCESS;
3441 }
3442
3443 static void
3444 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3445 {
3446 uint32_t swfw_sync;
3447 uint32_t swmask = mask;
3448
3449 DEBUGFUNC("e1000_swfw_sync_release");
3450
3451 if (hw->swfwhw_semaphore_present) {
3452 e1000_release_software_flag(hw);
3453 return;
3454 }
3455
3456 if (!hw->swfw_sync_present) {
3457 e1000_put_hw_eeprom_semaphore(hw);
3458 return;
3459 }
3460
3461 /* if (e1000_get_hw_eeprom_semaphore(hw))
3462 * return -E1000_ERR_SWFW_SYNC; */
3463 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3464 /* empty */
3465
3466 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3467 swfw_sync &= ~swmask;
3468 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3469
3470 e1000_put_hw_eeprom_semaphore(hw);
3471 }
3472
3473 /*****************************************************************************
3474 * Reads the value from a PHY register, if the value is on a specific non zero
3475 * page, sets the page first.
3476 * hw - Struct containing variables accessed by shared code
3477 * reg_addr - address of the PHY register to read
3478 ******************************************************************************/
3479 int32_t
3480 e1000_read_phy_reg(struct e1000_hw *hw,
3481 uint32_t reg_addr,
3482 uint16_t *phy_data)
3483 {
3484 uint32_t ret_val;
3485 uint16_t swfw;
3486
3487 DEBUGFUNC("e1000_read_phy_reg");
3488
3489 if ((hw->mac_type == e1000_80003es2lan) &&
3490 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3491 swfw = E1000_SWFW_PHY1_SM;
3492 } else {
3493 swfw = E1000_SWFW_PHY0_SM;
3494 }
3495 if (e1000_swfw_sync_acquire(hw, swfw))
3496 return -E1000_ERR_SWFW_SYNC;
3497
3498 if ((hw->phy_type == e1000_phy_igp ||
3499 hw->phy_type == e1000_phy_igp_3 ||
3500 hw->phy_type == e1000_phy_igp_2) &&
3501 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3502 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3503 (uint16_t)reg_addr);
3504 if (ret_val) {
3505 e1000_swfw_sync_release(hw, swfw);
3506 return ret_val;
3507 }
3508 } else if (hw->phy_type == e1000_phy_gg82563) {
3509 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3510 (hw->mac_type == e1000_80003es2lan)) {
3511 /* Select Configuration Page */
3512 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3513 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3514 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3515 } else {
3516 /* Use Alternative Page Select register to access
3517 * registers 30 and 31
3518 */
3519 ret_val = e1000_write_phy_reg_ex(hw,
3520 GG82563_PHY_PAGE_SELECT_ALT,
3521 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3522 }
3523
3524 if (ret_val) {
3525 e1000_swfw_sync_release(hw, swfw);
3526 return ret_val;
3527 }
3528 }
3529 }
3530
3531 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3532 phy_data);
3533
3534 e1000_swfw_sync_release(hw, swfw);
3535 return ret_val;
3536 }
3537
3538 static int32_t
3539 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3540 uint16_t *phy_data)
3541 {
3542 uint32_t i;
3543 uint32_t mdic = 0;
3544 const uint32_t phy_addr = 1;
3545
3546 DEBUGFUNC("e1000_read_phy_reg_ex");
3547
3548 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3549 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3550 return -E1000_ERR_PARAM;
3551 }
3552
3553 if (hw->mac_type > e1000_82543) {
3554 /* Set up Op-code, Phy Address, and register address in the MDI
3555 * Control register. The MAC will take care of interfacing with the
3556 * PHY to retrieve the desired data.
3557 */
3558 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3559 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3560 (E1000_MDIC_OP_READ));
3561
3562 E1000_WRITE_REG(hw, MDIC, mdic);
3563
3564 /* Poll the ready bit to see if the MDI read completed */
3565 for (i = 0; i < 64; i++) {
3566 udelay(50);
3567 mdic = E1000_READ_REG(hw, MDIC);
3568 if (mdic & E1000_MDIC_READY) break;
3569 }
3570 if (!(mdic & E1000_MDIC_READY)) {
3571 DEBUGOUT("MDI Read did not complete\n");
3572 return -E1000_ERR_PHY;
3573 }
3574 if (mdic & E1000_MDIC_ERROR) {
3575 DEBUGOUT("MDI Error\n");
3576 return -E1000_ERR_PHY;
3577 }
3578 *phy_data = (uint16_t) mdic;
3579 } else {
3580 /* We must first send a preamble through the MDIO pin to signal the
3581 * beginning of an MII instruction. This is done by sending 32
3582 * consecutive "1" bits.
3583 */
3584 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3585
3586 /* Now combine the next few fields that are required for a read
3587 * operation. We use this method instead of calling the
3588 * e1000_shift_out_mdi_bits routine five different times. The format of
3589 * a MII read instruction consists of a shift out of 14 bits and is
3590 * defined as follows:
3591 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3592 * followed by a shift in of 18 bits. This first two bits shifted in
3593 * are TurnAround bits used to avoid contention on the MDIO pin when a
3594 * READ operation is performed. These two bits are thrown away
3595 * followed by a shift in of 16 bits which contains the desired data.
3596 */
3597 mdic = ((reg_addr) | (phy_addr << 5) |
3598 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3599
3600 e1000_shift_out_mdi_bits(hw, mdic, 14);
3601
3602 /* Now that we've shifted out the read command to the MII, we need to
3603 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3604 * register address.
3605 */
3606 *phy_data = e1000_shift_in_mdi_bits(hw);
3607 }
3608 return E1000_SUCCESS;
3609 }
3610
3611 /******************************************************************************
3612 * Writes a value to a PHY register
3613 *
3614 * hw - Struct containing variables accessed by shared code
3615 * reg_addr - address of the PHY register to write
3616 * data - data to write to the PHY
3617 ******************************************************************************/
3618 int32_t
3619 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3620 uint16_t phy_data)
3621 {
3622 uint32_t ret_val;
3623 uint16_t swfw;
3624
3625 DEBUGFUNC("e1000_write_phy_reg");
3626
3627 if ((hw->mac_type == e1000_80003es2lan) &&
3628 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3629 swfw = E1000_SWFW_PHY1_SM;
3630 } else {
3631 swfw = E1000_SWFW_PHY0_SM;
3632 }
3633 if (e1000_swfw_sync_acquire(hw, swfw))
3634 return -E1000_ERR_SWFW_SYNC;
3635
3636 if ((hw->phy_type == e1000_phy_igp ||
3637 hw->phy_type == e1000_phy_igp_3 ||
3638 hw->phy_type == e1000_phy_igp_2) &&
3639 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3640 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3641 (uint16_t)reg_addr);
3642 if (ret_val) {
3643 e1000_swfw_sync_release(hw, swfw);
3644 return ret_val;
3645 }
3646 } else if (hw->phy_type == e1000_phy_gg82563) {
3647 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3648 (hw->mac_type == e1000_80003es2lan)) {
3649 /* Select Configuration Page */
3650 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3651 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3652 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3653 } else {
3654 /* Use Alternative Page Select register to access
3655 * registers 30 and 31
3656 */
3657 ret_val = e1000_write_phy_reg_ex(hw,
3658 GG82563_PHY_PAGE_SELECT_ALT,
3659 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3660 }
3661
3662 if (ret_val) {
3663 e1000_swfw_sync_release(hw, swfw);
3664 return ret_val;
3665 }
3666 }
3667 }
3668
3669 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3670 phy_data);
3671
3672 e1000_swfw_sync_release(hw, swfw);
3673 return ret_val;
3674 }
3675
3676 static int32_t
3677 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3678 uint16_t phy_data)
3679 {
3680 uint32_t i;
3681 uint32_t mdic = 0;
3682 const uint32_t phy_addr = 1;
3683
3684 DEBUGFUNC("e1000_write_phy_reg_ex");
3685
3686 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3687 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3688 return -E1000_ERR_PARAM;
3689 }
3690
3691 if (hw->mac_type > e1000_82543) {
3692 /* Set up Op-code, Phy Address, register address, and data intended
3693 * for the PHY register in the MDI Control register. The MAC will take
3694 * care of interfacing with the PHY to send the desired data.
3695 */
3696 mdic = (((uint32_t) phy_data) |
3697 (reg_addr << E1000_MDIC_REG_SHIFT) |
3698 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3699 (E1000_MDIC_OP_WRITE));
3700
3701 E1000_WRITE_REG(hw, MDIC, mdic);
3702
3703 /* Poll the ready bit to see if the MDI read completed */
3704 for (i = 0; i < 641; i++) {
3705 udelay(5);
3706 mdic = E1000_READ_REG(hw, MDIC);
3707 if (mdic & E1000_MDIC_READY) break;
3708 }
3709 if (!(mdic & E1000_MDIC_READY)) {
3710 DEBUGOUT("MDI Write did not complete\n");
3711 return -E1000_ERR_PHY;
3712 }
3713 } else {
3714 /* We'll need to use the SW defined pins to shift the write command
3715 * out to the PHY. We first send a preamble to the PHY to signal the
3716 * beginning of the MII instruction. This is done by sending 32
3717 * consecutive "1" bits.
3718 */
3719 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3720
3721 /* Now combine the remaining required fields that will indicate a
3722 * write operation. We use this method instead of calling the
3723 * e1000_shift_out_mdi_bits routine for each field in the command. The
3724 * format of a MII write instruction is as follows:
3725 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3726 */
3727 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3728 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3729 mdic <<= 16;
3730 mdic |= (uint32_t) phy_data;
3731
3732 e1000_shift_out_mdi_bits(hw, mdic, 32);
3733 }
3734
3735 return E1000_SUCCESS;
3736 }
3737
3738 static int32_t
3739 e1000_read_kmrn_reg(struct e1000_hw *hw,
3740 uint32_t reg_addr,
3741 uint16_t *data)
3742 {
3743 uint32_t reg_val;
3744 uint16_t swfw;
3745 DEBUGFUNC("e1000_read_kmrn_reg");
3746
3747 if ((hw->mac_type == e1000_80003es2lan) &&
3748 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3749 swfw = E1000_SWFW_PHY1_SM;
3750 } else {
3751 swfw = E1000_SWFW_PHY0_SM;
3752 }
3753 if (e1000_swfw_sync_acquire(hw, swfw))
3754 return -E1000_ERR_SWFW_SYNC;
3755
3756 /* Write register address */
3757 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3758 E1000_KUMCTRLSTA_OFFSET) |
3759 E1000_KUMCTRLSTA_REN;
3760 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3761 udelay(2);
3762
3763 /* Read the data returned */
3764 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3765 *data = (uint16_t)reg_val;
3766
3767 e1000_swfw_sync_release(hw, swfw);
3768 return E1000_SUCCESS;
3769 }
3770
3771 static int32_t
3772 e1000_write_kmrn_reg(struct e1000_hw *hw,
3773 uint32_t reg_addr,
3774 uint16_t data)
3775 {
3776 uint32_t reg_val;
3777 uint16_t swfw;
3778 DEBUGFUNC("e1000_write_kmrn_reg");
3779
3780 if ((hw->mac_type == e1000_80003es2lan) &&
3781 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3782 swfw = E1000_SWFW_PHY1_SM;
3783 } else {
3784 swfw = E1000_SWFW_PHY0_SM;
3785 }
3786 if (e1000_swfw_sync_acquire(hw, swfw))
3787 return -E1000_ERR_SWFW_SYNC;
3788
3789 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3790 E1000_KUMCTRLSTA_OFFSET) | data;
3791 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3792 udelay(2);
3793
3794 e1000_swfw_sync_release(hw, swfw);
3795 return E1000_SUCCESS;
3796 }
3797
3798 /******************************************************************************
3799 * Returns the PHY to the power-on reset state
3800 *
3801 * hw - Struct containing variables accessed by shared code
3802 ******************************************************************************/
3803 int32_t
3804 e1000_phy_hw_reset(struct e1000_hw *hw)
3805 {
3806 uint32_t ctrl, ctrl_ext;
3807 uint32_t led_ctrl;
3808 int32_t ret_val;
3809 uint16_t swfw;
3810
3811 DEBUGFUNC("e1000_phy_hw_reset");
3812
3813 /* In the case of the phy reset being blocked, it's not an error, we
3814 * simply return success without performing the reset. */
3815 ret_val = e1000_check_phy_reset_block(hw);
3816 if (ret_val)
3817 return E1000_SUCCESS;
3818
3819 DEBUGOUT("Resetting Phy...\n");
3820
3821 if (hw->mac_type > e1000_82543) {
3822 if ((hw->mac_type == e1000_80003es2lan) &&
3823 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3824 swfw = E1000_SWFW_PHY1_SM;
3825 } else {
3826 swfw = E1000_SWFW_PHY0_SM;
3827 }
3828 if (e1000_swfw_sync_acquire(hw, swfw)) {
3829 DEBUGOUT("Unable to acquire swfw sync\n");
3830 return -E1000_ERR_SWFW_SYNC;
3831 }
3832 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3833 * bit. Then, take it out of reset.
3834 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3835 * and deassert. For e1000_82571 hardware and later, we instead delay
3836 * for 50us between and 10ms after the deassertion.
3837 */
3838 ctrl = E1000_READ_REG(hw, CTRL);
3839 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3840 E1000_WRITE_FLUSH(hw);
3841
3842 if (hw->mac_type < e1000_82571)
3843 msleep(10);
3844 else
3845 udelay(100);
3846
3847 E1000_WRITE_REG(hw, CTRL, ctrl);
3848 E1000_WRITE_FLUSH(hw);
3849
3850 if (hw->mac_type >= e1000_82571)
3851 mdelay(10);
3852
3853 e1000_swfw_sync_release(hw, swfw);
3854 } else {
3855 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3856 * bit to put the PHY into reset. Then, take it out of reset.
3857 */
3858 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3859 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3860 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3861 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3862 E1000_WRITE_FLUSH(hw);
3863 msleep(10);
3864 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3865 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3866 E1000_WRITE_FLUSH(hw);
3867 }
3868 udelay(150);
3869
3870 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3871 /* Configure activity LED after PHY reset */
3872 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3873 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3874 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3875 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3876 }
3877
3878 /* Wait for FW to finish PHY configuration. */
3879 ret_val = e1000_get_phy_cfg_done(hw);
3880 if (ret_val != E1000_SUCCESS)
3881 return ret_val;
3882 e1000_release_software_semaphore(hw);
3883
3884 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3885 ret_val = e1000_init_lcd_from_nvm(hw);
3886
3887 return ret_val;
3888 }
3889
3890 /******************************************************************************
3891 * Resets the PHY
3892 *
3893 * hw - Struct containing variables accessed by shared code
3894 *
3895 * Sets bit 15 of the MII Control register
3896 ******************************************************************************/
3897 int32_t
3898 e1000_phy_reset(struct e1000_hw *hw)
3899 {
3900 int32_t ret_val;
3901 uint16_t phy_data;
3902
3903 DEBUGFUNC("e1000_phy_reset");
3904
3905 /* In the case of the phy reset being blocked, it's not an error, we
3906 * simply return success without performing the reset. */
3907 ret_val = e1000_check_phy_reset_block(hw);
3908 if (ret_val)
3909 return E1000_SUCCESS;
3910
3911 switch (hw->phy_type) {
3912 case e1000_phy_igp:
3913 case e1000_phy_igp_2:
3914 case e1000_phy_igp_3:
3915 case e1000_phy_ife:
3916 ret_val = e1000_phy_hw_reset(hw);
3917 if (ret_val)
3918 return ret_val;
3919 break;
3920 default:
3921 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3922 if (ret_val)
3923 return ret_val;
3924
3925 phy_data |= MII_CR_RESET;
3926 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3927 if (ret_val)
3928 return ret_val;
3929
3930 udelay(1);
3931 break;
3932 }
3933
3934 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3935 e1000_phy_init_script(hw);
3936
3937 return E1000_SUCCESS;
3938 }
3939
3940 /******************************************************************************
3941 * Work-around for 82566 power-down: on D3 entry-
3942 * 1) disable gigabit link
3943 * 2) write VR power-down enable
3944 * 3) read it back
3945 * if successful continue, else issue LCD reset and repeat
3946 *
3947 * hw - struct containing variables accessed by shared code
3948 ******************************************************************************/
3949 void
3950 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3951 {
3952 int32_t reg;
3953 uint16_t phy_data;
3954 int32_t retry = 0;
3955
3956 DEBUGFUNC("e1000_phy_powerdown_workaround");
3957
3958 if (hw->phy_type != e1000_phy_igp_3)
3959 return;
3960
3961 do {
3962 /* Disable link */
3963 reg = E1000_READ_REG(hw, PHY_CTRL);
3964 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3965 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3966
3967 /* Write VR power-down enable - bits 9:8 should be 10b */
3968 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3969 phy_data |= (1 << 9);
3970 phy_data &= ~(1 << 8);
3971 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3972
3973 /* Read it back and test */
3974 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3975 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3976 break;
3977
3978 /* Issue PHY reset and repeat at most one more time */
3979 reg = E1000_READ_REG(hw, CTRL);
3980 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3981 retry++;
3982 } while (retry);
3983
3984 return;
3985
3986 }
3987
3988 /******************************************************************************
3989 * Work-around for 82566 Kumeran PCS lock loss:
3990 * On link status change (i.e. PCI reset, speed change) and link is up and
3991 * speed is gigabit-
3992 * 0) if workaround is optionally disabled do nothing
3993 * 1) wait 1ms for Kumeran link to come up
3994 * 2) check Kumeran Diagnostic register PCS lock loss bit
3995 * 3) if not set the link is locked (all is good), otherwise...
3996 * 4) reset the PHY
3997 * 5) repeat up to 10 times
3998 * Note: this is only called for IGP3 copper when speed is 1gb.
3999 *
4000 * hw - struct containing variables accessed by shared code
4001 ******************************************************************************/
4002 static int32_t
4003 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4004 {
4005 int32_t ret_val;
4006 int32_t reg;
4007 int32_t cnt;
4008 uint16_t phy_data;
4009
4010 if (hw->kmrn_lock_loss_workaround_disabled)
4011 return E1000_SUCCESS;
4012
4013 /* Make sure link is up before proceeding. If not just return.
4014 * Attempting this while link is negotiating fouled up link
4015 * stability */
4016 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4017 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4018
4019 if (phy_data & MII_SR_LINK_STATUS) {
4020 for (cnt = 0; cnt < 10; cnt++) {
4021 /* read once to clear */
4022 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4023 if (ret_val)
4024 return ret_val;
4025 /* and again to get new status */
4026 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4027 if (ret_val)
4028 return ret_val;
4029
4030 /* check for PCS lock */
4031 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4032 return E1000_SUCCESS;
4033
4034 /* Issue PHY reset */
4035 e1000_phy_hw_reset(hw);
4036 mdelay(5);
4037 }
4038 /* Disable GigE link negotiation */
4039 reg = E1000_READ_REG(hw, PHY_CTRL);
4040 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4041 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4042
4043 /* unable to acquire PCS lock */
4044 return E1000_ERR_PHY;
4045 }
4046
4047 return E1000_SUCCESS;
4048 }
4049
4050 /******************************************************************************
4051 * Probes the expected PHY address for known PHY IDs
4052 *
4053 * hw - Struct containing variables accessed by shared code
4054 ******************************************************************************/
4055 static int32_t
4056 e1000_detect_gig_phy(struct e1000_hw *hw)
4057 {
4058 int32_t phy_init_status, ret_val;
4059 uint16_t phy_id_high, phy_id_low;
4060 boolean_t match = FALSE;
4061
4062 DEBUGFUNC("e1000_detect_gig_phy");
4063
4064 if (hw->phy_id != 0)
4065 return E1000_SUCCESS;
4066
4067 /* The 82571 firmware may still be configuring the PHY. In this
4068 * case, we cannot access the PHY until the configuration is done. So
4069 * we explicitly set the PHY values. */
4070 if (hw->mac_type == e1000_82571 ||
4071 hw->mac_type == e1000_82572) {
4072 hw->phy_id = IGP01E1000_I_PHY_ID;
4073 hw->phy_type = e1000_phy_igp_2;
4074 return E1000_SUCCESS;
4075 }
4076
4077 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4078 * around that forces PHY page 0 to be set or the reads fail. The rest of
4079 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4080 * So for ESB-2 we need to have this set so our reads won't fail. If the
4081 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4082 * this out as well. */
4083 if (hw->mac_type == e1000_80003es2lan)
4084 hw->phy_type = e1000_phy_gg82563;
4085
4086 /* Read the PHY ID Registers to identify which PHY is onboard. */
4087 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4088 if (ret_val)
4089 return ret_val;
4090
4091 hw->phy_id = (uint32_t) (phy_id_high << 16);
4092 udelay(20);
4093 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4094 if (ret_val)
4095 return ret_val;
4096
4097 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4098 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4099
4100 switch (hw->mac_type) {
4101 case e1000_82543:
4102 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4103 break;
4104 case e1000_82544:
4105 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4106 break;
4107 case e1000_82540:
4108 case e1000_82545:
4109 case e1000_82545_rev_3:
4110 case e1000_82546:
4111 case e1000_82546_rev_3:
4112 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4113 break;
4114 case e1000_82541:
4115 case e1000_82541_rev_2:
4116 case e1000_82547:
4117 case e1000_82547_rev_2:
4118 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4119 break;
4120 case e1000_82573:
4121 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4122 break;
4123 case e1000_80003es2lan:
4124 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4125 break;
4126 case e1000_ich8lan:
4127 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4128 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4129 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4130 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4131 break;
4132 default:
4133 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4134 return -E1000_ERR_CONFIG;
4135 }
4136 phy_init_status = e1000_set_phy_type(hw);
4137
4138 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4139 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4140 return E1000_SUCCESS;
4141 }
4142 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4143 return -E1000_ERR_PHY;
4144 }
4145
4146 /******************************************************************************
4147 * Resets the PHY's DSP
4148 *
4149 * hw - Struct containing variables accessed by shared code
4150 ******************************************************************************/
4151 static int32_t
4152 e1000_phy_reset_dsp(struct e1000_hw *hw)
4153 {
4154 int32_t ret_val;
4155 DEBUGFUNC("e1000_phy_reset_dsp");
4156
4157 do {
4158 if (hw->phy_type != e1000_phy_gg82563) {
4159 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4160 if (ret_val) break;
4161 }
4162 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4163 if (ret_val) break;
4164 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4165 if (ret_val) break;
4166 ret_val = E1000_SUCCESS;
4167 } while (0);
4168
4169 return ret_val;
4170 }
4171
4172 /******************************************************************************
4173 * Get PHY information from various PHY registers for igp PHY only.
4174 *
4175 * hw - Struct containing variables accessed by shared code
4176 * phy_info - PHY information structure
4177 ******************************************************************************/
4178 static int32_t
4179 e1000_phy_igp_get_info(struct e1000_hw *hw,
4180 struct e1000_phy_info *phy_info)
4181 {
4182 int32_t ret_val;
4183 uint16_t phy_data, min_length, max_length, average;
4184 e1000_rev_polarity polarity;
4185
4186 DEBUGFUNC("e1000_phy_igp_get_info");
4187
4188 /* The downshift status is checked only once, after link is established,
4189 * and it stored in the hw->speed_downgraded parameter. */
4190 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4191
4192 /* IGP01E1000 does not need to support it. */
4193 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4194
4195 /* IGP01E1000 always correct polarity reversal */
4196 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4197
4198 /* Check polarity status */
4199 ret_val = e1000_check_polarity(hw, &polarity);
4200 if (ret_val)
4201 return ret_val;
4202
4203 phy_info->cable_polarity = polarity;
4204
4205 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4206 if (ret_val)
4207 return ret_val;
4208
4209 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4210 IGP01E1000_PSSR_MDIX_SHIFT);
4211
4212 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4213 IGP01E1000_PSSR_SPEED_1000MBPS) {
4214 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4215 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4216 if (ret_val)
4217 return ret_val;
4218
4219 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4220 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4221 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4222 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4223 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4224 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4225
4226 /* Get cable length */
4227 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4228 if (ret_val)
4229 return ret_val;
4230
4231 /* Translate to old method */
4232 average = (max_length + min_length) / 2;
4233
4234 if (average <= e1000_igp_cable_length_50)
4235 phy_info->cable_length = e1000_cable_length_50;
4236 else if (average <= e1000_igp_cable_length_80)
4237 phy_info->cable_length = e1000_cable_length_50_80;
4238 else if (average <= e1000_igp_cable_length_110)
4239 phy_info->cable_length = e1000_cable_length_80_110;
4240 else if (average <= e1000_igp_cable_length_140)
4241 phy_info->cable_length = e1000_cable_length_110_140;
4242 else
4243 phy_info->cable_length = e1000_cable_length_140;
4244 }
4245
4246 return E1000_SUCCESS;
4247 }
4248
4249 /******************************************************************************
4250 * Get PHY information from various PHY registers for ife PHY only.
4251 *
4252 * hw - Struct containing variables accessed by shared code
4253 * phy_info - PHY information structure
4254 ******************************************************************************/
4255 static int32_t
4256 e1000_phy_ife_get_info(struct e1000_hw *hw,
4257 struct e1000_phy_info *phy_info)
4258 {
4259 int32_t ret_val;
4260 uint16_t phy_data;
4261 e1000_rev_polarity polarity;
4262
4263 DEBUGFUNC("e1000_phy_ife_get_info");
4264
4265 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4266 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4267
4268 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4269 if (ret_val)
4270 return ret_val;
4271 phy_info->polarity_correction =
4272 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4273 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4274 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4275
4276 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4277 ret_val = e1000_check_polarity(hw, &polarity);
4278 if (ret_val)
4279 return ret_val;
4280 } else {
4281 /* Polarity is forced. */
4282 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4283 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4284 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4285 }
4286 phy_info->cable_polarity = polarity;
4287
4288 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4289 if (ret_val)
4290 return ret_val;
4291
4292 phy_info->mdix_mode = (e1000_auto_x_mode)
4293 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4294 IFE_PMC_MDIX_MODE_SHIFT);
4295
4296 return E1000_SUCCESS;
4297 }
4298
4299 /******************************************************************************
4300 * Get PHY information from various PHY registers fot m88 PHY only.
4301 *
4302 * hw - Struct containing variables accessed by shared code
4303 * phy_info - PHY information structure
4304 ******************************************************************************/
4305 static int32_t
4306 e1000_phy_m88_get_info(struct e1000_hw *hw,
4307 struct e1000_phy_info *phy_info)
4308 {
4309 int32_t ret_val;
4310 uint16_t phy_data;
4311 e1000_rev_polarity polarity;
4312
4313 DEBUGFUNC("e1000_phy_m88_get_info");
4314
4315 /* The downshift status is checked only once, after link is established,
4316 * and it stored in the hw->speed_downgraded parameter. */
4317 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4318
4319 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4320 if (ret_val)
4321 return ret_val;
4322
4323 phy_info->extended_10bt_distance =
4324 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4325 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4326 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4327
4328 phy_info->polarity_correction =
4329 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4330 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4331 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4332
4333 /* Check polarity status */
4334 ret_val = e1000_check_polarity(hw, &polarity);
4335 if (ret_val)
4336 return ret_val;
4337 phy_info->cable_polarity = polarity;
4338
4339 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4340 if (ret_val)
4341 return ret_val;
4342
4343 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4344 M88E1000_PSSR_MDIX_SHIFT);
4345
4346 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4347 /* Cable Length Estimation and Local/Remote Receiver Information
4348 * are only valid at 1000 Mbps.
4349 */
4350 if (hw->phy_type != e1000_phy_gg82563) {
4351 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4352 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4353 } else {
4354 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4355 &phy_data);
4356 if (ret_val)
4357 return ret_val;
4358
4359 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4360 }
4361
4362 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4363 if (ret_val)
4364 return ret_val;
4365
4366 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4367 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4368 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4369 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4370 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4371 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4372
4373 }
4374
4375 return E1000_SUCCESS;
4376 }
4377
4378 /******************************************************************************
4379 * Get PHY information from various PHY registers
4380 *
4381 * hw - Struct containing variables accessed by shared code
4382 * phy_info - PHY information structure
4383 ******************************************************************************/
4384 int32_t
4385 e1000_phy_get_info(struct e1000_hw *hw,
4386 struct e1000_phy_info *phy_info)
4387 {
4388 int32_t ret_val;
4389 uint16_t phy_data;
4390
4391 DEBUGFUNC("e1000_phy_get_info");
4392
4393 phy_info->cable_length = e1000_cable_length_undefined;
4394 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4395 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4396 phy_info->downshift = e1000_downshift_undefined;
4397 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4398 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4399 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4400 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4401
4402 if (hw->media_type != e1000_media_type_copper) {
4403 DEBUGOUT("PHY info is only valid for copper media\n");
4404 return -E1000_ERR_CONFIG;
4405 }
4406
4407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4408 if (ret_val)
4409 return ret_val;
4410
4411 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4412 if (ret_val)
4413 return ret_val;
4414
4415 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4416 DEBUGOUT("PHY info is only valid if link is up\n");
4417 return -E1000_ERR_CONFIG;
4418 }
4419
4420 if (hw->phy_type == e1000_phy_igp ||
4421 hw->phy_type == e1000_phy_igp_3 ||
4422 hw->phy_type == e1000_phy_igp_2)
4423 return e1000_phy_igp_get_info(hw, phy_info);
4424 else if (hw->phy_type == e1000_phy_ife)
4425 return e1000_phy_ife_get_info(hw, phy_info);
4426 else
4427 return e1000_phy_m88_get_info(hw, phy_info);
4428 }
4429
4430 int32_t
4431 e1000_validate_mdi_setting(struct e1000_hw *hw)
4432 {
4433 DEBUGFUNC("e1000_validate_mdi_settings");
4434
4435 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4436 DEBUGOUT("Invalid MDI setting detected\n");
4437 hw->mdix = 1;
4438 return -E1000_ERR_CONFIG;
4439 }
4440 return E1000_SUCCESS;
4441 }
4442
4443
4444 /******************************************************************************
4445 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4446 * is configured. Additionally, if this is ICH8, the flash controller GbE
4447 * registers must be mapped, or this will crash.
4448 *
4449 * hw - Struct containing variables accessed by shared code
4450 *****************************************************************************/
4451 int32_t
4452 e1000_init_eeprom_params(struct e1000_hw *hw)
4453 {
4454 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4455 uint32_t eecd = E1000_READ_REG(hw, EECD);
4456 int32_t ret_val = E1000_SUCCESS;
4457 uint16_t eeprom_size;
4458
4459 DEBUGFUNC("e1000_init_eeprom_params");
4460
4461 switch (hw->mac_type) {
4462 case e1000_82542_rev2_0:
4463 case e1000_82542_rev2_1:
4464 case e1000_82543:
4465 case e1000_82544:
4466 eeprom->type = e1000_eeprom_microwire;
4467 eeprom->word_size = 64;
4468 eeprom->opcode_bits = 3;
4469 eeprom->address_bits = 6;
4470 eeprom->delay_usec = 50;
4471 eeprom->use_eerd = FALSE;
4472 eeprom->use_eewr = FALSE;
4473 break;
4474 case e1000_82540:
4475 case e1000_82545:
4476 case e1000_82545_rev_3:
4477 case e1000_82546:
4478 case e1000_82546_rev_3:
4479 eeprom->type = e1000_eeprom_microwire;
4480 eeprom->opcode_bits = 3;
4481 eeprom->delay_usec = 50;
4482 if (eecd & E1000_EECD_SIZE) {
4483 eeprom->word_size = 256;
4484 eeprom->address_bits = 8;
4485 } else {
4486 eeprom->word_size = 64;
4487 eeprom->address_bits = 6;
4488 }
4489 eeprom->use_eerd = FALSE;
4490 eeprom->use_eewr = FALSE;
4491 break;
4492 case e1000_82541:
4493 case e1000_82541_rev_2:
4494 case e1000_82547:
4495 case e1000_82547_rev_2:
4496 if (eecd & E1000_EECD_TYPE) {
4497 eeprom->type = e1000_eeprom_spi;
4498 eeprom->opcode_bits = 8;
4499 eeprom->delay_usec = 1;
4500 if (eecd & E1000_EECD_ADDR_BITS) {
4501 eeprom->page_size = 32;
4502 eeprom->address_bits = 16;
4503 } else {
4504 eeprom->page_size = 8;
4505 eeprom->address_bits = 8;
4506 }
4507 } else {
4508 eeprom->type = e1000_eeprom_microwire;
4509 eeprom->opcode_bits = 3;
4510 eeprom->delay_usec = 50;
4511 if (eecd & E1000_EECD_ADDR_BITS) {
4512 eeprom->word_size = 256;
4513 eeprom->address_bits = 8;
4514 } else {
4515 eeprom->word_size = 64;
4516 eeprom->address_bits = 6;
4517 }
4518 }
4519 eeprom->use_eerd = FALSE;
4520 eeprom->use_eewr = FALSE;
4521 break;
4522 case e1000_82571:
4523 case e1000_82572:
4524 eeprom->type = e1000_eeprom_spi;
4525 eeprom->opcode_bits = 8;
4526 eeprom->delay_usec = 1;
4527 if (eecd & E1000_EECD_ADDR_BITS) {
4528 eeprom->page_size = 32;
4529 eeprom->address_bits = 16;
4530 } else {
4531 eeprom->page_size = 8;
4532 eeprom->address_bits = 8;
4533 }
4534 eeprom->use_eerd = FALSE;
4535 eeprom->use_eewr = FALSE;
4536 break;
4537 case e1000_82573:
4538 eeprom->type = e1000_eeprom_spi;
4539 eeprom->opcode_bits = 8;
4540 eeprom->delay_usec = 1;
4541 if (eecd & E1000_EECD_ADDR_BITS) {
4542 eeprom->page_size = 32;
4543 eeprom->address_bits = 16;
4544 } else {
4545 eeprom->page_size = 8;
4546 eeprom->address_bits = 8;
4547 }
4548 eeprom->use_eerd = TRUE;
4549 eeprom->use_eewr = TRUE;
4550 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4551 eeprom->type = e1000_eeprom_flash;
4552 eeprom->word_size = 2048;
4553
4554 /* Ensure that the Autonomous FLASH update bit is cleared due to
4555 * Flash update issue on parts which use a FLASH for NVM. */
4556 eecd &= ~E1000_EECD_AUPDEN;
4557 E1000_WRITE_REG(hw, EECD, eecd);
4558 }
4559 break;
4560 case e1000_80003es2lan:
4561 eeprom->type = e1000_eeprom_spi;
4562 eeprom->opcode_bits = 8;
4563 eeprom->delay_usec = 1;
4564 if (eecd & E1000_EECD_ADDR_BITS) {
4565 eeprom->page_size = 32;
4566 eeprom->address_bits = 16;
4567 } else {
4568 eeprom->page_size = 8;
4569 eeprom->address_bits = 8;
4570 }
4571 eeprom->use_eerd = TRUE;
4572 eeprom->use_eewr = FALSE;
4573 break;
4574 case e1000_ich8lan:
4575 {
4576 int32_t i = 0;
4577 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4578
4579 eeprom->type = e1000_eeprom_ich8;
4580 eeprom->use_eerd = FALSE;
4581 eeprom->use_eewr = FALSE;
4582 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4583
4584 /* Zero the shadow RAM structure. But don't load it from NVM
4585 * so as to save time for driver init */
4586 if (hw->eeprom_shadow_ram != NULL) {
4587 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4588 hw->eeprom_shadow_ram[i].modified = FALSE;
4589 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4590 }
4591 }
4592
4593 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4594 ICH_FLASH_SECTOR_SIZE;
4595
4596 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4597 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4598
4599 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4600
4601 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4602
4603 break;
4604 }
4605 default:
4606 break;
4607 }
4608
4609 if (eeprom->type == e1000_eeprom_spi) {
4610 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4611 * 32KB (incremented by powers of 2).
4612 */
4613 if (hw->mac_type <= e1000_82547_rev_2) {
4614 /* Set to default value for initial eeprom read. */
4615 eeprom->word_size = 64;
4616 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4617 if (ret_val)
4618 return ret_val;
4619 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4620 /* 256B eeprom size was not supported in earlier hardware, so we
4621 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4622 * is never the result used in the shifting logic below. */
4623 if (eeprom_size)
4624 eeprom_size++;
4625 } else {
4626 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4627 E1000_EECD_SIZE_EX_SHIFT);
4628 }
4629
4630 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4631 }
4632 return ret_val;
4633 }
4634
4635 /******************************************************************************
4636 * Raises the EEPROM's clock input.
4637 *
4638 * hw - Struct containing variables accessed by shared code
4639 * eecd - EECD's current value
4640 *****************************************************************************/
4641 static void
4642 e1000_raise_ee_clk(struct e1000_hw *hw,
4643 uint32_t *eecd)
4644 {
4645 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4646 * wait <delay> microseconds.
4647 */
4648 *eecd = *eecd | E1000_EECD_SK;
4649 E1000_WRITE_REG(hw, EECD, *eecd);
4650 E1000_WRITE_FLUSH(hw);
4651 udelay(hw->eeprom.delay_usec);
4652 }
4653
4654 /******************************************************************************
4655 * Lowers the EEPROM's clock input.
4656 *
4657 * hw - Struct containing variables accessed by shared code
4658 * eecd - EECD's current value
4659 *****************************************************************************/
4660 static void
4661 e1000_lower_ee_clk(struct e1000_hw *hw,
4662 uint32_t *eecd)
4663 {
4664 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4665 * wait 50 microseconds.
4666 */
4667 *eecd = *eecd & ~E1000_EECD_SK;
4668 E1000_WRITE_REG(hw, EECD, *eecd);
4669 E1000_WRITE_FLUSH(hw);
4670 udelay(hw->eeprom.delay_usec);
4671 }
4672
4673 /******************************************************************************
4674 * Shift data bits out to the EEPROM.
4675 *
4676 * hw - Struct containing variables accessed by shared code
4677 * data - data to send to the EEPROM
4678 * count - number of bits to shift out
4679 *****************************************************************************/
4680 static void
4681 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4682 uint16_t data,
4683 uint16_t count)
4684 {
4685 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4686 uint32_t eecd;
4687 uint32_t mask;
4688
4689 /* We need to shift "count" bits out to the EEPROM. So, value in the
4690 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4691 * In order to do this, "data" must be broken down into bits.
4692 */
4693 mask = 0x01 << (count - 1);
4694 eecd = E1000_READ_REG(hw, EECD);
4695 if (eeprom->type == e1000_eeprom_microwire) {
4696 eecd &= ~E1000_EECD_DO;
4697 } else if (eeprom->type == e1000_eeprom_spi) {
4698 eecd |= E1000_EECD_DO;
4699 }
4700 do {
4701 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4702 * and then raising and then lowering the clock (the SK bit controls
4703 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4704 * by setting "DI" to "0" and then raising and then lowering the clock.
4705 */
4706 eecd &= ~E1000_EECD_DI;
4707
4708 if (data & mask)
4709 eecd |= E1000_EECD_DI;
4710
4711 E1000_WRITE_REG(hw, EECD, eecd);
4712 E1000_WRITE_FLUSH(hw);
4713
4714 udelay(eeprom->delay_usec);
4715
4716 e1000_raise_ee_clk(hw, &eecd);
4717 e1000_lower_ee_clk(hw, &eecd);
4718
4719 mask = mask >> 1;
4720
4721 } while (mask);
4722
4723 /* We leave the "DI" bit set to "0" when we leave this routine. */
4724 eecd &= ~E1000_EECD_DI;
4725 E1000_WRITE_REG(hw, EECD, eecd);
4726 }
4727
4728 /******************************************************************************
4729 * Shift data bits in from the EEPROM
4730 *
4731 * hw - Struct containing variables accessed by shared code
4732 *****************************************************************************/
4733 static uint16_t
4734 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4735 uint16_t count)
4736 {
4737 uint32_t eecd;
4738 uint32_t i;
4739 uint16_t data;
4740
4741 /* In order to read a register from the EEPROM, we need to shift 'count'
4742 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4743 * input to the EEPROM (setting the SK bit), and then reading the value of
4744 * the "DO" bit. During this "shifting in" process the "DI" bit should
4745 * always be clear.
4746 */
4747
4748 eecd = E1000_READ_REG(hw, EECD);
4749
4750 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4751 data = 0;
4752
4753 for (i = 0; i < count; i++) {
4754 data = data << 1;
4755 e1000_raise_ee_clk(hw, &eecd);
4756
4757 eecd = E1000_READ_REG(hw, EECD);
4758
4759 eecd &= ~(E1000_EECD_DI);
4760 if (eecd & E1000_EECD_DO)
4761 data |= 1;
4762
4763 e1000_lower_ee_clk(hw, &eecd);
4764 }
4765
4766 return data;
4767 }
4768
4769 /******************************************************************************
4770 * Prepares EEPROM for access
4771 *
4772 * hw - Struct containing variables accessed by shared code
4773 *
4774 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4775 * function should be called before issuing a command to the EEPROM.
4776 *****************************************************************************/
4777 static int32_t
4778 e1000_acquire_eeprom(struct e1000_hw *hw)
4779 {
4780 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4781 uint32_t eecd, i=0;
4782
4783 DEBUGFUNC("e1000_acquire_eeprom");
4784
4785 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4786 return -E1000_ERR_SWFW_SYNC;
4787 eecd = E1000_READ_REG(hw, EECD);
4788
4789 if (hw->mac_type != e1000_82573) {
4790 /* Request EEPROM Access */
4791 if (hw->mac_type > e1000_82544) {
4792 eecd |= E1000_EECD_REQ;
4793 E1000_WRITE_REG(hw, EECD, eecd);
4794 eecd = E1000_READ_REG(hw, EECD);
4795 while ((!(eecd & E1000_EECD_GNT)) &&
4796 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4797 i++;
4798 udelay(5);
4799 eecd = E1000_READ_REG(hw, EECD);
4800 }
4801 if (!(eecd & E1000_EECD_GNT)) {
4802 eecd &= ~E1000_EECD_REQ;
4803 E1000_WRITE_REG(hw, EECD, eecd);
4804 DEBUGOUT("Could not acquire EEPROM grant\n");
4805 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4806 return -E1000_ERR_EEPROM;
4807 }
4808 }
4809 }
4810
4811 /* Setup EEPROM for Read/Write */
4812
4813 if (eeprom->type == e1000_eeprom_microwire) {
4814 /* Clear SK and DI */
4815 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4816 E1000_WRITE_REG(hw, EECD, eecd);
4817
4818 /* Set CS */
4819 eecd |= E1000_EECD_CS;
4820 E1000_WRITE_REG(hw, EECD, eecd);
4821 } else if (eeprom->type == e1000_eeprom_spi) {
4822 /* Clear SK and CS */
4823 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4824 E1000_WRITE_REG(hw, EECD, eecd);
4825 udelay(1);
4826 }
4827
4828 return E1000_SUCCESS;
4829 }
4830
4831 /******************************************************************************
4832 * Returns EEPROM to a "standby" state
4833 *
4834 * hw - Struct containing variables accessed by shared code
4835 *****************************************************************************/
4836 static void
4837 e1000_standby_eeprom(struct e1000_hw *hw)
4838 {
4839 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4840 uint32_t eecd;
4841
4842 eecd = E1000_READ_REG(hw, EECD);
4843
4844 if (eeprom->type == e1000_eeprom_microwire) {
4845 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4846 E1000_WRITE_REG(hw, EECD, eecd);
4847 E1000_WRITE_FLUSH(hw);
4848 udelay(eeprom->delay_usec);
4849
4850 /* Clock high */
4851 eecd |= E1000_EECD_SK;
4852 E1000_WRITE_REG(hw, EECD, eecd);
4853 E1000_WRITE_FLUSH(hw);
4854 udelay(eeprom->delay_usec);
4855
4856 /* Select EEPROM */
4857 eecd |= E1000_EECD_CS;
4858 E1000_WRITE_REG(hw, EECD, eecd);
4859 E1000_WRITE_FLUSH(hw);
4860 udelay(eeprom->delay_usec);
4861
4862 /* Clock low */
4863 eecd &= ~E1000_EECD_SK;
4864 E1000_WRITE_REG(hw, EECD, eecd);
4865 E1000_WRITE_FLUSH(hw);
4866 udelay(eeprom->delay_usec);
4867 } else if (eeprom->type == e1000_eeprom_spi) {
4868 /* Toggle CS to flush commands */
4869 eecd |= E1000_EECD_CS;
4870 E1000_WRITE_REG(hw, EECD, eecd);
4871 E1000_WRITE_FLUSH(hw);
4872 udelay(eeprom->delay_usec);
4873 eecd &= ~E1000_EECD_CS;
4874 E1000_WRITE_REG(hw, EECD, eecd);
4875 E1000_WRITE_FLUSH(hw);
4876 udelay(eeprom->delay_usec);
4877 }
4878 }
4879
4880 /******************************************************************************
4881 * Terminates a command by inverting the EEPROM's chip select pin
4882 *
4883 * hw - Struct containing variables accessed by shared code
4884 *****************************************************************************/
4885 static void
4886 e1000_release_eeprom(struct e1000_hw *hw)
4887 {
4888 uint32_t eecd;
4889
4890 DEBUGFUNC("e1000_release_eeprom");
4891
4892 eecd = E1000_READ_REG(hw, EECD);
4893
4894 if (hw->eeprom.type == e1000_eeprom_spi) {
4895 eecd |= E1000_EECD_CS; /* Pull CS high */
4896 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4897
4898 E1000_WRITE_REG(hw, EECD, eecd);
4899
4900 udelay(hw->eeprom.delay_usec);
4901 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4902 /* cleanup eeprom */
4903
4904 /* CS on Microwire is active-high */
4905 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4906
4907 E1000_WRITE_REG(hw, EECD, eecd);
4908
4909 /* Rising edge of clock */
4910 eecd |= E1000_EECD_SK;
4911 E1000_WRITE_REG(hw, EECD, eecd);
4912 E1000_WRITE_FLUSH(hw);
4913 udelay(hw->eeprom.delay_usec);
4914
4915 /* Falling edge of clock */
4916 eecd &= ~E1000_EECD_SK;
4917 E1000_WRITE_REG(hw, EECD, eecd);
4918 E1000_WRITE_FLUSH(hw);
4919 udelay(hw->eeprom.delay_usec);
4920 }
4921
4922 /* Stop requesting EEPROM access */
4923 if (hw->mac_type > e1000_82544) {
4924 eecd &= ~E1000_EECD_REQ;
4925 E1000_WRITE_REG(hw, EECD, eecd);
4926 }
4927
4928 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4929 }
4930
4931 /******************************************************************************
4932 * Reads a 16 bit word from the EEPROM.
4933 *
4934 * hw - Struct containing variables accessed by shared code
4935 *****************************************************************************/
4936 static int32_t
4937 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4938 {
4939 uint16_t retry_count = 0;
4940 uint8_t spi_stat_reg;
4941
4942 DEBUGFUNC("e1000_spi_eeprom_ready");
4943
4944 /* Read "Status Register" repeatedly until the LSB is cleared. The
4945 * EEPROM will signal that the command has been completed by clearing
4946 * bit 0 of the internal status register. If it's not cleared within
4947 * 5 milliseconds, then error out.
4948 */
4949 retry_count = 0;
4950 do {
4951 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4952 hw->eeprom.opcode_bits);
4953 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4954 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4955 break;
4956
4957 udelay(5);
4958 retry_count += 5;
4959
4960 e1000_standby_eeprom(hw);
4961 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4962
4963 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4964 * only 0-5mSec on 5V devices)
4965 */
4966 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4967 DEBUGOUT("SPI EEPROM Status error\n");
4968 return -E1000_ERR_EEPROM;
4969 }
4970
4971 return E1000_SUCCESS;
4972 }
4973
4974 /******************************************************************************
4975 * Reads a 16 bit word from the EEPROM.
4976 *
4977 * hw - Struct containing variables accessed by shared code
4978 * offset - offset of word in the EEPROM to read
4979 * data - word read from the EEPROM
4980 * words - number of words to read
4981 *****************************************************************************/
4982 int32_t
4983 e1000_read_eeprom(struct e1000_hw *hw,
4984 uint16_t offset,
4985 uint16_t words,
4986 uint16_t *data)
4987 {
4988 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4989 uint32_t i = 0;
4990
4991 DEBUGFUNC("e1000_read_eeprom");
4992
4993 /* If eeprom is not yet detected, do so now */
4994 if (eeprom->word_size == 0)
4995 e1000_init_eeprom_params(hw);
4996
4997 /* A check for invalid values: offset too large, too many words, and not
4998 * enough words.
4999 */
5000 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5001 (words == 0)) {
5002 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
5003 return -E1000_ERR_EEPROM;
5004 }
5005
5006 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
5007 * directly. In this case, we need to acquire the EEPROM so that
5008 * FW or other port software does not interrupt.
5009 */
5010 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
5011 hw->eeprom.use_eerd == FALSE) {
5012 /* Prepare the EEPROM for bit-bang reading */
5013 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5014 return -E1000_ERR_EEPROM;
5015 }
5016
5017 /* Eerd register EEPROM access requires no eeprom aquire/release */
5018 if (eeprom->use_eerd == TRUE)
5019 return e1000_read_eeprom_eerd(hw, offset, words, data);
5020
5021 /* ICH EEPROM access is done via the ICH flash controller */
5022 if (eeprom->type == e1000_eeprom_ich8)
5023 return e1000_read_eeprom_ich8(hw, offset, words, data);
5024
5025 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5026 * acquired the EEPROM at this point, so any returns should relase it */
5027 if (eeprom->type == e1000_eeprom_spi) {
5028 uint16_t word_in;
5029 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5030
5031 if (e1000_spi_eeprom_ready(hw)) {
5032 e1000_release_eeprom(hw);
5033 return -E1000_ERR_EEPROM;
5034 }
5035
5036 e1000_standby_eeprom(hw);
5037
5038 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5039 if ((eeprom->address_bits == 8) && (offset >= 128))
5040 read_opcode |= EEPROM_A8_OPCODE_SPI;
5041
5042 /* Send the READ command (opcode + addr) */
5043 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5044 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5045
5046 /* Read the data. The address of the eeprom internally increments with
5047 * each byte (spi) being read, saving on the overhead of eeprom setup
5048 * and tear-down. The address counter will roll over if reading beyond
5049 * the size of the eeprom, thus allowing the entire memory to be read
5050 * starting from any offset. */
5051 for (i = 0; i < words; i++) {
5052 word_in = e1000_shift_in_ee_bits(hw, 16);
5053 data[i] = (word_in >> 8) | (word_in << 8);
5054 }
5055 } else if (eeprom->type == e1000_eeprom_microwire) {
5056 for (i = 0; i < words; i++) {
5057 /* Send the READ command (opcode + addr) */
5058 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5059 eeprom->opcode_bits);
5060 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5061 eeprom->address_bits);
5062
5063 /* Read the data. For microwire, each word requires the overhead
5064 * of eeprom setup and tear-down. */
5065 data[i] = e1000_shift_in_ee_bits(hw, 16);
5066 e1000_standby_eeprom(hw);
5067 }
5068 }
5069
5070 /* End this read operation */
5071 e1000_release_eeprom(hw);
5072
5073 return E1000_SUCCESS;
5074 }
5075
5076 /******************************************************************************
5077 * Reads a 16 bit word from the EEPROM using the EERD register.
5078 *
5079 * hw - Struct containing variables accessed by shared code
5080 * offset - offset of word in the EEPROM to read
5081 * data - word read from the EEPROM
5082 * words - number of words to read
5083 *****************************************************************************/
5084 static int32_t
5085 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5086 uint16_t offset,
5087 uint16_t words,
5088 uint16_t *data)
5089 {
5090 uint32_t i, eerd = 0;
5091 int32_t error = 0;
5092
5093 for (i = 0; i < words; i++) {
5094 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5095 E1000_EEPROM_RW_REG_START;
5096
5097 E1000_WRITE_REG(hw, EERD, eerd);
5098 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5099
5100 if (error) {
5101 break;
5102 }
5103 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5104
5105 }
5106
5107 return error;
5108 }
5109
5110 /******************************************************************************
5111 * Writes a 16 bit word from the EEPROM using the EEWR register.
5112 *
5113 * hw - Struct containing variables accessed by shared code
5114 * offset - offset of word in the EEPROM to read
5115 * data - word read from the EEPROM
5116 * words - number of words to read
5117 *****************************************************************************/
5118 static int32_t
5119 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5120 uint16_t offset,
5121 uint16_t words,
5122 uint16_t *data)
5123 {
5124 uint32_t register_value = 0;
5125 uint32_t i = 0;
5126 int32_t error = 0;
5127
5128 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5129 return -E1000_ERR_SWFW_SYNC;
5130
5131 for (i = 0; i < words; i++) {
5132 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5133 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5134 E1000_EEPROM_RW_REG_START;
5135
5136 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5137 if (error) {
5138 break;
5139 }
5140
5141 E1000_WRITE_REG(hw, EEWR, register_value);
5142
5143 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5144
5145 if (error) {
5146 break;
5147 }
5148 }
5149
5150 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5151 return error;
5152 }
5153
5154 /******************************************************************************
5155 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5156 *
5157 * hw - Struct containing variables accessed by shared code
5158 *****************************************************************************/
5159 static int32_t
5160 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5161 {
5162 uint32_t attempts = 100000;
5163 uint32_t i, reg = 0;
5164 int32_t done = E1000_ERR_EEPROM;
5165
5166 for (i = 0; i < attempts; i++) {
5167 if (eerd == E1000_EEPROM_POLL_READ)
5168 reg = E1000_READ_REG(hw, EERD);
5169 else
5170 reg = E1000_READ_REG(hw, EEWR);
5171
5172 if (reg & E1000_EEPROM_RW_REG_DONE) {
5173 done = E1000_SUCCESS;
5174 break;
5175 }
5176 udelay(5);
5177 }
5178
5179 return done;
5180 }
5181
5182 /***************************************************************************
5183 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5184 *
5185 * hw - Struct containing variables accessed by shared code
5186 ****************************************************************************/
5187 static boolean_t
5188 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5189 {
5190 uint32_t eecd = 0;
5191
5192 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5193
5194 if (hw->mac_type == e1000_ich8lan)
5195 return FALSE;
5196
5197 if (hw->mac_type == e1000_82573) {
5198 eecd = E1000_READ_REG(hw, EECD);
5199
5200 /* Isolate bits 15 & 16 */
5201 eecd = ((eecd >> 15) & 0x03);
5202
5203 /* If both bits are set, device is Flash type */
5204 if (eecd == 0x03) {
5205 return FALSE;
5206 }
5207 }
5208 return TRUE;
5209 }
5210
5211 /******************************************************************************
5212 * Verifies that the EEPROM has a valid checksum
5213 *
5214 * hw - Struct containing variables accessed by shared code
5215 *
5216 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5217 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5218 * valid.
5219 *****************************************************************************/
5220 int32_t
5221 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5222 {
5223 uint16_t checksum = 0;
5224 uint16_t i, eeprom_data;
5225
5226 DEBUGFUNC("e1000_validate_eeprom_checksum");
5227
5228 if ((hw->mac_type == e1000_82573) &&
5229 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5230 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5231 * 10h-12h. Checksum may need to be fixed. */
5232 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5233 if ((eeprom_data & 0x10) == 0) {
5234 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5235 * has already been fixed. If the checksum is still wrong and this
5236 * bit is a 1, we need to return bad checksum. Otherwise, we need
5237 * to set this bit to a 1 and update the checksum. */
5238 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5239 if ((eeprom_data & 0x8000) == 0) {
5240 eeprom_data |= 0x8000;
5241 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5242 e1000_update_eeprom_checksum(hw);
5243 }
5244 }
5245 }
5246
5247 if (hw->mac_type == e1000_ich8lan) {
5248 /* Drivers must allocate the shadow ram structure for the
5249 * EEPROM checksum to be updated. Otherwise, this bit as well
5250 * as the checksum must both be set correctly for this
5251 * validation to pass.
5252 */
5253 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5254 if ((eeprom_data & 0x40) == 0) {
5255 eeprom_data |= 0x40;
5256 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5257 e1000_update_eeprom_checksum(hw);
5258 }
5259 }
5260
5261 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5262 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5263 DEBUGOUT("EEPROM Read Error\n");
5264 return -E1000_ERR_EEPROM;
5265 }
5266 checksum += eeprom_data;
5267 }
5268
5269 if (checksum == (uint16_t) EEPROM_SUM)
5270 return E1000_SUCCESS;
5271 else {
5272 DEBUGOUT("EEPROM Checksum Invalid\n");
5273 return -E1000_ERR_EEPROM;
5274 }
5275 }
5276
5277 /******************************************************************************
5278 * Calculates the EEPROM checksum and writes it to the EEPROM
5279 *
5280 * hw - Struct containing variables accessed by shared code
5281 *
5282 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5283 * Writes the difference to word offset 63 of the EEPROM.
5284 *****************************************************************************/
5285 int32_t
5286 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5287 {
5288 uint32_t ctrl_ext;
5289 uint16_t checksum = 0;
5290 uint16_t i, eeprom_data;
5291
5292 DEBUGFUNC("e1000_update_eeprom_checksum");
5293
5294 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5295 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5296 DEBUGOUT("EEPROM Read Error\n");
5297 return -E1000_ERR_EEPROM;
5298 }
5299 checksum += eeprom_data;
5300 }
5301 checksum = (uint16_t) EEPROM_SUM - checksum;
5302 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5303 DEBUGOUT("EEPROM Write Error\n");
5304 return -E1000_ERR_EEPROM;
5305 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5306 e1000_commit_shadow_ram(hw);
5307 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5308 e1000_commit_shadow_ram(hw);
5309 /* Reload the EEPROM, or else modifications will not appear
5310 * until after next adapter reset. */
5311 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5312 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5313 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5314 msleep(10);
5315 }
5316 return E1000_SUCCESS;
5317 }
5318
5319 /******************************************************************************
5320 * Parent function for writing words to the different EEPROM types.
5321 *
5322 * hw - Struct containing variables accessed by shared code
5323 * offset - offset within the EEPROM to be written to
5324 * words - number of words to write
5325 * data - 16 bit word to be written to the EEPROM
5326 *
5327 * If e1000_update_eeprom_checksum is not called after this function, the
5328 * EEPROM will most likely contain an invalid checksum.
5329 *****************************************************************************/
5330 int32_t
5331 e1000_write_eeprom(struct e1000_hw *hw,
5332 uint16_t offset,
5333 uint16_t words,
5334 uint16_t *data)
5335 {
5336 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5337 int32_t status = 0;
5338
5339 DEBUGFUNC("e1000_write_eeprom");
5340
5341 /* If eeprom is not yet detected, do so now */
5342 if (eeprom->word_size == 0)
5343 e1000_init_eeprom_params(hw);
5344
5345 /* A check for invalid values: offset too large, too many words, and not
5346 * enough words.
5347 */
5348 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5349 (words == 0)) {
5350 DEBUGOUT("\"words\" parameter out of bounds\n");
5351 return -E1000_ERR_EEPROM;
5352 }
5353
5354 /* 82573 writes only through eewr */
5355 if (eeprom->use_eewr == TRUE)
5356 return e1000_write_eeprom_eewr(hw, offset, words, data);
5357
5358 if (eeprom->type == e1000_eeprom_ich8)
5359 return e1000_write_eeprom_ich8(hw, offset, words, data);
5360
5361 /* Prepare the EEPROM for writing */
5362 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5363 return -E1000_ERR_EEPROM;
5364
5365 if (eeprom->type == e1000_eeprom_microwire) {
5366 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5367 } else {
5368 status = e1000_write_eeprom_spi(hw, offset, words, data);
5369 msleep(10);
5370 }
5371
5372 /* Done with writing */
5373 e1000_release_eeprom(hw);
5374
5375 return status;
5376 }
5377
5378 /******************************************************************************
5379 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5380 *
5381 * hw - Struct containing variables accessed by shared code
5382 * offset - offset within the EEPROM to be written to
5383 * words - number of words to write
5384 * data - pointer to array of 8 bit words to be written to the EEPROM
5385 *
5386 *****************************************************************************/
5387 static int32_t
5388 e1000_write_eeprom_spi(struct e1000_hw *hw,
5389 uint16_t offset,
5390 uint16_t words,
5391 uint16_t *data)
5392 {
5393 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5394 uint16_t widx = 0;
5395
5396 DEBUGFUNC("e1000_write_eeprom_spi");
5397
5398 while (widx < words) {
5399 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5400
5401 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5402
5403 e1000_standby_eeprom(hw);
5404
5405 /* Send the WRITE ENABLE command (8 bit opcode ) */
5406 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5407 eeprom->opcode_bits);
5408
5409 e1000_standby_eeprom(hw);
5410
5411 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5412 if ((eeprom->address_bits == 8) && (offset >= 128))
5413 write_opcode |= EEPROM_A8_OPCODE_SPI;
5414
5415 /* Send the Write command (8-bit opcode + addr) */
5416 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5417
5418 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5419 eeprom->address_bits);
5420
5421 /* Send the data */
5422
5423 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5424 while (widx < words) {
5425 uint16_t word_out = data[widx];
5426 word_out = (word_out >> 8) | (word_out << 8);
5427 e1000_shift_out_ee_bits(hw, word_out, 16);
5428 widx++;
5429
5430 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5431 * operation, while the smaller eeproms are capable of an 8-byte
5432 * PAGE WRITE operation. Break the inner loop to pass new address
5433 */
5434 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5435 e1000_standby_eeprom(hw);
5436 break;
5437 }
5438 }
5439 }
5440
5441 return E1000_SUCCESS;
5442 }
5443
5444 /******************************************************************************
5445 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5446 *
5447 * hw - Struct containing variables accessed by shared code
5448 * offset - offset within the EEPROM to be written to
5449 * words - number of words to write
5450 * data - pointer to array of 16 bit words to be written to the EEPROM
5451 *
5452 *****************************************************************************/
5453 static int32_t
5454 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5455 uint16_t offset,
5456 uint16_t words,
5457 uint16_t *data)
5458 {
5459 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5460 uint32_t eecd;
5461 uint16_t words_written = 0;
5462 uint16_t i = 0;
5463
5464 DEBUGFUNC("e1000_write_eeprom_microwire");
5465
5466 /* Send the write enable command to the EEPROM (3-bit opcode plus
5467 * 6/8-bit dummy address beginning with 11). It's less work to include
5468 * the 11 of the dummy address as part of the opcode than it is to shift
5469 * it over the correct number of bits for the address. This puts the
5470 * EEPROM into write/erase mode.
5471 */
5472 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5473 (uint16_t)(eeprom->opcode_bits + 2));
5474
5475 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5476
5477 /* Prepare the EEPROM */
5478 e1000_standby_eeprom(hw);
5479
5480 while (words_written < words) {
5481 /* Send the Write command (3-bit opcode + addr) */
5482 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5483 eeprom->opcode_bits);
5484
5485 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5486 eeprom->address_bits);
5487
5488 /* Send the data */
5489 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5490
5491 /* Toggle the CS line. This in effect tells the EEPROM to execute
5492 * the previous command.
5493 */
5494 e1000_standby_eeprom(hw);
5495
5496 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5497 * signal that the command has been completed by raising the DO signal.
5498 * If DO does not go high in 10 milliseconds, then error out.
5499 */
5500 for (i = 0; i < 200; i++) {
5501 eecd = E1000_READ_REG(hw, EECD);
5502 if (eecd & E1000_EECD_DO) break;
5503 udelay(50);
5504 }
5505 if (i == 200) {
5506 DEBUGOUT("EEPROM Write did not complete\n");
5507 return -E1000_ERR_EEPROM;
5508 }
5509
5510 /* Recover from write */
5511 e1000_standby_eeprom(hw);
5512
5513 words_written++;
5514 }
5515
5516 /* Send the write disable command to the EEPROM (3-bit opcode plus
5517 * 6/8-bit dummy address beginning with 10). It's less work to include
5518 * the 10 of the dummy address as part of the opcode than it is to shift
5519 * it over the correct number of bits for the address. This takes the
5520 * EEPROM out of write/erase mode.
5521 */
5522 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5523 (uint16_t)(eeprom->opcode_bits + 2));
5524
5525 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5526
5527 return E1000_SUCCESS;
5528 }
5529
5530 /******************************************************************************
5531 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5532 * in the eeprom cache and the non modified values in the currently active bank
5533 * to the new bank.
5534 *
5535 * hw - Struct containing variables accessed by shared code
5536 * offset - offset of word in the EEPROM to read
5537 * data - word read from the EEPROM
5538 * words - number of words to read
5539 *****************************************************************************/
5540 static int32_t
5541 e1000_commit_shadow_ram(struct e1000_hw *hw)
5542 {
5543 uint32_t attempts = 100000;
5544 uint32_t eecd = 0;
5545 uint32_t flop = 0;
5546 uint32_t i = 0;
5547 int32_t error = E1000_SUCCESS;
5548 uint32_t old_bank_offset = 0;
5549 uint32_t new_bank_offset = 0;
5550 uint8_t low_byte = 0;
5551 uint8_t high_byte = 0;
5552 boolean_t sector_write_failed = FALSE;
5553
5554 if (hw->mac_type == e1000_82573) {
5555 /* The flop register will be used to determine if flash type is STM */
5556 flop = E1000_READ_REG(hw, FLOP);
5557 for (i=0; i < attempts; i++) {
5558 eecd = E1000_READ_REG(hw, EECD);
5559 if ((eecd & E1000_EECD_FLUPD) == 0) {
5560 break;
5561 }
5562 udelay(5);
5563 }
5564
5565 if (i == attempts) {
5566 return -E1000_ERR_EEPROM;
5567 }
5568
5569 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5570 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5571 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5572 }
5573
5574 /* Perform the flash update */
5575 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5576
5577 for (i=0; i < attempts; i++) {
5578 eecd = E1000_READ_REG(hw, EECD);
5579 if ((eecd & E1000_EECD_FLUPD) == 0) {
5580 break;
5581 }
5582 udelay(5);
5583 }
5584
5585 if (i == attempts) {
5586 return -E1000_ERR_EEPROM;
5587 }
5588 }
5589
5590 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5591 /* We're writing to the opposite bank so if we're on bank 1,
5592 * write to bank 0 etc. We also need to erase the segment that
5593 * is going to be written */
5594 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5595 new_bank_offset = hw->flash_bank_size * 2;
5596 old_bank_offset = 0;
5597 e1000_erase_ich8_4k_segment(hw, 1);
5598 } else {
5599 old_bank_offset = hw->flash_bank_size * 2;
5600 new_bank_offset = 0;
5601 e1000_erase_ich8_4k_segment(hw, 0);
5602 }
5603
5604 sector_write_failed = FALSE;
5605 /* Loop for every byte in the shadow RAM,
5606 * which is in units of words. */
5607 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5608 /* Determine whether to write the value stored
5609 * in the other NVM bank or a modified value stored
5610 * in the shadow RAM */
5611 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5612 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5613 udelay(100);
5614 error = e1000_verify_write_ich8_byte(hw,
5615 (i << 1) + new_bank_offset, low_byte);
5616
5617 if (error != E1000_SUCCESS)
5618 sector_write_failed = TRUE;
5619 else {
5620 high_byte =
5621 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5622 udelay(100);
5623 }
5624 } else {
5625 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5626 &low_byte);
5627 udelay(100);
5628 error = e1000_verify_write_ich8_byte(hw,
5629 (i << 1) + new_bank_offset, low_byte);
5630
5631 if (error != E1000_SUCCESS)
5632 sector_write_failed = TRUE;
5633 else {
5634 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5635 &high_byte);
5636 udelay(100);
5637 }
5638 }
5639
5640 /* If the write of the low byte was successful, go ahread and
5641 * write the high byte while checking to make sure that if it
5642 * is the signature byte, then it is handled properly */
5643 if (sector_write_failed == FALSE) {
5644 /* If the word is 0x13, then make sure the signature bits
5645 * (15:14) are 11b until the commit has completed.
5646 * This will allow us to write 10b which indicates the
5647 * signature is valid. We want to do this after the write
5648 * has completed so that we don't mark the segment valid
5649 * while the write is still in progress */
5650 if (i == E1000_ICH_NVM_SIG_WORD)
5651 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5652
5653 error = e1000_verify_write_ich8_byte(hw,
5654 (i << 1) + new_bank_offset + 1, high_byte);
5655 if (error != E1000_SUCCESS)
5656 sector_write_failed = TRUE;
5657
5658 } else {
5659 /* If the write failed then break from the loop and
5660 * return an error */
5661 break;
5662 }
5663 }
5664
5665 /* Don't bother writing the segment valid bits if sector
5666 * programming failed. */
5667 if (sector_write_failed == FALSE) {
5668 /* Finally validate the new segment by setting bit 15:14
5669 * to 10b in word 0x13 , this can be done without an
5670 * erase as well since these bits are 11 to start with
5671 * and we need to change bit 14 to 0b */
5672 e1000_read_ich8_byte(hw,
5673 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5674 &high_byte);
5675 high_byte &= 0xBF;
5676 error = e1000_verify_write_ich8_byte(hw,
5677 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5678 /* And invalidate the previously valid segment by setting
5679 * its signature word (0x13) high_byte to 0b. This can be
5680 * done without an erase because flash erase sets all bits
5681 * to 1's. We can write 1's to 0's without an erase */
5682 if (error == E1000_SUCCESS) {
5683 error = e1000_verify_write_ich8_byte(hw,
5684 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5685 }
5686
5687 /* Clear the now not used entry in the cache */
5688 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5689 hw->eeprom_shadow_ram[i].modified = FALSE;
5690 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5691 }
5692 }
5693 }
5694
5695 return error;
5696 }
5697
5698 /******************************************************************************
5699 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5700 * second function of dual function devices
5701 *
5702 * hw - Struct containing variables accessed by shared code
5703 *****************************************************************************/
5704 int32_t
5705 e1000_read_mac_addr(struct e1000_hw * hw)
5706 {
5707 uint16_t offset;
5708 uint16_t eeprom_data, i;
5709
5710 DEBUGFUNC("e1000_read_mac_addr");
5711
5712 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5713 offset = i >> 1;
5714 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5715 DEBUGOUT("EEPROM Read Error\n");
5716 return -E1000_ERR_EEPROM;
5717 }
5718 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5719 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5720 }
5721
5722 switch (hw->mac_type) {
5723 default:
5724 break;
5725 case e1000_82546:
5726 case e1000_82546_rev_3:
5727 case e1000_82571:
5728 case e1000_80003es2lan:
5729 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5730 hw->perm_mac_addr[5] ^= 0x01;
5731 break;
5732 }
5733
5734 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5735 hw->mac_addr[i] = hw->perm_mac_addr[i];
5736 return E1000_SUCCESS;
5737 }
5738
5739 /******************************************************************************
5740 * Initializes receive address filters.
5741 *
5742 * hw - Struct containing variables accessed by shared code
5743 *
5744 * Places the MAC address in receive address register 0 and clears the rest
5745 * of the receive addresss registers. Clears the multicast table. Assumes
5746 * the receiver is in reset when the routine is called.
5747 *****************************************************************************/
5748 static void
5749 e1000_init_rx_addrs(struct e1000_hw *hw)
5750 {
5751 uint32_t i;
5752 uint32_t rar_num;
5753
5754 DEBUGFUNC("e1000_init_rx_addrs");
5755
5756 /* Setup the receive address. */
5757 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5758
5759 e1000_rar_set(hw, hw->mac_addr, 0);
5760
5761 rar_num = E1000_RAR_ENTRIES;
5762
5763 /* Reserve a spot for the Locally Administered Address to work around
5764 * an 82571 issue in which a reset on one port will reload the MAC on
5765 * the other port. */
5766 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5767 rar_num -= 1;
5768 if (hw->mac_type == e1000_ich8lan)
5769 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5770
5771 /* Zero out the other 15 receive addresses. */
5772 DEBUGOUT("Clearing RAR[1-15]\n");
5773 for (i = 1; i < rar_num; i++) {
5774 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5775 E1000_WRITE_FLUSH(hw);
5776 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5777 E1000_WRITE_FLUSH(hw);
5778 }
5779 }
5780
5781 /******************************************************************************
5782 * Hashes an address to determine its location in the multicast table
5783 *
5784 * hw - Struct containing variables accessed by shared code
5785 * mc_addr - the multicast address to hash
5786 *****************************************************************************/
5787 uint32_t
5788 e1000_hash_mc_addr(struct e1000_hw *hw,
5789 uint8_t *mc_addr)
5790 {
5791 uint32_t hash_value = 0;
5792
5793 /* The portion of the address that is used for the hash table is
5794 * determined by the mc_filter_type setting.
5795 */
5796 switch (hw->mc_filter_type) {
5797 /* [0] [1] [2] [3] [4] [5]
5798 * 01 AA 00 12 34 56
5799 * LSB MSB
5800 */
5801 case 0:
5802 if (hw->mac_type == e1000_ich8lan) {
5803 /* [47:38] i.e. 0x158 for above example address */
5804 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5805 } else {
5806 /* [47:36] i.e. 0x563 for above example address */
5807 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5808 }
5809 break;
5810 case 1:
5811 if (hw->mac_type == e1000_ich8lan) {
5812 /* [46:37] i.e. 0x2B1 for above example address */
5813 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5814 } else {
5815 /* [46:35] i.e. 0xAC6 for above example address */
5816 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5817 }
5818 break;
5819 case 2:
5820 if (hw->mac_type == e1000_ich8lan) {
5821 /*[45:36] i.e. 0x163 for above example address */
5822 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5823 } else {
5824 /* [45:34] i.e. 0x5D8 for above example address */
5825 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5826 }
5827 break;
5828 case 3:
5829 if (hw->mac_type == e1000_ich8lan) {
5830 /* [43:34] i.e. 0x18D for above example address */
5831 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5832 } else {
5833 /* [43:32] i.e. 0x634 for above example address */
5834 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5835 }
5836 break;
5837 }
5838
5839 hash_value &= 0xFFF;
5840 if (hw->mac_type == e1000_ich8lan)
5841 hash_value &= 0x3FF;
5842
5843 return hash_value;
5844 }
5845
5846 /******************************************************************************
5847 * Sets the bit in the multicast table corresponding to the hash value.
5848 *
5849 * hw - Struct containing variables accessed by shared code
5850 * hash_value - Multicast address hash value
5851 *****************************************************************************/
5852 void
5853 e1000_mta_set(struct e1000_hw *hw,
5854 uint32_t hash_value)
5855 {
5856 uint32_t hash_bit, hash_reg;
5857 uint32_t mta;
5858 uint32_t temp;
5859
5860 /* The MTA is a register array of 128 32-bit registers.
5861 * It is treated like an array of 4096 bits. We want to set
5862 * bit BitArray[hash_value]. So we figure out what register
5863 * the bit is in, read it, OR in the new bit, then write
5864 * back the new value. The register is determined by the
5865 * upper 7 bits of the hash value and the bit within that
5866 * register are determined by the lower 5 bits of the value.
5867 */
5868 hash_reg = (hash_value >> 5) & 0x7F;
5869 if (hw->mac_type == e1000_ich8lan)
5870 hash_reg &= 0x1F;
5871
5872 hash_bit = hash_value & 0x1F;
5873
5874 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5875
5876 mta |= (1 << hash_bit);
5877
5878 /* If we are on an 82544 and we are trying to write an odd offset
5879 * in the MTA, save off the previous entry before writing and
5880 * restore the old value after writing.
5881 */
5882 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5883 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5884 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5885 E1000_WRITE_FLUSH(hw);
5886 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5887 E1000_WRITE_FLUSH(hw);
5888 } else {
5889 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5890 E1000_WRITE_FLUSH(hw);
5891 }
5892 }
5893
5894 /******************************************************************************
5895 * Puts an ethernet address into a receive address register.
5896 *
5897 * hw - Struct containing variables accessed by shared code
5898 * addr - Address to put into receive address register
5899 * index - Receive address register to write
5900 *****************************************************************************/
5901 void
5902 e1000_rar_set(struct e1000_hw *hw,
5903 uint8_t *addr,
5904 uint32_t index)
5905 {
5906 uint32_t rar_low, rar_high;
5907
5908 /* HW expects these in little endian so we reverse the byte order
5909 * from network order (big endian) to little endian
5910 */
5911 rar_low = ((uint32_t) addr[0] |
5912 ((uint32_t) addr[1] << 8) |
5913 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5914 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5915
5916 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5917 * unit hang.
5918 *
5919 * Description:
5920 * If there are any Rx frames queued up or otherwise present in the HW
5921 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5922 * hang. To work around this issue, we have to disable receives and
5923 * flush out all Rx frames before we enable RSS. To do so, we modify we
5924 * redirect all Rx traffic to manageability and then reset the HW.
5925 * This flushes away Rx frames, and (since the redirections to
5926 * manageability persists across resets) keeps new ones from coming in
5927 * while we work. Then, we clear the Address Valid AV bit for all MAC
5928 * addresses and undo the re-direction to manageability.
5929 * Now, frames are coming in again, but the MAC won't accept them, so
5930 * far so good. We now proceed to initialize RSS (if necessary) and
5931 * configure the Rx unit. Last, we re-enable the AV bits and continue
5932 * on our merry way.
5933 */
5934 switch (hw->mac_type) {
5935 case e1000_82571:
5936 case e1000_82572:
5937 case e1000_80003es2lan:
5938 if (hw->leave_av_bit_off == TRUE)
5939 break;
5940 default:
5941 /* Indicate to hardware the Address is Valid. */
5942 rar_high |= E1000_RAH_AV;
5943 break;
5944 }
5945
5946 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5947 E1000_WRITE_FLUSH(hw);
5948 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5949 E1000_WRITE_FLUSH(hw);
5950 }
5951
5952 /******************************************************************************
5953 * Writes a value to the specified offset in the VLAN filter table.
5954 *
5955 * hw - Struct containing variables accessed by shared code
5956 * offset - Offset in VLAN filer table to write
5957 * value - Value to write into VLAN filter table
5958 *****************************************************************************/
5959 void
5960 e1000_write_vfta(struct e1000_hw *hw,
5961 uint32_t offset,
5962 uint32_t value)
5963 {
5964 uint32_t temp;
5965
5966 if (hw->mac_type == e1000_ich8lan)
5967 return;
5968
5969 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5970 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5971 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5972 E1000_WRITE_FLUSH(hw);
5973 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5974 E1000_WRITE_FLUSH(hw);
5975 } else {
5976 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5977 E1000_WRITE_FLUSH(hw);
5978 }
5979 }
5980
5981 /******************************************************************************
5982 * Clears the VLAN filer table
5983 *
5984 * hw - Struct containing variables accessed by shared code
5985 *****************************************************************************/
5986 static void
5987 e1000_clear_vfta(struct e1000_hw *hw)
5988 {
5989 uint32_t offset;
5990 uint32_t vfta_value = 0;
5991 uint32_t vfta_offset = 0;
5992 uint32_t vfta_bit_in_reg = 0;
5993
5994 if (hw->mac_type == e1000_ich8lan)
5995 return;
5996
5997 if (hw->mac_type == e1000_82573) {
5998 if (hw->mng_cookie.vlan_id != 0) {
5999 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
6000 * ID. The following operations determine which 32b entry
6001 * (i.e. offset) into the array we want to set the VLAN ID
6002 * (i.e. bit) of the manageability unit. */
6003 vfta_offset = (hw->mng_cookie.vlan_id >>
6004 E1000_VFTA_ENTRY_SHIFT) &
6005 E1000_VFTA_ENTRY_MASK;
6006 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6007 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
6008 }
6009 }
6010 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
6011 /* If the offset we want to clear is the same offset of the
6012 * manageability VLAN ID, then clear all bits except that of the
6013 * manageability unit */
6014 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6015 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6016 E1000_WRITE_FLUSH(hw);
6017 }
6018 }
6019
6020 static int32_t
6021 e1000_id_led_init(struct e1000_hw * hw)
6022 {
6023 uint32_t ledctl;
6024 const uint32_t ledctl_mask = 0x000000FF;
6025 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6026 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6027 uint16_t eeprom_data, i, temp;
6028 const uint16_t led_mask = 0x0F;
6029
6030 DEBUGFUNC("e1000_id_led_init");
6031
6032 if (hw->mac_type < e1000_82540) {
6033 /* Nothing to do */
6034 return E1000_SUCCESS;
6035 }
6036
6037 ledctl = E1000_READ_REG(hw, LEDCTL);
6038 hw->ledctl_default = ledctl;
6039 hw->ledctl_mode1 = hw->ledctl_default;
6040 hw->ledctl_mode2 = hw->ledctl_default;
6041
6042 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6043 DEBUGOUT("EEPROM Read Error\n");
6044 return -E1000_ERR_EEPROM;
6045 }
6046
6047 if ((hw->mac_type == e1000_82573) &&
6048 (eeprom_data == ID_LED_RESERVED_82573))
6049 eeprom_data = ID_LED_DEFAULT_82573;
6050 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6051 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6052 if (hw->mac_type == e1000_ich8lan)
6053 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6054 else
6055 eeprom_data = ID_LED_DEFAULT;
6056 }
6057
6058 for (i = 0; i < 4; i++) {
6059 temp = (eeprom_data >> (i << 2)) & led_mask;
6060 switch (temp) {
6061 case ID_LED_ON1_DEF2:
6062 case ID_LED_ON1_ON2:
6063 case ID_LED_ON1_OFF2:
6064 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6065 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6066 break;
6067 case ID_LED_OFF1_DEF2:
6068 case ID_LED_OFF1_ON2:
6069 case ID_LED_OFF1_OFF2:
6070 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6071 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6072 break;
6073 default:
6074 /* Do nothing */
6075 break;
6076 }
6077 switch (temp) {
6078 case ID_LED_DEF1_ON2:
6079 case ID_LED_ON1_ON2:
6080 case ID_LED_OFF1_ON2:
6081 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6082 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6083 break;
6084 case ID_LED_DEF1_OFF2:
6085 case ID_LED_ON1_OFF2:
6086 case ID_LED_OFF1_OFF2:
6087 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6088 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6089 break;
6090 default:
6091 /* Do nothing */
6092 break;
6093 }
6094 }
6095 return E1000_SUCCESS;
6096 }
6097
6098 /******************************************************************************
6099 * Prepares SW controlable LED for use and saves the current state of the LED.
6100 *
6101 * hw - Struct containing variables accessed by shared code
6102 *****************************************************************************/
6103 int32_t
6104 e1000_setup_led(struct e1000_hw *hw)
6105 {
6106 uint32_t ledctl;
6107 int32_t ret_val = E1000_SUCCESS;
6108
6109 DEBUGFUNC("e1000_setup_led");
6110
6111 switch (hw->mac_type) {
6112 case e1000_82542_rev2_0:
6113 case e1000_82542_rev2_1:
6114 case e1000_82543:
6115 case e1000_82544:
6116 /* No setup necessary */
6117 break;
6118 case e1000_82541:
6119 case e1000_82547:
6120 case e1000_82541_rev_2:
6121 case e1000_82547_rev_2:
6122 /* Turn off PHY Smart Power Down (if enabled) */
6123 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6124 &hw->phy_spd_default);
6125 if (ret_val)
6126 return ret_val;
6127 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6128 (uint16_t)(hw->phy_spd_default &
6129 ~IGP01E1000_GMII_SPD));
6130 if (ret_val)
6131 return ret_val;
6132 /* Fall Through */
6133 default:
6134 if (hw->media_type == e1000_media_type_fiber) {
6135 ledctl = E1000_READ_REG(hw, LEDCTL);
6136 /* Save current LEDCTL settings */
6137 hw->ledctl_default = ledctl;
6138 /* Turn off LED0 */
6139 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6140 E1000_LEDCTL_LED0_BLINK |
6141 E1000_LEDCTL_LED0_MODE_MASK);
6142 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6143 E1000_LEDCTL_LED0_MODE_SHIFT);
6144 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6145 } else if (hw->media_type == e1000_media_type_copper)
6146 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6147 break;
6148 }
6149
6150 return E1000_SUCCESS;
6151 }
6152
6153
6154 /******************************************************************************
6155 * Used on 82571 and later Si that has LED blink bits.
6156 * Callers must use their own timer and should have already called
6157 * e1000_id_led_init()
6158 * Call e1000_cleanup led() to stop blinking
6159 *
6160 * hw - Struct containing variables accessed by shared code
6161 *****************************************************************************/
6162 int32_t
6163 e1000_blink_led_start(struct e1000_hw *hw)
6164 {
6165 int16_t i;
6166 uint32_t ledctl_blink = 0;
6167
6168 DEBUGFUNC("e1000_id_led_blink_on");
6169
6170 if (hw->mac_type < e1000_82571) {
6171 /* Nothing to do */
6172 return E1000_SUCCESS;
6173 }
6174 if (hw->media_type == e1000_media_type_fiber) {
6175 /* always blink LED0 for PCI-E fiber */
6176 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6177 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6178 } else {
6179 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6180 ledctl_blink = hw->ledctl_mode2;
6181 for (i=0; i < 4; i++)
6182 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6183 E1000_LEDCTL_MODE_LED_ON)
6184 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6185 }
6186
6187 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6188
6189 return E1000_SUCCESS;
6190 }
6191
6192 /******************************************************************************
6193 * Restores the saved state of the SW controlable LED.
6194 *
6195 * hw - Struct containing variables accessed by shared code
6196 *****************************************************************************/
6197 int32_t
6198 e1000_cleanup_led(struct e1000_hw *hw)
6199 {
6200 int32_t ret_val = E1000_SUCCESS;
6201
6202 DEBUGFUNC("e1000_cleanup_led");
6203
6204 switch (hw->mac_type) {
6205 case e1000_82542_rev2_0:
6206 case e1000_82542_rev2_1:
6207 case e1000_82543:
6208 case e1000_82544:
6209 /* No cleanup necessary */
6210 break;
6211 case e1000_82541:
6212 case e1000_82547:
6213 case e1000_82541_rev_2:
6214 case e1000_82547_rev_2:
6215 /* Turn on PHY Smart Power Down (if previously enabled) */
6216 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6217 hw->phy_spd_default);
6218 if (ret_val)
6219 return ret_val;
6220 /* Fall Through */
6221 default:
6222 if (hw->phy_type == e1000_phy_ife) {
6223 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6224 break;
6225 }
6226 /* Restore LEDCTL settings */
6227 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6228 break;
6229 }
6230
6231 return E1000_SUCCESS;
6232 }
6233
6234 /******************************************************************************
6235 * Turns on the software controllable LED
6236 *
6237 * hw - Struct containing variables accessed by shared code
6238 *****************************************************************************/
6239 int32_t
6240 e1000_led_on(struct e1000_hw *hw)
6241 {
6242 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6243
6244 DEBUGFUNC("e1000_led_on");
6245
6246 switch (hw->mac_type) {
6247 case e1000_82542_rev2_0:
6248 case e1000_82542_rev2_1:
6249 case e1000_82543:
6250 /* Set SW Defineable Pin 0 to turn on the LED */
6251 ctrl |= E1000_CTRL_SWDPIN0;
6252 ctrl |= E1000_CTRL_SWDPIO0;
6253 break;
6254 case e1000_82544:
6255 if (hw->media_type == e1000_media_type_fiber) {
6256 /* Set SW Defineable Pin 0 to turn on the LED */
6257 ctrl |= E1000_CTRL_SWDPIN0;
6258 ctrl |= E1000_CTRL_SWDPIO0;
6259 } else {
6260 /* Clear SW Defineable Pin 0 to turn on the LED */
6261 ctrl &= ~E1000_CTRL_SWDPIN0;
6262 ctrl |= E1000_CTRL_SWDPIO0;
6263 }
6264 break;
6265 default:
6266 if (hw->media_type == e1000_media_type_fiber) {
6267 /* Clear SW Defineable Pin 0 to turn on the LED */
6268 ctrl &= ~E1000_CTRL_SWDPIN0;
6269 ctrl |= E1000_CTRL_SWDPIO0;
6270 } else if (hw->phy_type == e1000_phy_ife) {
6271 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6272 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6273 } else if (hw->media_type == e1000_media_type_copper) {
6274 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6275 return E1000_SUCCESS;
6276 }
6277 break;
6278 }
6279
6280 E1000_WRITE_REG(hw, CTRL, ctrl);
6281
6282 return E1000_SUCCESS;
6283 }
6284
6285 /******************************************************************************
6286 * Turns off the software controllable LED
6287 *
6288 * hw - Struct containing variables accessed by shared code
6289 *****************************************************************************/
6290 int32_t
6291 e1000_led_off(struct e1000_hw *hw)
6292 {
6293 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6294
6295 DEBUGFUNC("e1000_led_off");
6296
6297 switch (hw->mac_type) {
6298 case e1000_82542_rev2_0:
6299 case e1000_82542_rev2_1:
6300 case e1000_82543:
6301 /* Clear SW Defineable Pin 0 to turn off the LED */
6302 ctrl &= ~E1000_CTRL_SWDPIN0;
6303 ctrl |= E1000_CTRL_SWDPIO0;
6304 break;
6305 case e1000_82544:
6306 if (hw->media_type == e1000_media_type_fiber) {
6307 /* Clear SW Defineable Pin 0 to turn off the LED */
6308 ctrl &= ~E1000_CTRL_SWDPIN0;
6309 ctrl |= E1000_CTRL_SWDPIO0;
6310 } else {
6311 /* Set SW Defineable Pin 0 to turn off the LED */
6312 ctrl |= E1000_CTRL_SWDPIN0;
6313 ctrl |= E1000_CTRL_SWDPIO0;
6314 }
6315 break;
6316 default:
6317 if (hw->media_type == e1000_media_type_fiber) {
6318 /* Set SW Defineable Pin 0 to turn off the LED */
6319 ctrl |= E1000_CTRL_SWDPIN0;
6320 ctrl |= E1000_CTRL_SWDPIO0;
6321 } else if (hw->phy_type == e1000_phy_ife) {
6322 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6323 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6324 } else if (hw->media_type == e1000_media_type_copper) {
6325 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6326 return E1000_SUCCESS;
6327 }
6328 break;
6329 }
6330
6331 E1000_WRITE_REG(hw, CTRL, ctrl);
6332
6333 return E1000_SUCCESS;
6334 }
6335
6336 /******************************************************************************
6337 * Clears all hardware statistics counters.
6338 *
6339 * hw - Struct containing variables accessed by shared code
6340 *****************************************************************************/
6341 static void
6342 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6343 {
6344 volatile uint32_t temp;
6345
6346 temp = E1000_READ_REG(hw, CRCERRS);
6347 temp = E1000_READ_REG(hw, SYMERRS);
6348 temp = E1000_READ_REG(hw, MPC);
6349 temp = E1000_READ_REG(hw, SCC);
6350 temp = E1000_READ_REG(hw, ECOL);
6351 temp = E1000_READ_REG(hw, MCC);
6352 temp = E1000_READ_REG(hw, LATECOL);
6353 temp = E1000_READ_REG(hw, COLC);
6354 temp = E1000_READ_REG(hw, DC);
6355 temp = E1000_READ_REG(hw, SEC);
6356 temp = E1000_READ_REG(hw, RLEC);
6357 temp = E1000_READ_REG(hw, XONRXC);
6358 temp = E1000_READ_REG(hw, XONTXC);
6359 temp = E1000_READ_REG(hw, XOFFRXC);
6360 temp = E1000_READ_REG(hw, XOFFTXC);
6361 temp = E1000_READ_REG(hw, FCRUC);
6362
6363 if (hw->mac_type != e1000_ich8lan) {
6364 temp = E1000_READ_REG(hw, PRC64);
6365 temp = E1000_READ_REG(hw, PRC127);
6366 temp = E1000_READ_REG(hw, PRC255);
6367 temp = E1000_READ_REG(hw, PRC511);
6368 temp = E1000_READ_REG(hw, PRC1023);
6369 temp = E1000_READ_REG(hw, PRC1522);
6370 }
6371
6372 temp = E1000_READ_REG(hw, GPRC);
6373 temp = E1000_READ_REG(hw, BPRC);
6374 temp = E1000_READ_REG(hw, MPRC);
6375 temp = E1000_READ_REG(hw, GPTC);
6376 temp = E1000_READ_REG(hw, GORCL);
6377 temp = E1000_READ_REG(hw, GORCH);
6378 temp = E1000_READ_REG(hw, GOTCL);
6379 temp = E1000_READ_REG(hw, GOTCH);
6380 temp = E1000_READ_REG(hw, RNBC);
6381 temp = E1000_READ_REG(hw, RUC);
6382 temp = E1000_READ_REG(hw, RFC);
6383 temp = E1000_READ_REG(hw, ROC);
6384 temp = E1000_READ_REG(hw, RJC);
6385 temp = E1000_READ_REG(hw, TORL);
6386 temp = E1000_READ_REG(hw, TORH);
6387 temp = E1000_READ_REG(hw, TOTL);
6388 temp = E1000_READ_REG(hw, TOTH);
6389 temp = E1000_READ_REG(hw, TPR);
6390 temp = E1000_READ_REG(hw, TPT);
6391
6392 if (hw->mac_type != e1000_ich8lan) {
6393 temp = E1000_READ_REG(hw, PTC64);
6394 temp = E1000_READ_REG(hw, PTC127);
6395 temp = E1000_READ_REG(hw, PTC255);
6396 temp = E1000_READ_REG(hw, PTC511);
6397 temp = E1000_READ_REG(hw, PTC1023);
6398 temp = E1000_READ_REG(hw, PTC1522);
6399 }
6400
6401 temp = E1000_READ_REG(hw, MPTC);
6402 temp = E1000_READ_REG(hw, BPTC);
6403
6404 if (hw->mac_type < e1000_82543) return;
6405
6406 temp = E1000_READ_REG(hw, ALGNERRC);
6407 temp = E1000_READ_REG(hw, RXERRC);
6408 temp = E1000_READ_REG(hw, TNCRS);
6409 temp = E1000_READ_REG(hw, CEXTERR);
6410 temp = E1000_READ_REG(hw, TSCTC);
6411 temp = E1000_READ_REG(hw, TSCTFC);
6412
6413 if (hw->mac_type <= e1000_82544) return;
6414
6415 temp = E1000_READ_REG(hw, MGTPRC);
6416 temp = E1000_READ_REG(hw, MGTPDC);
6417 temp = E1000_READ_REG(hw, MGTPTC);
6418
6419 if (hw->mac_type <= e1000_82547_rev_2) return;
6420
6421 temp = E1000_READ_REG(hw, IAC);
6422 temp = E1000_READ_REG(hw, ICRXOC);
6423
6424 if (hw->mac_type == e1000_ich8lan) return;
6425
6426 temp = E1000_READ_REG(hw, ICRXPTC);
6427 temp = E1000_READ_REG(hw, ICRXATC);
6428 temp = E1000_READ_REG(hw, ICTXPTC);
6429 temp = E1000_READ_REG(hw, ICTXATC);
6430 temp = E1000_READ_REG(hw, ICTXQEC);
6431 temp = E1000_READ_REG(hw, ICTXQMTC);
6432 temp = E1000_READ_REG(hw, ICRXDMTC);
6433 }
6434
6435 /******************************************************************************
6436 * Resets Adaptive IFS to its default state.
6437 *
6438 * hw - Struct containing variables accessed by shared code
6439 *
6440 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6441 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6442 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6443 * before calling this function.
6444 *****************************************************************************/
6445 void
6446 e1000_reset_adaptive(struct e1000_hw *hw)
6447 {
6448 DEBUGFUNC("e1000_reset_adaptive");
6449
6450 if (hw->adaptive_ifs) {
6451 if (!hw->ifs_params_forced) {
6452 hw->current_ifs_val = 0;
6453 hw->ifs_min_val = IFS_MIN;
6454 hw->ifs_max_val = IFS_MAX;
6455 hw->ifs_step_size = IFS_STEP;
6456 hw->ifs_ratio = IFS_RATIO;
6457 }
6458 hw->in_ifs_mode = FALSE;
6459 E1000_WRITE_REG(hw, AIT, 0);
6460 } else {
6461 DEBUGOUT("Not in Adaptive IFS mode!\n");
6462 }
6463 }
6464
6465 /******************************************************************************
6466 * Called during the callback/watchdog routine to update IFS value based on
6467 * the ratio of transmits to collisions.
6468 *
6469 * hw - Struct containing variables accessed by shared code
6470 * tx_packets - Number of transmits since last callback
6471 * total_collisions - Number of collisions since last callback
6472 *****************************************************************************/
6473 void
6474 e1000_update_adaptive(struct e1000_hw *hw)
6475 {
6476 DEBUGFUNC("e1000_update_adaptive");
6477
6478 if (hw->adaptive_ifs) {
6479 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6480 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6481 hw->in_ifs_mode = TRUE;
6482 if (hw->current_ifs_val < hw->ifs_max_val) {
6483 if (hw->current_ifs_val == 0)
6484 hw->current_ifs_val = hw->ifs_min_val;
6485 else
6486 hw->current_ifs_val += hw->ifs_step_size;
6487 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6488 }
6489 }
6490 } else {
6491 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6492 hw->current_ifs_val = 0;
6493 hw->in_ifs_mode = FALSE;
6494 E1000_WRITE_REG(hw, AIT, 0);
6495 }
6496 }
6497 } else {
6498 DEBUGOUT("Not in Adaptive IFS mode!\n");
6499 }
6500 }
6501
6502 /******************************************************************************
6503 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6504 *
6505 * hw - Struct containing variables accessed by shared code
6506 * frame_len - The length of the frame in question
6507 * mac_addr - The Ethernet destination address of the frame in question
6508 *****************************************************************************/
6509 void
6510 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6511 struct e1000_hw_stats *stats,
6512 uint32_t frame_len,
6513 uint8_t *mac_addr)
6514 {
6515 uint64_t carry_bit;
6516
6517 /* First adjust the frame length. */
6518 frame_len--;
6519 /* We need to adjust the statistics counters, since the hardware
6520 * counters overcount this packet as a CRC error and undercount
6521 * the packet as a good packet
6522 */
6523 /* This packet should not be counted as a CRC error. */
6524 stats->crcerrs--;
6525 /* This packet does count as a Good Packet Received. */
6526 stats->gprc++;
6527
6528 /* Adjust the Good Octets received counters */
6529 carry_bit = 0x80000000 & stats->gorcl;
6530 stats->gorcl += frame_len;
6531 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6532 * Received Count) was one before the addition,
6533 * AND it is zero after, then we lost the carry out,
6534 * need to add one to Gorch (Good Octets Received Count High).
6535 * This could be simplified if all environments supported
6536 * 64-bit integers.
6537 */
6538 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6539 stats->gorch++;
6540 /* Is this a broadcast or multicast? Check broadcast first,
6541 * since the test for a multicast frame will test positive on
6542 * a broadcast frame.
6543 */
6544 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6545 /* Broadcast packet */
6546 stats->bprc++;
6547 else if (*mac_addr & 0x01)
6548 /* Multicast packet */
6549 stats->mprc++;
6550
6551 if (frame_len == hw->max_frame_size) {
6552 /* In this case, the hardware has overcounted the number of
6553 * oversize frames.
6554 */
6555 if (stats->roc > 0)
6556 stats->roc--;
6557 }
6558
6559 /* Adjust the bin counters when the extra byte put the frame in the
6560 * wrong bin. Remember that the frame_len was adjusted above.
6561 */
6562 if (frame_len == 64) {
6563 stats->prc64++;
6564 stats->prc127--;
6565 } else if (frame_len == 127) {
6566 stats->prc127++;
6567 stats->prc255--;
6568 } else if (frame_len == 255) {
6569 stats->prc255++;
6570 stats->prc511--;
6571 } else if (frame_len == 511) {
6572 stats->prc511++;
6573 stats->prc1023--;
6574 } else if (frame_len == 1023) {
6575 stats->prc1023++;
6576 stats->prc1522--;
6577 } else if (frame_len == 1522) {
6578 stats->prc1522++;
6579 }
6580 }
6581
6582 /******************************************************************************
6583 * Gets the current PCI bus type, speed, and width of the hardware
6584 *
6585 * hw - Struct containing variables accessed by shared code
6586 *****************************************************************************/
6587 void
6588 e1000_get_bus_info(struct e1000_hw *hw)
6589 {
6590 int32_t ret_val;
6591 uint16_t pci_ex_link_status;
6592 uint32_t status;
6593
6594 switch (hw->mac_type) {
6595 case e1000_82542_rev2_0:
6596 case e1000_82542_rev2_1:
6597 hw->bus_type = e1000_bus_type_pci;
6598 hw->bus_speed = e1000_bus_speed_unknown;
6599 hw->bus_width = e1000_bus_width_unknown;
6600 break;
6601 case e1000_82571:
6602 case e1000_82572:
6603 case e1000_82573:
6604 case e1000_80003es2lan:
6605 hw->bus_type = e1000_bus_type_pci_express;
6606 hw->bus_speed = e1000_bus_speed_2500;
6607 ret_val = e1000_read_pcie_cap_reg(hw,
6608 PCI_EX_LINK_STATUS,
6609 &pci_ex_link_status);
6610 if (ret_val)
6611 hw->bus_width = e1000_bus_width_unknown;
6612 else
6613 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6614 PCI_EX_LINK_WIDTH_SHIFT;
6615 break;
6616 case e1000_ich8lan:
6617 hw->bus_type = e1000_bus_type_pci_express;
6618 hw->bus_speed = e1000_bus_speed_2500;
6619 hw->bus_width = e1000_bus_width_pciex_1;
6620 break;
6621 default:
6622 status = E1000_READ_REG(hw, STATUS);
6623 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6624 e1000_bus_type_pcix : e1000_bus_type_pci;
6625
6626 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6627 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6628 e1000_bus_speed_66 : e1000_bus_speed_120;
6629 } else if (hw->bus_type == e1000_bus_type_pci) {
6630 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6631 e1000_bus_speed_66 : e1000_bus_speed_33;
6632 } else {
6633 switch (status & E1000_STATUS_PCIX_SPEED) {
6634 case E1000_STATUS_PCIX_SPEED_66:
6635 hw->bus_speed = e1000_bus_speed_66;
6636 break;
6637 case E1000_STATUS_PCIX_SPEED_100:
6638 hw->bus_speed = e1000_bus_speed_100;
6639 break;
6640 case E1000_STATUS_PCIX_SPEED_133:
6641 hw->bus_speed = e1000_bus_speed_133;
6642 break;
6643 default:
6644 hw->bus_speed = e1000_bus_speed_reserved;
6645 break;
6646 }
6647 }
6648 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6649 e1000_bus_width_64 : e1000_bus_width_32;
6650 break;
6651 }
6652 }
6653
6654 /******************************************************************************
6655 * Writes a value to one of the devices registers using port I/O (as opposed to
6656 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6657 *
6658 * hw - Struct containing variables accessed by shared code
6659 * offset - offset to write to
6660 * value - value to write
6661 *****************************************************************************/
6662 static void
6663 e1000_write_reg_io(struct e1000_hw *hw,
6664 uint32_t offset,
6665 uint32_t value)
6666 {
6667 unsigned long io_addr = hw->io_base;
6668 unsigned long io_data = hw->io_base + 4;
6669
6670 e1000_io_write(hw, io_addr, offset);
6671 e1000_io_write(hw, io_data, value);
6672 }
6673
6674 /******************************************************************************
6675 * Estimates the cable length.
6676 *
6677 * hw - Struct containing variables accessed by shared code
6678 * min_length - The estimated minimum length
6679 * max_length - The estimated maximum length
6680 *
6681 * returns: - E1000_ERR_XXX
6682 * E1000_SUCCESS
6683 *
6684 * This function always returns a ranged length (minimum & maximum).
6685 * So for M88 phy's, this function interprets the one value returned from the
6686 * register to the minimum and maximum range.
6687 * For IGP phy's, the function calculates the range by the AGC registers.
6688 *****************************************************************************/
6689 static int32_t
6690 e1000_get_cable_length(struct e1000_hw *hw,
6691 uint16_t *min_length,
6692 uint16_t *max_length)
6693 {
6694 int32_t ret_val;
6695 uint16_t agc_value = 0;
6696 uint16_t i, phy_data;
6697 uint16_t cable_length;
6698
6699 DEBUGFUNC("e1000_get_cable_length");
6700
6701 *min_length = *max_length = 0;
6702
6703 /* Use old method for Phy older than IGP */
6704 if (hw->phy_type == e1000_phy_m88) {
6705
6706 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6707 &phy_data);
6708 if (ret_val)
6709 return ret_val;
6710 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6711 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6712
6713 /* Convert the enum value to ranged values */
6714 switch (cable_length) {
6715 case e1000_cable_length_50:
6716 *min_length = 0;
6717 *max_length = e1000_igp_cable_length_50;
6718 break;
6719 case e1000_cable_length_50_80:
6720 *min_length = e1000_igp_cable_length_50;
6721 *max_length = e1000_igp_cable_length_80;
6722 break;
6723 case e1000_cable_length_80_110:
6724 *min_length = e1000_igp_cable_length_80;
6725 *max_length = e1000_igp_cable_length_110;
6726 break;
6727 case e1000_cable_length_110_140:
6728 *min_length = e1000_igp_cable_length_110;
6729 *max_length = e1000_igp_cable_length_140;
6730 break;
6731 case e1000_cable_length_140:
6732 *min_length = e1000_igp_cable_length_140;
6733 *max_length = e1000_igp_cable_length_170;
6734 break;
6735 default:
6736 return -E1000_ERR_PHY;
6737 break;
6738 }
6739 } else if (hw->phy_type == e1000_phy_gg82563) {
6740 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6741 &phy_data);
6742 if (ret_val)
6743 return ret_val;
6744 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6745
6746 switch (cable_length) {
6747 case e1000_gg_cable_length_60:
6748 *min_length = 0;
6749 *max_length = e1000_igp_cable_length_60;
6750 break;
6751 case e1000_gg_cable_length_60_115:
6752 *min_length = e1000_igp_cable_length_60;
6753 *max_length = e1000_igp_cable_length_115;
6754 break;
6755 case e1000_gg_cable_length_115_150:
6756 *min_length = e1000_igp_cable_length_115;
6757 *max_length = e1000_igp_cable_length_150;
6758 break;
6759 case e1000_gg_cable_length_150:
6760 *min_length = e1000_igp_cable_length_150;
6761 *max_length = e1000_igp_cable_length_180;
6762 break;
6763 default:
6764 return -E1000_ERR_PHY;
6765 break;
6766 }
6767 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6768 uint16_t cur_agc_value;
6769 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6770 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6771 {IGP01E1000_PHY_AGC_A,
6772 IGP01E1000_PHY_AGC_B,
6773 IGP01E1000_PHY_AGC_C,
6774 IGP01E1000_PHY_AGC_D};
6775 /* Read the AGC registers for all channels */
6776 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6777
6778 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6779 if (ret_val)
6780 return ret_val;
6781
6782 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6783
6784 /* Value bound check. */
6785 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6786 (cur_agc_value == 0))
6787 return -E1000_ERR_PHY;
6788
6789 agc_value += cur_agc_value;
6790
6791 /* Update minimal AGC value. */
6792 if (min_agc_value > cur_agc_value)
6793 min_agc_value = cur_agc_value;
6794 }
6795
6796 /* Remove the minimal AGC result for length < 50m */
6797 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6798 agc_value -= min_agc_value;
6799
6800 /* Get the average length of the remaining 3 channels */
6801 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6802 } else {
6803 /* Get the average length of all the 4 channels. */
6804 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6805 }
6806
6807 /* Set the range of the calculated length. */
6808 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6809 IGP01E1000_AGC_RANGE) > 0) ?
6810 (e1000_igp_cable_length_table[agc_value] -
6811 IGP01E1000_AGC_RANGE) : 0;
6812 *max_length = e1000_igp_cable_length_table[agc_value] +
6813 IGP01E1000_AGC_RANGE;
6814 } else if (hw->phy_type == e1000_phy_igp_2 ||
6815 hw->phy_type == e1000_phy_igp_3) {
6816 uint16_t cur_agc_index, max_agc_index = 0;
6817 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6818 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6819 {IGP02E1000_PHY_AGC_A,
6820 IGP02E1000_PHY_AGC_B,
6821 IGP02E1000_PHY_AGC_C,
6822 IGP02E1000_PHY_AGC_D};
6823 /* Read the AGC registers for all channels */
6824 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6825 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6826 if (ret_val)
6827 return ret_val;
6828
6829 /* Getting bits 15:9, which represent the combination of course and
6830 * fine gain values. The result is a number that can be put into
6831 * the lookup table to obtain the approximate cable length. */
6832 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6833 IGP02E1000_AGC_LENGTH_MASK;
6834
6835 /* Array index bound check. */
6836 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6837 (cur_agc_index == 0))
6838 return -E1000_ERR_PHY;
6839
6840 /* Remove min & max AGC values from calculation. */
6841 if (e1000_igp_2_cable_length_table[min_agc_index] >
6842 e1000_igp_2_cable_length_table[cur_agc_index])
6843 min_agc_index = cur_agc_index;
6844 if (e1000_igp_2_cable_length_table[max_agc_index] <
6845 e1000_igp_2_cable_length_table[cur_agc_index])
6846 max_agc_index = cur_agc_index;
6847
6848 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6849 }
6850
6851 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6852 e1000_igp_2_cable_length_table[max_agc_index]);
6853 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6854
6855 /* Calculate cable length with the error range of +/- 10 meters. */
6856 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6857 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6858 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6859 }
6860
6861 return E1000_SUCCESS;
6862 }
6863
6864 /******************************************************************************
6865 * Check the cable polarity
6866 *
6867 * hw - Struct containing variables accessed by shared code
6868 * polarity - output parameter : 0 - Polarity is not reversed
6869 * 1 - Polarity is reversed.
6870 *
6871 * returns: - E1000_ERR_XXX
6872 * E1000_SUCCESS
6873 *
6874 * For phy's older then IGP, this function simply reads the polarity bit in the
6875 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6876 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6877 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6878 * IGP01E1000_PHY_PCS_INIT_REG.
6879 *****************************************************************************/
6880 static int32_t
6881 e1000_check_polarity(struct e1000_hw *hw,
6882 e1000_rev_polarity *polarity)
6883 {
6884 int32_t ret_val;
6885 uint16_t phy_data;
6886
6887 DEBUGFUNC("e1000_check_polarity");
6888
6889 if ((hw->phy_type == e1000_phy_m88) ||
6890 (hw->phy_type == e1000_phy_gg82563)) {
6891 /* return the Polarity bit in the Status register. */
6892 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6893 &phy_data);
6894 if (ret_val)
6895 return ret_val;
6896 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6897 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6898 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6899
6900 } else if (hw->phy_type == e1000_phy_igp ||
6901 hw->phy_type == e1000_phy_igp_3 ||
6902 hw->phy_type == e1000_phy_igp_2) {
6903 /* Read the Status register to check the speed */
6904 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6905 &phy_data);
6906 if (ret_val)
6907 return ret_val;
6908
6909 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6910 * find the polarity status */
6911 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6912 IGP01E1000_PSSR_SPEED_1000MBPS) {
6913
6914 /* Read the GIG initialization PCS register (0x00B4) */
6915 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6916 &phy_data);
6917 if (ret_val)
6918 return ret_val;
6919
6920 /* Check the polarity bits */
6921 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6922 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6923 } else {
6924 /* For 10 Mbps, read the polarity bit in the status register. (for
6925 * 100 Mbps this bit is always 0) */
6926 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6927 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6928 }
6929 } else if (hw->phy_type == e1000_phy_ife) {
6930 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6931 &phy_data);
6932 if (ret_val)
6933 return ret_val;
6934 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6935 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6936 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6937 }
6938 return E1000_SUCCESS;
6939 }
6940
6941 /******************************************************************************
6942 * Check if Downshift occured
6943 *
6944 * hw - Struct containing variables accessed by shared code
6945 * downshift - output parameter : 0 - No Downshift ocured.
6946 * 1 - Downshift ocured.
6947 *
6948 * returns: - E1000_ERR_XXX
6949 * E1000_SUCCESS
6950 *
6951 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6952 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6953 * Link Health register. In IGP this bit is latched high, so the driver must
6954 * read it immediately after link is established.
6955 *****************************************************************************/
6956 static int32_t
6957 e1000_check_downshift(struct e1000_hw *hw)
6958 {
6959 int32_t ret_val;
6960 uint16_t phy_data;
6961
6962 DEBUGFUNC("e1000_check_downshift");
6963
6964 if (hw->phy_type == e1000_phy_igp ||
6965 hw->phy_type == e1000_phy_igp_3 ||
6966 hw->phy_type == e1000_phy_igp_2) {
6967 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6968 &phy_data);
6969 if (ret_val)
6970 return ret_val;
6971
6972 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6973 } else if ((hw->phy_type == e1000_phy_m88) ||
6974 (hw->phy_type == e1000_phy_gg82563)) {
6975 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6976 &phy_data);
6977 if (ret_val)
6978 return ret_val;
6979
6980 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6981 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6982 } else if (hw->phy_type == e1000_phy_ife) {
6983 /* e1000_phy_ife supports 10/100 speed only */
6984 hw->speed_downgraded = FALSE;
6985 }
6986
6987 return E1000_SUCCESS;
6988 }
6989
6990 /*****************************************************************************
6991 *
6992 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6993 * gigabit link is achieved to improve link quality.
6994 *
6995 * hw: Struct containing variables accessed by shared code
6996 *
6997 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6998 * E1000_SUCCESS at any other case.
6999 *
7000 ****************************************************************************/
7001
7002 static int32_t
7003 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7004 boolean_t link_up)
7005 {
7006 int32_t ret_val;
7007 uint16_t phy_data, phy_saved_data, speed, duplex, i;
7008 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7009 {IGP01E1000_PHY_AGC_PARAM_A,
7010 IGP01E1000_PHY_AGC_PARAM_B,
7011 IGP01E1000_PHY_AGC_PARAM_C,
7012 IGP01E1000_PHY_AGC_PARAM_D};
7013 uint16_t min_length, max_length;
7014
7015 DEBUGFUNC("e1000_config_dsp_after_link_change");
7016
7017 if (hw->phy_type != e1000_phy_igp)
7018 return E1000_SUCCESS;
7019
7020 if (link_up) {
7021 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7022 if (ret_val) {
7023 DEBUGOUT("Error getting link speed and duplex\n");
7024 return ret_val;
7025 }
7026
7027 if (speed == SPEED_1000) {
7028
7029 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7030 if (ret_val)
7031 return ret_val;
7032
7033 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7034 min_length >= e1000_igp_cable_length_50) {
7035
7036 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7037 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7038 &phy_data);
7039 if (ret_val)
7040 return ret_val;
7041
7042 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7043
7044 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7045 phy_data);
7046 if (ret_val)
7047 return ret_val;
7048 }
7049 hw->dsp_config_state = e1000_dsp_config_activated;
7050 }
7051
7052 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7053 (min_length < e1000_igp_cable_length_50)) {
7054
7055 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7056 uint32_t idle_errs = 0;
7057
7058 /* clear previous idle error counts */
7059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7060 &phy_data);
7061 if (ret_val)
7062 return ret_val;
7063
7064 for (i = 0; i < ffe_idle_err_timeout; i++) {
7065 udelay(1000);
7066 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7067 &phy_data);
7068 if (ret_val)
7069 return ret_val;
7070
7071 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7072 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7073 hw->ffe_config_state = e1000_ffe_config_active;
7074
7075 ret_val = e1000_write_phy_reg(hw,
7076 IGP01E1000_PHY_DSP_FFE,
7077 IGP01E1000_PHY_DSP_FFE_CM_CP);
7078 if (ret_val)
7079 return ret_val;
7080 break;
7081 }
7082
7083 if (idle_errs)
7084 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7085 }
7086 }
7087 }
7088 } else {
7089 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7090 /* Save off the current value of register 0x2F5B to be restored at
7091 * the end of the routines. */
7092 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7093
7094 if (ret_val)
7095 return ret_val;
7096
7097 /* Disable the PHY transmitter */
7098 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7099
7100 if (ret_val)
7101 return ret_val;
7102
7103 mdelay(20);
7104
7105 ret_val = e1000_write_phy_reg(hw, 0x0000,
7106 IGP01E1000_IEEE_FORCE_GIGA);
7107 if (ret_val)
7108 return ret_val;
7109 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7110 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7111 if (ret_val)
7112 return ret_val;
7113
7114 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7115 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7116
7117 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7118 if (ret_val)
7119 return ret_val;
7120 }
7121
7122 ret_val = e1000_write_phy_reg(hw, 0x0000,
7123 IGP01E1000_IEEE_RESTART_AUTONEG);
7124 if (ret_val)
7125 return ret_val;
7126
7127 mdelay(20);
7128
7129 /* Now enable the transmitter */
7130 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7131
7132 if (ret_val)
7133 return ret_val;
7134
7135 hw->dsp_config_state = e1000_dsp_config_enabled;
7136 }
7137
7138 if (hw->ffe_config_state == e1000_ffe_config_active) {
7139 /* Save off the current value of register 0x2F5B to be restored at
7140 * the end of the routines. */
7141 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7142
7143 if (ret_val)
7144 return ret_val;
7145
7146 /* Disable the PHY transmitter */
7147 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7148
7149 if (ret_val)
7150 return ret_val;
7151
7152 mdelay(20);
7153
7154 ret_val = e1000_write_phy_reg(hw, 0x0000,
7155 IGP01E1000_IEEE_FORCE_GIGA);
7156 if (ret_val)
7157 return ret_val;
7158 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7159 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7160 if (ret_val)
7161 return ret_val;
7162
7163 ret_val = e1000_write_phy_reg(hw, 0x0000,
7164 IGP01E1000_IEEE_RESTART_AUTONEG);
7165 if (ret_val)
7166 return ret_val;
7167
7168 mdelay(20);
7169
7170 /* Now enable the transmitter */
7171 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7172
7173 if (ret_val)
7174 return ret_val;
7175
7176 hw->ffe_config_state = e1000_ffe_config_enabled;
7177 }
7178 }
7179 return E1000_SUCCESS;
7180 }
7181
7182 /*****************************************************************************
7183 * Set PHY to class A mode
7184 * Assumes the following operations will follow to enable the new class mode.
7185 * 1. Do a PHY soft reset
7186 * 2. Restart auto-negotiation or force link.
7187 *
7188 * hw - Struct containing variables accessed by shared code
7189 ****************************************************************************/
7190 static int32_t
7191 e1000_set_phy_mode(struct e1000_hw *hw)
7192 {
7193 int32_t ret_val;
7194 uint16_t eeprom_data;
7195
7196 DEBUGFUNC("e1000_set_phy_mode");
7197
7198 if ((hw->mac_type == e1000_82545_rev_3) &&
7199 (hw->media_type == e1000_media_type_copper)) {
7200 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7201 if (ret_val) {
7202 return ret_val;
7203 }
7204
7205 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7206 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7207 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7208 if (ret_val)
7209 return ret_val;
7210 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7211 if (ret_val)
7212 return ret_val;
7213
7214 hw->phy_reset_disable = FALSE;
7215 }
7216 }
7217
7218 return E1000_SUCCESS;
7219 }
7220
7221 /*****************************************************************************
7222 *
7223 * This function sets the lplu state according to the active flag. When
7224 * activating lplu this function also disables smart speed and vise versa.
7225 * lplu will not be activated unless the device autonegotiation advertisment
7226 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7227 * hw: Struct containing variables accessed by shared code
7228 * active - true to enable lplu false to disable lplu.
7229 *
7230 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7231 * E1000_SUCCESS at any other case.
7232 *
7233 ****************************************************************************/
7234
7235 static int32_t
7236 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7237 boolean_t active)
7238 {
7239 uint32_t phy_ctrl = 0;
7240 int32_t ret_val;
7241 uint16_t phy_data;
7242 DEBUGFUNC("e1000_set_d3_lplu_state");
7243
7244 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7245 && hw->phy_type != e1000_phy_igp_3)
7246 return E1000_SUCCESS;
7247
7248 /* During driver activity LPLU should not be used or it will attain link
7249 * from the lowest speeds starting from 10Mbps. The capability is used for
7250 * Dx transitions and states */
7251 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7252 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7253 if (ret_val)
7254 return ret_val;
7255 } else if (hw->mac_type == e1000_ich8lan) {
7256 /* MAC writes into PHY register based on the state transition
7257 * and start auto-negotiation. SW driver can overwrite the settings
7258 * in CSR PHY power control E1000_PHY_CTRL register. */
7259 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7260 } else {
7261 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7262 if (ret_val)
7263 return ret_val;
7264 }
7265
7266 if (!active) {
7267 if (hw->mac_type == e1000_82541_rev_2 ||
7268 hw->mac_type == e1000_82547_rev_2) {
7269 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7270 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7271 if (ret_val)
7272 return ret_val;
7273 } else {
7274 if (hw->mac_type == e1000_ich8lan) {
7275 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7276 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7277 } else {
7278 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7279 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7280 phy_data);
7281 if (ret_val)
7282 return ret_val;
7283 }
7284 }
7285
7286 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7287 * Dx states where the power conservation is most important. During
7288 * driver activity we should enable SmartSpeed, so performance is
7289 * maintained. */
7290 if (hw->smart_speed == e1000_smart_speed_on) {
7291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7292 &phy_data);
7293 if (ret_val)
7294 return ret_val;
7295
7296 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7297 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7298 phy_data);
7299 if (ret_val)
7300 return ret_val;
7301 } else if (hw->smart_speed == e1000_smart_speed_off) {
7302 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7303 &phy_data);
7304 if (ret_val)
7305 return ret_val;
7306
7307 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7308 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7309 phy_data);
7310 if (ret_val)
7311 return ret_val;
7312 }
7313
7314 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7315 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7316 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7317
7318 if (hw->mac_type == e1000_82541_rev_2 ||
7319 hw->mac_type == e1000_82547_rev_2) {
7320 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7321 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7322 if (ret_val)
7323 return ret_val;
7324 } else {
7325 if (hw->mac_type == e1000_ich8lan) {
7326 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7327 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7328 } else {
7329 phy_data |= IGP02E1000_PM_D3_LPLU;
7330 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7331 phy_data);
7332 if (ret_val)
7333 return ret_val;
7334 }
7335 }
7336
7337 /* When LPLU is enabled we should disable SmartSpeed */
7338 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7339 if (ret_val)
7340 return ret_val;
7341
7342 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7343 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7344 if (ret_val)
7345 return ret_val;
7346
7347 }
7348 return E1000_SUCCESS;
7349 }
7350
7351 /*****************************************************************************
7352 *
7353 * This function sets the lplu d0 state according to the active flag. When
7354 * activating lplu this function also disables smart speed and vise versa.
7355 * lplu will not be activated unless the device autonegotiation advertisment
7356 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7357 * hw: Struct containing variables accessed by shared code
7358 * active - true to enable lplu false to disable lplu.
7359 *
7360 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7361 * E1000_SUCCESS at any other case.
7362 *
7363 ****************************************************************************/
7364
7365 static int32_t
7366 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7367 boolean_t active)
7368 {
7369 uint32_t phy_ctrl = 0;
7370 int32_t ret_val;
7371 uint16_t phy_data;
7372 DEBUGFUNC("e1000_set_d0_lplu_state");
7373
7374 if (hw->mac_type <= e1000_82547_rev_2)
7375 return E1000_SUCCESS;
7376
7377 if (hw->mac_type == e1000_ich8lan) {
7378 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7379 } else {
7380 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7381 if (ret_val)
7382 return ret_val;
7383 }
7384
7385 if (!active) {
7386 if (hw->mac_type == e1000_ich8lan) {
7387 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7388 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7389 } else {
7390 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7391 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7392 if (ret_val)
7393 return ret_val;
7394 }
7395
7396 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7397 * Dx states where the power conservation is most important. During
7398 * driver activity we should enable SmartSpeed, so performance is
7399 * maintained. */
7400 if (hw->smart_speed == e1000_smart_speed_on) {
7401 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7402 &phy_data);
7403 if (ret_val)
7404 return ret_val;
7405
7406 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7407 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7408 phy_data);
7409 if (ret_val)
7410 return ret_val;
7411 } else if (hw->smart_speed == e1000_smart_speed_off) {
7412 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7413 &phy_data);
7414 if (ret_val)
7415 return ret_val;
7416
7417 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7418 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7419 phy_data);
7420 if (ret_val)
7421 return ret_val;
7422 }
7423
7424
7425 } else {
7426
7427 if (hw->mac_type == e1000_ich8lan) {
7428 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7429 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7430 } else {
7431 phy_data |= IGP02E1000_PM_D0_LPLU;
7432 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7433 if (ret_val)
7434 return ret_val;
7435 }
7436
7437 /* When LPLU is enabled we should disable SmartSpeed */
7438 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7439 if (ret_val)
7440 return ret_val;
7441
7442 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7443 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7444 if (ret_val)
7445 return ret_val;
7446
7447 }
7448 return E1000_SUCCESS;
7449 }
7450
7451 /******************************************************************************
7452 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7453 *
7454 * hw - Struct containing variables accessed by shared code
7455 *****************************************************************************/
7456 static int32_t
7457 e1000_set_vco_speed(struct e1000_hw *hw)
7458 {
7459 int32_t ret_val;
7460 uint16_t default_page = 0;
7461 uint16_t phy_data;
7462
7463 DEBUGFUNC("e1000_set_vco_speed");
7464
7465 switch (hw->mac_type) {
7466 case e1000_82545_rev_3:
7467 case e1000_82546_rev_3:
7468 break;
7469 default:
7470 return E1000_SUCCESS;
7471 }
7472
7473 /* Set PHY register 30, page 5, bit 8 to 0 */
7474
7475 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7476 if (ret_val)
7477 return ret_val;
7478
7479 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7480 if (ret_val)
7481 return ret_val;
7482
7483 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7484 if (ret_val)
7485 return ret_val;
7486
7487 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7488 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7489 if (ret_val)
7490 return ret_val;
7491
7492 /* Set PHY register 30, page 4, bit 11 to 1 */
7493
7494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7495 if (ret_val)
7496 return ret_val;
7497
7498 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7499 if (ret_val)
7500 return ret_val;
7501
7502 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7503 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7504 if (ret_val)
7505 return ret_val;
7506
7507 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7508 if (ret_val)
7509 return ret_val;
7510
7511 return E1000_SUCCESS;
7512 }
7513
7514
7515 /*****************************************************************************
7516 * This function reads the cookie from ARC ram.
7517 *
7518 * returns: - E1000_SUCCESS .
7519 ****************************************************************************/
7520 static int32_t
7521 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7522 {
7523 uint8_t i;
7524 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7525 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7526
7527 length = (length >> 2);
7528 offset = (offset >> 2);
7529
7530 for (i = 0; i < length; i++) {
7531 *((uint32_t *) buffer + i) =
7532 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7533 }
7534 return E1000_SUCCESS;
7535 }
7536
7537
7538 /*****************************************************************************
7539 * This function checks whether the HOST IF is enabled for command operaton
7540 * and also checks whether the previous command is completed.
7541 * It busy waits in case of previous command is not completed.
7542 *
7543 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7544 * timeout
7545 * - E1000_SUCCESS for success.
7546 ****************************************************************************/
7547 static int32_t
7548 e1000_mng_enable_host_if(struct e1000_hw * hw)
7549 {
7550 uint32_t hicr;
7551 uint8_t i;
7552
7553 /* Check that the host interface is enabled. */
7554 hicr = E1000_READ_REG(hw, HICR);
7555 if ((hicr & E1000_HICR_EN) == 0) {
7556 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7557 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7558 }
7559 /* check the previous command is completed */
7560 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7561 hicr = E1000_READ_REG(hw, HICR);
7562 if (!(hicr & E1000_HICR_C))
7563 break;
7564 mdelay(1);
7565 }
7566
7567 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7568 DEBUGOUT("Previous command timeout failed .\n");
7569 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7570 }
7571 return E1000_SUCCESS;
7572 }
7573
7574 /*****************************************************************************
7575 * This function writes the buffer content at the offset given on the host if.
7576 * It also does alignment considerations to do the writes in most efficient way.
7577 * Also fills up the sum of the buffer in *buffer parameter.
7578 *
7579 * returns - E1000_SUCCESS for success.
7580 ****************************************************************************/
7581 static int32_t
7582 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7583 uint16_t length, uint16_t offset, uint8_t *sum)
7584 {
7585 uint8_t *tmp;
7586 uint8_t *bufptr = buffer;
7587 uint32_t data = 0;
7588 uint16_t remaining, i, j, prev_bytes;
7589
7590 /* sum = only sum of the data and it is not checksum */
7591
7592 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7593 return -E1000_ERR_PARAM;
7594 }
7595
7596 tmp = (uint8_t *)&data;
7597 prev_bytes = offset & 0x3;
7598 offset &= 0xFFFC;
7599 offset >>= 2;
7600
7601 if (prev_bytes) {
7602 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7603 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7604 *(tmp + j) = *bufptr++;
7605 *sum += *(tmp + j);
7606 }
7607 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7608 length -= j - prev_bytes;
7609 offset++;
7610 }
7611
7612 remaining = length & 0x3;
7613 length -= remaining;
7614
7615 /* Calculate length in DWORDs */
7616 length >>= 2;
7617
7618 /* The device driver writes the relevant command block into the
7619 * ram area. */
7620 for (i = 0; i < length; i++) {
7621 for (j = 0; j < sizeof(uint32_t); j++) {
7622 *(tmp + j) = *bufptr++;
7623 *sum += *(tmp + j);
7624 }
7625
7626 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7627 }
7628 if (remaining) {
7629 for (j = 0; j < sizeof(uint32_t); j++) {
7630 if (j < remaining)
7631 *(tmp + j) = *bufptr++;
7632 else
7633 *(tmp + j) = 0;
7634
7635 *sum += *(tmp + j);
7636 }
7637 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7638 }
7639
7640 return E1000_SUCCESS;
7641 }
7642
7643
7644 /*****************************************************************************
7645 * This function writes the command header after does the checksum calculation.
7646 *
7647 * returns - E1000_SUCCESS for success.
7648 ****************************************************************************/
7649 static int32_t
7650 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7651 struct e1000_host_mng_command_header * hdr)
7652 {
7653 uint16_t i;
7654 uint8_t sum;
7655 uint8_t *buffer;
7656
7657 /* Write the whole command header structure which includes sum of
7658 * the buffer */
7659
7660 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7661
7662 sum = hdr->checksum;
7663 hdr->checksum = 0;
7664
7665 buffer = (uint8_t *) hdr;
7666 i = length;
7667 while (i--)
7668 sum += buffer[i];
7669
7670 hdr->checksum = 0 - sum;
7671
7672 length >>= 2;
7673 /* The device driver writes the relevant command block into the ram area. */
7674 for (i = 0; i < length; i++) {
7675 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7676 E1000_WRITE_FLUSH(hw);
7677 }
7678
7679 return E1000_SUCCESS;
7680 }
7681
7682
7683 /*****************************************************************************
7684 * This function indicates to ARC that a new command is pending which completes
7685 * one write operation by the driver.
7686 *
7687 * returns - E1000_SUCCESS for success.
7688 ****************************************************************************/
7689 static int32_t
7690 e1000_mng_write_commit(struct e1000_hw * hw)
7691 {
7692 uint32_t hicr;
7693
7694 hicr = E1000_READ_REG(hw, HICR);
7695 /* Setting this bit tells the ARC that a new command is pending. */
7696 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7697
7698 return E1000_SUCCESS;
7699 }
7700
7701
7702 /*****************************************************************************
7703 * This function checks the mode of the firmware.
7704 *
7705 * returns - TRUE when the mode is IAMT or FALSE.
7706 ****************************************************************************/
7707 boolean_t
7708 e1000_check_mng_mode(struct e1000_hw *hw)
7709 {
7710 uint32_t fwsm;
7711
7712 fwsm = E1000_READ_REG(hw, FWSM);
7713
7714 if (hw->mac_type == e1000_ich8lan) {
7715 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7716 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7717 return TRUE;
7718 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7719 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7720 return TRUE;
7721
7722 return FALSE;
7723 }
7724
7725
7726 /*****************************************************************************
7727 * This function writes the dhcp info .
7728 ****************************************************************************/
7729 int32_t
7730 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7731 uint16_t length)
7732 {
7733 int32_t ret_val;
7734 struct e1000_host_mng_command_header hdr;
7735
7736 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7737 hdr.command_length = length;
7738 hdr.reserved1 = 0;
7739 hdr.reserved2 = 0;
7740 hdr.checksum = 0;
7741
7742 ret_val = e1000_mng_enable_host_if(hw);
7743 if (ret_val == E1000_SUCCESS) {
7744 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7745 &(hdr.checksum));
7746 if (ret_val == E1000_SUCCESS) {
7747 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7748 if (ret_val == E1000_SUCCESS)
7749 ret_val = e1000_mng_write_commit(hw);
7750 }
7751 }
7752 return ret_val;
7753 }
7754
7755
7756 /*****************************************************************************
7757 * This function calculates the checksum.
7758 *
7759 * returns - checksum of buffer contents.
7760 ****************************************************************************/
7761 static uint8_t
7762 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7763 {
7764 uint8_t sum = 0;
7765 uint32_t i;
7766
7767 if (!buffer)
7768 return 0;
7769
7770 for (i=0; i < length; i++)
7771 sum += buffer[i];
7772
7773 return (uint8_t) (0 - sum);
7774 }
7775
7776 /*****************************************************************************
7777 * This function checks whether tx pkt filtering needs to be enabled or not.
7778 *
7779 * returns - TRUE for packet filtering or FALSE.
7780 ****************************************************************************/
7781 boolean_t
7782 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7783 {
7784 /* called in init as well as watchdog timer functions */
7785
7786 int32_t ret_val, checksum;
7787 boolean_t tx_filter = FALSE;
7788 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7789 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7790
7791 if (e1000_check_mng_mode(hw)) {
7792 ret_val = e1000_mng_enable_host_if(hw);
7793 if (ret_val == E1000_SUCCESS) {
7794 ret_val = e1000_host_if_read_cookie(hw, buffer);
7795 if (ret_val == E1000_SUCCESS) {
7796 checksum = hdr->checksum;
7797 hdr->checksum = 0;
7798 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7799 checksum == e1000_calculate_mng_checksum((char *)buffer,
7800 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7801 if (hdr->status &
7802 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7803 tx_filter = TRUE;
7804 } else
7805 tx_filter = TRUE;
7806 } else
7807 tx_filter = TRUE;
7808 }
7809 }
7810
7811 hw->tx_pkt_filtering = tx_filter;
7812 return tx_filter;
7813 }
7814
7815 /******************************************************************************
7816 * Verifies the hardware needs to allow ARPs to be processed by the host
7817 *
7818 * hw - Struct containing variables accessed by shared code
7819 *
7820 * returns: - TRUE/FALSE
7821 *
7822 *****************************************************************************/
7823 uint32_t
7824 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7825 {
7826 uint32_t manc;
7827 uint32_t fwsm, factps;
7828
7829 if (hw->asf_firmware_present) {
7830 manc = E1000_READ_REG(hw, MANC);
7831
7832 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7833 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7834 return FALSE;
7835 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7836 fwsm = E1000_READ_REG(hw, FWSM);
7837 factps = E1000_READ_REG(hw, FACTPS);
7838
7839 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7840 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7841 return TRUE;
7842 } else
7843 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7844 return TRUE;
7845 }
7846 return FALSE;
7847 }
7848
7849 static int32_t
7850 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7851 {
7852 int32_t ret_val;
7853 uint16_t mii_status_reg;
7854 uint16_t i;
7855
7856 /* Polarity reversal workaround for forced 10F/10H links. */
7857
7858 /* Disable the transmitter on the PHY */
7859
7860 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7861 if (ret_val)
7862 return ret_val;
7863 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7864 if (ret_val)
7865 return ret_val;
7866
7867 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7868 if (ret_val)
7869 return ret_val;
7870
7871 /* This loop will early-out if the NO link condition has been met. */
7872 for (i = PHY_FORCE_TIME; i > 0; i--) {
7873 /* Read the MII Status Register and wait for Link Status bit
7874 * to be clear.
7875 */
7876
7877 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7878 if (ret_val)
7879 return ret_val;
7880
7881 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7882 if (ret_val)
7883 return ret_val;
7884
7885 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7886 mdelay(100);
7887 }
7888
7889 /* Recommended delay time after link has been lost */
7890 mdelay(1000);
7891
7892 /* Now we will re-enable th transmitter on the PHY */
7893
7894 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7895 if (ret_val)
7896 return ret_val;
7897 mdelay(50);
7898 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7899 if (ret_val)
7900 return ret_val;
7901 mdelay(50);
7902 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7903 if (ret_val)
7904 return ret_val;
7905 mdelay(50);
7906 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7907 if (ret_val)
7908 return ret_val;
7909
7910 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7911 if (ret_val)
7912 return ret_val;
7913
7914 /* This loop will early-out if the link condition has been met. */
7915 for (i = PHY_FORCE_TIME; i > 0; i--) {
7916 /* Read the MII Status Register and wait for Link Status bit
7917 * to be set.
7918 */
7919
7920 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7921 if (ret_val)
7922 return ret_val;
7923
7924 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7925 if (ret_val)
7926 return ret_val;
7927
7928 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7929 mdelay(100);
7930 }
7931 return E1000_SUCCESS;
7932 }
7933
7934 /***************************************************************************
7935 *
7936 * Disables PCI-Express master access.
7937 *
7938 * hw: Struct containing variables accessed by shared code
7939 *
7940 * returns: - none.
7941 *
7942 ***************************************************************************/
7943 static void
7944 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7945 {
7946 uint32_t ctrl;
7947
7948 DEBUGFUNC("e1000_set_pci_express_master_disable");
7949
7950 if (hw->bus_type != e1000_bus_type_pci_express)
7951 return;
7952
7953 ctrl = E1000_READ_REG(hw, CTRL);
7954 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7955 E1000_WRITE_REG(hw, CTRL, ctrl);
7956 }
7957
7958 /*******************************************************************************
7959 *
7960 * Disables PCI-Express master access and verifies there are no pending requests
7961 *
7962 * hw: Struct containing variables accessed by shared code
7963 *
7964 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7965 * caused the master requests to be disabled.
7966 * E1000_SUCCESS master requests disabled.
7967 *
7968 ******************************************************************************/
7969 int32_t
7970 e1000_disable_pciex_master(struct e1000_hw *hw)
7971 {
7972 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7973
7974 DEBUGFUNC("e1000_disable_pciex_master");
7975
7976 if (hw->bus_type != e1000_bus_type_pci_express)
7977 return E1000_SUCCESS;
7978
7979 e1000_set_pci_express_master_disable(hw);
7980
7981 while (timeout) {
7982 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7983 break;
7984 else
7985 udelay(100);
7986 timeout--;
7987 }
7988
7989 if (!timeout) {
7990 DEBUGOUT("Master requests are pending.\n");
7991 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7992 }
7993
7994 return E1000_SUCCESS;
7995 }
7996
7997 /*******************************************************************************
7998 *
7999 * Check for EEPROM Auto Read bit done.
8000 *
8001 * hw: Struct containing variables accessed by shared code
8002 *
8003 * returns: - E1000_ERR_RESET if fail to reset MAC
8004 * E1000_SUCCESS at any other case.
8005 *
8006 ******************************************************************************/
8007 static int32_t
8008 e1000_get_auto_rd_done(struct e1000_hw *hw)
8009 {
8010 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
8011
8012 DEBUGFUNC("e1000_get_auto_rd_done");
8013
8014 switch (hw->mac_type) {
8015 default:
8016 msleep(5);
8017 break;
8018 case e1000_82571:
8019 case e1000_82572:
8020 case e1000_82573:
8021 case e1000_80003es2lan:
8022 case e1000_ich8lan:
8023 while (timeout) {
8024 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8025 break;
8026 else msleep(1);
8027 timeout--;
8028 }
8029
8030 if (!timeout) {
8031 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8032 return -E1000_ERR_RESET;
8033 }
8034 break;
8035 }
8036
8037 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8038 * Need to wait for PHY configuration completion before accessing NVM
8039 * and PHY. */
8040 if (hw->mac_type == e1000_82573)
8041 msleep(25);
8042
8043 return E1000_SUCCESS;
8044 }
8045
8046 /***************************************************************************
8047 * Checks if the PHY configuration is done
8048 *
8049 * hw: Struct containing variables accessed by shared code
8050 *
8051 * returns: - E1000_ERR_RESET if fail to reset MAC
8052 * E1000_SUCCESS at any other case.
8053 *
8054 ***************************************************************************/
8055 static int32_t
8056 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8057 {
8058 int32_t timeout = PHY_CFG_TIMEOUT;
8059 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8060
8061 DEBUGFUNC("e1000_get_phy_cfg_done");
8062
8063 switch (hw->mac_type) {
8064 default:
8065 mdelay(10);
8066 break;
8067 case e1000_80003es2lan:
8068 /* Separate *_CFG_DONE_* bit for each port */
8069 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8070 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8071 /* Fall Through */
8072 case e1000_82571:
8073 case e1000_82572:
8074 while (timeout) {
8075 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8076 break;
8077 else
8078 msleep(1);
8079 timeout--;
8080 }
8081 if (!timeout) {
8082 DEBUGOUT("MNG configuration cycle has not completed.\n");
8083 return -E1000_ERR_RESET;
8084 }
8085 break;
8086 }
8087
8088 return E1000_SUCCESS;
8089 }
8090
8091 /***************************************************************************
8092 *
8093 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8094 * adapter or Eeprom access.
8095 *
8096 * hw: Struct containing variables accessed by shared code
8097 *
8098 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8099 * E1000_SUCCESS at any other case.
8100 *
8101 ***************************************************************************/
8102 static int32_t
8103 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8104 {
8105 int32_t timeout;
8106 uint32_t swsm;
8107
8108 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8109
8110 if (!hw->eeprom_semaphore_present)
8111 return E1000_SUCCESS;
8112
8113 if (hw->mac_type == e1000_80003es2lan) {
8114 /* Get the SW semaphore. */
8115 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8116 return -E1000_ERR_EEPROM;
8117 }
8118
8119 /* Get the FW semaphore. */
8120 timeout = hw->eeprom.word_size + 1;
8121 while (timeout) {
8122 swsm = E1000_READ_REG(hw, SWSM);
8123 swsm |= E1000_SWSM_SWESMBI;
8124 E1000_WRITE_REG(hw, SWSM, swsm);
8125 /* if we managed to set the bit we got the semaphore. */
8126 swsm = E1000_READ_REG(hw, SWSM);
8127 if (swsm & E1000_SWSM_SWESMBI)
8128 break;
8129
8130 udelay(50);
8131 timeout--;
8132 }
8133
8134 if (!timeout) {
8135 /* Release semaphores */
8136 e1000_put_hw_eeprom_semaphore(hw);
8137 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8138 return -E1000_ERR_EEPROM;
8139 }
8140
8141 return E1000_SUCCESS;
8142 }
8143
8144 /***************************************************************************
8145 * This function clears HW semaphore bits.
8146 *
8147 * hw: Struct containing variables accessed by shared code
8148 *
8149 * returns: - None.
8150 *
8151 ***************************************************************************/
8152 static void
8153 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8154 {
8155 uint32_t swsm;
8156
8157 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8158
8159 if (!hw->eeprom_semaphore_present)
8160 return;
8161
8162 swsm = E1000_READ_REG(hw, SWSM);
8163 if (hw->mac_type == e1000_80003es2lan) {
8164 /* Release both semaphores. */
8165 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8166 } else
8167 swsm &= ~(E1000_SWSM_SWESMBI);
8168 E1000_WRITE_REG(hw, SWSM, swsm);
8169 }
8170
8171 /***************************************************************************
8172 *
8173 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8174 *
8175 * hw: Struct containing variables accessed by shared code
8176 *
8177 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8178 * E1000_SUCCESS at any other case.
8179 *
8180 ***************************************************************************/
8181 static int32_t
8182 e1000_get_software_semaphore(struct e1000_hw *hw)
8183 {
8184 int32_t timeout = hw->eeprom.word_size + 1;
8185 uint32_t swsm;
8186
8187 DEBUGFUNC("e1000_get_software_semaphore");
8188
8189 if (hw->mac_type != e1000_80003es2lan) {
8190 return E1000_SUCCESS;
8191 }
8192
8193 while (timeout) {
8194 swsm = E1000_READ_REG(hw, SWSM);
8195 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8196 if (!(swsm & E1000_SWSM_SMBI))
8197 break;
8198 mdelay(1);
8199 timeout--;
8200 }
8201
8202 if (!timeout) {
8203 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8204 return -E1000_ERR_RESET;
8205 }
8206
8207 return E1000_SUCCESS;
8208 }
8209
8210 /***************************************************************************
8211 *
8212 * Release semaphore bit (SMBI).
8213 *
8214 * hw: Struct containing variables accessed by shared code
8215 *
8216 ***************************************************************************/
8217 static void
8218 e1000_release_software_semaphore(struct e1000_hw *hw)
8219 {
8220 uint32_t swsm;
8221
8222 DEBUGFUNC("e1000_release_software_semaphore");
8223
8224 if (hw->mac_type != e1000_80003es2lan) {
8225 return;
8226 }
8227
8228 swsm = E1000_READ_REG(hw, SWSM);
8229 /* Release the SW semaphores.*/
8230 swsm &= ~E1000_SWSM_SMBI;
8231 E1000_WRITE_REG(hw, SWSM, swsm);
8232 }
8233
8234 /******************************************************************************
8235 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8236 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8237 * the caller to figure out how to deal with it.
8238 *
8239 * hw - Struct containing variables accessed by shared code
8240 *
8241 * returns: - E1000_BLK_PHY_RESET
8242 * E1000_SUCCESS
8243 *
8244 *****************************************************************************/
8245 int32_t
8246 e1000_check_phy_reset_block(struct e1000_hw *hw)
8247 {
8248 uint32_t manc = 0;
8249 uint32_t fwsm = 0;
8250
8251 if (hw->mac_type == e1000_ich8lan) {
8252 fwsm = E1000_READ_REG(hw, FWSM);
8253 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8254 : E1000_BLK_PHY_RESET;
8255 }
8256
8257 if (hw->mac_type > e1000_82547_rev_2)
8258 manc = E1000_READ_REG(hw, MANC);
8259 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8260 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8261 }
8262
8263 static uint8_t
8264 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8265 {
8266 uint32_t fwsm;
8267
8268 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8269 * may not be provided a DMA clock when no manageability features are
8270 * enabled. We do not want to perform any reads/writes to these registers
8271 * if this is the case. We read FWSM to determine the manageability mode.
8272 */
8273 switch (hw->mac_type) {
8274 case e1000_82571:
8275 case e1000_82572:
8276 case e1000_82573:
8277 case e1000_80003es2lan:
8278 fwsm = E1000_READ_REG(hw, FWSM);
8279 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8280 return TRUE;
8281 break;
8282 case e1000_ich8lan:
8283 return TRUE;
8284 default:
8285 break;
8286 }
8287 return FALSE;
8288 }
8289
8290
8291 /******************************************************************************
8292 * Configure PCI-Ex no-snoop
8293 *
8294 * hw - Struct containing variables accessed by shared code.
8295 * no_snoop - Bitmap of no-snoop events.
8296 *
8297 * returns: E1000_SUCCESS
8298 *
8299 *****************************************************************************/
8300 static int32_t
8301 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8302 {
8303 uint32_t gcr_reg = 0;
8304
8305 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8306
8307 if (hw->bus_type == e1000_bus_type_unknown)
8308 e1000_get_bus_info(hw);
8309
8310 if (hw->bus_type != e1000_bus_type_pci_express)
8311 return E1000_SUCCESS;
8312
8313 if (no_snoop) {
8314 gcr_reg = E1000_READ_REG(hw, GCR);
8315 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8316 gcr_reg |= no_snoop;
8317 E1000_WRITE_REG(hw, GCR, gcr_reg);
8318 }
8319 if (hw->mac_type == e1000_ich8lan) {
8320 uint32_t ctrl_ext;
8321
8322 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8323
8324 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8325 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8326 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8327 }
8328
8329 return E1000_SUCCESS;
8330 }
8331
8332 /***************************************************************************
8333 *
8334 * Get software semaphore FLAG bit (SWFLAG).
8335 * SWFLAG is used to synchronize the access to all shared resource between
8336 * SW, FW and HW.
8337 *
8338 * hw: Struct containing variables accessed by shared code
8339 *
8340 ***************************************************************************/
8341 static int32_t
8342 e1000_get_software_flag(struct e1000_hw *hw)
8343 {
8344 int32_t timeout = PHY_CFG_TIMEOUT;
8345 uint32_t extcnf_ctrl;
8346
8347 DEBUGFUNC("e1000_get_software_flag");
8348
8349 if (hw->mac_type == e1000_ich8lan) {
8350 while (timeout) {
8351 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8352 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8353 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8354
8355 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8356 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8357 break;
8358 mdelay(1);
8359 timeout--;
8360 }
8361
8362 if (!timeout) {
8363 DEBUGOUT("FW or HW locks the resource too long.\n");
8364 return -E1000_ERR_CONFIG;
8365 }
8366 }
8367
8368 return E1000_SUCCESS;
8369 }
8370
8371 /***************************************************************************
8372 *
8373 * Release software semaphore FLAG bit (SWFLAG).
8374 * SWFLAG is used to synchronize the access to all shared resource between
8375 * SW, FW and HW.
8376 *
8377 * hw: Struct containing variables accessed by shared code
8378 *
8379 ***************************************************************************/
8380 static void
8381 e1000_release_software_flag(struct e1000_hw *hw)
8382 {
8383 uint32_t extcnf_ctrl;
8384
8385 DEBUGFUNC("e1000_release_software_flag");
8386
8387 if (hw->mac_type == e1000_ich8lan) {
8388 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8389 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8390 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8391 }
8392
8393 return;
8394 }
8395
8396 /******************************************************************************
8397 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8398 * register.
8399 *
8400 * hw - Struct containing variables accessed by shared code
8401 * offset - offset of word in the EEPROM to read
8402 * data - word read from the EEPROM
8403 * words - number of words to read
8404 *****************************************************************************/
8405 static int32_t
8406 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8407 uint16_t *data)
8408 {
8409 int32_t error = E1000_SUCCESS;
8410 uint32_t flash_bank = 0;
8411 uint32_t act_offset = 0;
8412 uint32_t bank_offset = 0;
8413 uint16_t word = 0;
8414 uint16_t i = 0;
8415
8416 /* We need to know which is the valid flash bank. In the event
8417 * that we didn't allocate eeprom_shadow_ram, we may not be
8418 * managing flash_bank. So it cannot be trusted and needs
8419 * to be updated with each read.
8420 */
8421 /* Value of bit 22 corresponds to the flash bank we're on. */
8422 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8423
8424 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8425 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8426
8427 error = e1000_get_software_flag(hw);
8428 if (error != E1000_SUCCESS)
8429 return error;
8430
8431 for (i = 0; i < words; i++) {
8432 if (hw->eeprom_shadow_ram != NULL &&
8433 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8434 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8435 } else {
8436 /* The NVM part needs a byte offset, hence * 2 */
8437 act_offset = bank_offset + ((offset + i) * 2);
8438 error = e1000_read_ich8_word(hw, act_offset, &word);
8439 if (error != E1000_SUCCESS)
8440 break;
8441 data[i] = word;
8442 }
8443 }
8444
8445 e1000_release_software_flag(hw);
8446
8447 return error;
8448 }
8449
8450 /******************************************************************************
8451 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8452 * register. Actually, writes are written to the shadow ram cache in the hw
8453 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8454 * the NVM, which occurs when the NVM checksum is updated.
8455 *
8456 * hw - Struct containing variables accessed by shared code
8457 * offset - offset of word in the EEPROM to write
8458 * words - number of words to write
8459 * data - words to write to the EEPROM
8460 *****************************************************************************/
8461 static int32_t
8462 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8463 uint16_t *data)
8464 {
8465 uint32_t i = 0;
8466 int32_t error = E1000_SUCCESS;
8467
8468 error = e1000_get_software_flag(hw);
8469 if (error != E1000_SUCCESS)
8470 return error;
8471
8472 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8473 * allocated. Subsequent reads to the modified words are read from
8474 * this cached structure as well. Writes will only go into this
8475 * cached structure unless it's followed by a call to
8476 * e1000_update_eeprom_checksum() where it will commit the changes
8477 * and clear the "modified" field.
8478 */
8479 if (hw->eeprom_shadow_ram != NULL) {
8480 for (i = 0; i < words; i++) {
8481 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8482 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8483 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8484 } else {
8485 error = -E1000_ERR_EEPROM;
8486 break;
8487 }
8488 }
8489 } else {
8490 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8491 * as they don't perform any NVM writes. An attempt in doing so
8492 * will result in this error.
8493 */
8494 error = -E1000_ERR_EEPROM;
8495 }
8496
8497 e1000_release_software_flag(hw);
8498
8499 return error;
8500 }
8501
8502 /******************************************************************************
8503 * This function does initial flash setup so that a new read/write/erase cycle
8504 * can be started.
8505 *
8506 * hw - The pointer to the hw structure
8507 ****************************************************************************/
8508 static int32_t
8509 e1000_ich8_cycle_init(struct e1000_hw *hw)
8510 {
8511 union ich8_hws_flash_status hsfsts;
8512 int32_t error = E1000_ERR_EEPROM;
8513 int32_t i = 0;
8514
8515 DEBUGFUNC("e1000_ich8_cycle_init");
8516
8517 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8518
8519 /* May be check the Flash Des Valid bit in Hw status */
8520 if (hsfsts.hsf_status.fldesvalid == 0) {
8521 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8522 return error;
8523 }
8524
8525 /* Clear FCERR in Hw status by writing 1 */
8526 /* Clear DAEL in Hw status by writing a 1 */
8527 hsfsts.hsf_status.flcerr = 1;
8528 hsfsts.hsf_status.dael = 1;
8529
8530 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8531
8532 /* Either we should have a hardware SPI cycle in progress bit to check
8533 * against, in order to start a new cycle or FDONE bit should be changed
8534 * in the hardware so that it is 1 after harware reset, which can then be
8535 * used as an indication whether a cycle is in progress or has been
8536 * completed .. we should also have some software semaphore mechanism to
8537 * guard FDONE or the cycle in progress bit so that two threads access to
8538 * those bits can be sequentiallized or a way so that 2 threads dont
8539 * start the cycle at the same time */
8540
8541 if (hsfsts.hsf_status.flcinprog == 0) {
8542 /* There is no cycle running at present, so we can start a cycle */
8543 /* Begin by setting Flash Cycle Done. */
8544 hsfsts.hsf_status.flcdone = 1;
8545 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8546 error = E1000_SUCCESS;
8547 } else {
8548 /* otherwise poll for sometime so the current cycle has a chance
8549 * to end before giving up. */
8550 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8551 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8552 if (hsfsts.hsf_status.flcinprog == 0) {
8553 error = E1000_SUCCESS;
8554 break;
8555 }
8556 udelay(1);
8557 }
8558 if (error == E1000_SUCCESS) {
8559 /* Successful in waiting for previous cycle to timeout,
8560 * now set the Flash Cycle Done. */
8561 hsfsts.hsf_status.flcdone = 1;
8562 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8563 } else {
8564 DEBUGOUT("Flash controller busy, cannot get access");
8565 }
8566 }
8567 return error;
8568 }
8569
8570 /******************************************************************************
8571 * This function starts a flash cycle and waits for its completion
8572 *
8573 * hw - The pointer to the hw structure
8574 ****************************************************************************/
8575 static int32_t
8576 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8577 {
8578 union ich8_hws_flash_ctrl hsflctl;
8579 union ich8_hws_flash_status hsfsts;
8580 int32_t error = E1000_ERR_EEPROM;
8581 uint32_t i = 0;
8582
8583 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8584 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8585 hsflctl.hsf_ctrl.flcgo = 1;
8586 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8587
8588 /* wait till FDONE bit is set to 1 */
8589 do {
8590 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8591 if (hsfsts.hsf_status.flcdone == 1)
8592 break;
8593 udelay(1);
8594 i++;
8595 } while (i < timeout);
8596 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8597 error = E1000_SUCCESS;
8598 }
8599 return error;
8600 }
8601
8602 /******************************************************************************
8603 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8604 *
8605 * hw - The pointer to the hw structure
8606 * index - The index of the byte or word to read.
8607 * size - Size of data to read, 1=byte 2=word
8608 * data - Pointer to the word to store the value read.
8609 *****************************************************************************/
8610 static int32_t
8611 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8612 uint32_t size, uint16_t* data)
8613 {
8614 union ich8_hws_flash_status hsfsts;
8615 union ich8_hws_flash_ctrl hsflctl;
8616 uint32_t flash_linear_address;
8617 uint32_t flash_data = 0;
8618 int32_t error = -E1000_ERR_EEPROM;
8619 int32_t count = 0;
8620
8621 DEBUGFUNC("e1000_read_ich8_data");
8622
8623 if (size < 1 || size > 2 || data == 0x0 ||
8624 index > ICH_FLASH_LINEAR_ADDR_MASK)
8625 return error;
8626
8627 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8628 hw->flash_base_addr;
8629
8630 do {
8631 udelay(1);
8632 /* Steps */
8633 error = e1000_ich8_cycle_init(hw);
8634 if (error != E1000_SUCCESS)
8635 break;
8636
8637 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8638 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8639 hsflctl.hsf_ctrl.fldbcount = size - 1;
8640 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8641 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8642
8643 /* Write the last 24 bits of index into Flash Linear address field in
8644 * Flash Address */
8645 /* TODO: TBD maybe check the index against the size of flash */
8646
8647 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8648
8649 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8650
8651 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8652 * sequence a few more times, else read in (shift in) the Flash Data0,
8653 * the order is least significant byte first msb to lsb */
8654 if (error == E1000_SUCCESS) {
8655 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8656 if (size == 1) {
8657 *data = (uint8_t)(flash_data & 0x000000FF);
8658 } else if (size == 2) {
8659 *data = (uint16_t)(flash_data & 0x0000FFFF);
8660 }
8661 break;
8662 } else {
8663 /* If we've gotten here, then things are probably completely hosed,
8664 * but if the error condition is detected, it won't hurt to give
8665 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8666 */
8667 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8668 if (hsfsts.hsf_status.flcerr == 1) {
8669 /* Repeat for some time before giving up. */
8670 continue;
8671 } else if (hsfsts.hsf_status.flcdone == 0) {
8672 DEBUGOUT("Timeout error - flash cycle did not complete.");
8673 break;
8674 }
8675 }
8676 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8677
8678 return error;
8679 }
8680
8681 /******************************************************************************
8682 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8683 *
8684 * hw - The pointer to the hw structure
8685 * index - The index of the byte/word to read.
8686 * size - Size of data to read, 1=byte 2=word
8687 * data - The byte(s) to write to the NVM.
8688 *****************************************************************************/
8689 static int32_t
8690 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8691 uint16_t data)
8692 {
8693 union ich8_hws_flash_status hsfsts;
8694 union ich8_hws_flash_ctrl hsflctl;
8695 uint32_t flash_linear_address;
8696 uint32_t flash_data = 0;
8697 int32_t error = -E1000_ERR_EEPROM;
8698 int32_t count = 0;
8699
8700 DEBUGFUNC("e1000_write_ich8_data");
8701
8702 if (size < 1 || size > 2 || data > size * 0xff ||
8703 index > ICH_FLASH_LINEAR_ADDR_MASK)
8704 return error;
8705
8706 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8707 hw->flash_base_addr;
8708
8709 do {
8710 udelay(1);
8711 /* Steps */
8712 error = e1000_ich8_cycle_init(hw);
8713 if (error != E1000_SUCCESS)
8714 break;
8715
8716 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8717 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8718 hsflctl.hsf_ctrl.fldbcount = size -1;
8719 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8720 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8721
8722 /* Write the last 24 bits of index into Flash Linear address field in
8723 * Flash Address */
8724 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8725
8726 if (size == 1)
8727 flash_data = (uint32_t)data & 0x00FF;
8728 else
8729 flash_data = (uint32_t)data;
8730
8731 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8732
8733 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8734 * sequence a few more times else done */
8735 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8736 if (error == E1000_SUCCESS) {
8737 break;
8738 } else {
8739 /* If we're here, then things are most likely completely hosed,
8740 * but if the error condition is detected, it won't hurt to give
8741 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8742 */
8743 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8744 if (hsfsts.hsf_status.flcerr == 1) {
8745 /* Repeat for some time before giving up. */
8746 continue;
8747 } else if (hsfsts.hsf_status.flcdone == 0) {
8748 DEBUGOUT("Timeout error - flash cycle did not complete.");
8749 break;
8750 }
8751 }
8752 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8753
8754 return error;
8755 }
8756
8757 /******************************************************************************
8758 * Reads a single byte from the NVM using the ICH8 flash access registers.
8759 *
8760 * hw - pointer to e1000_hw structure
8761 * index - The index of the byte to read.
8762 * data - Pointer to a byte to store the value read.
8763 *****************************************************************************/
8764 static int32_t
8765 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8766 {
8767 int32_t status = E1000_SUCCESS;
8768 uint16_t word = 0;
8769
8770 status = e1000_read_ich8_data(hw, index, 1, &word);
8771 if (status == E1000_SUCCESS) {
8772 *data = (uint8_t)word;
8773 }
8774
8775 return status;
8776 }
8777
8778 /******************************************************************************
8779 * Writes a single byte to the NVM using the ICH8 flash access registers.
8780 * Performs verification by reading back the value and then going through
8781 * a retry algorithm before giving up.
8782 *
8783 * hw - pointer to e1000_hw structure
8784 * index - The index of the byte to write.
8785 * byte - The byte to write to the NVM.
8786 *****************************************************************************/
8787 static int32_t
8788 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8789 {
8790 int32_t error = E1000_SUCCESS;
8791 int32_t program_retries = 0;
8792
8793 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8794
8795 error = e1000_write_ich8_byte(hw, index, byte);
8796
8797 if (error != E1000_SUCCESS) {
8798 for (program_retries = 0; program_retries < 100; program_retries++) {
8799 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8800 error = e1000_write_ich8_byte(hw, index, byte);
8801 udelay(100);
8802 if (error == E1000_SUCCESS)
8803 break;
8804 }
8805 }
8806
8807 if (program_retries == 100)
8808 error = E1000_ERR_EEPROM;
8809
8810 return error;
8811 }
8812
8813 /******************************************************************************
8814 * Writes a single byte to the NVM using the ICH8 flash access registers.
8815 *
8816 * hw - pointer to e1000_hw structure
8817 * index - The index of the byte to read.
8818 * data - The byte to write to the NVM.
8819 *****************************************************************************/
8820 static int32_t
8821 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8822 {
8823 int32_t status = E1000_SUCCESS;
8824 uint16_t word = (uint16_t)data;
8825
8826 status = e1000_write_ich8_data(hw, index, 1, word);
8827
8828 return status;
8829 }
8830
8831 /******************************************************************************
8832 * Reads a word from the NVM using the ICH8 flash access registers.
8833 *
8834 * hw - pointer to e1000_hw structure
8835 * index - The starting byte index of the word to read.
8836 * data - Pointer to a word to store the value read.
8837 *****************************************************************************/
8838 static int32_t
8839 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8840 {
8841 int32_t status = E1000_SUCCESS;
8842 status = e1000_read_ich8_data(hw, index, 2, data);
8843 return status;
8844 }
8845
8846 /******************************************************************************
8847 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8848 * based.
8849 *
8850 * hw - pointer to e1000_hw structure
8851 * bank - 0 for first bank, 1 for second bank
8852 *
8853 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8854 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8855 * bank size may be 4, 8 or 64 KBytes
8856 *****************************************************************************/
8857 int32_t
8858 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8859 {
8860 union ich8_hws_flash_status hsfsts;
8861 union ich8_hws_flash_ctrl hsflctl;
8862 uint32_t flash_linear_address;
8863 int32_t count = 0;
8864 int32_t error = E1000_ERR_EEPROM;
8865 int32_t iteration;
8866 int32_t sub_sector_size = 0;
8867 int32_t bank_size;
8868 int32_t j = 0;
8869 int32_t error_flag = 0;
8870
8871 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8872
8873 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8874 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8875 * consecutive sectors. The start index for the nth Hw sector can be
8876 * calculated as bank * 4096 + n * 256
8877 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8878 * The start index for the nth Hw sector can be calculated
8879 * as bank * 4096
8880 * 10: The HW sector is 8K bytes
8881 * 11: The Hw sector size is 64K bytes */
8882 if (hsfsts.hsf_status.berasesz == 0x0) {
8883 /* Hw sector size 256 */
8884 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8885 bank_size = ICH_FLASH_SECTOR_SIZE;
8886 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8887 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8888 bank_size = ICH_FLASH_SEG_SIZE_4K;
8889 iteration = 1;
8890 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8891 bank_size = ICH_FLASH_SEG_SIZE_64K;
8892 iteration = 1;
8893 } else {
8894 return error;
8895 }
8896
8897 for (j = 0; j < iteration ; j++) {
8898 do {
8899 count++;
8900 /* Steps */
8901 error = e1000_ich8_cycle_init(hw);
8902 if (error != E1000_SUCCESS) {
8903 error_flag = 1;
8904 break;
8905 }
8906
8907 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8908 * Control */
8909 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8910 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8911 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8912
8913 /* Write the last 24 bits of an index within the block into Flash
8914 * Linear address field in Flash Address. This probably needs to
8915 * be calculated here based off the on-chip erase sector size and
8916 * the software bank size (4, 8 or 64 KBytes) */
8917 flash_linear_address = bank * bank_size + j * sub_sector_size;
8918 flash_linear_address += hw->flash_base_addr;
8919 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8920
8921 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8922
8923 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8924 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8925 * sequence a few more times else Done */
8926 if (error == E1000_SUCCESS) {
8927 break;
8928 } else {
8929 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8930 if (hsfsts.hsf_status.flcerr == 1) {
8931 /* repeat for some time before giving up */
8932 continue;
8933 } else if (hsfsts.hsf_status.flcdone == 0) {
8934 error_flag = 1;
8935 break;
8936 }
8937 }
8938 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8939 if (error_flag == 1)
8940 break;
8941 }
8942 if (error_flag != 1)
8943 error = E1000_SUCCESS;
8944 return error;
8945 }
8946
8947 static int32_t
8948 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8949 uint32_t cnf_base_addr, uint32_t cnf_size)
8950 {
8951 uint32_t ret_val = E1000_SUCCESS;
8952 uint16_t word_addr, reg_data, reg_addr;
8953 uint16_t i;
8954
8955 /* cnf_base_addr is in DWORD */
8956 word_addr = (uint16_t)(cnf_base_addr << 1);
8957
8958 /* cnf_size is returned in size of dwords */
8959 for (i = 0; i < cnf_size; i++) {
8960 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8961 if (ret_val)
8962 return ret_val;
8963
8964 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8965 if (ret_val)
8966 return ret_val;
8967
8968 ret_val = e1000_get_software_flag(hw);
8969 if (ret_val != E1000_SUCCESS)
8970 return ret_val;
8971
8972 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8973
8974 e1000_release_software_flag(hw);
8975 }
8976
8977 return ret_val;
8978 }
8979
8980
8981 /******************************************************************************
8982 * This function initializes the PHY from the NVM on ICH8 platforms. This
8983 * is needed due to an issue where the NVM configuration is not properly
8984 * autoloaded after power transitions. Therefore, after each PHY reset, we
8985 * will load the configuration data out of the NVM manually.
8986 *
8987 * hw: Struct containing variables accessed by shared code
8988 *****************************************************************************/
8989 static int32_t
8990 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8991 {
8992 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8993
8994 if (hw->phy_type != e1000_phy_igp_3)
8995 return E1000_SUCCESS;
8996
8997 /* Check if SW needs configure the PHY */
8998 reg_data = E1000_READ_REG(hw, FEXTNVM);
8999 if (!(reg_data & FEXTNVM_SW_CONFIG))
9000 return E1000_SUCCESS;
9001
9002 /* Wait for basic configuration completes before proceeding*/
9003 loop = 0;
9004 do {
9005 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9006 udelay(100);
9007 loop++;
9008 } while ((!reg_data) && (loop < 50));
9009
9010 /* Clear the Init Done bit for the next init event */
9011 reg_data = E1000_READ_REG(hw, STATUS);
9012 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9013 E1000_WRITE_REG(hw, STATUS, reg_data);
9014
9015 /* Make sure HW does not configure LCD from PHY extended configuration
9016 before SW configuration */
9017 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9018 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9019 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9020 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9021 cnf_size >>= 16;
9022 if (cnf_size) {
9023 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9024 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9025 /* cnf_base_addr is in DWORD */
9026 cnf_base_addr >>= 16;
9027
9028 /* Configure LCD from extended configuration region. */
9029 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9030 cnf_size);
9031 if (ret_val)
9032 return ret_val;
9033 }
9034 }
9035
9036 return E1000_SUCCESS;
9037 }
9038
Tomato firmware and modifications.