2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
45 #define DRV_NAME "pata_scc"
46 #define DRV_VERSION "0.2"
48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
51 #define SCC_CTRL_BAR 0
52 #define SCC_BMID_BAR 1
54 /* offset of CTRL registers */
55 #define SCC_CTL_PIOSHT 0x000
56 #define SCC_CTL_PIOCT 0x004
57 #define SCC_CTL_MDMACT 0x008
58 #define SCC_CTL_MCRCST 0x00C
59 #define SCC_CTL_SDMACT 0x010
60 #define SCC_CTL_SCRCST 0x014
61 #define SCC_CTL_UDENVT 0x018
62 #define SCC_CTL_TDVHSEL 0x020
63 #define SCC_CTL_MODEREG 0x024
64 #define SCC_CTL_ECMODE 0xF00
65 #define SCC_CTL_MAEA0 0xF50
66 #define SCC_CTL_MAEC0 0xF54
67 #define SCC_CTL_CCKCTRL 0xFF0
69 /* offset of BMID registers */
70 #define SCC_DMA_CMD 0x000
71 #define SCC_DMA_STATUS 0x004
72 #define SCC_DMA_TABLE_OFS 0x008
73 #define SCC_DMA_INTMASK 0x010
74 #define SCC_DMA_INTST 0x014
75 #define SCC_DMA_PTERADD 0x018
76 #define SCC_REG_CMD_ADDR 0x020
77 #define SCC_REG_DATA 0x000
78 #define SCC_REG_ERR 0x004
79 #define SCC_REG_FEATURE 0x004
80 #define SCC_REG_NSECT 0x008
81 #define SCC_REG_LBAL 0x00C
82 #define SCC_REG_LBAM 0x010
83 #define SCC_REG_LBAH 0x014
84 #define SCC_REG_DEVICE 0x018
85 #define SCC_REG_STATUS 0x01C
86 #define SCC_REG_CMD 0x01C
87 #define SCC_REG_ALTSTATUS 0x020
90 #define TDVHSEL_MASTER 0x00000001
91 #define TDVHSEL_SLAVE 0x00000004
93 #define MODE_JCUSFEN 0x00000080
95 #define ECMODE_VALUE 0x01
97 #define CCKCTRL_ATARESET 0x00040000
98 #define CCKCTRL_BUFCNT 0x00020000
99 #define CCKCTRL_CRST 0x00010000
100 #define CCKCTRL_OCLKEN 0x00000100
101 #define CCKCTRL_ATACLKOEN 0x00000002
102 #define CCKCTRL_LCLKEN 0x00000001
104 #define QCHCD_IOS_SS 0x00000001
106 #define QCHSD_STPDIAG 0x00020000
108 #define INTMASK_MSK 0xD1000012
109 #define INTSTS_SERROR 0x80000000
110 #define INTSTS_PRERR 0x40000000
111 #define INTSTS_RERR 0x10000000
112 #define INTSTS_ICERR 0x01000000
113 #define INTSTS_BMSINT 0x00000010
114 #define INTSTS_BMHE 0x00000008
115 #define INTSTS_IOIRQS 0x00000004
116 #define INTSTS_INTRQ 0x00000002
117 #define INTSTS_ACTEINT 0x00000001
120 /* PIO transfer mode table */
122 static const unsigned long JCHSTtbl
[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
128 static const unsigned long JCHHTtbl
[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
134 static const unsigned long JCHCTtbl
[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
139 /* DMA transfer mode table */
140 /* JCHDCTM/JCHDCTS */
141 static const unsigned long JCHDCTxtbl
[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
146 /* JCSTWTM/JCSTWTS */
147 static const unsigned long JCSTWTxtbl
[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
153 static const unsigned long JCTSStbl
[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
159 static const unsigned long JCENVTtbl
[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
164 /* JCACTSELS/JCACTSELM */
165 static const unsigned long JCACTSELtbl
[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
170 static const struct pci_device_id scc_pci_tbl
[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_SCC_ATA
,
172 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
173 { } /* terminate list */
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
181 * Set PIO mode for device.
184 * None (inherited from caller).
187 static void scc_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
189 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
190 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
191 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
192 void __iomem
*piosht_port
= ctrl_base
+ SCC_CTL_PIOSHT
;
193 void __iomem
*pioct_port
= ctrl_base
+ SCC_CTL_PIOCT
;
197 reg
= in_be32(cckctrl_port
);
198 if (reg
& CCKCTRL_ATACLKOEN
)
199 offset
= 1; /* 133MHz */
201 offset
= 0; /* 100MHz */
203 reg
= JCHSTtbl
[offset
][pio
] << 16 | JCHHTtbl
[offset
][pio
];
204 out_be32(piosht_port
, reg
);
205 reg
= JCHCTtbl
[offset
][pio
];
206 out_be32(pioct_port
, reg
);
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
213 * @udma: udma mode, 0 - 6
215 * Set UDMA mode for device.
218 * None (inherited from caller).
221 static void scc_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
223 unsigned int udma
= adev
->dma_mode
;
224 unsigned int is_slave
= (adev
->devno
!= 0);
226 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
227 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
228 void __iomem
*mdmact_port
= ctrl_base
+ SCC_CTL_MDMACT
;
229 void __iomem
*mcrcst_port
= ctrl_base
+ SCC_CTL_MCRCST
;
230 void __iomem
*sdmact_port
= ctrl_base
+ SCC_CTL_SDMACT
;
231 void __iomem
*scrcst_port
= ctrl_base
+ SCC_CTL_SCRCST
;
232 void __iomem
*udenvt_port
= ctrl_base
+ SCC_CTL_UDENVT
;
233 void __iomem
*tdvhsel_port
= ctrl_base
+ SCC_CTL_TDVHSEL
;
236 if (in_be32(cckctrl_port
) & CCKCTRL_ATACLKOEN
)
237 offset
= 1; /* 133MHz */
239 offset
= 0; /* 100MHz */
241 if (speed
>= XFER_UDMA_0
)
242 idx
= speed
- XFER_UDMA_0
;
247 out_be32(sdmact_port
, JCHDCTxtbl
[offset
][idx
]);
248 out_be32(scrcst_port
, JCSTWTxtbl
[offset
][idx
]);
249 out_be32(tdvhsel_port
,
250 (in_be32(tdvhsel_port
) & ~TDVHSEL_SLAVE
) | (JCACTSELtbl
[offset
][idx
] << 2));
252 out_be32(mdmact_port
, JCHDCTxtbl
[offset
][idx
]);
253 out_be32(mcrcst_port
, JCSTWTxtbl
[offset
][idx
]);
254 out_be32(tdvhsel_port
,
255 (in_be32(tdvhsel_port
) & ~TDVHSEL_MASTER
) | JCACTSELtbl
[offset
][idx
]);
257 out_be32(udenvt_port
,
258 JCTSStbl
[offset
][idx
] << 16 | JCENVTtbl
[offset
][idx
]);
262 * scc_tf_load - send taskfile registers to host controller
263 * @ap: Port to which output is sent
264 * @tf: ATA taskfile register set
266 * Note: Original code is ata_tf_load().
269 static void scc_tf_load (struct ata_port
*ap
, const struct ata_taskfile
*tf
)
271 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
272 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
274 if (tf
->ctl
!= ap
->last_ctl
) {
275 out_be32(ioaddr
->ctl_addr
, tf
->ctl
);
276 ap
->last_ctl
= tf
->ctl
;
280 if (is_addr
&& (tf
->flags
& ATA_TFLAG_LBA48
)) {
281 out_be32(ioaddr
->feature_addr
, tf
->hob_feature
);
282 out_be32(ioaddr
->nsect_addr
, tf
->hob_nsect
);
283 out_be32(ioaddr
->lbal_addr
, tf
->hob_lbal
);
284 out_be32(ioaddr
->lbam_addr
, tf
->hob_lbam
);
285 out_be32(ioaddr
->lbah_addr
, tf
->hob_lbah
);
286 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
295 out_be32(ioaddr
->feature_addr
, tf
->feature
);
296 out_be32(ioaddr
->nsect_addr
, tf
->nsect
);
297 out_be32(ioaddr
->lbal_addr
, tf
->lbal
);
298 out_be32(ioaddr
->lbam_addr
, tf
->lbam
);
299 out_be32(ioaddr
->lbah_addr
, tf
->lbah
);
300 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
308 if (tf
->flags
& ATA_TFLAG_DEVICE
) {
309 out_be32(ioaddr
->device_addr
, tf
->device
);
310 VPRINTK("device 0x%X\n", tf
->device
);
317 * scc_check_status - Read device status reg & clear interrupt
318 * @ap: port where the device is
320 * Note: Original code is ata_check_status().
323 static u8
scc_check_status (struct ata_port
*ap
)
325 return in_be32(ap
->ioaddr
.status_addr
);
329 * scc_tf_read - input device's ATA taskfile shadow registers
330 * @ap: Port from which input is read
331 * @tf: ATA taskfile register set for storing input
333 * Note: Original code is ata_tf_read().
336 static void scc_tf_read (struct ata_port
*ap
, struct ata_taskfile
*tf
)
338 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
340 tf
->command
= scc_check_status(ap
);
341 tf
->feature
= in_be32(ioaddr
->error_addr
);
342 tf
->nsect
= in_be32(ioaddr
->nsect_addr
);
343 tf
->lbal
= in_be32(ioaddr
->lbal_addr
);
344 tf
->lbam
= in_be32(ioaddr
->lbam_addr
);
345 tf
->lbah
= in_be32(ioaddr
->lbah_addr
);
346 tf
->device
= in_be32(ioaddr
->device_addr
);
348 if (tf
->flags
& ATA_TFLAG_LBA48
) {
349 out_be32(ioaddr
->ctl_addr
, tf
->ctl
| ATA_HOB
);
350 tf
->hob_feature
= in_be32(ioaddr
->error_addr
);
351 tf
->hob_nsect
= in_be32(ioaddr
->nsect_addr
);
352 tf
->hob_lbal
= in_be32(ioaddr
->lbal_addr
);
353 tf
->hob_lbam
= in_be32(ioaddr
->lbam_addr
);
354 tf
->hob_lbah
= in_be32(ioaddr
->lbah_addr
);
355 out_be32(ioaddr
->ctl_addr
, tf
->ctl
);
356 ap
->last_ctl
= tf
->ctl
;
361 * scc_exec_command - issue ATA command to host controller
362 * @ap: port to which command is being issued
363 * @tf: ATA taskfile register set
365 * Note: Original code is ata_exec_command().
368 static void scc_exec_command (struct ata_port
*ap
,
369 const struct ata_taskfile
*tf
)
371 DPRINTK("ata%u: cmd 0x%X\n", ap
->print_id
, tf
->command
);
373 out_be32(ap
->ioaddr
.command_addr
, tf
->command
);
378 * scc_check_altstatus - Read device alternate status reg
379 * @ap: port where the device is
382 static u8
scc_check_altstatus (struct ata_port
*ap
)
384 return in_be32(ap
->ioaddr
.altstatus_addr
);
388 * scc_std_dev_select - Select device 0/1 on ATA bus
389 * @ap: ATA channel to manipulate
390 * @device: ATA device (numbered from zero) to select
392 * Note: Original code is ata_std_dev_select().
395 static void scc_std_dev_select (struct ata_port
*ap
, unsigned int device
)
400 tmp
= ATA_DEVICE_OBS
;
402 tmp
= ATA_DEVICE_OBS
| ATA_DEV1
;
404 out_be32(ap
->ioaddr
.device_addr
, tmp
);
409 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
410 * @qc: Info associated with this ATA transaction.
412 * Note: Original code is ata_bmdma_setup().
415 static void scc_bmdma_setup (struct ata_queued_cmd
*qc
)
417 struct ata_port
*ap
= qc
->ap
;
418 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
420 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
422 /* load PRD table addr */
423 out_be32(mmio
+ SCC_DMA_TABLE_OFS
, ap
->prd_dma
);
425 /* specify data direction, triple-check start bit is clear */
426 dmactl
= in_be32(mmio
+ SCC_DMA_CMD
);
427 dmactl
&= ~(ATA_DMA_WR
| ATA_DMA_START
);
429 dmactl
|= ATA_DMA_WR
;
430 out_be32(mmio
+ SCC_DMA_CMD
, dmactl
);
432 /* issue r/w command */
433 ap
->ops
->exec_command(ap
, &qc
->tf
);
437 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
438 * @qc: Info associated with this ATA transaction.
440 * Note: Original code is ata_bmdma_start().
443 static void scc_bmdma_start (struct ata_queued_cmd
*qc
)
445 struct ata_port
*ap
= qc
->ap
;
447 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
449 /* start host DMA transaction */
450 dmactl
= in_be32(mmio
+ SCC_DMA_CMD
);
451 out_be32(mmio
+ SCC_DMA_CMD
, dmactl
| ATA_DMA_START
);
455 * scc_devchk - PATA device presence detection
456 * @ap: ATA channel to examine
457 * @device: Device to examine (starting at zero)
459 * Note: Original code is ata_devchk().
462 static unsigned int scc_devchk (struct ata_port
*ap
,
465 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
468 ap
->ops
->dev_select(ap
, device
);
470 out_be32(ioaddr
->nsect_addr
, 0x55);
471 out_be32(ioaddr
->lbal_addr
, 0xaa);
473 out_be32(ioaddr
->nsect_addr
, 0xaa);
474 out_be32(ioaddr
->lbal_addr
, 0x55);
476 out_be32(ioaddr
->nsect_addr
, 0x55);
477 out_be32(ioaddr
->lbal_addr
, 0xaa);
479 nsect
= in_be32(ioaddr
->nsect_addr
);
480 lbal
= in_be32(ioaddr
->lbal_addr
);
482 if ((nsect
== 0x55) && (lbal
== 0xaa))
483 return 1; /* we found a device */
485 return 0; /* nothing found */
489 * scc_bus_post_reset - PATA device post reset
491 * Note: Original code is ata_bus_post_reset().
494 static int scc_bus_post_reset(struct ata_port
*ap
, unsigned int devmask
,
495 unsigned long deadline
)
497 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
498 unsigned int dev0
= devmask
& (1 << 0);
499 unsigned int dev1
= devmask
& (1 << 1);
502 /* if device 0 was found in ata_devchk, wait for its
506 rc
= ata_wait_ready(ap
, deadline
);
507 if (rc
&& rc
!= -ENODEV
)
511 /* if device 1 was found in ata_devchk, wait for
512 * register access, then wait for BSY to clear
517 ap
->ops
->dev_select(ap
, 1);
518 nsect
= in_be32(ioaddr
->nsect_addr
);
519 lbal
= in_be32(ioaddr
->lbal_addr
);
520 if ((nsect
== 1) && (lbal
== 1))
522 if (time_after(jiffies
, deadline
))
524 msleep(50); /* give drive a breather */
527 rc
= ata_wait_ready(ap
, deadline
);
528 if (rc
&& rc
!= -ENODEV
)
532 /* is all this really necessary? */
533 ap
->ops
->dev_select(ap
, 0);
535 ap
->ops
->dev_select(ap
, 1);
537 ap
->ops
->dev_select(ap
, 0);
543 * scc_bus_softreset - PATA device software reset
545 * Note: Original code is ata_bus_softreset().
548 static unsigned int scc_bus_softreset(struct ata_port
*ap
, unsigned int devmask
,
549 unsigned long deadline
)
551 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
553 DPRINTK("ata%u: bus reset via SRST\n", ap
->print_id
);
555 /* software reset. causes dev0 to be selected */
556 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
558 out_be32(ioaddr
->ctl_addr
, ap
->ctl
| ATA_SRST
);
560 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
562 /* spec mandates ">= 2ms" before checking status.
563 * We wait 150ms, because that was the magic delay used for
564 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
565 * between when the ATA command register is written, and then
566 * status is checked. Because waiting for "a while" before
567 * checking status is fine, post SRST, we perform this magic
568 * delay here as well.
570 * Old drivers/ide uses the 2mS rule and then waits for ready
574 /* Before we perform post reset processing we want to see if
575 * the bus shows 0xFF because the odd clown forgets the D7
578 if (scc_check_status(ap
) == 0xFF)
581 scc_bus_post_reset(ap
, devmask
, deadline
);
587 * scc_std_softreset - reset host port via ATA SRST
589 * @classes: resulting classes of attached devices
590 * @deadline: deadline jiffies for the operation
592 * Note: Original code is ata_std_softreset().
595 static int scc_std_softreset (struct ata_port
*ap
, unsigned int *classes
,
596 unsigned long deadline
)
598 unsigned int slave_possible
= ap
->flags
& ATA_FLAG_SLAVE_POSS
;
599 unsigned int devmask
= 0, err_mask
;
604 if (ata_port_offline(ap
)) {
605 classes
[0] = ATA_DEV_NONE
;
609 /* determine if device 0/1 are present */
610 if (scc_devchk(ap
, 0))
612 if (slave_possible
&& scc_devchk(ap
, 1))
615 /* select device 0 again */
616 ap
->ops
->dev_select(ap
, 0);
618 /* issue bus reset */
619 DPRINTK("about to softreset, devmask=%x\n", devmask
);
620 err_mask
= scc_bus_softreset(ap
, devmask
, deadline
);
622 ata_port_printk(ap
, KERN_ERR
, "SRST failed (err_mask=0x%x)\n",
627 /* determine by signature whether we have ATA or ATAPI devices */
628 classes
[0] = ata_dev_try_classify(ap
, 0, &err
);
629 if (slave_possible
&& err
!= 0x81)
630 classes
[1] = ata_dev_try_classify(ap
, 1, &err
);
633 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes
[0], classes
[1]);
638 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
639 * @qc: Command we are ending DMA for
642 static void scc_bmdma_stop (struct ata_queued_cmd
*qc
)
644 struct ata_port
*ap
= qc
->ap
;
645 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
646 void __iomem
*bmid_base
= ap
->host
->iomap
[SCC_BMID_BAR
];
650 reg
= in_be32(bmid_base
+ SCC_DMA_INTST
);
652 if (reg
& INTSTS_SERROR
) {
653 printk(KERN_WARNING
"%s: SERROR\n", DRV_NAME
);
654 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_SERROR
|INTSTS_BMSINT
);
655 out_be32(bmid_base
+ SCC_DMA_CMD
,
656 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
660 if (reg
& INTSTS_PRERR
) {
662 maea0
= in_be32(ctrl_base
+ SCC_CTL_MAEA0
);
663 maec0
= in_be32(ctrl_base
+ SCC_CTL_MAEC0
);
664 printk(KERN_WARNING
"%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME
, maea0
, maec0
);
665 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_PRERR
|INTSTS_BMSINT
);
666 out_be32(bmid_base
+ SCC_DMA_CMD
,
667 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
671 if (reg
& INTSTS_RERR
) {
672 printk(KERN_WARNING
"%s: Response Error\n", DRV_NAME
);
673 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_RERR
|INTSTS_BMSINT
);
674 out_be32(bmid_base
+ SCC_DMA_CMD
,
675 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
679 if (reg
& INTSTS_ICERR
) {
680 out_be32(bmid_base
+ SCC_DMA_CMD
,
681 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
682 printk(KERN_WARNING
"%s: Illegal Configuration\n", DRV_NAME
);
683 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_ICERR
|INTSTS_BMSINT
);
687 if (reg
& INTSTS_BMSINT
) {
688 unsigned int classes
;
689 unsigned long deadline
= jiffies
+ ATA_TMOUT_BOOT
;
690 printk(KERN_WARNING
"%s: Internal Bus Error\n", DRV_NAME
);
691 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_BMSINT
);
693 scc_std_softreset(ap
, &classes
, deadline
);
697 if (reg
& INTSTS_BMHE
) {
698 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_BMHE
);
702 if (reg
& INTSTS_ACTEINT
) {
703 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_ACTEINT
);
707 if (reg
& INTSTS_IOIRQS
) {
708 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_IOIRQS
);
714 /* clear start/stop bit */
715 out_be32(bmid_base
+ SCC_DMA_CMD
,
716 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
718 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
719 ata_altstatus(ap
); /* dummy read */
723 * scc_bmdma_status - Read PCI IDE BMDMA status
724 * @ap: Port associated with this ATA transaction.
727 static u8
scc_bmdma_status (struct ata_port
*ap
)
730 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
732 host_stat
= in_be32(mmio
+ SCC_DMA_STATUS
);
734 /* Workaround for PTERADD: emulate DMA_INTR when
735 * - IDE_STATUS[ERR] = 1
736 * - INT_STATUS[INTRQ] = 1
737 * - DMA_STATUS[IORACTA] = 1
739 if (!(host_stat
& ATA_DMA_INTR
)) {
740 u32 int_status
= in_be32(mmio
+ SCC_DMA_INTST
);
741 if (ata_altstatus(ap
) & ATA_ERR
&&
742 int_status
& INTSTS_INTRQ
&&
743 host_stat
& ATA_DMA_ACTIVE
)
744 host_stat
|= ATA_DMA_INTR
;
751 * scc_data_xfer - Transfer data by PIO
752 * @adev: device for this I/O
754 * @buflen: buffer length
755 * @write_data: read/write
757 * Note: Original code is ata_data_xfer().
760 static void scc_data_xfer (struct ata_device
*adev
, unsigned char *buf
,
761 unsigned int buflen
, int write_data
)
763 struct ata_port
*ap
= adev
->ap
;
764 unsigned int words
= buflen
>> 1;
766 u16
*buf16
= (u16
*) buf
;
767 void __iomem
*mmio
= ap
->ioaddr
.data_addr
;
769 /* Transfer multiple of 2 bytes */
771 for (i
= 0; i
< words
; i
++)
772 out_be32(mmio
, cpu_to_le16(buf16
[i
]));
774 for (i
= 0; i
< words
; i
++)
775 buf16
[i
] = le16_to_cpu(in_be32(mmio
));
778 /* Transfer trailing 1 byte, if any. */
779 if (unlikely(buflen
& 0x01)) {
780 u16 align_buf
[1] = { 0 };
781 unsigned char *trailing_buf
= buf
+ buflen
- 1;
784 memcpy(align_buf
, trailing_buf
, 1);
785 out_be32(mmio
, cpu_to_le16(align_buf
[0]));
787 align_buf
[0] = le16_to_cpu(in_be32(mmio
));
788 memcpy(trailing_buf
, align_buf
, 1);
794 * scc_irq_on - Enable interrupts on a port.
795 * @ap: Port on which interrupts are enabled.
797 * Note: Original code is ata_irq_on().
800 static u8
scc_irq_on (struct ata_port
*ap
)
802 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
805 ap
->ctl
&= ~ATA_NIEN
;
806 ap
->last_ctl
= ap
->ctl
;
808 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
809 tmp
= ata_wait_idle(ap
);
811 ap
->ops
->irq_clear(ap
);
817 * scc_irq_ack - Acknowledge a device interrupt.
818 * @ap: Port on which interrupts are enabled.
820 * Note: Original code is ata_irq_ack().
823 static u8
scc_irq_ack (struct ata_port
*ap
, unsigned int chk_drq
)
825 unsigned int bits
= chk_drq
? ATA_BUSY
| ATA_DRQ
: ATA_BUSY
;
826 u8 host_stat
, post_stat
, status
;
828 status
= ata_busy_wait(ap
, bits
, 1000);
831 printk(KERN_ERR
"abnormal status 0x%X\n", status
);
833 /* get controller status; clear intr, err bits */
834 host_stat
= in_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
);
835 out_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
,
836 host_stat
| ATA_DMA_INTR
| ATA_DMA_ERR
);
838 post_stat
= in_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
);
840 if (ata_msg_intr(ap
))
841 printk(KERN_INFO
"%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
843 host_stat
, post_stat
, status
);
849 * scc_bmdma_freeze - Freeze BMDMA controller port
850 * @ap: port to freeze
852 * Note: Original code is ata_bmdma_freeze().
855 static void scc_bmdma_freeze (struct ata_port
*ap
)
857 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
860 ap
->last_ctl
= ap
->ctl
;
862 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
864 /* Under certain circumstances, some controllers raise IRQ on
865 * ATA_NIEN manipulation. Also, many controllers fail to mask
866 * previously pending IRQ on ATA_NIEN assertion. Clear it.
870 ap
->ops
->irq_clear(ap
);
874 * scc_pata_prereset - prepare for reset
875 * @ap: ATA port to be reset
876 * @deadline: deadline jiffies for the operation
879 static int scc_pata_prereset(struct ata_port
*ap
, unsigned long deadline
)
881 ap
->cbl
= ATA_CBL_PATA80
;
882 return ata_std_prereset(ap
, deadline
);
886 * scc_std_postreset - standard postreset callback
887 * @ap: the target ata_port
888 * @classes: classes of attached devices
890 * Note: Original code is ata_std_postreset().
893 static void scc_std_postreset (struct ata_port
*ap
, unsigned int *classes
)
897 /* re-enable interrupts */
898 if (!ap
->ops
->error_handler
)
901 /* is double-select really necessary? */
902 if (classes
[0] != ATA_DEV_NONE
)
903 ap
->ops
->dev_select(ap
, 1);
904 if (classes
[1] != ATA_DEV_NONE
)
905 ap
->ops
->dev_select(ap
, 0);
907 /* bail out if no device is present */
908 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
909 DPRINTK("EXIT, no device\n");
913 /* set up device control */
914 if (ap
->ioaddr
.ctl_addr
)
915 out_be32(ap
->ioaddr
.ctl_addr
, ap
->ctl
);
921 * scc_error_handler - Stock error handler for BMDMA controller
922 * @ap: port to handle error for
925 static void scc_error_handler (struct ata_port
*ap
)
927 ata_bmdma_drive_eh(ap
, scc_pata_prereset
, scc_std_softreset
, NULL
,
932 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
933 * @ap: Port associated with this ATA transaction.
935 * Note: Original code is ata_bmdma_irq_clear().
938 static void scc_bmdma_irq_clear (struct ata_port
*ap
)
940 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
945 out_be32(mmio
+ SCC_DMA_STATUS
, in_be32(mmio
+ SCC_DMA_STATUS
));
949 * scc_port_start - Set port up for dma.
950 * @ap: Port to initialize
952 * Allocate space for PRD table using ata_port_start().
953 * Set PRD table address for PTERADD. (PRD Transfer End Read)
956 static int scc_port_start (struct ata_port
*ap
)
958 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
961 rc
= ata_port_start(ap
);
965 out_be32(mmio
+ SCC_DMA_PTERADD
, ap
->prd_dma
);
970 * scc_port_stop - Undo scc_port_start()
971 * @ap: Port to shut down
976 static void scc_port_stop (struct ata_port
*ap
)
978 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
980 out_be32(mmio
+ SCC_DMA_PTERADD
, 0);
983 static struct scsi_host_template scc_sht
= {
984 .module
= THIS_MODULE
,
986 .ioctl
= ata_scsi_ioctl
,
987 .queuecommand
= ata_scsi_queuecmd
,
988 .can_queue
= ATA_DEF_QUEUE
,
989 .this_id
= ATA_SHT_THIS_ID
,
990 .sg_tablesize
= LIBATA_MAX_PRD
,
991 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
992 .emulated
= ATA_SHT_EMULATED
,
993 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
994 .proc_name
= DRV_NAME
,
995 .dma_boundary
= ATA_DMA_BOUNDARY
,
996 .slave_configure
= ata_scsi_slave_config
,
997 .slave_destroy
= ata_scsi_slave_destroy
,
998 .bios_param
= ata_std_bios_param
,
1001 static const struct ata_port_operations scc_pata_ops
= {
1002 .port_disable
= ata_port_disable
,
1003 .set_piomode
= scc_set_piomode
,
1004 .set_dmamode
= scc_set_dmamode
,
1005 .mode_filter
= ata_pci_default_filter
,
1007 .tf_load
= scc_tf_load
,
1008 .tf_read
= scc_tf_read
,
1009 .exec_command
= scc_exec_command
,
1010 .check_status
= scc_check_status
,
1011 .check_altstatus
= scc_check_altstatus
,
1012 .dev_select
= scc_std_dev_select
,
1014 .bmdma_setup
= scc_bmdma_setup
,
1015 .bmdma_start
= scc_bmdma_start
,
1016 .bmdma_stop
= scc_bmdma_stop
,
1017 .bmdma_status
= scc_bmdma_status
,
1018 .data_xfer
= scc_data_xfer
,
1020 .qc_prep
= ata_qc_prep
,
1021 .qc_issue
= ata_qc_issue_prot
,
1023 .freeze
= scc_bmdma_freeze
,
1024 .error_handler
= scc_error_handler
,
1025 .post_internal_cmd
= scc_bmdma_stop
,
1027 .irq_clear
= scc_bmdma_irq_clear
,
1028 .irq_on
= scc_irq_on
,
1029 .irq_ack
= scc_irq_ack
,
1031 .port_start
= scc_port_start
,
1032 .port_stop
= scc_port_stop
,
1035 static struct ata_port_info scc_port_info
[] = {
1037 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_MMIO
| ATA_FLAG_NO_LEGACY
,
1038 .pio_mask
= 0x1f, /* pio0-4 */
1040 .udma_mask
= ATA_UDMA6
,
1041 .port_ops
= &scc_pata_ops
,
1046 * scc_reset_controller - initialize SCC PATA controller.
1049 static int scc_reset_controller(struct ata_host
*host
)
1051 void __iomem
*ctrl_base
= host
->iomap
[SCC_CTRL_BAR
];
1052 void __iomem
*bmid_base
= host
->iomap
[SCC_BMID_BAR
];
1053 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
1054 void __iomem
*mode_port
= ctrl_base
+ SCC_CTL_MODEREG
;
1055 void __iomem
*ecmode_port
= ctrl_base
+ SCC_CTL_ECMODE
;
1056 void __iomem
*intmask_port
= bmid_base
+ SCC_DMA_INTMASK
;
1057 void __iomem
*dmastatus_port
= bmid_base
+ SCC_DMA_STATUS
;
1060 out_be32(cckctrl_port
, reg
);
1061 reg
|= CCKCTRL_ATACLKOEN
;
1062 out_be32(cckctrl_port
, reg
);
1063 reg
|= CCKCTRL_LCLKEN
| CCKCTRL_OCLKEN
;
1064 out_be32(cckctrl_port
, reg
);
1065 reg
|= CCKCTRL_CRST
;
1066 out_be32(cckctrl_port
, reg
);
1069 reg
= in_be32(cckctrl_port
);
1070 if (reg
& CCKCTRL_CRST
)
1075 reg
|= CCKCTRL_ATARESET
;
1076 out_be32(cckctrl_port
, reg
);
1077 out_be32(ecmode_port
, ECMODE_VALUE
);
1078 out_be32(mode_port
, MODE_JCUSFEN
);
1079 out_be32(intmask_port
, INTMASK_MSK
);
1081 if (in_be32(dmastatus_port
) & QCHSD_STPDIAG
) {
1082 printk(KERN_WARNING
"%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME
);
1090 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1091 * @ioaddr: IO address structure to be initialized
1092 * @base: base address of BMID region
1095 static void scc_setup_ports (struct ata_ioports
*ioaddr
, void __iomem
*base
)
1097 ioaddr
->cmd_addr
= base
+ SCC_REG_CMD_ADDR
;
1098 ioaddr
->altstatus_addr
= ioaddr
->cmd_addr
+ SCC_REG_ALTSTATUS
;
1099 ioaddr
->ctl_addr
= ioaddr
->cmd_addr
+ SCC_REG_ALTSTATUS
;
1100 ioaddr
->bmdma_addr
= base
;
1101 ioaddr
->data_addr
= ioaddr
->cmd_addr
+ SCC_REG_DATA
;
1102 ioaddr
->error_addr
= ioaddr
->cmd_addr
+ SCC_REG_ERR
;
1103 ioaddr
->feature_addr
= ioaddr
->cmd_addr
+ SCC_REG_FEATURE
;
1104 ioaddr
->nsect_addr
= ioaddr
->cmd_addr
+ SCC_REG_NSECT
;
1105 ioaddr
->lbal_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAL
;
1106 ioaddr
->lbam_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAM
;
1107 ioaddr
->lbah_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAH
;
1108 ioaddr
->device_addr
= ioaddr
->cmd_addr
+ SCC_REG_DEVICE
;
1109 ioaddr
->status_addr
= ioaddr
->cmd_addr
+ SCC_REG_STATUS
;
1110 ioaddr
->command_addr
= ioaddr
->cmd_addr
+ SCC_REG_CMD
;
1113 static int scc_host_init(struct ata_host
*host
)
1115 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1118 rc
= scc_reset_controller(host
);
1122 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1125 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1129 scc_setup_ports(&host
->ports
[0]->ioaddr
, host
->iomap
[SCC_BMID_BAR
]);
1131 pci_set_master(pdev
);
1137 * scc_init_one - Register SCC PATA device with kernel services
1138 * @pdev: PCI device to register
1139 * @ent: Entry in scc_pci_tbl matching with @pdev
1142 * Inherited from PCI layer (may sleep).
1145 * Zero on success, or -ERRNO value.
1148 static int scc_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1150 static int printed_version
;
1151 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1152 const struct ata_port_info
*ppi
[] = { &scc_port_info
[board_idx
], NULL
};
1153 struct ata_host
*host
;
1156 if (!printed_version
++)
1157 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1158 "version " DRV_VERSION
"\n");
1160 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, 1);
1164 rc
= pcim_enable_device(pdev
);
1168 rc
= pcim_iomap_regions(pdev
, (1 << SCC_CTRL_BAR
) | (1 << SCC_BMID_BAR
), DRV_NAME
);
1170 pcim_pin_device(pdev
);
1173 host
->iomap
= pcim_iomap_table(pdev
);
1175 rc
= scc_host_init(host
);
1179 return ata_host_activate(host
, pdev
->irq
, ata_interrupt
, IRQF_SHARED
,
1183 static struct pci_driver scc_pci_driver
= {
1185 .id_table
= scc_pci_tbl
,
1186 .probe
= scc_init_one
,
1187 .remove
= ata_pci_remove_one
,
1189 .suspend
= ata_pci_device_suspend
,
1190 .resume
= ata_pci_device_resume
,
1194 static int __init
scc_init (void)
1198 DPRINTK("pci_register_driver\n");
1199 rc
= pci_register_driver(&scc_pci_driver
);
1207 static void __exit
scc_exit (void)
1209 pci_unregister_driver(&scc_pci_driver
);
1212 module_init(scc_init
);
1213 module_exit(scc_exit
);
1215 MODULE_AUTHOR("Toshiba corp");
1216 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1217 MODULE_LICENSE("GPL");
1218 MODULE_DEVICE_TABLE(pci
, scc_pci_tbl
);
1219 MODULE_VERSION(DRV_VERSION
);