2 * arch/sh/boards/se/7343/irq.c
5 #include <linux/init.h>
6 #include <linux/interrupt.h>
10 #include <asm/mach/se7343.h>
13 disable_intreq_irq(unsigned int irq
)
15 int bit
= irq
- OFFCHIP_IRQ_BASE
;
18 val
= ctrl_inw(PA_CPLD_IMSK
);
20 ctrl_outw(val
, PA_CPLD_IMSK
);
24 enable_intreq_irq(unsigned int irq
)
26 int bit
= irq
- OFFCHIP_IRQ_BASE
;
29 val
= ctrl_inw(PA_CPLD_IMSK
);
31 ctrl_outw(val
, PA_CPLD_IMSK
);
35 mask_and_ack_intreq_irq(unsigned int irq
)
37 disable_intreq_irq(irq
);
41 startup_intreq_irq(unsigned int irq
)
43 enable_intreq_irq(irq
);
48 shutdown_intreq_irq(unsigned int irq
)
50 disable_intreq_irq(irq
);
54 end_intreq_irq(unsigned int irq
)
56 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
57 enable_intreq_irq(irq
);
60 static struct hw_interrupt_type intreq_irq_type
= {
61 .typename
= "FPGA-IRQ",
62 .startup
= startup_intreq_irq
,
63 .shutdown
= shutdown_intreq_irq
,
64 .enable
= enable_intreq_irq
,
65 .disable
= disable_intreq_irq
,
66 .ack
= mask_and_ack_intreq_irq
,
71 make_intreq_irq(unsigned int irq
)
73 disable_irq_nosync(irq
);
74 irq_desc
[irq
].chip
= &intreq_irq_type
;
75 disable_intreq_irq(irq
);
79 shmse_irq_demux(int irq
)
84 if (irq
== IRQ5_IRQ
) {
85 /* Read status Register */
86 val
= ctrl_inw(PA_CPLD_ST
);
89 return OFFCHIP_IRQ_BASE
+ bit
- 1;
94 /* IRQ5 is multiplexed between the following sources:
98 * 4. Serial Controller
100 * We configure IRQ5 as a cascade IRQ.
102 static struct irqaction irq5
= { no_action
, 0, CPU_MASK_NONE
, "IRQ5-cascade",
105 static struct ipr_data se7343_irq5_ipr_map
[] = {
106 { IRQ5_IRQ
, IRQ5_IPR_ADDR
+2, IRQ5_IPR_POS
, IRQ5_PRIORITY
},
108 static struct ipr_data se7343_siof0_vpu_ipr_map
[] = {
109 { SIOF0_IRQ
, SIOF0_IPR_ADDR
, SIOF0_IPR_POS
, SIOF0_PRIORITY
},
110 { VPU_IRQ
, VPU_IPR_ADDR
, VPU_IPR_POS
, 8 },
112 static struct ipr_data se7343_other_ipr_map
[] = {
113 { DMTE0_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
},
114 { DMTE1_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
},
115 { DMTE2_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
},
116 { DMTE3_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
},
117 { DMTE4_IRQ
, DMA2_IPR_ADDR
, DMA2_IPR_POS
, DMA2_PRIORITY
},
118 { DMTE5_IRQ
, DMA2_IPR_ADDR
, DMA2_IPR_POS
, DMA2_PRIORITY
},
121 { IIC0_ALI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
},
122 { IIC0_TACKI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
},
123 { IIC0_WAITI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
},
124 { IIC0_DTEI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
},
126 { IIC1_ALI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
},
127 { IIC1_TACKI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
},
128 { IIC1_WAITI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
},
129 { IIC1_DTEI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
},
132 { SIOF0_IRQ
, SIOF0_IPR_ADDR
, SIOF0_IPR_POS
, SIOF0_PRIORITY
},
135 { SIU_IRQ
, SIU_IPR_ADDR
, SIU_IPR_POS
, SIU_PRIORITY
},
138 { CEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
},
139 { BEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
},
140 { VEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
},
144 { MFI_IRQ
, MFI_IPR_ADDR
, MFI_IPR_POS
, MFI_PRIORITY
},
147 { LCDC_IRQ
, LCDC_IPR_ADDR
, LCDC_IPR_POS
, LCDC_PRIORITY
},
151 * Initialize IRQ setting
154 init_7343se_IRQ(void)
156 /* Setup Multiplexed interrupts */
157 ctrl_outw(8, PA_CPLD_MODESET
); /* Set all CPLD interrupts to active
160 /* Mask all CPLD controller interrupts */
161 ctrl_outw(0x0fff, PA_CPLD_IMSK
);
163 /* PC Card interrupts */
164 make_intreq_irq(PC_IRQ0
);
165 make_intreq_irq(PC_IRQ1
);
166 make_intreq_irq(PC_IRQ2
);
167 make_intreq_irq(PC_IRQ3
);
169 /* Extension Slot Interrupts */
170 make_intreq_irq(EXT_IRQ0
);
171 make_intreq_irq(EXT_IRQ1
);
172 make_intreq_irq(EXT_IRQ2
);
173 make_intreq_irq(EXT_IRQ3
);
175 /* USB Controller interrupts */
176 make_intreq_irq(USB_IRQ0
);
177 make_intreq_irq(USB_IRQ1
);
179 /* Serial Controller interrupts */
180 make_intreq_irq(UART_IRQ0
);
181 make_intreq_irq(UART_IRQ1
);
183 /* Setup all external interrupts to be active low */
184 ctrl_outw(0xaaaa, INTC_ICR1
);
186 make_ipr_irq(se7343_irq5_ipr_map
, ARRAY_SIZE(se7343_irq5_ipr_map
));
188 setup_irq(IRQ5_IRQ
, &irq5
);
189 /* Set port control to use IRQ5 */
190 *(u16
*)0xA4050108 &= ~0xc;
192 make_ipr_irq(se7343_siof0_vpu_ipr_map
, ARRAY_SIZE(se7343_siof0_vpu_ipr_map
));
194 ctrl_outb(0x0f, INTC_IMCR5
); /* enable SCIF IRQ */
196 make_ipr_irq(se7343_other_ipr_map
, ARRAY_SIZE(se7343_other_ipr_map
));
198 ctrl_outw(0x2000, PA_MRSHPC
+ 0x0c); /* mrshpc irq enable */