release/src-rt-6.x/linux/linux-2.6/arch/ppc/platforms/4xx/ebony.c

   1 /*
   2  * Ebony board specific routines
   3  *
   4  * Matt Porter <mporter@kernel.crashing.org>
   5  * Copyright 2002-2005 MontaVista Software Inc.
   6  *
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  * Copyright (c) 2003-2005 Zultys Technologies
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/types.h>
  24 #include <linux/major.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/console.h>
  27 #include <linux/delay.h>
  28 #include <linux/ide.h>
  29 #include <linux/initrd.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/root_dev.h>
  32 #include <linux/tty.h>
  33 #include <linux/serial.h>
  34 #include <linux/serial_core.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/dma.h>
  40 #include <asm/io.h>
  41 #include <asm/machdep.h>
  42 #include <asm/ocp.h>
  43 #include <asm/pci-bridge.h>
  44 #include <asm/time.h>
  45 #include <asm/todc.h>
  46 #include <asm/bootinfo.h>
  47 #include <asm/ppc4xx_pic.h>
  48 #include <asm/ppcboot.h>
  49 #include <asm/tlbflush.h>
  50
  51 #include <syslib/gen550.h>
  52 #include <syslib/ibm440gp_common.h>
  53
  54 extern bd_t __res;
  55
  56 static struct ibm44x_clocks clocks __initdata;
  57
  58 /*
  59  * Ebony external IRQ triggering/polarity settings
  60  */
  61 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  62         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ0: PCI slot 0 */
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ1: PCI slot 1 */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ2: PCI slot 2 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ3: PCI slot 3 */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ4: IRDA */
  67         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),      /* IRQ5: SMI pushbutton */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ6: PHYs */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ7: AUX */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ8: EXT */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ9: EXT */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ10: EXT */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ11: EXT */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ12: EXT */
  75 };
  76
  77 static void __init
  78 ebony_calibrate_decr(void)
  79 {
  80         unsigned int freq;
  81
  82         /*
  83          * Determine system clock speed
  84          *
  85          * If we are on Rev. B silicon, then use
  86          * default external system clock.  If we are
  87          * on Rev. C silicon then errata forces us to
  88          * use the internal clock.
  89          */
  90         if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
  91                 freq = EBONY_440GP_RB_SYSCLK;
  92         else
  93                 freq = EBONY_440GP_RC_SYSCLK;
  94
  95         ibm44x_calibrate_decr(freq);
  96 }
  97
  98 static int
  99 ebony_show_cpuinfo(struct seq_file *m)
 100 {
 101         seq_printf(m, "vendor\t\t: IBM\n");
 102         seq_printf(m, "machine\t\t: Ebony\n");
 103
 104         return 0;
 105 }
 106
 107 static inline int
 108 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 109 {
 110         static char pci_irq_table[][4] =
 111         /*
 112          *      PCI IDSEL/INTPIN->INTLINE
 113          *         A   B   C   D
 114          */
 115         {
 116                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
 117                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
 118                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
 119                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
 120         };
 121
 122         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 123         return PCI_IRQ_TABLE_LOOKUP;
 124 }
 125
 126 #define PCIX_WRITEL(value, offset) \
 127         (writel(value, pcix_reg_base + offset))
 128
 129 /*
 130  * FIXME: This is only here to "make it work".  This will move
 131  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 132  * configuration library. -Matt
 133  */
 134 static void __init
 135 ebony_setup_pcix(void)
 136 {
 137         void __iomem *pcix_reg_base;
 138
 139         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 140
 141         /* Disable all windows */
 142         PCIX_WRITEL(0, PCIX0_POM0SA);
 143         PCIX_WRITEL(0, PCIX0_POM1SA);
 144         PCIX_WRITEL(0, PCIX0_POM2SA);
 145         PCIX_WRITEL(0, PCIX0_PIM0SA);
 146         PCIX_WRITEL(0, PCIX0_PIM1SA);
 147         PCIX_WRITEL(0, PCIX0_PIM2SA);
 148
 149         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 150         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 151         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 152         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 153         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 154         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 155
 156         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 157         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 158         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 159         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 160
 161         eieio();
 162 }
 163
 164 static void __init
 165 ebony_setup_hose(void)
 166 {
 167         struct pci_controller *hose;
 168
 169         /* Configure windows on the PCI-X host bridge */
 170         ebony_setup_pcix();
 171
 172         hose = pcibios_alloc_controller();
 173
 174         if (!hose)
 175                 return;
 176
 177         hose->first_busno = 0;
 178         hose->last_busno = 0xff;
 179
 180         hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
 181
 182         pci_init_resource(&hose->io_resource,
 183                         EBONY_PCI_LOWER_IO,
 184                         EBONY_PCI_UPPER_IO,
 185                         IORESOURCE_IO,
 186                         "PCI host bridge");
 187
 188         pci_init_resource(&hose->mem_resources[0],
 189                         EBONY_PCI_LOWER_MEM,
 190                         EBONY_PCI_UPPER_MEM,
 191                         IORESOURCE_MEM,
 192                         "PCI host bridge");
 193
 194         hose->io_space.start = EBONY_PCI_LOWER_IO;
 195         hose->io_space.end = EBONY_PCI_UPPER_IO;
 196         hose->mem_space.start = EBONY_PCI_LOWER_MEM;
 197         hose->mem_space.end = EBONY_PCI_UPPER_MEM;
 198         hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
 199         isa_io_base = (unsigned long)hose->io_base_virt;
 200
 201         setup_indirect_pci(hose,
 202                         EBONY_PCI_CFGA_PLB32,
 203                         EBONY_PCI_CFGD_PLB32);
 204         hose->set_cfg_type = 1;
 205
 206         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 207
 208         ppc_md.pci_swizzle = common_swizzle;
 209         ppc_md.pci_map_irq = ebony_map_irq;
 210 }
 211
 212 TODC_ALLOC();
 213
 214 static void __init
 215 ebony_early_serial_map(void)
 216 {
 217         struct uart_port port;
 218
 219         /* Setup ioremapped serial port access */
 220         memset(&port, 0, sizeof(port));
 221         port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
 222         port.irq = 0;
 223         port.uartclk = clocks.uart0;
 224         port.regshift = 0;
 225         port.iotype = UPIO_MEM;
 226         port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
 227         port.line = 0;
 228
 229         if (early_serial_setup(&port) != 0) {
 230                 printk("Early serial init of port 0 failed\n");
 231         }
 232
 233 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 234         /* Configure debug serial access */
 235         gen550_init(0, &port);
 236
 237         /* Purge TLB entry added in head_44x.S for early serial access */
 238         _tlbie(UART0_IO_BASE);
 239 #endif
 240
 241         port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
 242         port.irq = 1;
 243         port.uartclk = clocks.uart1;
 244         port.line = 1;
 245
 246         if (early_serial_setup(&port) != 0) {
 247                 printk("Early serial init of port 1 failed\n");
 248         }
 249
 250 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 251         /* Configure debug serial access */
 252         gen550_init(1, &port);
 253 #endif
 254 }
 255
 256 static void __init
 257 ebony_setup_arch(void)
 258 {
 259         struct ocp_def *def;
 260         struct ocp_func_emac_data *emacdata;
 261
 262         /* Set mac_addr for each EMAC */
 263         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 264         emacdata = def->additions;
 265         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 266         emacdata->phy_mode = PHY_MODE_RMII;
 267         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 268
 269         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 270         emacdata = def->additions;
 271         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 272         emacdata->phy_mode = PHY_MODE_RMII;
 273         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 274
 275         /*
 276          * Determine various clocks.
 277          * To be completely correct we should get SysClk
 278          * from FPGA, because it can be changed by on-board switches
 279          * --ebs
 280          */
 281         ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
 282         ocp_sys_info.opb_bus_freq = clocks.opb;
 283
 284         /* Setup TODC access */
 285         TODC_INIT(TODC_TYPE_DS1743,
 286                         0,
 287                         0,
 288                         ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
 289                         8);
 290
 291         /* init to some ~sane value until calibrate_delay() runs */
 292         loops_per_jiffy = 50000000/HZ;
 293
 294         /* Setup PCI host bridge */
 295         ebony_setup_hose();
 296
 297 #ifdef CONFIG_BLK_DEV_INITRD
 298         if (initrd_start)
 299                 ROOT_DEV = Root_RAM0;
 300         else
 301 #endif
 302 #ifdef CONFIG_ROOT_NFS
 303                 ROOT_DEV = Root_NFS;
 304 #else
 305                 ROOT_DEV = Root_HDA1;
 306 #endif
 307
 308         ebony_early_serial_map();
 309
 310         /* Identify the system */
 311         printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
 312 }
 313
 314 void __init platform_init(unsigned long r3, unsigned long r4,
 315                 unsigned long r5, unsigned long r6, unsigned long r7)
 316 {
 317         ibm44x_platform_init(r3, r4, r5, r6, r7);
 318
 319         ppc_md.setup_arch = ebony_setup_arch;
 320         ppc_md.show_cpuinfo = ebony_show_cpuinfo;
 321         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 322
 323         ppc_md.calibrate_decr = ebony_calibrate_decr;
 324         ppc_md.time_init = todc_time_init;
 325         ppc_md.set_rtc_time = todc_set_rtc_time;
 326         ppc_md.get_rtc_time = todc_get_rtc_time;
 327
 328         ppc_md.nvram_read_val = todc_direct_read_val;
 329         ppc_md.nvram_write_val = todc_direct_write_val;
 330 #ifdef CONFIG_KGDB
 331         ppc_md.early_serial_map = ebony_early_serial_map;
 332 #endif
 333 }
 334