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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / ppc / kernel / pci.c
blob5e723c4c2571b0a3dc886032a92681a9927b9d7c
1 /*
2 * Common prep/chrp pci routines. -- Cort
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/pci.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/capability.h>
11 #include <linux/sched.h>
12 #include <linux/errno.h>
13 #include <linux/bootmem.h>
14
15 #include <asm/processor.h>
16 #include <asm/io.h>
17 #include <asm/prom.h>
18 #include <asm/sections.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/byteorder.h>
21 #include <asm/irq.h>
22 #include <asm/uaccess.h>
23 #include <asm/machdep.h>
24
25 #undef DEBUG
26
27 #ifdef DEBUG
28 #define DBG(x...) printk(x)
29 #else
30 #define DBG(x...)
31 #endif
32
33 unsigned long isa_io_base = 0;
34 unsigned long isa_mem_base = 0;
35 unsigned long pci_dram_offset = 0;
36 int pcibios_assign_bus_offset = 1;
37
38 void pcibios_make_OF_bus_map(void);
39
40 static int pci_relocate_bridge_resource(struct pci_bus *bus, int i);
41 static int probe_resource(struct pci_bus *parent, struct resource *pr,
42 struct resource *res, struct resource **conflict);
43 static void update_bridge_base(struct pci_bus *bus, int i);
44 static void pcibios_fixup_resources(struct pci_dev* dev);
45 static void fixup_broken_pcnet32(struct pci_dev* dev);
46 static int reparent_resources(struct resource *parent, struct resource *res);
47 static void fixup_cpc710_pci64(struct pci_dev* dev);
48
49 /* By default, we don't re-assign bus numbers.
50 */
51 int pci_assign_all_buses;
52
53 struct pci_controller* hose_head;
54 struct pci_controller** hose_tail = &hose_head;
55
56 static int pci_bus_count;
57
58 static void
59 fixup_broken_pcnet32(struct pci_dev* dev)
60 {
61 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
62 dev->vendor = PCI_VENDOR_ID_AMD;
63 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
64 }
65 }
66 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
67
68 static void
69 fixup_cpc710_pci64(struct pci_dev* dev)
70 {
71 /* Hide the PCI64 BARs from the kernel as their content doesn't
72 * fit well in the resource management
73 */
74 dev->resource[0].start = dev->resource[0].end = 0;
75 dev->resource[0].flags = 0;
76 dev->resource[1].start = dev->resource[1].end = 0;
77 dev->resource[1].flags = 0;
78 }
79 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
80
81 static void
82 pcibios_fixup_resources(struct pci_dev *dev)
83 {
84 struct pci_controller* hose = (struct pci_controller *)dev->sysdata;
85 int i;
86 unsigned long offset;
87
88 if (!hose) {
89 printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev));
90 return;
91 }
92 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
93 struct resource *res = dev->resource + i;
94 if (!res->flags)
95 continue;
96 if (res->end == 0xffffffff) {
97 DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n",
98 pci_name(dev), i,
99 (unsigned long long)res->start,
100 (unsigned long long)res->end);
101 res->end -= res->start;
102 res->start = 0;
103 res->flags |= IORESOURCE_UNSET;
104 continue;
105 }
106 offset = 0;
107 if (res->flags & IORESOURCE_MEM) {
108 offset = hose->pci_mem_offset;
109 } else if (res->flags & IORESOURCE_IO) {
110 offset = (unsigned long) hose->io_base_virt
111 - isa_io_base;
112 }
113 if (offset != 0) {
114 res->start += offset;
115 res->end += offset;
116 #ifdef DEBUG
117 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
118 i, res->flags, pci_name(dev),
119 res->start - offset, res->start);
120 #endif
121 }
122 }
123
124 /* Call machine specific resource fixup */
125 if (ppc_md.pcibios_fixup_resources)
126 ppc_md.pcibios_fixup_resources(dev);
127 }
128 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
129
130 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
131 struct resource *res)
132 {
133 unsigned long offset = 0;
134 struct pci_controller *hose = dev->sysdata;
135
136 if (hose && res->flags & IORESOURCE_IO)
137 offset = (unsigned long)hose->io_base_virt - isa_io_base;
138 else if (hose && res->flags & IORESOURCE_MEM)
139 offset = hose->pci_mem_offset;
140 region->start = res->start - offset;
141 region->end = res->end - offset;
142 }
143 EXPORT_SYMBOL(pcibios_resource_to_bus);
144
145 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
146 struct pci_bus_region *region)
147 {
148 unsigned long offset = 0;
149 struct pci_controller *hose = dev->sysdata;
150
151 if (hose && res->flags & IORESOURCE_IO)
152 offset = (unsigned long)hose->io_base_virt - isa_io_base;
153 else if (hose && res->flags & IORESOURCE_MEM)
154 offset = hose->pci_mem_offset;
155 res->start = region->start + offset;
156 res->end = region->end + offset;
157 }
158 EXPORT_SYMBOL(pcibios_bus_to_resource);
159
160 /*
161 * We need to avoid collisions with `mirrored' VGA ports
162 * and other strange ISA hardware, so we always want the
163 * addresses to be allocated in the 0x000-0x0ff region
164 * modulo 0x400.
165 *
166 * Why? Because some silly external IO cards only decode
167 * the low 10 bits of the IO address. The 0x00-0xff region
168 * is reserved for motherboard devices that decode all 16
169 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
170 * but we want to try to avoid allocating at 0x2900-0x2bff
171 * which might have be mirrored at 0x0100-0x03ff..
172 */
173 void pcibios_align_resource(void *data, struct resource *res,
174 resource_size_t size, resource_size_t align)
175 {
176 struct pci_dev *dev = data;
177
178 if (res->flags & IORESOURCE_IO) {
179 resource_size_t start = res->start;
180
181 if (size > 0x100) {
182 printk(KERN_ERR "PCI: I/O Region %s/%d too large"
183 " (%lld bytes)\n", pci_name(dev),
184 dev->resource - res, (unsigned long long)size);
185 }
186
187 if (start & 0x300) {
188 start = (start + 0x3ff) & ~0x3ff;
189 res->start = start;
190 }
191 }
192 }
193 EXPORT_SYMBOL(pcibios_align_resource);
194
195 /*
196 * Handle resources of PCI devices. If the world were perfect, we could
197 * just allocate all the resource regions and do nothing more. It isn't.
198 * On the other hand, we cannot just re-allocate all devices, as it would
199 * require us to know lots of host bridge internals. So we attempt to
200 * keep as much of the original configuration as possible, but tweak it
201 * when it's found to be wrong.
202 *
203 * Known BIOS problems we have to work around:
204 * - I/O or memory regions not configured
205 * - regions configured, but not enabled in the command register
206 * - bogus I/O addresses above 64K used
207 * - expansion ROMs left enabled (this may sound harmless, but given
208 * the fact the PCI specs explicitly allow address decoders to be
209 * shared between expansion ROMs and other resource regions, it's
210 * at least dangerous)
211 *
212 * Our solution:
213 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
214 * This gives us fixed barriers on where we can allocate.
215 * (2) Allocate resources for all enabled devices. If there is
216 * a collision, just mark the resource as unallocated. Also
217 * disable expansion ROMs during this step.
218 * (3) Try to allocate resources for disabled devices. If the
219 * resources were assigned correctly, everything goes well,
220 * if they weren't, they won't disturb allocation of other
221 * resources.
222 * (4) Assign new addresses to resources which were either
223 * not configured at all or misconfigured. If explicitly
224 * requested by the user, configure expansion ROM address
225 * as well.
226 */
227
228 static void __init
229 pcibios_allocate_bus_resources(struct list_head *bus_list)
230 {
231 struct pci_bus *bus;
232 int i;
233 struct resource *res, *pr;
234
235 /* Depth-First Search on bus tree */
236 list_for_each_entry(bus, bus_list, node) {
237 for (i = 0; i < 4; ++i) {
238 if ((res = bus->resource[i]) == NULL || !res->flags
239 || res->start > res->end)
240 continue;
241 if (bus->parent == NULL)
242 pr = (res->flags & IORESOURCE_IO)?
243 &ioport_resource: &iomem_resource;
244 else {
245 pr = pci_find_parent_resource(bus->self, res);
246 if (pr == res) {
247 /* this happens when the generic PCI
248 * code (wrongly) decides that this
249 * bridge is transparent -- paulus
250 */
251 continue;
252 }
253 }
254
255 DBG("PCI: bridge rsrc %llx..%llx (%lx), parent %p\n",
256 (unsigned long long)res->start,
257 (unsigned long long)res->end, res->flags, pr);
258 if (pr) {
259 if (request_resource(pr, res) == 0)
260 continue;
261 /*
262 * Must be a conflict with an existing entry.
263 * Move that entry (or entries) under the
264 * bridge resource and try again.
265 */
266 if (reparent_resources(pr, res) == 0)
267 continue;
268 }
269 printk(KERN_ERR "PCI: Cannot allocate resource region "
270 "%d of PCI bridge %d\n", i, bus->number);
271 if (pci_relocate_bridge_resource(bus, i))
272 bus->resource[i] = NULL;
273 }
274 pcibios_allocate_bus_resources(&bus->children);
275 }
276 }
277
278 /*
279 * Reparent resource children of pr that conflict with res
280 * under res, and make res replace those children.
281 */
282 static int __init
283 reparent_resources(struct resource *parent, struct resource *res)
284 {
285 struct resource *p, **pp;
286 struct resource **firstpp = NULL;
287
288 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
289 if (p->end < res->start)
290 continue;
291 if (res->end < p->start)
292 break;
293 if (p->start < res->start || p->end > res->end)
294 return -1; /* not completely contained */
295 if (firstpp == NULL)
296 firstpp = pp;
297 }
298 if (firstpp == NULL)
299 return -1; /* didn't find any conflicting entries? */
300 res->parent = parent;
301 res->child = *firstpp;
302 res->sibling = *pp;
303 *firstpp = res;
304 *pp = NULL;
305 for (p = res->child; p != NULL; p = p->sibling) {
306 p->parent = res;
307 DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n",
308 p->name, (unsigned long long)p->start,
309 (unsigned long long)p->end, res->name);
310 }
311 return 0;
312 }
313
314 /*
315 * A bridge has been allocated a range which is outside the range
316 * of its parent bridge, so it needs to be moved.
317 */
318 static int __init
319 pci_relocate_bridge_resource(struct pci_bus *bus, int i)
320 {
321 struct resource *res, *pr, *conflict;
322 unsigned long try, size;
323 int j;
324 struct pci_bus *parent = bus->parent;
325
326 if (parent == NULL) {
327 /* shouldn't ever happen */
328 printk(KERN_ERR "PCI: can't move host bridge resource\n");
329 return -1;
330 }
331 res = bus->resource[i];
332 if (res == NULL)
333 return -1;
334 pr = NULL;
335 for (j = 0; j < 4; j++) {
336 struct resource *r = parent->resource[j];
337 if (!r)
338 continue;
339 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
340 continue;
341 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) {
342 pr = r;
343 break;
344 }
345 if (res->flags & IORESOURCE_PREFETCH)
346 pr = r;
347 }
348 if (pr == NULL)
349 return -1;
350 size = res->end - res->start;
351 if (pr->start > pr->end || size > pr->end - pr->start)
352 return -1;
353 try = pr->end;
354 for (;;) {
355 res->start = try - size;
356 res->end = try;
357 if (probe_resource(bus->parent, pr, res, &conflict) == 0)
358 break;
359 if (conflict->start <= pr->start + size)
360 return -1;
361 try = conflict->start - 1;
362 }
363 if (request_resource(pr, res)) {
364 DBG(KERN_ERR "PCI: huh? couldn't move to %llx..%llx\n",
365 (unsigned long long)res->start,
366 (unsigned long long)res->end);
367 return -1; /* "can't happen" */
368 }
369 update_bridge_base(bus, i);
370 printk(KERN_INFO "PCI: bridge %d resource %d moved to %llx..%llx\n",
371 bus->number, i, (unsigned long long)res->start,
372 (unsigned long long)res->end);
373 return 0;
374 }
375
376 static int __init
377 probe_resource(struct pci_bus *parent, struct resource *pr,
378 struct resource *res, struct resource **conflict)
379 {
380 struct pci_bus *bus;
381 struct pci_dev *dev;
382 struct resource *r;
383 int i;
384
385 for (r = pr->child; r != NULL; r = r->sibling) {
386 if (r->end >= res->start && res->end >= r->start) {
387 *conflict = r;
388 return 1;
389 }
390 }
391 list_for_each_entry(bus, &parent->children, node) {
392 for (i = 0; i < 4; ++i) {
393 if ((r = bus->resource[i]) == NULL)
394 continue;
395 if (!r->flags || r->start > r->end || r == res)
396 continue;
397 if (pci_find_parent_resource(bus->self, r) != pr)
398 continue;
399 if (r->end >= res->start && res->end >= r->start) {
400 *conflict = r;
401 return 1;
402 }
403 }
404 }
405 list_for_each_entry(dev, &parent->devices, bus_list) {
406 for (i = 0; i < 6; ++i) {
407 r = &dev->resource[i];
408 if (!r->flags || (r->flags & IORESOURCE_UNSET))
409 continue;
410 if (pci_find_parent_resource(dev, r) != pr)
411 continue;
412 if (r->end >= res->start && res->end >= r->start) {
413 *conflict = r;
414 return 1;
415 }
416 }
417 }
418 return 0;
419 }
420
421 static void __init
422 update_bridge_base(struct pci_bus *bus, int i)
423 {
424 struct resource *res = bus->resource[i];
425 u8 io_base_lo, io_limit_lo;
426 u16 mem_base, mem_limit;
427 u16 cmd;
428 unsigned long start, end, off;
429 struct pci_dev *dev = bus->self;
430 struct pci_controller *hose = dev->sysdata;
431
432 if (!hose) {
433 printk("update_bridge_base: no hose?\n");
434 return;
435 }
436 pci_read_config_word(dev, PCI_COMMAND, &cmd);
437 pci_write_config_word(dev, PCI_COMMAND,
438 cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY));
439 if (res->flags & IORESOURCE_IO) {
440 off = (unsigned long) hose->io_base_virt - isa_io_base;
441 start = res->start - off;
442 end = res->end - off;
443 io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK;
444 io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK;
445 if (end > 0xffff) {
446 pci_write_config_word(dev, PCI_IO_BASE_UPPER16,
447 start >> 16);
448 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,
449 end >> 16);
450 io_base_lo |= PCI_IO_RANGE_TYPE_32;
451 } else
452 io_base_lo |= PCI_IO_RANGE_TYPE_16;
453 pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo);
454 pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo);
455
456 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
457 == IORESOURCE_MEM) {
458 off = hose->pci_mem_offset;
459 mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK;
460 mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK;
461 pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base);
462 pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit);
463
464 } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH))
465 == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) {
466 off = hose->pci_mem_offset;
467 mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK;
468 mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK;
469 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base);
470 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
471
472 } else {
473 DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n",
474 pci_name(dev), i, res->flags);
475 }
476 pci_write_config_word(dev, PCI_COMMAND, cmd);
477 }
478
479 static inline void alloc_resource(struct pci_dev *dev, int idx)
480 {
481 struct resource *pr, *r = &dev->resource[idx];
482
483 DBG("PCI:%s: Resource %d: %016llx-%016llx (f=%lx)\n",
484 pci_name(dev), idx, (unsigned long long)r->start,
485 (unsigned long long)r->end, r->flags);
486 pr = pci_find_parent_resource(dev, r);
487 if (!pr || request_resource(pr, r) < 0) {
488 printk(KERN_ERR "PCI: Cannot allocate resource region %d"
489 " of device %s\n", idx, pci_name(dev));
490 if (pr)
491 DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n",
492 pr, (unsigned long long)pr->start,
493 (unsigned long long)pr->end, pr->flags);
494 /* We'll assign a new address later */
495 r->flags |= IORESOURCE_UNSET;
496 r->end -= r->start;
497 r->start = 0;
498 }
499 }
500
501 static void __init
502 pcibios_allocate_resources(int pass)
503 {
504 struct pci_dev *dev = NULL;
505 int idx, disabled;
506 u16 command;
507 struct resource *r;
508
509 for_each_pci_dev(dev) {
510 pci_read_config_word(dev, PCI_COMMAND, &command);
511 for (idx = 0; idx < 6; idx++) {
512 r = &dev->resource[idx];
513 if (r->parent) /* Already allocated */
514 continue;
515 if (!r->flags || (r->flags & IORESOURCE_UNSET))
516 continue; /* Not assigned at all */
517 if (r->flags & IORESOURCE_IO)
518 disabled = !(command & PCI_COMMAND_IO);
519 else
520 disabled = !(command & PCI_COMMAND_MEMORY);
521 if (pass == disabled)
522 alloc_resource(dev, idx);
523 }
524 if (pass)
525 continue;
526 r = &dev->resource[PCI_ROM_RESOURCE];
527 if (r->flags & IORESOURCE_ROM_ENABLE) {
528 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
529 u32 reg;
530 DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
531 r->flags &= ~IORESOURCE_ROM_ENABLE;
532 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
533 pci_write_config_dword(dev, dev->rom_base_reg,
534 reg & ~PCI_ROM_ADDRESS_ENABLE);
535 }
536 }
537 }
538
539 static void __init
540 pcibios_assign_resources(void)
541 {
542 struct pci_dev *dev = NULL;
543 int idx;
544 struct resource *r;
545
546 for_each_pci_dev(dev) {
547 int class = dev->class >> 8;
548
549 /* Don't touch classless devices and host bridges */
550 if (!class || class == PCI_CLASS_BRIDGE_HOST)
551 continue;
552
553 for (idx = 0; idx < 6; idx++) {
554 r = &dev->resource[idx];
555
556 /*
557 * We shall assign a new address to this resource,
558 * either because the BIOS (sic) forgot to do so
559 * or because we have decided the old address was
560 * unusable for some reason.
561 */
562 if ((r->flags & IORESOURCE_UNSET) && r->end &&
563 (!ppc_md.pcibios_enable_device_hook ||
564 !ppc_md.pcibios_enable_device_hook(dev, 1))) {
565 r->flags &= ~IORESOURCE_UNSET;
566 pci_assign_resource(dev, idx);
567 }
568 }
569
570 #if 0 /* don't assign ROMs */
571 r = &dev->resource[PCI_ROM_RESOURCE];
572 r->end -= r->start;
573 r->start = 0;
574 if (r->end)
575 pci_assign_resource(dev, PCI_ROM_RESOURCE);
576 #endif
577 }
578 }
579
580
581 int
582 pcibios_enable_resources(struct pci_dev *dev, int mask)
583 {
584 u16 cmd, old_cmd;
585 int idx;
586 struct resource *r;
587
588 pci_read_config_word(dev, PCI_COMMAND, &cmd);
589 old_cmd = cmd;
590 for (idx=0; idx<6; idx++) {
591 /* Only set up the requested stuff */
592 if (!(mask & (1<<idx)))
593 continue;
594
595 r = &dev->resource[idx];
596 if (r->flags & IORESOURCE_UNSET) {
597 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
598 return -EINVAL;
599 }
600 if (r->flags & IORESOURCE_IO)
601 cmd |= PCI_COMMAND_IO;
602 if (r->flags & IORESOURCE_MEM)
603 cmd |= PCI_COMMAND_MEMORY;
604 }
605 if (dev->resource[PCI_ROM_RESOURCE].start)
606 cmd |= PCI_COMMAND_MEMORY;
607 if (cmd != old_cmd) {
608 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
609 pci_write_config_word(dev, PCI_COMMAND, cmd);
610 }
611 return 0;
612 }
613
614 static int next_controller_index;
615
616 struct pci_controller * __init
617 pcibios_alloc_controller(void)
618 {
619 struct pci_controller *hose;
620
621 hose = (struct pci_controller *)alloc_bootmem(sizeof(*hose));
622 memset(hose, 0, sizeof(struct pci_controller));
623
624 *hose_tail = hose;
625 hose_tail = &hose->next;
626
627 hose->index = next_controller_index++;
628
629 return hose;
630 }
631
632 void pcibios_make_OF_bus_map(void)
633 {
634 }
635
636 /* Add sysfs properties */
637 void pcibios_add_platform_entries(struct pci_dev *pdev)
638 {
639 }
640
641
642 static int __init
643 pcibios_init(void)
644 {
645 struct pci_controller *hose;
646 struct pci_bus *bus;
647 int next_busno;
648
649 printk(KERN_INFO "PCI: Probing PCI hardware\n");
650
651 /* Scan all of the recorded PCI controllers. */
652 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
653 if (pci_assign_all_buses)
654 hose->first_busno = next_busno;
655 hose->last_busno = 0xff;
656 bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
657 hose->last_busno = bus->subordinate;
658 if (pci_assign_all_buses || next_busno <= hose->last_busno)
659 next_busno = hose->last_busno + pcibios_assign_bus_offset;
660 }
661 pci_bus_count = next_busno;
662
663 /* OpenFirmware based machines need a map of OF bus
664 * numbers vs. kernel bus numbers since we may have to
665 * remap them.
666 */
667 if (pci_assign_all_buses && have_of)
668 pcibios_make_OF_bus_map();
669
670 /* Do machine dependent PCI interrupt routing */
671 if (ppc_md.pci_swizzle && ppc_md.pci_map_irq)
672 pci_fixup_irqs(ppc_md.pci_swizzle, ppc_md.pci_map_irq);
673
674 /* Call machine dependent fixup */
675 if (ppc_md.pcibios_fixup)
676 ppc_md.pcibios_fixup();
677
678 /* Allocate and assign resources */
679 pcibios_allocate_bus_resources(&pci_root_buses);
680 pcibios_allocate_resources(0);
681 pcibios_allocate_resources(1);
682 pcibios_assign_resources();
683
684 /* Call machine dependent post-init code */
685 if (ppc_md.pcibios_after_init)
686 ppc_md.pcibios_after_init();
687
688 return 0;
689 }
690
691 subsys_initcall(pcibios_init);
692
693 unsigned char __init
694 common_swizzle(struct pci_dev *dev, unsigned char *pinp)
695 {
696 struct pci_controller *hose = dev->sysdata;
697
698 if (dev->bus->number != hose->first_busno) {
699 u8 pin = *pinp;
700 do {
701 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
702 /* Move up the chain of bridges. */
703 dev = dev->bus->self;
704 } while (dev->bus->self);
705 *pinp = pin;
706
707 /* The slot is the idsel of the last bridge. */
708 }
709 return PCI_SLOT(dev->devfn);
710 }
711
712 unsigned long resource_fixup(struct pci_dev * dev, struct resource * res,
713 unsigned long start, unsigned long size)
714 {
715 return start;
716 }
717
718 void __init pcibios_fixup_bus(struct pci_bus *bus)
719 {
720 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
721 unsigned long io_offset;
722 struct resource *res;
723 int i;
724
725 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
726 if (bus->parent == NULL) {
727 /* This is a host bridge - fill in its resources */
728 hose->bus = bus;
729
730 bus->resource[0] = res = &hose->io_resource;
731 if (!res->flags) {
732 if (io_offset)
733 printk(KERN_ERR "I/O resource not set for host"
734 " bridge %d\n", hose->index);
735 res->start = 0;
736 res->end = IO_SPACE_LIMIT;
737 res->flags = IORESOURCE_IO;
738 }
739 res->start += io_offset;
740 res->end += io_offset;
741
742 for (i = 0; i < 3; ++i) {
743 res = &hose->mem_resources[i];
744 if (!res->flags) {
745 if (i > 0)
746 continue;
747 printk(KERN_ERR "Memory resource not set for "
748 "host bridge %d\n", hose->index);
749 res->start = hose->pci_mem_offset;
750 res->end = ~0U;
751 res->flags = IORESOURCE_MEM;
752 }
753 bus->resource[i+1] = res;
754 }
755 } else {
756 /* This is a subordinate bridge */
757 pci_read_bridge_bases(bus);
758
759 for (i = 0; i < 4; ++i) {
760 if ((res = bus->resource[i]) == NULL)
761 continue;
762 if (!res->flags)
763 continue;
764 if (io_offset && (res->flags & IORESOURCE_IO)) {
765 res->start += io_offset;
766 res->end += io_offset;
767 } else if (hose->pci_mem_offset
768 && (res->flags & IORESOURCE_MEM)) {
769 res->start += hose->pci_mem_offset;
770 res->end += hose->pci_mem_offset;
771 }
772 }
773 }
774
775 if (ppc_md.pcibios_fixup_bus)
776 ppc_md.pcibios_fixup_bus(bus);
777 }
778
779 char __init *pcibios_setup(char *str)
780 {
781 return str;
782 }
783
784 /* the next one is stolen from the alpha port... */
785 void __init
786 pcibios_update_irq(struct pci_dev *dev, int irq)
787 {
788 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
789 /* XXX FIXME - update OF device tree node interrupt property */
790 }
791
792 int pcibios_enable_device(struct pci_dev *dev, int mask)
793 {
794 u16 cmd, old_cmd;
795 int idx;
796 struct resource *r;
797
798 if (ppc_md.pcibios_enable_device_hook)
799 if (ppc_md.pcibios_enable_device_hook(dev, 0))
800 return -EINVAL;
801
802 pci_read_config_word(dev, PCI_COMMAND, &cmd);
803 old_cmd = cmd;
804 for (idx=0; idx<6; idx++) {
805 r = &dev->resource[idx];
806 if (r->flags & IORESOURCE_UNSET) {
807 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
808 return -EINVAL;
809 }
810 if (r->flags & IORESOURCE_IO)
811 cmd |= PCI_COMMAND_IO;
812 if (r->flags & IORESOURCE_MEM)
813 cmd |= PCI_COMMAND_MEMORY;
814 }
815 if (cmd != old_cmd) {
816 printk("PCI: Enabling device %s (%04x -> %04x)\n",
817 pci_name(dev), old_cmd, cmd);
818 pci_write_config_word(dev, PCI_COMMAND, cmd);
819 }
820 return 0;
821 }
822
823 struct pci_controller*
824 pci_bus_to_hose(int bus)
825 {
826 struct pci_controller* hose = hose_head;
827
828 for (; hose; hose = hose->next)
829 if (bus >= hose->first_busno && bus <= hose->last_busno)
830 return hose;
831 return NULL;
832 }
833
834 void __iomem *
835 pci_bus_io_base(unsigned int bus)
836 {
837 struct pci_controller *hose;
838
839 hose = pci_bus_to_hose(bus);
840 if (!hose)
841 return NULL;
842 return hose->io_base_virt;
843 }
844
845 unsigned long
846 pci_bus_io_base_phys(unsigned int bus)
847 {
848 struct pci_controller *hose;
849
850 hose = pci_bus_to_hose(bus);
851 if (!hose)
852 return 0;
853 return hose->io_base_phys;
854 }
855
856 unsigned long
857 pci_bus_mem_base_phys(unsigned int bus)
858 {
859 struct pci_controller *hose;
860
861 hose = pci_bus_to_hose(bus);
862 if (!hose)
863 return 0;
864 return hose->pci_mem_offset;
865 }
866
867 unsigned long
868 pci_resource_to_bus(struct pci_dev *pdev, struct resource *res)
869 {
870 /* Hack alert again ! See comments in chrp_pci.c
871 */
872 struct pci_controller* hose =
873 (struct pci_controller *)pdev->sysdata;
874 if (hose && res->flags & IORESOURCE_MEM)
875 return res->start - hose->pci_mem_offset;
876 /* We may want to do something with IOs here... */
877 return res->start;
878 }
879
880
881 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
882 resource_size_t *offset,
883 enum pci_mmap_state mmap_state)
884 {
885 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
886 unsigned long io_offset = 0;
887 int i, res_bit;
888
889 if (hose == 0)
890 return NULL; /* should never happen */
891
892 /* If memory, add on the PCI bridge address offset */
893 if (mmap_state == pci_mmap_mem) {
894 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
895 *offset += hose->pci_mem_offset;
896 #endif
897 res_bit = IORESOURCE_MEM;
898 } else {
899 io_offset = hose->io_base_virt - ___IO_BASE;
900 *offset += io_offset;
901 res_bit = IORESOURCE_IO;
902 }
903
904 /*
905 * Check that the offset requested corresponds to one of the
906 * resources of the device.
907 */
908 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
909 struct resource *rp = &dev->resource[i];
910 int flags = rp->flags;
911
912 /* treat ROM as memory (should be already) */
913 if (i == PCI_ROM_RESOURCE)
914 flags |= IORESOURCE_MEM;
915
916 /* Active and same type? */
917 if ((flags & res_bit) == 0)
918 continue;
919
920 /* In the range of this resource? */
921 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
922 continue;
923
924 /* found it! construct the final physical address */
925 if (mmap_state == pci_mmap_io)
926 *offset += hose->io_base_phys - io_offset;
927 return rp;
928 }
929
930 return NULL;
931 }
932
933 /*
934 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
935 * device mapping.
936 */
937 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
938 pgprot_t protection,
939 enum pci_mmap_state mmap_state,
940 int write_combine)
941 {
942 unsigned long prot = pgprot_val(protection);
943
944 /* Write combine is always 0 on non-memory space mappings. On
945 * memory space, if the user didn't pass 1, we check for a
946 * "prefetchable" resource. This is a bit hackish, but we use
947 * this to workaround the inability of /sysfs to provide a write
948 * combine bit
949 */
950 if (mmap_state != pci_mmap_mem)
951 write_combine = 0;
952 else if (write_combine == 0) {
953 if (rp->flags & IORESOURCE_PREFETCH)
954 write_combine = 1;
955 }
956
957 /* XXX would be nice to have a way to ask for write-through */
958 prot |= _PAGE_NO_CACHE;
959 if (write_combine)
960 prot &= ~_PAGE_GUARDED;
961 else
962 prot |= _PAGE_GUARDED;
963
964 printk("PCI map for %s:%llx, prot: %lx\n", pci_name(dev),
965 (unsigned long long)rp->start, prot);
966
967 return __pgprot(prot);
968 }
969
970 /*
971 * This one is used by /dev/mem and fbdev who have no clue about the
972 * PCI device, it tries to find the PCI device first and calls the
973 * above routine
974 */
975 pgprot_t pci_phys_mem_access_prot(struct file *file,
976 unsigned long pfn,
977 unsigned long size,
978 pgprot_t protection)
979 {
980 struct pci_dev *pdev = NULL;
981 struct resource *found = NULL;
982 unsigned long prot = pgprot_val(protection);
983 unsigned long offset = pfn << PAGE_SHIFT;
984 int i;
985
986 if (page_is_ram(pfn))
987 return prot;
988
989 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
990
991 for_each_pci_dev(pdev) {
992 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
993 struct resource *rp = &pdev->resource[i];
994 int flags = rp->flags;
995
996 /* Active and same type? */
997 if ((flags & IORESOURCE_MEM) == 0)
998 continue;
999 /* In the range of this resource? */
1000 if (offset < (rp->start & PAGE_MASK) ||
1001 offset > rp->end)
1002 continue;
1003 found = rp;
1004 break;
1005 }
1006 if (found)
1007 break;
1008 }
1009 if (found) {
1010 if (found->flags & IORESOURCE_PREFETCH)
1011 prot &= ~_PAGE_GUARDED;
1012 pci_dev_put(pdev);
1013 }
1014
1015 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
1016
1017 return __pgprot(prot);
1018 }
1019
1020
1021 /*
1022 * Perform the actual remap of the pages for a PCI device mapping, as
1023 * appropriate for this architecture. The region in the process to map
1024 * is described by vm_start and vm_end members of VMA, the base physical
1025 * address is found in vm_pgoff.
1026 * The pci device structure is provided so that architectures may make mapping
1027 * decisions on a per-device or per-bus basis.
1028 *
1029 * Returns a negative error code on failure, zero on success.
1030 */
1031 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1032 enum pci_mmap_state mmap_state,
1033 int write_combine)
1034 {
1035 resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
1036 struct resource *rp;
1037 int ret;
1038
1039 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
1040 if (rp == NULL)
1041 return -EINVAL;
1042
1043 vma->vm_pgoff = offset >> PAGE_SHIFT;
1044 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
1045 vma->vm_page_prot,
1046 mmap_state, write_combine);
1047
1048 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
1049 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1050
1051 return ret;
1052 }
1053
1054 /* Obsolete functions. Should be removed once the symbios driver
1055 * is fixed
1056 */
1057 unsigned long
1058 phys_to_bus(unsigned long pa)
1059 {
1060 struct pci_controller *hose;
1061 int i;
1062
1063 for (hose = hose_head; hose; hose = hose->next) {
1064 for (i = 0; i < 3; ++i) {
1065 if (pa >= hose->mem_resources[i].start
1066 && pa <= hose->mem_resources[i].end) {
1067 /*
1068 * XXX the hose->pci_mem_offset really
1069 * only applies to mem_resources[0].
1070 * We need a way to store an offset for
1071 * the others. -- paulus
1072 */
1073 if (i == 0)
1074 pa -= hose->pci_mem_offset;
1075 return pa;
1076 }
1077 }
1078 }
1079 /* hmmm, didn't find it */
1080 return 0;
1081 }
1082
1083 unsigned long
1084 pci_phys_to_bus(unsigned long pa, int busnr)
1085 {
1086 struct pci_controller* hose = pci_bus_to_hose(busnr);
1087 if (!hose)
1088 return pa;
1089 return pa - hose->pci_mem_offset;
1090 }
1091
1092 unsigned long
1093 pci_bus_to_phys(unsigned int ba, int busnr)
1094 {
1095 struct pci_controller* hose = pci_bus_to_hose(busnr);
1096 if (!hose)
1097 return ba;
1098 return ba + hose->pci_mem_offset;
1099 }
1100
1101 /* Provide information on locations of various I/O regions in physical
1102 * memory. Do this on a per-card basis so that we choose the right
1103 * root bridge.
1104 * Note that the returned IO or memory base is a physical address
1105 */
1106
1107 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1108 {
1109 struct pci_controller* hose;
1110 long result = -EOPNOTSUPP;
1111
1112 hose = pci_bus_to_hose(bus);
1113 if (!hose)
1114 return -ENODEV;
1115
1116 switch (which) {
1117 case IOBASE_BRIDGE_NUMBER:
1118 return (long)hose->first_busno;
1119 case IOBASE_MEMORY:
1120 return (long)hose->pci_mem_offset;
1121 case IOBASE_IO:
1122 return (long)hose->io_base_phys;
1123 case IOBASE_ISA_IO:
1124 return (long)isa_io_base;
1125 case IOBASE_ISA_MEM:
1126 return (long)isa_mem_base;
1127 }
1128
1129 return result;
1130 }
1131
1132 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1133 const struct resource *rsrc,
1134 resource_size_t *start, resource_size_t *end)
1135 {
1136 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
1137 resource_size_t offset = 0;
1138
1139 if (hose == NULL)
1140 return;
1141
1142 if (rsrc->flags & IORESOURCE_IO)
1143 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1144
1145 /* We pass a fully fixed up address to userland for MMIO instead of
1146 * a BAR value because X is lame and expects to be able to use that
1147 * to pass to /dev/mem !
1148 *
1149 * That means that we'll have potentially 64 bits values where some
1150 * userland apps only expect 32 (like X itself since it thinks only
1151 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1152 * 32 bits CHRPs :-(
1153 *
1154 * Hopefully, the sysfs insterface is immune to that gunk. Once X
1155 * has been fixed (and the fix spread enough), we can re-enable the
1156 * 2 lines below and pass down a BAR value to userland. In that case
1157 * we'll also have to re-enable the matching code in
1158 * __pci_mmap_make_offset().
1159 *
1160 * BenH.
1161 */
1162 #if 0
1163 else if (rsrc->flags & IORESOURCE_MEM)
1164 offset = hose->pci_mem_offset;
1165 #endif
1166
1167 *start = rsrc->start - offset;
1168 *end = rsrc->end - offset;
1169 }
1170
1171 void __init pci_init_resource(struct resource *res, resource_size_t start,
1172 resource_size_t end, int flags, char *name)
1173 {
1174 res->start = start;
1175 res->end = end;
1176 res->flags = flags;
1177 res->name = name;
1178 res->parent = NULL;
1179 res->sibling = NULL;
1180 res->child = NULL;
1181 }
1182
1183 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
1184 {
1185 unsigned long start = pci_resource_start(dev, bar);
1186 unsigned long len = pci_resource_len(dev, bar);
1187 unsigned long flags = pci_resource_flags(dev, bar);
1188
1189 if (!len)
1190 return NULL;
1191 if (max && len > max)
1192 len = max;
1193 if (flags & IORESOURCE_IO)
1194 return ioport_map(start, len);
1195 if (flags & IORESOURCE_MEM)
1196 /* Not checking IORESOURCE_CACHEABLE because PPC does
1197 * not currently distinguish between ioremap and
1198 * ioremap_nocache.
1199 */
1200 return ioremap(start, len);
1201 /* What? */
1202 return NULL;
1203 }
1204
1205 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
1206 {
1207 /* Nothing to do */
1208 }
1209 EXPORT_SYMBOL(pci_iomap);
1210 EXPORT_SYMBOL(pci_iounmap);
1211
1212 unsigned long pci_address_to_pio(phys_addr_t address)
1213 {
1214 struct pci_controller* hose = hose_head;
1215
1216 for (; hose; hose = hose->next) {
1217 unsigned int size = hose->io_resource.end -
1218 hose->io_resource.start + 1;
1219 if (address >= hose->io_base_phys &&
1220 address < (hose->io_base_phys + size)) {
1221 unsigned long base =
1222 (unsigned long)hose->io_base_virt - _IO_BASE;
1223 return base + (address - hose->io_base_phys);
1224 }
1225 }
1226 return (unsigned int)-1;
1227 }
1228 EXPORT_SYMBOL(pci_address_to_pio);
1229
1230 /*
1231 * Null PCI config access functions, for the case when we can't
1232 * find a hose.
1233 */
1234 #define NULL_PCI_OP(rw, size, type) \
1235 static int \
1236 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1237 { \
1238 return PCIBIOS_DEVICE_NOT_FOUND; \
1239 }
1240
1241 static int
1242 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1243 int len, u32 *val)
1244 {
1245 return PCIBIOS_DEVICE_NOT_FOUND;
1246 }
1247
1248 static int
1249 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1250 int len, u32 val)
1251 {
1252 return PCIBIOS_DEVICE_NOT_FOUND;
1253 }
1254
1255 static struct pci_ops null_pci_ops =
1256 {
1257 null_read_config,
1258 null_write_config
1259 };
1260
1261 /*
1262 * These functions are used early on before PCI scanning is done
1263 * and all of the pci_dev and pci_bus structures have been created.
1264 */
1265 static struct pci_bus *
1266 fake_pci_bus(struct pci_controller *hose, int busnr)
1267 {
1268 static struct pci_bus bus;
1269
1270 if (hose == 0) {
1271 hose = pci_bus_to_hose(busnr);
1272 if (hose == 0)
1273 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1274 }
1275 bus.number = busnr;
1276 bus.sysdata = hose;
1277 bus.ops = hose? hose->ops: &null_pci_ops;
1278 return &bus;
1279 }
1280
1281 #define EARLY_PCI_OP(rw, size, type) \
1282 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1283 int devfn, int offset, type value) \
1284 { \
1285 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1286 devfn, offset, value); \
1287 }
1288
1289 EARLY_PCI_OP(read, byte, u8 *)
1290 EARLY_PCI_OP(read, word, u16 *)
1291 EARLY_PCI_OP(read, dword, u32 *)
1292 EARLY_PCI_OP(write, byte, u8)
1293 EARLY_PCI_OP(write, word, u16)
1294 EARLY_PCI_OP(write, dword, u32)
Tomato firmware and modifications.