2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <linux/list.h>
23 #include <linux/syscalls.h>
24 #include <linux/irq.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/firmware.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
44 static int pci_initial_scan_done
;
46 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
47 static void do_bus_setup(struct pci_bus
*bus
);
48 static void phbs_remap_io(void);
50 /* pci_io_base -- the base address from which io bars are offsets.
51 * This is the lowest I/O base address (so bar values are always positive),
52 * and it *must* be the start of ISA space if an ISA bus exists because
53 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
54 * page is mapped and isa_io_limit prevents access to it.
56 unsigned long isa_io_base
; /* NULL if no ISA bus */
57 EXPORT_SYMBOL(isa_io_base
);
58 unsigned long pci_io_base
;
59 EXPORT_SYMBOL(pci_io_base
);
61 void iSeries_pcibios_init(void);
65 static struct dma_mapping_ops
*pci_dma_ops
;
67 int global_phb_number
; /* Global phb counter */
69 /* Cached ISA bridge dev. */
70 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
71 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev
);
73 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
75 pci_dma_ops
= dma_ops
;
78 struct dma_mapping_ops
*get_pci_dma_ops(void)
82 EXPORT_SYMBOL(get_pci_dma_ops
);
84 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
86 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
87 dev
->vendor
= PCI_VENDOR_ID_AMD
;
88 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
91 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
93 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
96 unsigned long offset
= 0;
97 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
102 if (res
->flags
& IORESOURCE_IO
)
103 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
105 if (res
->flags
& IORESOURCE_MEM
)
106 offset
= hose
->pci_mem_offset
;
108 region
->start
= res
->start
- offset
;
109 region
->end
= res
->end
- offset
;
112 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
113 struct pci_bus_region
*region
)
115 unsigned long offset
= 0;
116 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
121 if (res
->flags
& IORESOURCE_IO
)
122 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
124 if (res
->flags
& IORESOURCE_MEM
)
125 offset
= hose
->pci_mem_offset
;
127 res
->start
= region
->start
+ offset
;
128 res
->end
= region
->end
+ offset
;
131 #ifdef CONFIG_HOTPLUG
132 EXPORT_SYMBOL(pcibios_resource_to_bus
);
133 EXPORT_SYMBOL(pcibios_bus_to_resource
);
137 * We need to avoid collisions with `mirrored' VGA ports
138 * and other strange ISA hardware, so we always want the
139 * addresses to be allocated in the 0x000-0x0ff region
142 * Why? Because some silly external IO cards only decode
143 * the low 10 bits of the IO address. The 0x00-0xff region
144 * is reserved for motherboard devices that decode all 16
145 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
146 * but we want to try to avoid allocating at 0x2900-0x2bff
147 * which might have be mirrored at 0x0100-0x03ff..
149 void pcibios_align_resource(void *data
, struct resource
*res
,
150 resource_size_t size
, resource_size_t align
)
152 struct pci_dev
*dev
= data
;
153 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
154 resource_size_t start
= res
->start
;
155 unsigned long alignto
;
157 if (res
->flags
& IORESOURCE_IO
) {
158 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
160 /* Make sure we start at our min on all hoses */
161 if (start
- offset
< PCIBIOS_MIN_IO
)
162 start
= PCIBIOS_MIN_IO
+ offset
;
165 * Put everything into 0x00-0xff region modulo 0x400
168 start
= (start
+ 0x3ff) & ~0x3ff;
170 } else if (res
->flags
& IORESOURCE_MEM
) {
171 /* Make sure we start at our min on all hoses */
172 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
173 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
175 /* Align to multiple of size of minimum base. */
176 alignto
= max(0x1000UL
, align
);
177 start
= ALIGN(start
, alignto
);
183 static DEFINE_SPINLOCK(hose_spinlock
);
186 * pci_controller(phb) initialized common variables.
188 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
190 memset(hose
, 0, sizeof(struct pci_controller
));
192 spin_lock(&hose_spinlock
);
193 hose
->global_number
= global_phb_number
++;
194 list_add_tail(&hose
->list_node
, &hose_list
);
195 spin_unlock(&hose_spinlock
);
198 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
200 struct pci_controller
*phb
;
203 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
205 phb
= alloc_bootmem(sizeof (struct pci_controller
));
208 pci_setup_pci_controller(phb
);
209 phb
->arch_data
= dev
;
210 phb
->is_dynamic
= mem_init_done
;
212 int nid
= of_node_to_nid(dev
);
214 if (nid
< 0 || !node_online(nid
))
217 PHB_SET_NODE(phb
, nid
);
222 void pcibios_free_controller(struct pci_controller
*phb
)
224 spin_lock(&hose_spinlock
);
225 list_del(&phb
->list_node
);
226 spin_unlock(&hose_spinlock
);
232 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
235 struct pci_bus
*child_bus
;
237 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
240 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
241 struct resource
*r
= &dev
->resource
[i
];
243 if (r
->parent
|| !r
->start
|| !r
->flags
)
245 pci_claim_resource(dev
, i
);
249 list_for_each_entry(child_bus
, &b
->children
, node
)
250 pcibios_claim_one_bus(child_bus
);
252 #ifdef CONFIG_HOTPLUG
253 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
256 static void __init
pcibios_claim_of_setup(void)
260 if (firmware_has_feature(FW_FEATURE_ISERIES
))
263 list_for_each_entry(b
, &pci_root_buses
, node
)
264 pcibios_claim_one_bus(b
);
267 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
272 prop
= of_get_property(np
, name
, &len
);
273 if (prop
&& len
>= 4)
278 static unsigned int pci_parse_of_flags(u32 addr0
)
280 unsigned int flags
= 0;
282 if (addr0
& 0x02000000) {
283 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
284 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
285 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
286 if (addr0
& 0x40000000)
287 flags
|= IORESOURCE_PREFETCH
288 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
289 } else if (addr0
& 0x01000000)
290 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
294 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
296 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
300 struct resource
*res
;
305 addrs
= of_get_property(node
, "assigned-addresses", &proplen
);
308 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
309 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
310 flags
= pci_parse_of_flags(addrs
[0]);
313 base
= GET_64BIT(addrs
, 1);
314 size
= GET_64BIT(addrs
, 3);
318 DBG(" base: %llx, size: %llx, i: %x\n",
319 (unsigned long long)base
, (unsigned long long)size
, i
);
321 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
322 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
323 } else if (i
== dev
->rom_base_reg
) {
324 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
325 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
327 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
331 res
->end
= base
+ size
- 1;
333 res
->name
= pci_name(dev
);
334 fixup_resource(res
, dev
);
338 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
339 struct pci_bus
*bus
, int devfn
)
344 dev
= alloc_pci_dev();
347 type
= of_get_property(node
, "device_type", NULL
);
351 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
355 dev
->dev
.parent
= bus
->bridge
;
356 dev
->dev
.bus
= &pci_bus_type
;
358 dev
->multifunction
= 0; /* maybe a lie? */
360 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
361 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
362 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
363 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
365 dev
->cfg_size
= pci_cfg_space_size(dev
);
367 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
368 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
369 dev
->class = get_int_prop(node
, "class-code", 0);
371 DBG(" class: 0x%x\n", dev
->class);
373 dev
->current_state
= 4; /* unknown power state */
374 dev
->error_state
= pci_channel_io_normal
;
376 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
377 /* a PCI-PCI bridge */
378 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
379 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
380 } else if (!strcmp(type
, "cardbus")) {
381 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
383 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
384 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
385 /* Maybe do a default OF mapping here */
389 pci_parse_of_addrs(node
, dev
);
391 DBG(" adding to system ...\n");
393 pci_device_add(dev
, bus
);
397 EXPORT_SYMBOL(of_create_pci_dev
);
399 void __devinit
of_scan_bus(struct device_node
*node
,
402 struct device_node
*child
= NULL
;
407 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
409 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
410 DBG(" * %s\n", child
->full_name
);
411 reg
= of_get_property(child
, "reg", ®len
);
412 if (reg
== NULL
|| reglen
< 20)
414 devfn
= (reg
[0] >> 8) & 0xff;
416 /* create a new pci_dev for this device */
417 dev
= of_create_pci_dev(child
, bus
, devfn
);
420 DBG("dev header type: %x\n", dev
->hdr_type
);
422 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
423 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
424 of_scan_pci_bridge(child
, dev
);
429 EXPORT_SYMBOL(of_scan_bus
);
431 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
435 const u32
*busrange
, *ranges
;
437 struct resource
*res
;
441 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
443 /* parse bus-range property */
444 busrange
= of_get_property(node
, "bus-range", &len
);
445 if (busrange
== NULL
|| len
!= 8) {
446 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
450 ranges
= of_get_property(node
, "ranges", &len
);
451 if (ranges
== NULL
) {
452 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
457 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
459 printk(KERN_ERR
"Failed to create pci bus for %s\n",
464 bus
->primary
= dev
->bus
->number
;
465 bus
->subordinate
= busrange
[1];
469 /* parse ranges property */
470 /* PCI #address-cells == 3 and #size-cells == 2 always */
471 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
472 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
474 bus
->resource
[i
] = res
;
478 for (; len
>= 32; len
-= 32, ranges
+= 8) {
479 flags
= pci_parse_of_flags(ranges
[0]);
480 size
= GET_64BIT(ranges
, 6);
481 if (flags
== 0 || size
== 0)
483 if (flags
& IORESOURCE_IO
) {
484 res
= bus
->resource
[0];
486 printk(KERN_ERR
"PCI: ignoring extra I/O range"
487 " for bridge %s\n", node
->full_name
);
491 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
492 printk(KERN_ERR
"PCI: too many memory ranges"
493 " for bridge %s\n", node
->full_name
);
496 res
= bus
->resource
[i
];
499 res
->start
= GET_64BIT(ranges
, 1);
500 res
->end
= res
->start
+ size
- 1;
502 fixup_resource(res
, dev
);
504 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
506 DBG(" bus name: %s\n", bus
->name
);
508 mode
= PCI_PROBE_NORMAL
;
509 if (ppc_md
.pci_probe_mode
)
510 mode
= ppc_md
.pci_probe_mode(bus
);
511 DBG(" probe mode: %d\n", mode
);
513 if (mode
== PCI_PROBE_DEVTREE
)
514 of_scan_bus(node
, bus
);
515 else if (mode
== PCI_PROBE_NORMAL
)
516 pci_scan_child_bus(bus
);
518 EXPORT_SYMBOL(of_scan_pci_bridge
);
520 void __devinit
scan_phb(struct pci_controller
*hose
)
523 struct device_node
*node
= hose
->arch_data
;
525 struct resource
*res
;
527 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
529 bus
= pci_create_bus(hose
->parent
, hose
->first_busno
, hose
->ops
, node
);
531 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
532 hose
->global_number
);
535 bus
->secondary
= hose
->first_busno
;
538 bus
->resource
[0] = res
= &hose
->io_resource
;
539 if (res
->flags
&& request_resource(&ioport_resource
, res
))
540 printk(KERN_ERR
"Failed to request PCI IO region "
541 "on PCI domain %04x\n", hose
->global_number
);
543 for (i
= 0; i
< 3; ++i
) {
544 res
= &hose
->mem_resources
[i
];
545 bus
->resource
[i
+1] = res
;
546 if (res
->flags
&& request_resource(&iomem_resource
, res
))
547 printk(KERN_ERR
"Failed to request PCI memory region "
548 "on PCI domain %04x\n", hose
->global_number
);
551 mode
= PCI_PROBE_NORMAL
;
553 if (node
&& ppc_md
.pci_probe_mode
)
554 mode
= ppc_md
.pci_probe_mode(bus
);
555 DBG(" probe mode: %d\n", mode
);
556 if (mode
== PCI_PROBE_DEVTREE
) {
557 bus
->subordinate
= hose
->last_busno
;
558 of_scan_bus(node
, bus
);
561 if (mode
== PCI_PROBE_NORMAL
)
562 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
565 static int __init
pcibios_init(void)
567 struct pci_controller
*hose
, *tmp
;
569 /* For now, override phys_mem_access_prot. If we need it,
570 * later, we may move that initialization to each ppc_md
572 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
574 if (firmware_has_feature(FW_FEATURE_ISERIES
))
575 iSeries_pcibios_init();
577 printk(KERN_DEBUG
"PCI: Probing PCI hardware\n");
579 /* Scan all of the recorded PCI controllers. */
580 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
582 pci_bus_add_devices(hose
->bus
);
585 if (!firmware_has_feature(FW_FEATURE_ISERIES
)) {
587 pcibios_claim_of_setup();
589 /* FIXME: `else' will be removed when
590 pci_assign_unassigned_resources() is able to work
591 correctly with [partially] allocated PCI tree. */
592 pci_assign_unassigned_resources();
595 /* Call machine dependent final fixup */
596 if (ppc_md
.pcibios_fixup
)
597 ppc_md
.pcibios_fixup();
599 /* Cache the location of the ISA bridge (if we have one) */
600 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
601 if (ppc64_isabridge_dev
!= NULL
)
602 printk(KERN_DEBUG
"ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
604 if (!firmware_has_feature(FW_FEATURE_ISERIES
))
605 /* map in PCI I/O space */
608 pci_initial_scan_done
= 1;
610 printk(KERN_DEBUG
"PCI: Probing PCI hardware done\n");
615 subsys_initcall(pcibios_init
);
617 char __init
*pcibios_setup(char *str
)
622 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
627 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
630 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
631 struct resource
*res
= &dev
->resource
[i
];
633 /* Only set up the requested stuff */
634 if (!(mask
& (1<<i
)))
637 if (res
->flags
& IORESOURCE_IO
)
638 cmd
|= PCI_COMMAND_IO
;
639 if (res
->flags
& IORESOURCE_MEM
)
640 cmd
|= PCI_COMMAND_MEMORY
;
644 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
646 /* Enable the appropriate bits in the PCI command register. */
647 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
653 * Return the domain number for this bus.
655 int pci_domain_nr(struct pci_bus
*bus
)
657 if (firmware_has_feature(FW_FEATURE_ISERIES
))
660 struct pci_controller
*hose
= pci_bus_to_host(bus
);
662 return hose
->global_number
;
666 EXPORT_SYMBOL(pci_domain_nr
);
668 /* Decide whether to display the domain number in /proc */
669 int pci_proc_domain(struct pci_bus
*bus
)
671 if (firmware_has_feature(FW_FEATURE_ISERIES
))
674 struct pci_controller
*hose
= pci_bus_to_host(bus
);
680 * Platform support for /proc/bus/pci/X/Y mmap()s,
681 * modelled on the sparc64 implementation by Dave Miller.
686 * Adjust vm_pgoff of VMA such that it is the physical page offset
687 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
689 * Basically, the user finds the base address for his device which he wishes
690 * to mmap. They read the 32-bit value from the config space base register,
691 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
692 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
694 * Returns negative error code on failure, zero on success.
696 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
697 resource_size_t
*offset
,
698 enum pci_mmap_state mmap_state
)
700 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
701 unsigned long io_offset
= 0;
705 return NULL
; /* should never happen */
707 /* If memory, add on the PCI bridge address offset */
708 if (mmap_state
== pci_mmap_mem
) {
709 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
710 *offset
+= hose
->pci_mem_offset
;
712 res_bit
= IORESOURCE_MEM
;
714 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
715 *offset
+= io_offset
;
716 res_bit
= IORESOURCE_IO
;
720 * Check that the offset requested corresponds to one of the
721 * resources of the device.
723 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
724 struct resource
*rp
= &dev
->resource
[i
];
725 int flags
= rp
->flags
;
727 /* treat ROM as memory (should be already) */
728 if (i
== PCI_ROM_RESOURCE
)
729 flags
|= IORESOURCE_MEM
;
731 /* Active and same type? */
732 if ((flags
& res_bit
) == 0)
735 /* In the range of this resource? */
736 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
739 /* found it! construct the final physical address */
740 if (mmap_state
== pci_mmap_io
)
741 *offset
+= hose
->io_base_phys
- io_offset
;
749 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
752 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
754 enum pci_mmap_state mmap_state
,
757 unsigned long prot
= pgprot_val(protection
);
759 /* Write combine is always 0 on non-memory space mappings. On
760 * memory space, if the user didn't pass 1, we check for a
761 * "prefetchable" resource. This is a bit hackish, but we use
762 * this to workaround the inability of /sysfs to provide a write
765 if (mmap_state
!= pci_mmap_mem
)
767 else if (write_combine
== 0) {
768 if (rp
->flags
& IORESOURCE_PREFETCH
)
772 /* XXX would be nice to have a way to ask for write-through */
773 prot
|= _PAGE_NO_CACHE
;
775 prot
&= ~_PAGE_GUARDED
;
777 prot
|= _PAGE_GUARDED
;
779 return __pgprot(prot
);
783 * This one is used by /dev/mem and fbdev who have no clue about the
784 * PCI device, it tries to find the PCI device first and calls the
787 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
792 struct pci_dev
*pdev
= NULL
;
793 struct resource
*found
= NULL
;
794 unsigned long prot
= pgprot_val(protection
);
795 unsigned long offset
= pfn
<< PAGE_SHIFT
;
798 if (page_is_ram(pfn
))
799 return __pgprot(prot
);
801 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
803 for_each_pci_dev(pdev
) {
804 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
805 struct resource
*rp
= &pdev
->resource
[i
];
806 int flags
= rp
->flags
;
808 /* Active and same type? */
809 if ((flags
& IORESOURCE_MEM
) == 0)
811 /* In the range of this resource? */
812 if (offset
< (rp
->start
& PAGE_MASK
) ||
822 if (found
->flags
& IORESOURCE_PREFETCH
)
823 prot
&= ~_PAGE_GUARDED
;
827 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
829 return __pgprot(prot
);
834 * Perform the actual remap of the pages for a PCI device mapping, as
835 * appropriate for this architecture. The region in the process to map
836 * is described by vm_start and vm_end members of VMA, the base physical
837 * address is found in vm_pgoff.
838 * The pci device structure is provided so that architectures may make mapping
839 * decisions on a per-device or per-bus basis.
841 * Returns a negative error code on failure, zero on success.
843 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
844 enum pci_mmap_state mmap_state
, int write_combine
)
846 resource_size_t offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
850 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
854 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
855 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
857 mmap_state
, write_combine
);
859 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
860 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
865 static ssize_t
pci_show_devspec(struct device
*dev
,
866 struct device_attribute
*attr
, char *buf
)
868 struct pci_dev
*pdev
;
869 struct device_node
*np
;
871 pdev
= to_pci_dev (dev
);
872 np
= pci_device_to_OF_node(pdev
);
873 if (np
== NULL
|| np
->full_name
== NULL
)
875 return sprintf(buf
, "%s", np
->full_name
);
877 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
879 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
881 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
884 #define ISA_SPACE_MASK 0x1
885 #define ISA_SPACE_IO 0x1
887 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
888 unsigned long phb_io_base_phys
,
889 void __iomem
* phb_io_base_virt
)
891 /* Remove these asap */
905 struct isa_address isa_addr
;
906 struct pci_address pci_addr
;
910 const struct isa_range
*range
;
911 unsigned long pci_addr
;
912 unsigned int isa_addr
;
916 range
= of_get_property(isa_node
, "ranges", &rlen
);
917 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
918 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
920 __ioremap_explicit(phb_io_base_phys
,
921 (unsigned long)phb_io_base_virt
,
922 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
926 /* From "ISA Binding to 1275"
927 * The ranges property is laid out as an array of elements,
928 * each of which comprises:
929 * cells 0 - 1: an ISA address
930 * cells 2 - 4: a PCI address
931 * (size depending on dev->n_addr_cells)
932 * cell 5: the size of the range
934 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
935 isa_addr
= range
->isa_addr
.a_lo
;
936 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
937 range
->pci_addr
.a_lo
;
939 /* Assume these are both zero */
940 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
941 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
946 size
= PAGE_ALIGN(range
->size
);
948 __ioremap_explicit(phb_io_base_phys
,
949 (unsigned long) phb_io_base_virt
,
950 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
954 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
955 struct device_node
*dev
, int prim
)
957 const unsigned int *ranges
;
958 unsigned int pci_space
;
962 struct resource
*res
;
963 int np
, na
= of_n_addr_cells(dev
);
964 unsigned long pci_addr
, cpu_phys_addr
;
968 /* From "PCI Binding to 1275"
969 * The ranges property is laid out as an array of elements,
970 * each of which comprises:
971 * cells 0 - 2: a PCI address
972 * cells 3 or 3+4: a CPU physical address
973 * (size depending on dev->n_addr_cells)
974 * cells 4+5 or 5+6: the size of the range
976 ranges
= of_get_property(dev
, "ranges", &rlen
);
979 hose
->io_base_phys
= 0;
980 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
982 pci_space
= ranges
[0];
983 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
984 cpu_phys_addr
= of_translate_address(dev
, &ranges
[3]);
985 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
990 /* Now consume following elements while they are contiguous */
991 while (rlen
>= np
* sizeof(unsigned int)) {
992 unsigned long addr
, phys
;
994 if (ranges
[0] != pci_space
)
996 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
999 phys
= (phys
<< 32) | ranges
[4];
1000 if (addr
!= pci_addr
+ size
||
1001 phys
!= cpu_phys_addr
+ size
)
1004 size
+= ((unsigned long)ranges
[na
+3] << 32)
1007 rlen
-= np
* sizeof(unsigned int);
1010 switch ((pci_space
>> 24) & 0x3) {
1011 case 1: /* I/O space */
1012 hose
->io_base_phys
= cpu_phys_addr
- pci_addr
;
1013 /* handle from 0 to top of I/O window */
1014 hose
->pci_io_size
= pci_addr
+ size
;
1016 res
= &hose
->io_resource
;
1017 res
->flags
= IORESOURCE_IO
;
1018 res
->start
= pci_addr
;
1019 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1020 res
->start
, res
->start
+ size
- 1);
1022 case 2: /* memory space */
1024 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1028 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1030 res
= &hose
->mem_resources
[memno
];
1031 res
->flags
= IORESOURCE_MEM
;
1032 res
->start
= cpu_phys_addr
;
1033 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1034 res
->start
, res
->start
+ size
- 1);
1039 res
->name
= dev
->full_name
;
1040 res
->end
= res
->start
+ size
- 1;
1042 res
->sibling
= NULL
;
1048 void __devinit
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1050 unsigned long size
= hose
->pci_io_size
;
1051 unsigned long io_virt_offset
;
1052 struct resource
*res
;
1053 struct device_node
*isa_dn
;
1058 hose
->io_base_virt
= reserve_phb_iospace(size
);
1059 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1060 hose
->global_number
, hose
->io_base_phys
,
1061 (unsigned long) hose
->io_base_virt
);
1064 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1065 isa_dn
= of_find_node_by_type(NULL
, "isa");
1067 isa_io_base
= pci_io_base
;
1068 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1069 hose
->io_base_virt
);
1070 of_node_put(isa_dn
);
1074 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1075 res
= &hose
->io_resource
;
1076 res
->start
+= io_virt_offset
;
1077 res
->end
+= io_virt_offset
;
1079 /* If this is called after the initial PCI scan, then we need to
1080 * proceed to IO mappings now
1082 if (pci_initial_scan_done
)
1083 __ioremap_explicit(hose
->io_base_phys
,
1084 (unsigned long)hose
->io_base_virt
,
1086 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1089 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1092 unsigned long size
= hose
->pci_io_size
;
1093 unsigned long io_virt_offset
;
1094 struct resource
*res
;
1099 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1100 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1101 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1102 hose
->global_number
, hose
->io_base_phys
,
1103 (unsigned long) hose
->io_base_virt
);
1106 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1108 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1109 res
= &hose
->io_resource
;
1110 res
->start
+= io_virt_offset
;
1111 res
->end
+= io_virt_offset
;
1115 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1116 unsigned long *start_virt
, unsigned long *size
)
1118 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1119 struct resource
*res
;
1122 res
= bus
->resource
[0];
1125 res
= &hose
->io_resource
;
1127 if (res
->end
== 0 && res
->start
== 0)
1130 *start_virt
= pci_io_base
+ res
->start
;
1131 *start_phys
= *start_virt
+ hose
->io_base_phys
1132 - (unsigned long) hose
->io_base_virt
;
1134 if (res
->end
> res
->start
)
1135 *size
= res
->end
- res
->start
+ 1;
1137 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1138 __FUNCTION__
, res
->start
, res
->end
);
1145 int unmap_bus_range(struct pci_bus
*bus
)
1147 unsigned long start_phys
;
1148 unsigned long start_virt
;
1152 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1156 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1158 if (__iounmap_explicit((void __iomem
*) start_virt
, size
))
1163 EXPORT_SYMBOL(unmap_bus_range
);
1165 int remap_bus_range(struct pci_bus
*bus
)
1167 unsigned long start_phys
;
1168 unsigned long start_virt
;
1172 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1177 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1179 if (start_phys
== 0)
1181 printk(KERN_DEBUG
"mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1182 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1183 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1188 EXPORT_SYMBOL(remap_bus_range
);
1190 static void phbs_remap_io(void)
1192 struct pci_controller
*hose
, *tmp
;
1194 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1195 remap_bus_range(hose
->bus
);
1198 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1200 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1201 unsigned long offset
;
1203 if (res
->flags
& IORESOURCE_IO
) {
1204 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1206 res
->start
+= offset
;
1208 } else if (res
->flags
& IORESOURCE_MEM
) {
1209 res
->start
+= hose
->pci_mem_offset
;
1210 res
->end
+= hose
->pci_mem_offset
;
1214 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1215 struct pci_bus
*bus
)
1217 /* Update device resources. */
1220 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1221 if (dev
->resource
[i
].flags
)
1222 fixup_resource(&dev
->resource
[i
], dev
);
1224 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1226 void __devinit
pcibios_setup_new_device(struct pci_dev
*dev
)
1228 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1230 sd
->of_node
= pci_device_to_OF_node(dev
);
1232 DBG("PCI device %s OF node: %s\n", pci_name(dev
),
1233 sd
->of_node
? sd
->of_node
->full_name
: "<none>");
1235 sd
->dma_ops
= pci_dma_ops
;
1237 sd
->numa_node
= pcibus_to_node(dev
->bus
);
1241 if (ppc_md
.pci_dma_dev_setup
)
1242 ppc_md
.pci_dma_dev_setup(dev
);
1244 EXPORT_SYMBOL(pcibios_setup_new_device
);
1246 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1248 struct pci_dev
*dev
;
1250 if (ppc_md
.pci_dma_bus_setup
)
1251 ppc_md
.pci_dma_bus_setup(bus
);
1253 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1254 pcibios_setup_new_device(dev
);
1256 /* Read default IRQs and fixup if necessary */
1257 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1258 pci_read_irq_line(dev
);
1259 if (ppc_md
.pci_irq_fixup
)
1260 ppc_md
.pci_irq_fixup(dev
);
1264 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1266 struct pci_dev
*dev
= bus
->self
;
1267 struct device_node
*np
;
1269 np
= pci_bus_to_OF_node(bus
);
1271 DBG("pcibios_fixup_bus(%s)\n", np
? np
->full_name
: "<???>");
1273 if (dev
&& pci_probe_only
&&
1274 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1275 /* This is a subordinate bridge */
1277 pci_read_bridge_bases(bus
);
1278 pcibios_fixup_device_resources(dev
, bus
);
1283 if (!pci_probe_only
)
1286 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1287 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1288 pcibios_fixup_device_resources(dev
, bus
);
1290 EXPORT_SYMBOL(pcibios_fixup_bus
);
1293 * Reads the interrupt pin to determine if interrupt is use by card.
1294 * If the interrupt is used, then gets the interrupt line from the
1295 * openfirmware and sets it in the pci_dev and pci_config line.
1297 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1302 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
1305 memset(&oirq
, 0xff, sizeof(oirq
));
1307 /* Try to get a mapping from the device-tree */
1308 if (of_irq_map_pci(pci_dev
, &oirq
)) {
1311 /* If that fails, lets fallback to what is in the config
1312 * space and map that through the default controller. We
1313 * also set the type to level low since that's what PCI
1314 * interrupts are. If your platform does differently, then
1315 * either provide a proper interrupt tree or don't use this
1318 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
1322 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
1326 DBG(" -> no map ! Using irq line %d from PCI config\n", line
);
1328 virq
= irq_create_mapping(NULL
, line
);
1330 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
1332 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1333 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
1334 oirq
.controller
->full_name
);
1336 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
1339 if(virq
== NO_IRQ
) {
1340 DBG(" -> failed to map !\n");
1344 DBG(" -> mapped to linux irq %d\n", virq
);
1346 pci_dev
->irq
= virq
;
1350 EXPORT_SYMBOL(pci_read_irq_line
);
1352 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1353 const struct resource
*rsrc
,
1354 resource_size_t
*start
, resource_size_t
*end
)
1356 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1357 resource_size_t offset
= 0;
1362 if (rsrc
->flags
& IORESOURCE_IO
)
1363 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1365 /* We pass a fully fixed up address to userland for MMIO instead of
1366 * a BAR value because X is lame and expects to be able to use that
1367 * to pass to /dev/mem !
1369 * That means that we'll have potentially 64 bits values where some
1370 * userland apps only expect 32 (like X itself since it thinks only
1371 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
1374 * Hopefully, the sysfs insterface is immune to that gunk. Once X
1375 * has been fixed (and the fix spread enough), we can re-enable the
1376 * 2 lines below and pass down a BAR value to userland. In that case
1377 * we'll also have to re-enable the matching code in
1378 * __pci_mmap_make_offset().
1383 else if (rsrc
->flags
& IORESOURCE_MEM
)
1384 offset
= hose
->pci_mem_offset
;
1387 *start
= rsrc
->start
- offset
;
1388 *end
= rsrc
->end
- offset
;
1391 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1396 struct pci_controller
*hose
, *tmp
;
1397 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1398 if (hose
->arch_data
== node
)
1400 node
= node
->parent
;
1405 unsigned long pci_address_to_pio(phys_addr_t address
)
1407 struct pci_controller
*hose
, *tmp
;
1409 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1410 if (address
>= hose
->io_base_phys
&&
1411 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1412 unsigned long base
=
1413 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1414 return base
+ (address
- hose
->io_base_phys
);
1417 return (unsigned int)-1;
1419 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1422 #define IOBASE_BRIDGE_NUMBER 0
1423 #define IOBASE_MEMORY 1
1425 #define IOBASE_ISA_IO 3
1426 #define IOBASE_ISA_MEM 4
1428 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1429 unsigned long in_devfn
)
1431 struct pci_controller
* hose
;
1432 struct list_head
*ln
;
1433 struct pci_bus
*bus
= NULL
;
1434 struct device_node
*hose_node
;
1436 /* Argh ! Please forgive me for that hack, but that's the
1437 * simplest way to get existing XFree to not lockup on some
1438 * G5 machines... So when something asks for bus 0 io base
1439 * (bus 0 is HT root), we return the AGP one instead.
1441 if (machine_is_compatible("MacRISC4"))
1445 /* That syscall isn't quite compatible with PCI domains, but it's
1446 * used on pre-domains setup. We return the first match
1449 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1450 bus
= pci_bus_b(ln
);
1451 if (in_bus
>= bus
->number
&& in_bus
<= bus
->subordinate
)
1455 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1458 hose_node
= (struct device_node
*)bus
->sysdata
;
1459 hose
= PCI_DN(hose_node
)->phb
;
1462 case IOBASE_BRIDGE_NUMBER
:
1463 return (long)hose
->first_busno
;
1465 return (long)hose
->pci_mem_offset
;
1467 return (long)hose
->io_base_phys
;
1469 return (long)isa_io_base
;
1470 case IOBASE_ISA_MEM
:
1478 int pcibus_to_node(struct pci_bus
*bus
)
1480 struct pci_controller
*phb
= pci_bus_to_host(bus
);
1483 EXPORT_SYMBOL(pcibus_to_node
);