release/src-rt-6.x/linux/linux-2.6/arch/mips/mips-boards/malta/malta_int.c

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   4  * Copyright (C) 2001 Ralf Baechle
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Routines for generic manipulation of the interrupts found on the MIPS
  20  * Malta board.
  21  * The interrupt controller is located in the South Bridge a PIIX4 device
  22  * with two internal 82C95 interrupt controllers.
  23  */
  24 #include <linux/init.h>
  25 #include <linux/irq.h>
  26 #include <linux/sched.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/kernel_stat.h>
  30 #include <linux/kernel.h>
  31 #include <linux/random.h>
  32
  33 #include <asm/i8259.h>
  34 #include <asm/irq_cpu.h>
  35 #include <asm/io.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/mips-boards/malta.h>
  38 #include <asm/mips-boards/maltaint.h>
  39 #include <asm/mips-boards/piix4.h>
  40 #include <asm/gt64120.h>
  41 #include <asm/mips-boards/generic.h>
  42 #include <asm/mips-boards/msc01_pci.h>
  43 #include <asm/msc01_ic.h>
  44
  45 static DEFINE_SPINLOCK(mips_irq_lock);
  46
  47 static inline int mips_pcibios_iack(void)
  48 {
  49         int irq;
  50
  51         /*
  52          * Determine highest priority pending interrupt by performing
  53          * a PCI Interrupt Acknowledge cycle.
  54          */
  55         switch (mips_revision_sconid) {
  56         case MIPS_REVISION_SCON_SOCIT:
  57         case MIPS_REVISION_SCON_ROCIT:
  58         case MIPS_REVISION_SCON_SOCITSC:
  59         case MIPS_REVISION_SCON_SOCITSCP:
  60                 MSC_READ(MSC01_PCI_IACK, irq);
  61                 irq &= 0xff;
  62                 break;
  63         case MIPS_REVISION_SCON_GT64120:
  64                 irq = GT_READ(GT_PCI0_IACK_OFS);
  65                 irq &= 0xff;
  66                 break;
  67         case MIPS_REVISION_SCON_BONITO:
  68                 /* The following will generate a PCI IACK cycle on the
  69                  * Bonito controller. It's a little bit kludgy, but it
  70                  * was the easiest way to implement it in hardware at
  71                  * the given time.
  72                  */
  73                 BONITO_PCIMAP_CFG = 0x20000;
  74
  75                 /* Flush Bonito register block */
  76                 (void) BONITO_PCIMAP_CFG;
  77                 iob();    /* sync */
  78
  79                 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
  80                 iob();    /* sync */
  81                 irq &= 0xff;
  82                 BONITO_PCIMAP_CFG = 0;
  83                 break;
  84         default:
  85                 printk("Unknown system controller.\n");
  86                 return -1;
  87         }
  88         return irq;
  89 }
  90
  91 static inline int get_int(void)
  92 {
  93         unsigned long flags;
  94         int irq;
  95         spin_lock_irqsave(&mips_irq_lock, flags);
  96
  97         irq = mips_pcibios_iack();
  98
  99         /*
 100          * The only way we can decide if an interrupt is spurious
 101          * is by checking the 8259 registers.  This needs a spinlock
 102          * on an SMP system,  so leave it up to the generic code...
 103          */
 104
 105         spin_unlock_irqrestore(&mips_irq_lock, flags);
 106
 107         return irq;
 108 }
 109
 110 static void malta_hw0_irqdispatch(void)
 111 {
 112         int irq;
 113
 114         irq = get_int();
 115         if (irq < 0) {
 116                 return;  /* interrupt has already been cleared */
 117         }
 118
 119         do_IRQ(MALTA_INT_BASE + irq);
 120 }
 121
 122 static void corehi_irqdispatch(void)
 123 {
 124         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
 125         unsigned int pcimstat, intisr, inten, intpol;
 126         unsigned int intrcause,datalo,datahi;
 127         struct pt_regs *regs = get_irq_regs();
 128
 129         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
 130         printk("epc   : %08lx\nStatus: %08lx\n"
 131                "Cause : %08lx\nbadVaddr : %08lx\n",
 132                regs->cp0_epc, regs->cp0_status,
 133                regs->cp0_cause, regs->cp0_badvaddr);
 134
 135         /* Read all the registers and then print them as there is a
 136            problem with interspersed printk's upsetting the Bonito controller.
 137            Do it for the others too.
 138         */
 139
 140         switch (mips_revision_sconid) {
 141         case MIPS_REVISION_SCON_SOCIT:
 142         case MIPS_REVISION_SCON_ROCIT:
 143         case MIPS_REVISION_SCON_SOCITSC:
 144         case MIPS_REVISION_SCON_SOCITSCP:
 145                 ll_msc_irq();
 146                 break;
 147         case MIPS_REVISION_SCON_GT64120:
 148                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 149                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 150                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 151                 printk("GT_INTRCAUSE = %08x\n", intrcause);
 152                 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
 153                 break;
 154         case MIPS_REVISION_SCON_BONITO:
 155                 pcibadaddr = BONITO_PCIBADADDR;
 156                 pcimstat = BONITO_PCIMSTAT;
 157                 intisr = BONITO_INTISR;
 158                 inten = BONITO_INTEN;
 159                 intpol = BONITO_INTPOL;
 160                 intedge = BONITO_INTEDGE;
 161                 intsteer = BONITO_INTSTEER;
 162                 pcicmd = BONITO_PCICMD;
 163                 printk("BONITO_INTISR = %08x\n", intisr);
 164                 printk("BONITO_INTEN = %08x\n", inten);
 165                 printk("BONITO_INTPOL = %08x\n", intpol);
 166                 printk("BONITO_INTEDGE = %08x\n", intedge);
 167                 printk("BONITO_INTSTEER = %08x\n", intsteer);
 168                 printk("BONITO_PCICMD = %08x\n", pcicmd);
 169                 printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 170                 printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
 171                 break;
 172         }
 173
 174         /* We die here*/
 175         die("CoreHi interrupt", regs);
 176 }
 177
 178 static inline int clz(unsigned long x)
 179 {
 180         __asm__ (
 181         "       .set    push                                    \n"
 182         "       .set    mips32                                  \n"
 183         "       clz     %0, %1                                  \n"
 184         "       .set    pop                                     \n"
 185         : "=r" (x)
 186         : "r" (x));
 187
 188         return x;
 189 }
 190
 191 /*
 192  * Version of ffs that only looks at bits 12..15.
 193  */
 194 static inline unsigned int irq_ffs(unsigned int pending)
 195 {
 196 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 197         return -clz(pending) + 31 - CAUSEB_IP;
 198 #else
 199         unsigned int a0 = 7;
 200         unsigned int t0;
 201
 202         t0 = pending & 0xf000;
 203         t0 = t0 < 1;
 204         t0 = t0 << 2;
 205         a0 = a0 - t0;
 206         pending = pending << t0;
 207
 208         t0 = pending & 0xc000;
 209         t0 = t0 < 1;
 210         t0 = t0 << 1;
 211         a0 = a0 - t0;
 212         pending = pending << t0;
 213
 214         t0 = pending & 0x8000;
 215         t0 = t0 < 1;
 216         //t0 = t0 << 2;
 217         a0 = a0 - t0;
 218         //pending = pending << t0;
 219
 220         return a0;
 221 #endif
 222 }
 223
 224 /*
 225  * IRQs on the Malta board look basically (barring software IRQs which we
 226  * don't use at all and all external interrupt sources are combined together
 227  * on hardware interrupt 0 (MIPS IRQ 2)) like:
 228  *
 229  *      MIPS IRQ        Source
 230  *      --------        ------
 231  *             0        Software (ignored)
 232  *             1        Software (ignored)
 233  *             2        Combined hardware interrupt (hw0)
 234  *             3        Hardware (ignored)
 235  *             4        Hardware (ignored)
 236  *             5        Hardware (ignored)
 237  *             6        Hardware (ignored)
 238  *             7        R4k timer (what we use)
 239  *
 240  * We handle the IRQ according to _our_ priority which is:
 241  *
 242  * Highest ----     R4k Timer
 243  * Lowest  ----     Combined hardware interrupt
 244  *
 245  * then we just return, if multiple IRQs are pending then we will just take
 246  * another exception, big deal.
 247  */
 248
 249 asmlinkage void plat_irq_dispatch(void)
 250 {
 251         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 252         int irq;
 253
 254         irq = irq_ffs(pending);
 255
 256         if (irq == MIPSCPU_INT_I8259A)
 257                 malta_hw0_irqdispatch();
 258         else if (irq >= 0)
 259                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
 260         else
 261                 spurious_interrupt();
 262 }
 263
 264 static struct irqaction i8259irq = {
 265         .handler = no_action,
 266         .name = "XT-PIC cascade"
 267 };
 268
 269 static struct irqaction corehi_irqaction = {
 270         .handler = no_action,
 271         .name = "CoreHi"
 272 };
 273
 274 msc_irqmap_t __initdata msc_irqmap[] = {
 275         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 276         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 277 };
 278 int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
 279
 280 msc_irqmap_t __initdata msc_eicirqmap[] = {
 281         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 282         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 283         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 284         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 285         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 286         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 287         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 288         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 289         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 290         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 291 };
 292 int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 293
 294 void __init arch_init_irq(void)
 295 {
 296         init_i8259_irqs();
 297
 298         if (!cpu_has_veic)
 299                 mips_cpu_irq_init();
 300
 301         switch(mips_revision_sconid) {
 302         case MIPS_REVISION_SCON_SOCIT:
 303         case MIPS_REVISION_SCON_ROCIT:
 304                 if (cpu_has_veic)
 305                         init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
 306                 else
 307                         init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
 308                 break;
 309
 310         case MIPS_REVISION_SCON_SOCITSC:
 311         case MIPS_REVISION_SCON_SOCITSCP:
 312                 if (cpu_has_veic)
 313                         init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
 314                 else
 315                         init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
 316         }
 317
 318         if (cpu_has_veic) {
 319                 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
 320                 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
 321                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
 322                 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
 323         }
 324         else if (cpu_has_vint) {
 325                 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
 326                 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
 327 #ifdef CONFIG_MIPS_MT_SMTC
 328                 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
 329                         (0x100 << MIPSCPU_INT_I8259A));
 330                 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
 331                         &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
 332 #else /* Not SMTC */
 333                 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 334                 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 335 #endif /* CONFIG_MIPS_MT_SMTC */
 336         }
 337         else {
 338                 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
 339                 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
 340         }
 341 }