2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
16 #include <linux/init.h>
17 #include <linux/threads.h>
20 #include <asm/asmmacro.h>
21 #include <asm/irqflags.h>
22 #include <asm/regdef.h>
24 #include <asm/pgtable-bits.h>
25 #include <asm/mipsregs.h>
26 #include <asm/stackframe.h>
28 #include <kernel-entry-init.h>
30 .macro ARC64_TWIDDLE_PC
31 #if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
32 /* We get launched at a XKPHYS address but the kernel is linked to
33 run at a KSEG0 address, so jump there. */
41 * inputs are the text nasid in t1, data nasid in t2.
43 .macro MAPPED_KERNEL_SETUP_TLB
44 #ifdef CONFIG_MAPPED_KERNEL
46 * This needs to read the nasid - assume 0 for now.
47 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
50 dli t0, 0xffffffffc0000000
52 li t0, 0x1c000 # Offset of text into node memory
53 dsll t1, NASID_SHFT # Shift text nasid into place
54 dsll t2, NASID_SHFT # Same for data nasid
55 or t1, t1, t0 # Physical load address of kernel text
56 or t2, t2, t0 # Physical load address of kernel data
59 dsll t1, 6 # Get pfn into place
60 dsll t2, 6 # Get pfn into place
61 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
63 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
64 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
66 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
67 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
80 * For the moment disable interrupts, mark the kernel mode and
81 * set ST0_KX so that the CPU does not spit fire when using
82 * 64-bit addresses. A full initialization of the CPU's status
83 * register is done later in per_cpu_trap_init().
85 .macro setup_c0_status set clr
87 #ifdef CONFIG_MIPS_MT_SMTC
89 * For SMTC, we need to set privilege and disable interrupts only for
90 * the current TC, using the TCStatus register.
93 /* Fortunately CU 0 is in the same place in both registers */
94 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
95 li t1, ST0_CU0 | 0x08001c00
97 /* Clear TKSU, leave IXMT */
101 /* We need to leave the global IE bit set, but clear EXL...*/
103 or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
104 xor t0, ST0_EXL | ST0_ERL | \clr
108 or t0, ST0_CU0|\set|0x1f|\clr
117 .macro setup_c0_status_pri
119 setup_c0_status ST0_KX 0
125 .macro setup_c0_status_sec
127 setup_c0_status ST0_KX ST0_BEV
129 setup_c0_status 0 ST0_BEV
133 #ifdef CONFIG_BCM47XX
135 #define eret nop; nop; eret
142 * Reserved space for exception handlers.
143 * Necessary for machines which link their kernels at KSEG0.
147 EXPORT(stext) # used for profiling
150 #ifdef CONFIG_MIPS_SIM
152 * Give us a fighting chance of running if execution beings at the
153 * kernel load address. This is needed because this platform does
154 * not have a ELF loader yet.
160 NESTED(kernel_entry, 16, sp) # kernel entry point
162 kernel_entry_setup # cpu specific setup
168 #ifdef CONFIG_MIPS_MT_SMTC
170 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
171 * We still need to enable interrupts globally in Status,
174 * TCContext is used to track interrupt levels under
175 * service in SMTC kernel. Clear for boot TC before
176 * allowing any interrupts.
178 mtc0 zero, CP0_TCCONTEXT
184 #endif /* CONFIG_MIPS_MT_SMTC */
186 #if !defined(CONFIG_HWSIM) || defined(CONFIG_HWSIM_ZMEM)
187 PTR_LA t0, __bss_start # clear .bss
189 PTR_LA t1, __bss_stop - LONGSIZE
191 PTR_ADDIU t0, LONGSIZE
196 LONG_S a0, fw_arg0 # firmware arguments
201 MTC0 zero, CP0_CONTEXT # clear context register
202 PTR_LA $28, init_thread_union
203 /* Set the SP after an empty pt_regs. */
204 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
206 back_to_back_c0_hazard
207 set_saved_sp sp, t0, t1
208 PTR_SUBU sp, 4 * SZREG # init stack pointer
219 #ifndef CONFIG_HOTPLUG_CPU
220 __INIT /* no __CPUINIT; it's a 2.6.25 thing */
223 * SMP slave cpus entry point. Board specific code for bootstrap calls this
224 * function after setting up the stack and gp registers.
226 NESTED(smp_bootstrap, 16, sp)
227 #ifdef CONFIG_MIPS_MT_SMTC
229 * Read-modify-writes of Status must be atomic, and this
230 * is one case where CLI is invoked without EXL being
231 * necessarily set. The CLI and setup_c0_status will
232 * in fact be redundant for all but the first TC of
233 * each VPE being booted.
235 DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
237 #endif /* CONFIG_MIPS_MT_SMTC */
240 #ifdef CONFIG_MIPS_MT_SMTC
241 andi t2, t2, VPECONTROL_TE
245 #endif /* CONFIG_MIPS_MT_SMTC */
248 #endif /* CONFIG_SMP */
250 #ifndef CONFIG_HOTPLUG_CPU