release/src-rt-6.x/linux/linux-2.6/arch/mips/kernel/branch.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2001 MIPS Technologies, Inc.
   8  */
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/signal.h>
  12 #include <asm/branch.h>
  13 #include <asm/cpu.h>
  14 #include <asm/cpu-features.h>
  15 #include <asm/fpu.h>
  16 #include <asm/inst.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/uaccess.h>
  19
  20 /*
  21  * Compute the return address and do emulate branch simulation, if required.
  22  */
  23 int __compute_return_epc(struct pt_regs *regs)
  24 {
  25         unsigned int *addr, bit, fcr31, dspcontrol;
  26         long epc;
  27         union mips_instruction insn;
  28
  29         epc = regs->cp0_epc;
  30         if (epc & 3)
  31                 goto unaligned;
  32
  33         /*
  34          * Read the instruction
  35          */
  36         addr = (unsigned int *) epc;
  37         if (__get_user(insn.word, addr)) {
  38                 force_sig(SIGSEGV, current);
  39                 return -EFAULT;
  40         }
  41
  42         switch (insn.i_format.opcode) {
  43         /*
  44          * jr and jalr are in r_format format.
  45          */
  46         case spec_op:
  47                 switch (insn.r_format.func) {
  48                 case jalr_op:
  49                         regs->regs[insn.r_format.rd] = epc + 8;
  50                         /* Fall through */
  51                 case jr_op:
  52                         regs->cp0_epc = regs->regs[insn.r_format.rs];
  53                         break;
  54                 }
  55                 break;
  56
  57         /*
  58          * This group contains:
  59          * bltz_op, bgez_op, bltzl_op, bgezl_op,
  60          * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
  61          */
  62         case bcond_op:
  63                 switch (insn.i_format.rt) {
  64                 case bltz_op:
  65                 case bltzl_op:
  66                         if ((long)regs->regs[insn.i_format.rs] < 0)
  67                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  68                         else
  69                                 epc += 8;
  70                         regs->cp0_epc = epc;
  71                         break;
  72
  73                 case bgez_op:
  74                 case bgezl_op:
  75                         if ((long)regs->regs[insn.i_format.rs] >= 0)
  76                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  77                         else
  78                                 epc += 8;
  79                         regs->cp0_epc = epc;
  80                         break;
  81
  82                 case bltzal_op:
  83                 case bltzall_op:
  84                         regs->regs[31] = epc + 8;
  85                         if ((long)regs->regs[insn.i_format.rs] < 0)
  86                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  87                         else
  88                                 epc += 8;
  89                         regs->cp0_epc = epc;
  90                         break;
  91
  92                 case bgezal_op:
  93                 case bgezall_op:
  94                         regs->regs[31] = epc + 8;
  95                         if ((long)regs->regs[insn.i_format.rs] >= 0)
  96                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
  97                         else
  98                                 epc += 8;
  99                         regs->cp0_epc = epc;
 100                         break;
 101                 case bposge32_op:
 102                         if (!cpu_has_dsp)
 103                                 goto sigill;
 104
 105                         dspcontrol = rddsp(0x01);
 106
 107                         if (dspcontrol >= 32) {
 108                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 109                         } else
 110                                 epc += 8;
 111                         regs->cp0_epc = epc;
 112                         break;
 113                 }
 114                 break;
 115
 116         /*
 117          * These are unconditional and in j_format.
 118          */
 119         case jal_op:
 120                 regs->regs[31] = regs->cp0_epc + 8;
 121         case j_op:
 122                 epc += 4;
 123                 epc >>= 28;
 124                 epc <<= 28;
 125                 epc |= (insn.j_format.target << 2);
 126                 regs->cp0_epc = epc;
 127                 break;
 128
 129         /*
 130          * These are conditional and in i_format.
 131          */
 132         case beq_op:
 133         case beql_op:
 134                 if (regs->regs[insn.i_format.rs] ==
 135                     regs->regs[insn.i_format.rt])
 136                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 137                 else
 138                         epc += 8;
 139                 regs->cp0_epc = epc;
 140                 break;
 141
 142         case bne_op:
 143         case bnel_op:
 144                 if (regs->regs[insn.i_format.rs] !=
 145                     regs->regs[insn.i_format.rt])
 146                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 147                 else
 148                         epc += 8;
 149                 regs->cp0_epc = epc;
 150                 break;
 151
 152         case blez_op: /* not really i_format */
 153         case blezl_op:
 154                 /* rt field assumed to be zero */
 155                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 156                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 157                 else
 158                         epc += 8;
 159                 regs->cp0_epc = epc;
 160                 break;
 161
 162         case bgtz_op:
 163         case bgtzl_op:
 164                 /* rt field assumed to be zero */
 165                 if ((long)regs->regs[insn.i_format.rs] > 0)
 166                         epc = epc + 4 + (insn.i_format.simmediate << 2);
 167                 else
 168                         epc += 8;
 169                 regs->cp0_epc = epc;
 170                 break;
 171
 172         /*
 173          * And now the FPA/cp1 branch instructions.
 174          */
 175         case cop1_op:
 176                 preempt_disable();
 177                 if (is_fpu_owner())
 178                         asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 179                 else
 180                         fcr31 = current->thread.fpu.fcr31;
 181                 preempt_enable();
 182
 183                 bit = (insn.i_format.rt >> 2);
 184                 bit += (bit != 0);
 185                 bit += 23;
 186                 switch (insn.i_format.rt & 3) {
 187                 case 0: /* bc1f */
 188                 case 2: /* bc1fl */
 189                         if (~fcr31 & (1 << bit))
 190                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 191                         else
 192                                 epc += 8;
 193                         regs->cp0_epc = epc;
 194                         break;
 195
 196                 case 1: /* bc1t */
 197                 case 3: /* bc1tl */
 198                         if (fcr31 & (1 << bit))
 199                                 epc = epc + 4 + (insn.i_format.simmediate << 2);
 200                         else
 201                                 epc += 8;
 202                         regs->cp0_epc = epc;
 203                         break;
 204                 }
 205                 break;
 206         }
 207
 208         return 0;
 209
 210 unaligned:
 211         printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
 212         force_sig(SIGBUS, current);
 213         return -EFAULT;
 214
 215 sigill:
 216         printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
 217         force_sig(SIGBUS, current);
 218         return -EFAULT;
 219 }