3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
8 * Copyright 2004 Embedded Edge, LLC
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/spinlock.h>
38 #include <linux/string.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/module.h>
42 #include <asm/mach-au1x00/au1000.h>
43 #include <asm/mach-au1x00/au1xxx_dbdma.h>
44 #include <asm/system.h>
47 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
50 * The Descriptor Based DMA supports up to 16 channels.
52 * There are 32 devices defined. We keep an internal structure
53 * of devices using these channels, along with additional
56 * We allocate the descriptors and allow access to them through various
57 * functions. The drivers allocate the data buffers and assign them
60 static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock
);
62 /* I couldn't find a macro that did this......
64 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
66 static dbdma_global_t
*dbdma_gptr
= (dbdma_global_t
*)DDMA_GLOBAL_BASE
;
67 static int dbdma_initialized
=0;
68 static void au1xxx_dbdma_init(void);
70 static dbdev_tab_t dbdev_tab
[] = {
71 #ifdef CONFIG_SOC_AU1550
73 { DSCR_CMD0_UART0_TX
, DEV_FLAGS_OUT
, 0, 8, 0x11100004, 0, 0 },
74 { DSCR_CMD0_UART0_RX
, DEV_FLAGS_IN
, 0, 8, 0x11100000, 0, 0 },
75 { DSCR_CMD0_UART3_TX
, DEV_FLAGS_OUT
, 0, 8, 0x11400004, 0, 0 },
76 { DSCR_CMD0_UART3_RX
, DEV_FLAGS_IN
, 0, 8, 0x11400000, 0, 0 },
79 { DSCR_CMD0_DMA_REQ0
, 0, 0, 0, 0x00000000, 0, 0 },
80 { DSCR_CMD0_DMA_REQ1
, 0, 0, 0, 0x00000000, 0, 0 },
81 { DSCR_CMD0_DMA_REQ2
, 0, 0, 0, 0x00000000, 0, 0 },
82 { DSCR_CMD0_DMA_REQ3
, 0, 0, 0, 0x00000000, 0, 0 },
85 { DSCR_CMD0_USBDEV_RX0
, DEV_FLAGS_IN
, 4, 8, 0x10200000, 0, 0 },
86 { DSCR_CMD0_USBDEV_TX0
, DEV_FLAGS_OUT
, 4, 8, 0x10200004, 0, 0 },
87 { DSCR_CMD0_USBDEV_TX1
, DEV_FLAGS_OUT
, 4, 8, 0x10200008, 0, 0 },
88 { DSCR_CMD0_USBDEV_TX2
, DEV_FLAGS_OUT
, 4, 8, 0x1020000c, 0, 0 },
89 { DSCR_CMD0_USBDEV_RX3
, DEV_FLAGS_IN
, 4, 8, 0x10200010, 0, 0 },
90 { DSCR_CMD0_USBDEV_RX4
, DEV_FLAGS_IN
, 4, 8, 0x10200014, 0, 0 },
93 { DSCR_CMD0_PSC0_TX
, DEV_FLAGS_OUT
, 0, 0, 0x11a0001c, 0, 0 },
94 { DSCR_CMD0_PSC0_RX
, DEV_FLAGS_IN
, 0, 0, 0x11a0001c, 0, 0 },
97 { DSCR_CMD0_PSC1_TX
, DEV_FLAGS_OUT
, 0, 0, 0x11b0001c, 0, 0 },
98 { DSCR_CMD0_PSC1_RX
, DEV_FLAGS_IN
, 0, 0, 0x11b0001c, 0, 0 },
101 { DSCR_CMD0_PSC2_TX
, DEV_FLAGS_OUT
, 0, 0, 0x10a0001c, 0, 0 },
102 { DSCR_CMD0_PSC2_RX
, DEV_FLAGS_IN
, 0, 0, 0x10a0001c, 0, 0 },
105 { DSCR_CMD0_PSC3_TX
, DEV_FLAGS_OUT
, 0, 0, 0x10b0001c, 0, 0 },
106 { DSCR_CMD0_PSC3_RX
, DEV_FLAGS_IN
, 0, 0, 0x10b0001c, 0, 0 },
108 { DSCR_CMD0_PCI_WRITE
, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
109 { DSCR_CMD0_NAND_FLASH
, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
112 { DSCR_CMD0_MAC0_RX
, DEV_FLAGS_IN
, 0, 0, 0x00000000, 0, 0 },
113 { DSCR_CMD0_MAC0_TX
, DEV_FLAGS_OUT
, 0, 0, 0x00000000, 0, 0 },
116 { DSCR_CMD0_MAC1_RX
, DEV_FLAGS_IN
, 0, 0, 0x00000000, 0, 0 },
117 { DSCR_CMD0_MAC1_TX
, DEV_FLAGS_OUT
, 0, 0, 0x00000000, 0, 0 },
119 #endif /* CONFIG_SOC_AU1550 */
121 #ifdef CONFIG_SOC_AU1200
122 { DSCR_CMD0_UART0_TX
, DEV_FLAGS_OUT
, 0, 8, 0x11100004, 0, 0 },
123 { DSCR_CMD0_UART0_RX
, DEV_FLAGS_IN
, 0, 8, 0x11100000, 0, 0 },
124 { DSCR_CMD0_UART1_TX
, DEV_FLAGS_OUT
, 0, 8, 0x11200004, 0, 0 },
125 { DSCR_CMD0_UART1_RX
, DEV_FLAGS_IN
, 0, 8, 0x11200000, 0, 0 },
127 { DSCR_CMD0_DMA_REQ0
, 0, 0, 0, 0x00000000, 0, 0 },
128 { DSCR_CMD0_DMA_REQ1
, 0, 0, 0, 0x00000000, 0, 0 },
130 { DSCR_CMD0_MAE_BE
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
131 { DSCR_CMD0_MAE_FE
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
132 { DSCR_CMD0_MAE_BOTH
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
133 { DSCR_CMD0_LCD
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
135 { DSCR_CMD0_SDMS_TX0
, DEV_FLAGS_OUT
, 4, 8, 0x10600000, 0, 0 },
136 { DSCR_CMD0_SDMS_RX0
, DEV_FLAGS_IN
, 4, 8, 0x10600004, 0, 0 },
137 { DSCR_CMD0_SDMS_TX1
, DEV_FLAGS_OUT
, 4, 8, 0x10680000, 0, 0 },
138 { DSCR_CMD0_SDMS_RX1
, DEV_FLAGS_IN
, 4, 8, 0x10680004, 0, 0 },
140 { DSCR_CMD0_AES_RX
, DEV_FLAGS_IN
, 4, 32, 0x10300008, 0, 0 },
141 { DSCR_CMD0_AES_TX
, DEV_FLAGS_OUT
, 4, 32, 0x10300004, 0, 0 },
143 { DSCR_CMD0_PSC0_TX
, DEV_FLAGS_OUT
, 0, 16, 0x11a0001c, 0, 0 },
144 { DSCR_CMD0_PSC0_RX
, DEV_FLAGS_IN
, 0, 16, 0x11a0001c, 0, 0 },
145 { DSCR_CMD0_PSC0_SYNC
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
147 { DSCR_CMD0_PSC1_TX
, DEV_FLAGS_OUT
, 0, 16, 0x11b0001c, 0, 0 },
148 { DSCR_CMD0_PSC1_RX
, DEV_FLAGS_IN
, 0, 16, 0x11b0001c, 0, 0 },
149 { DSCR_CMD0_PSC1_SYNC
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
151 { DSCR_CMD0_CIM_RXA
, DEV_FLAGS_IN
, 0, 32, 0x14004020, 0, 0 },
152 { DSCR_CMD0_CIM_RXB
, DEV_FLAGS_IN
, 0, 32, 0x14004040, 0, 0 },
153 { DSCR_CMD0_CIM_RXC
, DEV_FLAGS_IN
, 0, 32, 0x14004060, 0, 0 },
154 { DSCR_CMD0_CIM_SYNC
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
156 { DSCR_CMD0_NAND_FLASH
, DEV_FLAGS_IN
, 0, 0, 0x00000000, 0, 0 },
158 #endif // CONFIG_SOC_AU1200
160 { DSCR_CMD0_THROTTLE
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
161 { DSCR_CMD0_ALWAYS
, DEV_FLAGS_ANYUSE
, 0, 0, 0x00000000, 0, 0 },
163 /* Provide 16 user definable device types */
164 { ~0, 0, 0, 0, 0, 0, 0 },
165 { ~0, 0, 0, 0, 0, 0, 0 },
166 { ~0, 0, 0, 0, 0, 0, 0 },
167 { ~0, 0, 0, 0, 0, 0, 0 },
168 { ~0, 0, 0, 0, 0, 0, 0 },
169 { ~0, 0, 0, 0, 0, 0, 0 },
170 { ~0, 0, 0, 0, 0, 0, 0 },
171 { ~0, 0, 0, 0, 0, 0, 0 },
172 { ~0, 0, 0, 0, 0, 0, 0 },
173 { ~0, 0, 0, 0, 0, 0, 0 },
174 { ~0, 0, 0, 0, 0, 0, 0 },
175 { ~0, 0, 0, 0, 0, 0, 0 },
176 { ~0, 0, 0, 0, 0, 0, 0 },
177 { ~0, 0, 0, 0, 0, 0, 0 },
178 { ~0, 0, 0, 0, 0, 0, 0 },
179 { ~0, 0, 0, 0, 0, 0, 0 },
182 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
184 static chan_tab_t
*chan_tab_ptr
[NUM_DBDMA_CHANS
];
187 find_dbdev_id (u32 id
)
191 for (i
= 0; i
< DBDEV_TAB_SIZE
; ++i
) {
199 void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t
*dp
)
201 return phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
203 EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt
);
206 au1xxx_ddma_add_device(dbdev_tab_t
*dev
)
210 static u16 new_id
=0x1000;
212 p
= find_dbdev_id(~0);
215 memcpy(p
, dev
, sizeof(dbdev_tab_t
));
216 p
->dev_id
= DSCR_DEV2CUSTOM_ID(new_id
,dev
->dev_id
);
220 printk("add_device: id:%x flags:%x padd:%x\n",
221 p
->dev_id
, p
->dev_flags
, p
->dev_physaddr
);
227 EXPORT_SYMBOL(au1xxx_ddma_add_device
);
229 /* Allocate a channel and return a non-zero descriptor if successful.
232 au1xxx_dbdma_chan_alloc(u32 srcid
, u32 destid
,
233 void (*callback
)(int, void *), void *callparam
)
239 dbdev_tab_t
*stp
, *dtp
;
243 /* We do the intialization on the first channel allocation.
244 * We have to wait because of the interrupt handler initialization
245 * which can't be done successfully during board set up.
247 if (!dbdma_initialized
)
249 dbdma_initialized
= 1;
251 if ((stp
= find_dbdev_id(srcid
)) == NULL
)
253 if ((dtp
= find_dbdev_id(destid
)) == NULL
)
259 /* Check to see if we can get both channels.
261 spin_lock_irqsave(&au1xxx_dbdma_spin_lock
, flags
);
262 if (!(stp
->dev_flags
& DEV_FLAGS_INUSE
) ||
263 (stp
->dev_flags
& DEV_FLAGS_ANYUSE
)) {
265 stp
->dev_flags
|= DEV_FLAGS_INUSE
;
266 if (!(dtp
->dev_flags
& DEV_FLAGS_INUSE
) ||
267 (dtp
->dev_flags
& DEV_FLAGS_ANYUSE
)) {
268 /* Got destination */
269 dtp
->dev_flags
|= DEV_FLAGS_INUSE
;
272 /* Can't get dest. Release src.
274 stp
->dev_flags
&= ~DEV_FLAGS_INUSE
;
281 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock
, flags
);
284 /* Let's see if we can allocate a channel for it.
288 spin_lock_irqsave(&au1xxx_dbdma_spin_lock
, flags
);
289 for (i
=0; i
<NUM_DBDMA_CHANS
; i
++) {
290 if (chan_tab_ptr
[i
] == NULL
) {
291 /* If kmalloc fails, it is caught below same
292 * as a channel not available.
294 ctp
= kmalloc(sizeof(chan_tab_t
), GFP_ATOMIC
);
295 chan_tab_ptr
[i
] = ctp
;
299 spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock
, flags
);
302 memset(ctp
, 0, sizeof(chan_tab_t
));
303 ctp
->chan_index
= chan
= i
;
304 dcp
= DDMA_CHANNEL_BASE
;
305 dcp
+= (0x0100 * chan
);
306 ctp
->chan_ptr
= (au1x_dma_chan_t
*)dcp
;
307 cp
= (au1x_dma_chan_t
*)dcp
;
309 ctp
->chan_dest
= dtp
;
310 ctp
->chan_callback
= callback
;
311 ctp
->chan_callparam
= callparam
;
313 /* Initialize channel configuration.
316 if (stp
->dev_intlevel
)
318 if (stp
->dev_intpolarity
)
320 if (dtp
->dev_intlevel
)
322 if (dtp
->dev_intpolarity
)
324 if ((stp
->dev_flags
& DEV_FLAGS_SYNC
) ||
325 (dtp
->dev_flags
& DEV_FLAGS_SYNC
))
330 /* Return a non-zero value that can be used to
331 * find the channel information in subsequent
334 rv
= (u32
)(&chan_tab_ptr
[chan
]);
337 /* Release devices */
338 stp
->dev_flags
&= ~DEV_FLAGS_INUSE
;
339 dtp
->dev_flags
&= ~DEV_FLAGS_INUSE
;
344 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc
);
346 /* Set the device width if source or destination is a FIFO.
347 * Should be 8, 16, or 32 bits.
350 au1xxx_dbdma_set_devwidth(u32 chanid
, int bits
)
354 dbdev_tab_t
*stp
, *dtp
;
356 ctp
= *((chan_tab_t
**)chanid
);
358 dtp
= ctp
->chan_dest
;
361 if (stp
->dev_flags
& DEV_FLAGS_IN
) { /* Source in fifo */
362 rv
= stp
->dev_devwidth
;
363 stp
->dev_devwidth
= bits
;
365 if (dtp
->dev_flags
& DEV_FLAGS_OUT
) { /* Destination out fifo */
366 rv
= dtp
->dev_devwidth
;
367 dtp
->dev_devwidth
= bits
;
372 EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth
);
374 /* Allocate a descriptor ring, initializing as much as possible.
377 au1xxx_dbdma_ring_alloc(u32 chanid
, int entries
)
380 u32 desc_base
, srcid
, destid
;
381 u32 cmd0
, cmd1
, src1
, dest1
;
384 dbdev_tab_t
*stp
, *dtp
;
385 au1x_ddma_desc_t
*dp
;
387 /* I guess we could check this to be within the
388 * range of the table......
390 ctp
= *((chan_tab_t
**)chanid
);
392 dtp
= ctp
->chan_dest
;
394 /* The descriptors must be 32-byte aligned. There is a
395 * possibility the allocation will give us such an address,
396 * and if we try that first we are likely to not waste larger
399 desc_base
= (u32
)kmalloc(entries
* sizeof(au1x_ddma_desc_t
),
404 if (desc_base
& 0x1f) {
405 /* Lost....do it again, allocate extra, and round
408 kfree((const void *)desc_base
);
409 i
= entries
* sizeof(au1x_ddma_desc_t
);
410 i
+= (sizeof(au1x_ddma_desc_t
) - 1);
411 if ((desc_base
= (u32
)kmalloc(i
, GFP_KERNEL
|GFP_DMA
)) == 0)
414 ctp
->cdb_membase
= desc_base
;
415 desc_base
= ALIGN_ADDR(desc_base
, sizeof(au1x_ddma_desc_t
));
417 ctp
->cdb_membase
= desc_base
;
419 dp
= (au1x_ddma_desc_t
*)desc_base
;
421 /* Keep track of the base descriptor.
423 ctp
->chan_desc_base
= dp
;
425 /* Initialize the rings with as much information as we know.
428 destid
= dtp
->dev_id
;
430 cmd0
= cmd1
= src1
= dest1
= 0;
433 cmd0
|= DSCR_CMD0_SID(srcid
);
434 cmd0
|= DSCR_CMD0_DID(destid
);
435 cmd0
|= DSCR_CMD0_IE
| DSCR_CMD0_CV
;
436 cmd0
|= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE
);
438 /* is it mem to mem transfer? */
439 if(((DSCR_CUSTOM2DEV_ID(srcid
) == DSCR_CMD0_THROTTLE
) || (DSCR_CUSTOM2DEV_ID(srcid
) == DSCR_CMD0_ALWAYS
)) &&
440 ((DSCR_CUSTOM2DEV_ID(destid
) == DSCR_CMD0_THROTTLE
) || (DSCR_CUSTOM2DEV_ID(destid
) == DSCR_CMD0_ALWAYS
))) {
441 cmd0
|= DSCR_CMD0_MEM
;
444 switch (stp
->dev_devwidth
) {
446 cmd0
|= DSCR_CMD0_SW(DSCR_CMD0_BYTE
);
449 cmd0
|= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD
);
453 cmd0
|= DSCR_CMD0_SW(DSCR_CMD0_WORD
);
457 switch (dtp
->dev_devwidth
) {
459 cmd0
|= DSCR_CMD0_DW(DSCR_CMD0_BYTE
);
462 cmd0
|= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD
);
466 cmd0
|= DSCR_CMD0_DW(DSCR_CMD0_WORD
);
470 /* If the device is marked as an in/out FIFO, ensure it is
473 if (stp
->dev_flags
& DEV_FLAGS_IN
)
474 cmd0
|= DSCR_CMD0_SN
; /* Source in fifo */
475 if (dtp
->dev_flags
& DEV_FLAGS_OUT
)
476 cmd0
|= DSCR_CMD0_DN
; /* Destination out fifo */
478 /* Set up source1. For now, assume no stride and increment.
479 * A channel attribute update can change this later.
481 switch (stp
->dev_tsize
) {
483 src1
|= DSCR_SRC1_STS(DSCR_xTS_SIZE1
);
486 src1
|= DSCR_SRC1_STS(DSCR_xTS_SIZE2
);
489 src1
|= DSCR_SRC1_STS(DSCR_xTS_SIZE4
);
493 src1
|= DSCR_SRC1_STS(DSCR_xTS_SIZE8
);
497 /* If source input is fifo, set static address.
499 if (stp
->dev_flags
& DEV_FLAGS_IN
) {
500 if ( stp
->dev_flags
& DEV_FLAGS_BURSTABLE
)
501 src1
|= DSCR_SRC1_SAM(DSCR_xAM_BURST
);
503 src1
|= DSCR_SRC1_SAM(DSCR_xAM_STATIC
);
506 if (stp
->dev_physaddr
)
507 src0
= stp
->dev_physaddr
;
509 /* Set up dest1. For now, assume no stride and increment.
510 * A channel attribute update can change this later.
512 switch (dtp
->dev_tsize
) {
514 dest1
|= DSCR_DEST1_DTS(DSCR_xTS_SIZE1
);
517 dest1
|= DSCR_DEST1_DTS(DSCR_xTS_SIZE2
);
520 dest1
|= DSCR_DEST1_DTS(DSCR_xTS_SIZE4
);
524 dest1
|= DSCR_DEST1_DTS(DSCR_xTS_SIZE8
);
528 /* If destination output is fifo, set static address.
530 if (dtp
->dev_flags
& DEV_FLAGS_OUT
) {
531 if ( dtp
->dev_flags
& DEV_FLAGS_BURSTABLE
)
532 dest1
|= DSCR_DEST1_DAM(DSCR_xAM_BURST
);
534 dest1
|= DSCR_DEST1_DAM(DSCR_xAM_STATIC
);
536 if (dtp
->dev_physaddr
)
537 dest0
= dtp
->dev_physaddr
;
540 printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
541 dtp
->dev_id
, stp
->dev_id
, cmd0
, cmd1
, src0
, src1
, dest0
, dest1
);
543 for (i
=0; i
<entries
; i
++) {
544 dp
->dscr_cmd0
= cmd0
;
545 dp
->dscr_cmd1
= cmd1
;
546 dp
->dscr_source0
= src0
;
547 dp
->dscr_source1
= src1
;
548 dp
->dscr_dest0
= dest0
;
549 dp
->dscr_dest1
= dest1
;
553 dp
->dscr_nxtptr
= DSCR_NXTPTR(virt_to_phys(dp
+ 1));
557 /* Make last descrptor point to the first.
560 dp
->dscr_nxtptr
= DSCR_NXTPTR(virt_to_phys(ctp
->chan_desc_base
));
561 ctp
->get_ptr
= ctp
->put_ptr
= ctp
->cur_ptr
= ctp
->chan_desc_base
;
563 return (u32
)(ctp
->chan_desc_base
);
565 EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc
);
567 /* Put a source buffer into the DMA ring.
568 * This updates the source pointer and byte count. Normally used
569 * for memory to fifo transfers.
572 _au1xxx_dbdma_put_source(u32 chanid
, void *buf
, int nbytes
, u32 flags
)
575 au1x_ddma_desc_t
*dp
;
577 /* I guess we could check this to be within the
578 * range of the table......
580 ctp
= *((chan_tab_t
**)chanid
);
582 /* We should have multiple callers for a particular channel,
583 * an interrupt doesn't affect this pointer nor the descriptor,
584 * so no locking should be needed.
588 /* If the descriptor is valid, we are way ahead of the DMA
589 * engine, so just return an error condition.
591 if (dp
->dscr_cmd0
& DSCR_CMD0_V
) {
595 /* Load up buffer address and byte count.
597 dp
->dscr_source0
= virt_to_phys(buf
);
598 dp
->dscr_cmd1
= nbytes
;
600 if (flags
& DDMA_FLAGS_IE
)
601 dp
->dscr_cmd0
|= DSCR_CMD0_IE
;
602 if (flags
& DDMA_FLAGS_NOIE
)
603 dp
->dscr_cmd0
&= ~DSCR_CMD0_IE
;
606 * There is an errata on the Au1200/Au1550 parts that could result
607 * in "stale" data being DMA'd. It has to do with the snoop logic on
608 * the dache eviction buffer. NONCOHERENT_IO is on by default for
609 * these parts. If it is fixedin the future, these dma_cache_inv will
610 * just be nothing more than empty macros. See io.h.
612 dma_cache_wback_inv((unsigned long)buf
, nbytes
);
613 dp
->dscr_cmd0
|= DSCR_CMD0_V
; /* Let it rip */
615 dma_cache_wback_inv((unsigned long)dp
, sizeof(dp
));
616 ctp
->chan_ptr
->ddma_dbell
= 0;
618 /* Get next descriptor pointer.
620 ctp
->put_ptr
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
622 /* return something not zero.
626 EXPORT_SYMBOL(_au1xxx_dbdma_put_source
);
628 /* Put a destination buffer into the DMA ring.
629 * This updates the destination pointer and byte count. Normally used
630 * to place an empty buffer into the ring for fifo to memory transfers.
633 _au1xxx_dbdma_put_dest(u32 chanid
, void *buf
, int nbytes
, u32 flags
)
636 au1x_ddma_desc_t
*dp
;
638 /* I guess we could check this to be within the
639 * range of the table......
641 ctp
= *((chan_tab_t
**)chanid
);
643 /* We should have multiple callers for a particular channel,
644 * an interrupt doesn't affect this pointer nor the descriptor,
645 * so no locking should be needed.
649 /* If the descriptor is valid, we are way ahead of the DMA
650 * engine, so just return an error condition.
652 if (dp
->dscr_cmd0
& DSCR_CMD0_V
)
655 /* Load up buffer address and byte count */
658 if (flags
& DDMA_FLAGS_IE
)
659 dp
->dscr_cmd0
|= DSCR_CMD0_IE
;
660 if (flags
& DDMA_FLAGS_NOIE
)
661 dp
->dscr_cmd0
&= ~DSCR_CMD0_IE
;
663 dp
->dscr_dest0
= virt_to_phys(buf
);
664 dp
->dscr_cmd1
= nbytes
;
666 printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
667 dp
->dscr_cmd0
, dp
->dscr_cmd1
, dp
->dscr_source0
,
668 dp
->dscr_source1
, dp
->dscr_dest0
, dp
->dscr_dest1
);
671 * There is an errata on the Au1200/Au1550 parts that could result in
672 * "stale" data being DMA'd. It has to do with the snoop logic on the
673 * dache eviction buffer. NONCOHERENT_IO is on by default for these
674 * parts. If it is fixedin the future, these dma_cache_inv will just
675 * be nothing more than empty macros. See io.h.
677 dma_cache_inv((unsigned long)buf
,nbytes
);
678 dp
->dscr_cmd0
|= DSCR_CMD0_V
; /* Let it rip */
680 dma_cache_wback_inv((unsigned long)dp
, sizeof(dp
));
681 ctp
->chan_ptr
->ddma_dbell
= 0;
683 /* Get next descriptor pointer.
685 ctp
->put_ptr
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
687 /* return something not zero.
691 EXPORT_SYMBOL(_au1xxx_dbdma_put_dest
);
693 /* Get a destination buffer into the DMA ring.
694 * Normally used to get a full buffer from the ring during fifo
695 * to memory transfers. This does not set the valid bit, you will
696 * have to put another destination buffer to keep the DMA going.
699 au1xxx_dbdma_get_dest(u32 chanid
, void **buf
, int *nbytes
)
702 au1x_ddma_desc_t
*dp
;
705 /* I guess we could check this to be within the
706 * range of the table......
708 ctp
= *((chan_tab_t
**)chanid
);
710 /* We should have multiple callers for a particular channel,
711 * an interrupt doesn't affect this pointer nor the descriptor,
712 * so no locking should be needed.
716 /* If the descriptor is valid, we are way ahead of the DMA
717 * engine, so just return an error condition.
719 if (dp
->dscr_cmd0
& DSCR_CMD0_V
)
722 /* Return buffer address and byte count.
724 *buf
= (void *)(phys_to_virt(dp
->dscr_dest0
));
725 *nbytes
= dp
->dscr_cmd1
;
728 /* Get next descriptor pointer.
730 ctp
->get_ptr
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
732 /* return something not zero.
737 EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest
);
740 au1xxx_dbdma_stop(u32 chanid
)
744 int halt_timeout
= 0;
746 ctp
= *((chan_tab_t
**)chanid
);
749 cp
->ddma_cfg
&= ~DDMA_CFG_EN
; /* Disable channel */
751 while (!(cp
->ddma_stat
& DDMA_STAT_H
)) {
754 if (halt_timeout
> 100) {
755 printk("warning: DMA channel won't halt\n");
759 /* clear current desc valid and doorbell */
760 cp
->ddma_stat
|= (DDMA_STAT_DB
| DDMA_STAT_V
);
763 EXPORT_SYMBOL(au1xxx_dbdma_stop
);
765 /* Start using the current descriptor pointer. If the dbdma encounters
766 * a not valid descriptor, it will stop. In this case, we can just
767 * continue by adding a buffer to the list and starting again.
770 au1xxx_dbdma_start(u32 chanid
)
775 ctp
= *((chan_tab_t
**)chanid
);
777 cp
->ddma_desptr
= virt_to_phys(ctp
->cur_ptr
);
778 cp
->ddma_cfg
|= DDMA_CFG_EN
; /* Enable channel */
783 EXPORT_SYMBOL(au1xxx_dbdma_start
);
786 au1xxx_dbdma_reset(u32 chanid
)
789 au1x_ddma_desc_t
*dp
;
791 au1xxx_dbdma_stop(chanid
);
793 ctp
= *((chan_tab_t
**)chanid
);
794 ctp
->get_ptr
= ctp
->put_ptr
= ctp
->cur_ptr
= ctp
->chan_desc_base
;
796 /* Run through the descriptors and reset the valid indicator.
798 dp
= ctp
->chan_desc_base
;
801 dp
->dscr_cmd0
&= ~DSCR_CMD0_V
;
802 /* reset our SW status -- this is used to determine
803 * if a descriptor is in use by upper level SW. Since
804 * posting can reset 'V' bit.
807 dp
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
808 } while (dp
!= ctp
->chan_desc_base
);
810 EXPORT_SYMBOL(au1xxx_dbdma_reset
);
813 au1xxx_get_dma_residue(u32 chanid
)
819 ctp
= *((chan_tab_t
**)chanid
);
822 /* This is only valid if the channel is stopped.
824 rv
= cp
->ddma_bytecnt
;
830 EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue
);
833 au1xxx_dbdma_chan_free(u32 chanid
)
836 dbdev_tab_t
*stp
, *dtp
;
838 ctp
= *((chan_tab_t
**)chanid
);
840 dtp
= ctp
->chan_dest
;
842 au1xxx_dbdma_stop(chanid
);
844 kfree((void *)ctp
->cdb_membase
);
846 stp
->dev_flags
&= ~DEV_FLAGS_INUSE
;
847 dtp
->dev_flags
&= ~DEV_FLAGS_INUSE
;
848 chan_tab_ptr
[ctp
->chan_index
] = NULL
;
852 EXPORT_SYMBOL(au1xxx_dbdma_chan_free
);
855 dbdma_interrupt(int irq
, void *dev_id
)
860 au1x_ddma_desc_t
*dp
;
863 intstat
= dbdma_gptr
->ddma_intstat
;
865 chan_index
= au_ffs(intstat
) - 1;
867 ctp
= chan_tab_ptr
[chan_index
];
876 if (ctp
->chan_callback
)
877 (ctp
->chan_callback
)(irq
, ctp
->chan_callparam
);
879 ctp
->cur_ptr
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
880 return IRQ_RETVAL(1);
883 static void au1xxx_dbdma_init(void)
887 dbdma_gptr
->ddma_config
= 0;
888 dbdma_gptr
->ddma_throttle
= 0;
889 dbdma_gptr
->ddma_inten
= 0xffff;
892 #if defined(CONFIG_SOC_AU1550)
893 irq_nr
= AU1550_DDMA_INT
;
894 #elif defined(CONFIG_SOC_AU1200)
895 irq_nr
= AU1200_DDMA_INT
;
897 #error Unknown Au1x00 SOC
900 if (request_irq(irq_nr
, dbdma_interrupt
, IRQF_DISABLED
,
901 "Au1xxx dbdma", (void *)dbdma_gptr
))
902 printk("Can't get 1550 dbdma irq");
906 au1xxx_dbdma_dump(u32 chanid
)
909 au1x_ddma_desc_t
*dp
;
910 dbdev_tab_t
*stp
, *dtp
;
914 ctp
= *((chan_tab_t
**)chanid
);
916 dtp
= ctp
->chan_dest
;
919 printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
920 (u32
)ctp
, (u32
)stp
, stp
- dbdev_tab
, (u32
)dtp
, dtp
- dbdev_tab
);
921 printk("desc base %x, get %x, put %x, cur %x\n",
922 (u32
)(ctp
->chan_desc_base
), (u32
)(ctp
->get_ptr
),
923 (u32
)(ctp
->put_ptr
), (u32
)(ctp
->cur_ptr
));
925 printk("dbdma chan %x\n", (u32
)cp
);
926 printk("cfg %08x, desptr %08x, statptr %08x\n",
927 cp
->ddma_cfg
, cp
->ddma_desptr
, cp
->ddma_statptr
);
928 printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
929 cp
->ddma_dbell
, cp
->ddma_irq
, cp
->ddma_stat
, cp
->ddma_bytecnt
);
932 /* Run through the descriptors
934 dp
= ctp
->chan_desc_base
;
937 printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
938 i
++, (u32
)dp
, dp
->dscr_cmd0
, dp
->dscr_cmd1
);
939 printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
940 dp
->dscr_source0
, dp
->dscr_source1
, dp
->dscr_dest0
, dp
->dscr_dest1
);
941 printk("stat %08x, nxtptr %08x\n",
942 dp
->dscr_stat
, dp
->dscr_nxtptr
);
943 dp
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
944 } while (dp
!= ctp
->chan_desc_base
);
947 /* Put a descriptor into the DMA ring.
948 * This updates the source/destination pointers and byte count.
951 au1xxx_dbdma_put_dscr(u32 chanid
, au1x_ddma_desc_t
*dscr
)
954 au1x_ddma_desc_t
*dp
;
957 /* I guess we could check this to be within the
958 * range of the table......
960 ctp
= *((chan_tab_t
**)chanid
);
962 /* We should have multiple callers for a particular channel,
963 * an interrupt doesn't affect this pointer nor the descriptor,
964 * so no locking should be needed.
968 /* If the descriptor is valid, we are way ahead of the DMA
969 * engine, so just return an error condition.
971 if (dp
->dscr_cmd0
& DSCR_CMD0_V
)
974 /* Load up buffer addresses and byte count.
976 dp
->dscr_dest0
= dscr
->dscr_dest0
;
977 dp
->dscr_source0
= dscr
->dscr_source0
;
978 dp
->dscr_dest1
= dscr
->dscr_dest1
;
979 dp
->dscr_source1
= dscr
->dscr_source1
;
980 dp
->dscr_cmd1
= dscr
->dscr_cmd1
;
981 nbytes
= dscr
->dscr_cmd1
;
982 /* Allow the caller to specifiy if an interrupt is generated */
983 dp
->dscr_cmd0
&= ~DSCR_CMD0_IE
;
984 dp
->dscr_cmd0
|= dscr
->dscr_cmd0
| DSCR_CMD0_V
;
985 ctp
->chan_ptr
->ddma_dbell
= 0;
987 /* Get next descriptor pointer.
989 ctp
->put_ptr
= phys_to_virt(DSCR_GET_NXTPTR(dp
->dscr_nxtptr
));
991 /* return something not zero.
996 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */