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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / linux / linux-2.6 / arch / arm / mach-s3c2412 / clock.c
blob6a8e4448770bdce38870138b780db90477932bcf
1 /* linux/arch/arm/mach-s3c2412/clock.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412,S3C2413 Clock control support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
34
35 #include <asm/mach/map.h>
36
37 #include <asm/hardware.h>
38 #include <asm/io.h>
39
40 #include <asm/arch/regs-serial.h>
41 #include <asm/arch/regs-clock.h>
42 #include <asm/arch/regs-gpio.h>
43
44 #include <asm/plat-s3c24xx/s3c2412.h>
45 #include <asm/plat-s3c24xx/clock.h>
46 #include <asm/plat-s3c24xx/cpu.h>
47
48 /* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
51 * software.
52 *
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
55 */
56
57 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
58 {
59 unsigned int clocks = clk->ctrlbit;
60 unsigned long clkcon;
61
62 clkcon = __raw_readl(S3C2410_CLKCON);
63
64 if (enable)
65 clkcon |= clocks;
66 else
67 clkcon &= ~clocks;
68
69 __raw_writel(clkcon, S3C2410_CLKCON);
70
71 return 0;
72 }
73
74 static int s3c2412_upll_enable(struct clk *clk, int enable)
75 {
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
78
79 if (!enable)
80 upllcon |= S3C2412_PLLCON_OFF;
81 else
82 upllcon &= ~S3C2412_PLLCON_OFF;
83
84 __raw_writel(upllcon, S3C2410_UPLLCON);
85
86 /* allow ~150uS for the PLL to settle and lock */
87
88 if (enable && (orig & S3C2412_PLLCON_OFF))
89 udelay(150);
90
91 return 0;
92 }
93
94 /* clock selections */
95
96 /* CPU EXTCLK input */
97 static struct clk clk_ext = {
98 .name = "extclk",
99 .id = -1,
100 };
101
102 static struct clk clk_erefclk = {
103 .name = "erefclk",
104 .id = -1,
105 };
106
107 static struct clk clk_urefclk = {
108 .name = "urefclk",
109 .id = -1,
110 };
111
112 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
113 {
114 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
115
116 if (parent == &clk_urefclk)
117 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
118 else if (parent == &clk_upll)
119 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
120 else
121 return -EINVAL;
122
123 clk->parent = parent;
124
125 __raw_writel(clksrc, S3C2412_CLKSRC);
126 return 0;
127 }
128
129 static struct clk clk_usysclk = {
130 .name = "usysclk",
131 .id = -1,
132 .parent = &clk_xtal,
133 .set_parent = s3c2412_setparent_usysclk,
134 };
135
136 static struct clk clk_mrefclk = {
137 .name = "mrefclk",
138 .parent = &clk_xtal,
139 .id = -1,
140 };
141
142 static struct clk clk_mdivclk = {
143 .name = "mdivclk",
144 .parent = &clk_xtal,
145 .id = -1,
146 };
147
148 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
149 {
150 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
151
152 if (parent == &clk_usysclk)
153 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
154 else if (parent == &clk_h)
155 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
156 else
157 return -EINVAL;
158
159 clk->parent = parent;
160
161 __raw_writel(clksrc, S3C2412_CLKSRC);
162 return 0;
163 }
164
165 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
166 unsigned long rate)
167 {
168 unsigned long parent_rate = clk_get_rate(clk->parent);
169 int div;
170
171 if (rate > parent_rate)
172 return parent_rate;
173
174 div = parent_rate / rate;
175 if (div > 2)
176 div = 2;
177
178 return parent_rate / div;
179 }
180
181 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
182 {
183 unsigned long parent_rate = clk_get_rate(clk->parent);
184 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
185
186 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
187 }
188
189 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
190 {
191 unsigned long parent_rate = clk_get_rate(clk->parent);
192 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
193
194 rate = s3c2412_roundrate_usbsrc(clk, rate);
195
196 if ((parent_rate / rate) == 2)
197 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
198 else
199 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
200
201 __raw_writel(clkdivn, S3C2410_CLKDIVN);
202 return 0;
203 }
204
205 static struct clk clk_usbsrc = {
206 .name = "usbsrc",
207 .id = -1,
208 .get_rate = s3c2412_getrate_usbsrc,
209 .set_rate = s3c2412_setrate_usbsrc,
210 .round_rate = s3c2412_roundrate_usbsrc,
211 .set_parent = s3c2412_setparent_usbsrc,
212 };
213
214 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
215 {
216 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
217
218 if (parent == &clk_mdivclk)
219 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
220 else if (parent == &clk_upll)
221 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
222 else
223 return -EINVAL;
224
225 clk->parent = parent;
226
227 __raw_writel(clksrc, S3C2412_CLKSRC);
228 return 0;
229 }
230
231 static struct clk clk_msysclk = {
232 .name = "msysclk",
233 .id = -1,
234 .set_parent = s3c2412_setparent_msysclk,
235 };
236
237 /* these next clocks have an divider immediately after them,
238 * so we can register them with their divider and leave out the
239 * intermediate clock stage
240 */
241 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
242 unsigned long rate)
243 {
244 unsigned long parent_rate = clk_get_rate(clk->parent);
245 int div;
246
247 if (rate > parent_rate)
248 return parent_rate;
249
250 /* note, we remove the +/- 1 calculations as they cancel out */
251
252 div = (rate / parent_rate);
253
254 if (div < 1)
255 div = 1;
256 else if (div > 16)
257 div = 16;
258
259 return parent_rate / div;
260 }
261
262 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
263 {
264 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
265
266 if (parent == &clk_erefclk)
267 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
268 else if (parent == &clk_mpll)
269 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
270 else
271 return -EINVAL;
272
273 clk->parent = parent;
274
275 __raw_writel(clksrc, S3C2412_CLKSRC);
276 return 0;
277 }
278
279 static unsigned long s3c2412_getrate_uart(struct clk *clk)
280 {
281 unsigned long parent_rate = clk_get_rate(clk->parent);
282 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
283
284 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
285 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
286
287 return parent_rate / (div + 1);
288 }
289
290 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
291 {
292 unsigned long parent_rate = clk_get_rate(clk->parent);
293 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
294
295 rate = s3c2412_roundrate_clksrc(clk, rate);
296
297 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
298 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
299
300 __raw_writel(clkdivn, S3C2410_CLKDIVN);
301 return 0;
302 }
303
304 static struct clk clk_uart = {
305 .name = "uartclk",
306 .id = -1,
307 .get_rate = s3c2412_getrate_uart,
308 .set_rate = s3c2412_setrate_uart,
309 .set_parent = s3c2412_setparent_uart,
310 .round_rate = s3c2412_roundrate_clksrc,
311 };
312
313 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
314 {
315 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
316
317 if (parent == &clk_erefclk)
318 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
319 else if (parent == &clk_mpll)
320 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
321 else
322 return -EINVAL;
323
324 clk->parent = parent;
325
326 __raw_writel(clksrc, S3C2412_CLKSRC);
327 return 0;
328 }
329
330 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
331 {
332 unsigned long parent_rate = clk_get_rate(clk->parent);
333 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
334
335 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
336 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
337
338 return parent_rate / (div + 1);
339 }
340
341 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
342 {
343 unsigned long parent_rate = clk_get_rate(clk->parent);
344 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
345
346 rate = s3c2412_roundrate_clksrc(clk, rate);
347
348 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
349 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
350
351 __raw_writel(clkdivn, S3C2410_CLKDIVN);
352 return 0;
353 }
354
355 static struct clk clk_i2s = {
356 .name = "i2sclk",
357 .id = -1,
358 .get_rate = s3c2412_getrate_i2s,
359 .set_rate = s3c2412_setrate_i2s,
360 .set_parent = s3c2412_setparent_i2s,
361 .round_rate = s3c2412_roundrate_clksrc,
362 };
363
364 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
365 {
366 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
367
368 if (parent == &clk_usysclk)
369 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
370 else if (parent == &clk_h)
371 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
372 else
373 return -EINVAL;
374
375 clk->parent = parent;
376
377 __raw_writel(clksrc, S3C2412_CLKSRC);
378 return 0;
379 }
380 static unsigned long s3c2412_getrate_cam(struct clk *clk)
381 {
382 unsigned long parent_rate = clk_get_rate(clk->parent);
383 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
384
385 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
386 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
387
388 return parent_rate / (div + 1);
389 }
390
391 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
392 {
393 unsigned long parent_rate = clk_get_rate(clk->parent);
394 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
395
396 rate = s3c2412_roundrate_clksrc(clk, rate);
397
398 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
399 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
400
401 __raw_writel(clkdivn, S3C2410_CLKDIVN);
402 return 0;
403 }
404
405 static struct clk clk_cam = {
406 .name = "camif-upll", /* same as 2440 name */
407 .id = -1,
408 .get_rate = s3c2412_getrate_cam,
409 .set_rate = s3c2412_setrate_cam,
410 .set_parent = s3c2412_setparent_cam,
411 .round_rate = s3c2412_roundrate_clksrc,
412 };
413
414 /* standard clock definitions */
415
416 static struct clk init_clocks_disable[] = {
417 {
418 .name = "nand",
419 .id = -1,
420 .parent = &clk_h,
421 .enable = s3c2412_clkcon_enable,
422 .ctrlbit = S3C2412_CLKCON_NAND,
423 }, {
424 .name = "sdi",
425 .id = -1,
426 .parent = &clk_p,
427 .enable = s3c2412_clkcon_enable,
428 .ctrlbit = S3C2412_CLKCON_SDI,
429 }, {
430 .name = "adc",
431 .id = -1,
432 .parent = &clk_p,
433 .enable = s3c2412_clkcon_enable,
434 .ctrlbit = S3C2412_CLKCON_ADC,
435 }, {
436 .name = "i2c",
437 .id = -1,
438 .parent = &clk_p,
439 .enable = s3c2412_clkcon_enable,
440 .ctrlbit = S3C2412_CLKCON_IIC,
441 }, {
442 .name = "iis",
443 .id = -1,
444 .parent = &clk_p,
445 .enable = s3c2412_clkcon_enable,
446 .ctrlbit = S3C2412_CLKCON_IIS,
447 }, {
448 .name = "spi",
449 .id = -1,
450 .parent = &clk_p,
451 .enable = s3c2412_clkcon_enable,
452 .ctrlbit = S3C2412_CLKCON_SPI,
453 }
454 };
455
456 static struct clk init_clocks[] = {
457 {
458 .name = "dma",
459 .id = 0,
460 .parent = &clk_h,
461 .enable = s3c2412_clkcon_enable,
462 .ctrlbit = S3C2412_CLKCON_DMA0,
463 }, {
464 .name = "dma",
465 .id = 1,
466 .parent = &clk_h,
467 .enable = s3c2412_clkcon_enable,
468 .ctrlbit = S3C2412_CLKCON_DMA1,
469 }, {
470 .name = "dma",
471 .id = 2,
472 .parent = &clk_h,
473 .enable = s3c2412_clkcon_enable,
474 .ctrlbit = S3C2412_CLKCON_DMA2,
475 }, {
476 .name = "dma",
477 .id = 3,
478 .parent = &clk_h,
479 .enable = s3c2412_clkcon_enable,
480 .ctrlbit = S3C2412_CLKCON_DMA3,
481 }, {
482 .name = "lcd",
483 .id = -1,
484 .parent = &clk_h,
485 .enable = s3c2412_clkcon_enable,
486 .ctrlbit = S3C2412_CLKCON_LCDC,
487 }, {
488 .name = "gpio",
489 .id = -1,
490 .parent = &clk_p,
491 .enable = s3c2412_clkcon_enable,
492 .ctrlbit = S3C2412_CLKCON_GPIO,
493 }, {
494 .name = "usb-host",
495 .id = -1,
496 .parent = &clk_h,
497 .enable = s3c2412_clkcon_enable,
498 .ctrlbit = S3C2412_CLKCON_USBH,
499 }, {
500 .name = "usb-device",
501 .id = -1,
502 .parent = &clk_h,
503 .enable = s3c2412_clkcon_enable,
504 .ctrlbit = S3C2412_CLKCON_USBD,
505 }, {
506 .name = "timers",
507 .id = -1,
508 .parent = &clk_p,
509 .enable = s3c2412_clkcon_enable,
510 .ctrlbit = S3C2412_CLKCON_PWMT,
511 }, {
512 .name = "uart",
513 .id = 0,
514 .parent = &clk_p,
515 .enable = s3c2412_clkcon_enable,
516 .ctrlbit = S3C2412_CLKCON_UART0,
517 }, {
518 .name = "uart",
519 .id = 1,
520 .parent = &clk_p,
521 .enable = s3c2412_clkcon_enable,
522 .ctrlbit = S3C2412_CLKCON_UART1,
523 }, {
524 .name = "uart",
525 .id = 2,
526 .parent = &clk_p,
527 .enable = s3c2412_clkcon_enable,
528 .ctrlbit = S3C2412_CLKCON_UART2,
529 }, {
530 .name = "rtc",
531 .id = -1,
532 .parent = &clk_p,
533 .enable = s3c2412_clkcon_enable,
534 .ctrlbit = S3C2412_CLKCON_RTC,
535 }, {
536 .name = "watchdog",
537 .id = -1,
538 .parent = &clk_p,
539 .ctrlbit = 0,
540 }, {
541 .name = "usb-bus-gadget",
542 .id = -1,
543 .parent = &clk_usb_bus,
544 .enable = s3c2412_clkcon_enable,
545 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
546 }, {
547 .name = "usb-bus-host",
548 .id = -1,
549 .parent = &clk_usb_bus,
550 .enable = s3c2412_clkcon_enable,
551 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
552 }
553 };
554
555 /* clocks to add where we need to check their parentage */
556
557 struct clk_init {
558 struct clk *clk;
559 unsigned int bit;
560 struct clk *src_0;
561 struct clk *src_1;
562 };
563
564 static struct clk_init clks_src[] __initdata = {
565 {
566 .clk = &clk_usysclk,
567 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
568 .src_0 = &clk_urefclk,
569 .src_1 = &clk_upll,
570 }, {
571 .clk = &clk_i2s,
572 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
573 .src_0 = &clk_erefclk,
574 .src_1 = &clk_mpll,
575 }, {
576 .clk = &clk_cam,
577 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
578 .src_0 = &clk_usysclk,
579 .src_1 = &clk_h,
580 }, {
581 .clk = &clk_msysclk,
582 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
583 .src_0 = &clk_mdivclk,
584 .src_1 = &clk_mpll,
585 }, {
586 .clk = &clk_uart,
587 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
588 .src_0 = &clk_erefclk,
589 .src_1 = &clk_mpll,
590 }, {
591 .clk = &clk_usbsrc,
592 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
593 .src_0 = &clk_usysclk,
594 .src_1 = &clk_h,
595 },
596 };
597
598 /* s3c2412_clk_initparents
599 *
600 * Initialise the parents for the clocks that we get at start-time
601 */
602
603 static void __init s3c2412_clk_initparents(void)
604 {
605 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
606 struct clk_init *cip = clks_src;
607 struct clk *src;
608 int ptr;
609 int ret;
610
611 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
612 ret = s3c24xx_register_clock(cip->clk);
613 if (ret < 0) {
614 printk(KERN_ERR "Failed to register clock %s (%d)\n",
615 cip->clk->name, ret);
616 }
617
618 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
619
620 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
621 clk_set_parent(cip->clk, src);
622 }
623 }
624
625 /* clocks to add straight away */
626
627 static struct clk *clks[] __initdata = {
628 &clk_ext,
629 &clk_usb_bus,
630 &clk_erefclk,
631 &clk_urefclk,
632 &clk_mrefclk,
633 };
634
635 int __init s3c2412_baseclk_add(void)
636 {
637 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
638 struct clk *clkp;
639 int ret;
640 int ptr;
641
642 clk_upll.enable = s3c2412_upll_enable;
643 clk_usb_bus.parent = &clk_usbsrc;
644 clk_usb_bus.rate = 0x0;
645
646 s3c2412_clk_initparents();
647
648 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
649 clkp = clks[ptr];
650
651 ret = s3c24xx_register_clock(clkp);
652 if (ret < 0) {
653 printk(KERN_ERR "Failed to register clock %s (%d)\n",
654 clkp->name, ret);
655 }
656 }
657
658 /* ensure usb bus clock is within correct rate of 48MHz */
659
660 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
661 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
662
663 /* for the moment, let's use the UPLL, and see if we can
664 * get 48MHz */
665
666 clk_set_parent(&clk_usysclk, &clk_upll);
667 clk_set_parent(&clk_usbsrc, &clk_usysclk);
668 clk_set_rate(&clk_usbsrc, 48*1000*1000);
669 }
670
671 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
672 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
673 print_mhz(clk_get_rate(&clk_upll)),
674 print_mhz(clk_get_rate(&clk_usb_bus)));
675
676 /* register clocks from clock array */
677
678 clkp = init_clocks;
679 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
680 /* ensure that we note the clock state */
681
682 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
683
684 ret = s3c24xx_register_clock(clkp);
685 if (ret < 0) {
686 printk(KERN_ERR "Failed to register clock %s (%d)\n",
687 clkp->name, ret);
688 }
689 }
690
691 /* We must be careful disabling the clocks we are not intending to
692 * be using at boot time, as subsytems such as the LCD which do
693 * their own DMA requests to the bus can cause the system to lockup
694 * if they where in the middle of requesting bus access.
695 *
696 * Disabling the LCD clock if the LCD is active is very dangerous,
697 * and therefore the bootloader should be careful to not enable
698 * the LCD clock if it is not needed.
699 */
700
701 /* install (and disable) the clocks we do not need immediately */
702
703 clkp = init_clocks_disable;
704 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
705
706 ret = s3c24xx_register_clock(clkp);
707 if (ret < 0) {
708 printk(KERN_ERR "Failed to register clock %s (%d)\n",
709 clkp->name, ret);
710 }
711
712 s3c2412_clkcon_enable(clkp, 0);
713 }
714
715 return 0;
716 }
Tomato firmware and modifications.