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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / include / bcmsrom_tbl.h
blob15a87ce5db832fffdba7597a09ebce4a6e5c2dc5
1 /*
2 * Table that encodes the srom formats for PCI/PCIe NICs.
3 *
4 * Copyright (C) 2011, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: bcmsrom_tbl.h 324896 2012-03-30 19:35:36Z $
19 */
20
21 #ifndef _bcmsrom_tbl_h_
22 #define _bcmsrom_tbl_h_
23
24 #include "sbpcmcia.h"
25 #include "wlioctl.h"
26
27 typedef struct {
28 const char *name;
29 uint32 revmask;
30 uint32 flags;
31 uint16 off;
32 uint16 mask;
33 } sromvar_t;
34
35 #define SRFL_MORE 1 /* value continues as described by the next entry */
36 #define SRFL_NOFFS 2 /* value bits can't be all one's */
37 #define SRFL_PRHEX 4 /* value is in hexdecimal format */
38 #define SRFL_PRSIGN 8 /* value is in signed decimal format */
39 #define SRFL_CCODE 0x10 /* value is in country code format */
40 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
41 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
42 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
43 #define SRFL_ARRAY 0x100 /* value is in an array. All elements EXCEPT FOR THE LAST
44 * ONE in the array should have this flag set.
45 */
46
47
48 /* Assumptions:
49 * - Ethernet address spans across 3 consective words
50 *
51 * Table rules:
52 * - Add multiple entries next to each other if a value spans across multiple words
53 * (even multiple fields in the same word) with each entry except the last having
54 * it's SRFL_MORE bit set.
55 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
56 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
57 * - The last entry's name field must be NULL to indicate the end of the table. Other
58 * entries must have non-NULL name.
59 */
60
61 static const sromvar_t pci_sromvars[] = {
62 {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff},
63 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
64 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
65 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
66 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
67 {"boardflags", 0x00000004, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff},
68 {"", 0, 0, SROM_BFL2, 0xffff},
69 {"boardflags", 0x00000008, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff},
70 {"", 0, 0, SROM3_BFL2, 0xffff},
71 {"boardflags", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL0, 0xffff},
72 {"", 0, 0, SROM4_BFL1, 0xffff},
73 {"boardflags", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL0, 0xffff},
74 {"", 0, 0, SROM5_BFL1, 0xffff},
75 {"boardflags", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL0, 0xffff},
76 {"", 0, 0, SROM8_BFL1, 0xffff},
77 {"boardflags2", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL2, 0xffff},
78 {"", 0, 0, SROM4_BFL3, 0xffff},
79 {"boardflags2", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL2, 0xffff},
80 {"", 0, 0, SROM5_BFL3, 0xffff},
81 {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff},
82 {"", 0, 0, SROM8_BFL3, 0xffff},
83 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
84
85 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
86 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
87 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
88 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
89 {"boardnum", 0x00000700, 0, SROM8_MACLO, 0xffff},
90 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
91 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
92 {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
93 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
94 {"regrev", 0x00000700, 0, SROM8_REGREV, 0x00ff},
95 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
96 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
97 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
98 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
99 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
100 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
101 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
102 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
103 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
104 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
105 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
106 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
107 {"ledbh0", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
108 {"ledbh1", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
109 {"ledbh2", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
110 {"ledbh3", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
111 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
112 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
113 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
114 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
115 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
116 {"pa0b0", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
117 {"pa0b1", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
118 {"pa0b2", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
119 {"pa0itssit", 0x00000700, 0, SROM8_W0_ITTMAXP, 0xff00},
120 {"pa0maxpwr", 0x00000700, 0, SROM8_W0_ITTMAXP, 0x00ff},
121 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
122 {"opo", 0x00000700, 0, SROM8_2G_OFDMPO, 0x00ff},
123 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
124 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
125 {"aa2g", 0x00000700, 0, SROM8_AA, 0x00ff},
126 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
127 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
128 {"aa5g", 0x00000700, 0, SROM8_AA, 0xff00},
129 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
130 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
131 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
132 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
133 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
134 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
135 {"ag0", 0x00000700, 0, SROM8_AG10, 0x00ff},
136 {"ag1", 0x00000700, 0, SROM8_AG10, 0xff00},
137 {"ag2", 0x00000700, 0, SROM8_AG32, 0x00ff},
138 {"ag3", 0x00000700, 0, SROM8_AG32, 0xff00},
139 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
140 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
141 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
142 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
143 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
144 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
145 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
146 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
147 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
148 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
149 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
150 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
151 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
152 {"pa1b0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
153 {"pa1b1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
154 {"pa1b2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
155 {"pa1lob0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
156 {"pa1lob1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
157 {"pa1lob2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
158 {"pa1hib0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
159 {"pa1hib1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
160 {"pa1hib2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
161 {"pa1itssit", 0x00000700, 0, SROM8_W1_ITTMAXP, 0xff00},
162 {"pa1maxpwr", 0x00000700, 0, SROM8_W1_ITTMAXP, 0x00ff},
163 {"pa1lomaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0xff00},
164 {"pa1himaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
165 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
166 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
167 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
168 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
169 {"bxa2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x1800},
170 {"rssisav2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x0700},
171 {"rssismc2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x00f0},
172 {"rssismf2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x000f},
173 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
174 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
175 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
176 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
177 {"bxa5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x1800},
178 {"rssisav5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x0700},
179 {"rssismc5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x00f0},
180 {"rssismf5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x000f},
181 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
182 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
183 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
184 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
185 {"tri2g", 0x00000700, 0, SROM8_TRI52G, 0x00ff},
186 {"tri5g", 0x00000700, 0, SROM8_TRI52G, 0xff00},
187 {"tri5gl", 0x00000700, 0, SROM8_TRI5GHL, 0x00ff},
188 {"tri5gh", 0x00000700, 0, SROM8_TRI5GHL, 0xff00},
189 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
190 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
191 {"rxpo2g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
192 {"rxpo5g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
193 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
194 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
195 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
196 {"txchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
197 {"rxchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
198 {"antswitch", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
199 {"tssipos2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
200 {"extpagain2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
201 {"pdetrange2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
202 {"triso2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
203 {"antswctl2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
204 {"tssipos5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
205 {"extpagain5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
206 {"pdetrange5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
207 {"triso5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
208 {"antswctl5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
209 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
210 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
211 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
212 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
213 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
214 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
215 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
216 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
217 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
218 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
219 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
220 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
221 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
222 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
223 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
224 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
225
226 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
227 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
228 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
229 {"ccode", 0x00000700, SRFL_CCODE, SROM8_CCODE, 0xffff},
230 {"macaddr", 0x00000700, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
231 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
232 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
233 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
234 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
235 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
236 {"leddc", 0x00000700, SRFL_NOFFS|SRFL_LEDDC, SROM8_LEDDC, 0xffff},
237 {"leddc", 0x000000e0, SRFL_NOFFS|SRFL_LEDDC, SROM5_LEDDC, 0xffff},
238 {"leddc", 0x00000010, SRFL_NOFFS|SRFL_LEDDC, SROM4_LEDDC, 0xffff},
239 {"leddc", 0x00000008, SRFL_NOFFS|SRFL_LEDDC, SROM3_LEDDC, 0xffff},
240
241 {"tempthresh", 0x00000700, 0, SROM8_THERMAL, 0xff00},
242 {"tempoffset", 0x00000700, 0, SROM8_THERMAL, 0x00ff},
243 {"rawtempsense", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
244 {"measpower", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
245 {"tempsense_slope", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff},
246 {"tempcorrx", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
247 {"tempsense_option", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x0300},
248 {"freqoffset_corr", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f},
249 {"iqcal_swp_dis", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
250 {"hw_iqcal_en", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
251 {"elna2g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0x00ff},
252 {"elna5g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0xff00},
253 {"phycal_tempdelta", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
254 {"temps_period", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00},
255 {"temps_hysteresis", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000},
256 {"measpower1", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f},
257 {"measpower2", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80},
258
259 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
260 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
261 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
262 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
263 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
264 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
265 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
266 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
267 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
268 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
269 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
270 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
271 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
272 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
273 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
274 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
275 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
276 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
277 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
278 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
279 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
280 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
281 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
282 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
283 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
284 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
285 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
286 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
287 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
288 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
289 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
290 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
291 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
292 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
293 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
294 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
295 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
296 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
297 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
298 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
299 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
300 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
301 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
302 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
303 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
304 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
305 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
306 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
307 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
308 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
309 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
310 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
311 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
312 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
313 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
314 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
315 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
316 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
317 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
318 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
319 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
320 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
321 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
322 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
323 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
324 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
325 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
326 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
327 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
328 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
329 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
330 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
331 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
332 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
333 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
334 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
335 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
336 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
337 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
338 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
339 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
340 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
341 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
342 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
343 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
344 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
345 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
346 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
347 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
348 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
349
350 /* power per rate from sromrev 9 */
351 {"cckbw202gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20, 0xffff},
352 {"cckbw20ul2gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
353 {"legofdmbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff},
354 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
355 {"legofdmbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 0xffff},
356 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
357 {"legofdmbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff},
358 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
359 {"legofdmbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 0xffff},
360 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
361 {"legofdmbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff},
362 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
363 {"legofdmbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 0xffff},
364 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
365 {"legofdmbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff},
366 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
367 {"legofdmbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 0xffff},
368 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
369 {"mcsbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
370 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
371 {"mcsbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
372 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
373 {"mcsbw402gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
374 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
375 {"mcsbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
376 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
377 {"mcsbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff},
378 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
379 {"mcsbw405glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
380 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
381 {"mcsbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
382 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
383 {"mcsbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff},
384 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
385 {"mcsbw405gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
386 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
387 {"mcsbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
388 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
389 {"mcsbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff},
390 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
391 {"mcsbw405ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
392 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
393 {"mcs32po", 0x00000600, 0, SROM9_PO_MCS32, 0xffff},
394 {"legofdm40duppo", 0x00000600, 0, SROM9_PO_LOFDM40DUP, 0xffff},
395 {"pcieingress_war", 0x00000700, 0, SROM8_PCIEINGRESS_WAR, 0xf},
396 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f},
397 {"rxgainerr2ga1", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x07c0},
398 {"rxgainerr2ga2", 0x00000700, 0, SROM8_RXGAINERR_2G, 0xf800},
399 {"rxgainerr5gla0", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x003f},
400 {"rxgainerr5gla1", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x07c0},
401 {"rxgainerr5gla2", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0xf800},
402 {"rxgainerr5gma0", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x003f},
403 {"rxgainerr5gma1", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x07c0},
404 {"rxgainerr5gma2", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0xf800},
405 {"rxgainerr5gha0", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x003f},
406 {"rxgainerr5gha1", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x07c0},
407 {"rxgainerr5gha2", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0xf800},
408 {"rxgainerr5gua0", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x003f},
409 {"rxgainerr5gua1", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x07c0},
410 {"rxgainerr5gua2", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0xf800},
411 {"sar2g", 0x00000600, 0, SROM9_SAR, 0x00ff},
412 {"sar5g", 0x00000600, 0, SROM9_SAR, 0xff00},
413 {"noiselvl2ga0", 0x00000700, 0, SROM8_NOISELVL_2G, 0x001f},
414 {"noiselvl2ga1", 0x00000700, 0, SROM8_NOISELVL_2G, 0x03e0},
415 {"noiselvl2ga2", 0x00000700, 0, SROM8_NOISELVL_2G, 0x7c00},
416 {"noiselvl5gla0", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x001f},
417 {"noiselvl5gla1", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x03e0},
418 {"noiselvl5gla2", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x7c00},
419 {"noiselvl5gma0", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x001f},
420 {"noiselvl5gma1", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x03e0},
421 {"noiselvl5gma2", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x7c00},
422 {"noiselvl5gha0", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x001f},
423 {"noiselvl5gha1", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x03e0},
424 {"noiselvl5gha2", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x7c00},
425 {"noiselvl5gua0", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x001f},
426 {"noiselvl5gua1", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x03e0},
427 {"noiselvl5gua2", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x7c00},
428 {"subband5gver", 0x00000700, 0, SROM8_SUBBAND_PPR, 0x7},
429
430 {"cckPwrOffset", 0x00000400, 0, SROM10_CCKPWROFFSET, 0xffff},
431 /* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY flag set */
432 {"swctrlmap_2g", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G, 0xffff},
433 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 1, 0xffff},
434 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 2, 0xffff},
435 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 3, 0xffff},
436 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 4, 0xffff},
437 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 5, 0xffff},
438 {"", 0x00000400, SRFL_MORE|SRFL_PRHEX|SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 6, 0xffff},
439 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 7, 0xffff},
440 {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff},
441
442 /* sromrev 11 */
443 {"boardflags3", 0xfffff800, SRFL_PRHEX|SRFL_MORE, SROM11_BFL3, 0xffff},
444 {"", 0, 0, SROM11_BFL3, 0xffff},
445 {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff},
446 {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff},
447 {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff},
448 {"regrev", 0xfffff800, 0, SROM11_REGREV, 0x00ff},
449 {"ledbh0", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0x00ff},
450 {"ledbh1", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0xff00},
451 {"ledbh2", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0x00ff},
452 {"ledbh3", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0xff00},
453 {"leddc", 0xfffff800, SRFL_NOFFS|SRFL_LEDDC, SROM11_LEDDC, 0xffff},
454 {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff},
455 {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00},
456 {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0x00ff},
457 {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0xff00},
458 {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff},
459 {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00},
460 {"aga1", 0xfffff800, 0, SROM11_AGA21, 0x00ff},
461 {"aga2", 0xfffff800, 0, SROM11_AGA21, 0xff00},
462 {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK},
463 {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK},
464 {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK},
465
466 {"tssiposslope2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0001},
467 {"epagain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x000e},
468 {"pdgain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x01f0},
469 {"tworangetssi2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0200},
470 {"papdcap2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0400},
471 {"femctrl", 0xfffff800, 0, SROM11_FEM_CFG1, 0xf800},
472
473 {"tssiposslope5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0001},
474 {"epagain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x000e},
475 {"pdgain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x01f0},
476 {"tworangetssi5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0200},
477 {"papdcap5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0400},
478 {"gainctrlsph", 0xfffff800, 0, SROM11_FEM_CFG2, 0xf800},
479
480 {"tempthresh", 0xfffff800, 0, SROM11_THERMAL, 0xff00},
481 {"tempoffset", 0xfffff800, 0, SROM11_THERMAL, 0x00ff},
482 {"rawtempsense", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0x01ff},
483 {"measpower", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0xfe00},
484 {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x00ff},
485 {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00},
486 {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0x0300},
487 {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff},
488 {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00},
489 {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000},
490 {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f},
491 {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80},
492 {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff},
493 {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff},
494 {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff},
495 {"pdoffset80ma0", 0xfffff800, 0, SROM11_PDOFF_80M_A0, 0xffff},
496 {"pdoffset80ma1", 0xfffff800, 0, SROM11_PDOFF_80M_A1, 0xffff},
497 {"pdoffset80ma2", 0xfffff800, 0, SROM11_PDOFF_80M_A2, 0xffff},
498
499 {"subband5gver", 0xfffff800, SRFL_PRHEX, SROM11_SUBBAND5GVER, 0xffff},
500
501 /* power per rate */
502 {"cckbw202gpo", 0xfffff800, 0, SROM11_CCKBW202GPO, 0xffff},
503 {"cckbw20ul2gpo", 0xfffff800, 0, SROM11_CCKBW20UL2GPO, 0xffff},
504 {"mcsbw202gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW202GPO, 0xffff},
505 {"", 0xfffff800, 0, SROM11_MCSBW202GPO_1, 0xffff},
506 {"mcsbw402gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW402GPO, 0xffff},
507 {"", 0xfffff800, 0, SROM11_MCSBW402GPO_1, 0xffff},
508 {"dot11agofdmhrbw202gpo", 0xfffff800, 0, SROM11_DOT11AGOFDMHRBW202GPO, 0xffff},
509 {"ofdmlrbw202gpo", 0xfffff800, 0, SROM11_OFDMLRBW202GPO, 0xffff},
510 {"mcsbw205glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GLPO, 0xffff},
511 {"", 0xfffff800, 0, SROM11_MCSBW205GLPO_1, 0xffff},
512 {"mcsbw405glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GLPO, 0xffff},
513 {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff},
514 {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff},
515 {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff},
516 {"mcsbw1605glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GLPO, 0xffff},
517 {"", 0xfffff800, 0, SROM11_MCSBW1605GLPO_1, 0xffff},
518 {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff},
519 {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff},
520 {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff},
521 {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff},
522 {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff},
523 {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff},
524 {"mcsbw1605gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GMPO, 0xffff},
525 {"", 0xfffff800, 0, SROM11_MCSBW1605GMPO_1, 0xffff},
526 {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff},
527 {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff},
528 {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff},
529 {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff},
530 {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff},
531 {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff},
532 {"mcsbw1605ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW1605GHPO, 0xffff},
533 {"", 0xfffff800, 0, SROM11_MCSBW1605GHPO_1, 0xffff},
534 {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xffff},
535 {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff},
536 {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff},
537 {"sb20in40hrrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff},
538 {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 0xffff},
539 {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff},
540 {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 0xffff},
541 {"sb40and80hr5gmpo", 0xfffff800, 0, SROM11_SB40AND80HR5GMPO, 0xffff},
542 {"sb20in80and160hr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GHPO, 0xffff},
543 {"sb40and80hr5ghpo", 0xfffff800, 0, SROM11_SB40AND80HR5GHPO, 0xffff},
544 {"sb20in40lrpo", 0xfffff800, 0, SROM11_SB20IN40LRPO, 0xffff},
545 {"sb20in80and160lr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GLPO, 0xffff},
546 {"sb40and80lr5glpo", 0xfffff800, 0, SROM11_SB40AND80LR5GLPO, 0xffff},
547 {"sb20in80and160lr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GMPO, 0xffff},
548 {"sb40and80lr5gmpo", 0xfffff800, 0, SROM11_SB40AND80LR5GMPO, 0xffff},
549 {"sb20in80and160lr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GHPO, 0xffff},
550 {"sb40and80lr5ghpo", 0xfffff800, 0, SROM11_SB40AND80LR5GHPO, 0xffff},
551 {"dot11agduphrpo", 0xfffff800, 0, SROM11_DOT11AGDUPHRPO, 0xffff},
552 {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff},
553
554 /* Misc */
555 {"pcieingress_war", 0xfffff800, 0, SROM11_PCIEINGRESS_WAR, 0xf},
556 {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff},
557 {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00},
558 {"noiselvl2ga0", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x001f},
559 {"noiselvl2ga1", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x03e0},
560 {"noiselvl2ga2", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x7c00},
561 {"noiselvl5gla0", 0xfffff800, 0, SROM11_NOISELVL_5GL, 0x001f},
562 {"noiselvl5gla1", 0xfffff800, 0, SROM11_NOISELVL_5GL, 0x03e0},
563 {"noiselvl5gla2", 0xfffff800, 0, SROM11_NOISELVL_5GL, 0x7c00},
564 {"noiselvl5gma0", 0xfffff800, 0, SROM11_NOISELVL_5GM, 0x001f},
565 {"noiselvl5gma1", 0xfffff800, 0, SROM11_NOISELVL_5GM, 0x03e0},
566 {"noiselvl5gma2", 0xfffff800, 0, SROM11_NOISELVL_5GM, 0x7c00},
567 {"noiselvl5gha0", 0xfffff800, 0, SROM11_NOISELVL_5GH, 0x001f},
568 {"noiselvl5gha1", 0xfffff800, 0, SROM11_NOISELVL_5GH, 0x03e0},
569 {"noiselvl5gha2", 0xfffff800, 0, SROM11_NOISELVL_5GH, 0x7c00},
570 {"noiselvl5gua0", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x001f},
571 {"noiselvl5gua1", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x03e0},
572 {"noiselvl5gua2", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x7c00},
573 {"rxgainerr2g", 0xfffff800, SRFL_PRHEX, SROM11_RXGAINERR_2G, 0xffff},
574 {"rxgainerr5g", 0xfffff800, SRFL_PRHEX|SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0xffff},
575 {"", 0xfffff800, SRFL_PRHEX|SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xffff},
576 {"", 0xfffff800, SRFL_PRHEX|SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xffff},
577 {"", 0xfffff800, SRFL_PRHEX, SROM11_RXGAINERR_5GU, 0xffff},
578 {NULL, 0, 0, 0, 0}
579 };
580
581 static const sromvar_t perpath_pci_sromvars[] = {
582 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
583 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
584 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
585 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
586 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
587 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
588 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
589 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
590 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
591 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
592 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
593 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
594 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
595 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
596 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
597 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
598 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
599 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
600 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
601 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
602 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
603 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
604 {"maxp2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0x00ff},
605 {"itt2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0xff00},
606 {"itt5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0xff00},
607 {"pa2gw0a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
608 {"pa2gw1a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
609 {"pa2gw2a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
610 {"maxp5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0x00ff},
611 {"maxp5gha", 0x00000700, 0, SROM8_5GLH_MAXP, 0x00ff},
612 {"maxp5gla", 0x00000700, 0, SROM8_5GLH_MAXP, 0xff00},
613 {"pa5gw0a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
614 {"pa5gw1a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
615 {"pa5gw2a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
616 {"pa5glw0a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
617 {"pa5glw1a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
618 {"pa5glw2a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
619 {"pa5ghw0a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
620 {"pa5ghw1a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
621 {"pa5ghw2a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
622
623 /* sromrev 11 */
624 {"maxp2ga", 0xfffff800, 0, SROM11_2G_MAXP, 0x00ff},
625 {"pa2ga", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA, 0xffff},
626 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1, 0xffff},
627 {"", 0xfffff800, SRFL_PRHEX, SROM11_2G_PA + 2, 0xffff},
628 {"rxgains5gmelnagaina", 0xfffff800, 0, SROM11_RXGAINS1, 0x0007},
629 {"rxgains5gmtrisoa", 0xfffff800, 0, SROM11_RXGAINS1, 0x0078},
630 {"rxgains5gmtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS1, 0x0080},
631 {"rxgains5ghelnagaina", 0xfffff800, 0, SROM11_RXGAINS1, 0x0700},
632 {"rxgains5ghtrisoa", 0xfffff800, 0, SROM11_RXGAINS1, 0x7800},
633 {"rxgains5ghtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS1, 0x8000},
634 {"rxgains2gelnagaina", 0xfffff800, 0, SROM11_RXGAINS, 0x0007},
635 {"rxgains2gtrisoa", 0xfffff800, 0, SROM11_RXGAINS, 0x0078},
636 {"rxgains2gtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS, 0x0080},
637 {"rxgains5gelnagaina", 0xfffff800, 0, SROM11_RXGAINS, 0x0700},
638 {"rxgains5gtrisoa", 0xfffff800, 0, SROM11_RXGAINS, 0x7800},
639 {"rxgains5gtrelnabypa", 0xfffff800, 0, SROM11_RXGAINS, 0x8000},
640 {"maxp5ga", 0xfffff800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0x00ff},
641 {"", 0xfffff800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0xff00},
642 {"", 0xfffff800, SRFL_ARRAY, SROM11_5GB3B2_MAXP, 0x00ff},
643 {"", 0xfffff800, 0, SROM11_5GB3B2_MAXP, 0xff00},
644 {"pa5ga", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA, 0xffff},
645 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1, 0xffff},
646 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2, 0xffff},
647 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA, 0xffff},
648 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1, 0xffff},
649 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2, 0xffff},
650 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA, 0xffff},
651 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1, 0xffff},
652 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2, 0xffff},
653 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA, 0xffff},
654 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1, 0xffff},
655 {"", 0xfffff800, SRFL_PRHEX, SROM11_5GB3_PA + 2, 0xffff},
656
657 {NULL, 0, 0, 0, 0}
658 };
659
660 #if !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
661 #define PHY_TYPE_HT 7 /* HT-Phy value */
662 #define PHY_TYPE_N 4 /* N-Phy value */
663 #define PHY_TYPE_LP 5 /* LP-Phy value */
664 #endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
665 #if !defined(PHY_TYPE_AC)
666 #define PHY_TYPE_AC 11 /* AC-Phy value */
667 #endif /* !defined(PHY_TYPE_AC) */
668 #if !defined(PHY_TYPE_NULL)
669 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
670 #endif /* !defined(PHY_TYPE_NULL) */
671
672 typedef struct {
673 uint16 phy_type;
674 uint16 bandrange;
675 uint16 chain;
676 const char *vars;
677 } pavars_t;
678
679 static const pavars_t pavars[] = {
680 /* HTPHY */
681 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
682 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
683 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 2, "pa2gw0a2 pa2gw1a2 pa2gw2a2"},
684 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
685 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
686 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 2, "pa5glw0a2 pa5glw1a2 pa5glw2a2"},
687 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
688 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
689 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 2, "pa5gw0a2 pa5gw1a2 pa5gw2a2"},
690 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
691 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
692 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
693 /* HTPHY PPR_SUBBAND */
694 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 0, "pa5gllw0a0 pa5gllw1a0 pa5gllw2a0"},
695 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 1, "pa5gllw0a1 pa5gllw1a1 pa5gllw2a1"},
696 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 2, "pa5gllw0a2 pa5gllw1a2 pa5gllw2a2"},
697 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 0, "pa5glhw0a0 pa5glhw1a0 pa5glhw2a0"},
698 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 1, "pa5glhw0a1 pa5glhw1a1 pa5glhw2a1"},
699 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 2, "pa5glhw0a2 pa5glhw1a2 pa5glhw2a2"},
700 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 0, "pa5gmlw0a0 pa5gmlw1a0 pa5gmlw2a0"},
701 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 1, "pa5gmlw0a1 pa5gmlw1a1 pa5gmlw2a1"},
702 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 2, "pa5gmlw0a2 pa5gmlw1a2 pa5gmlw2a2"},
703 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 0, "pa5gmhw0a0 pa5gmhw1a0 pa5gmhw2a0"},
704 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 1, "pa5gmhw0a1 pa5gmhw1a1 pa5gmhw2a1"},
705 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 2, "pa5gmhw0a2 pa5gmhw1a2 pa5gmhw2a2"},
706 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
707 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
708 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
709 /* NPHY */
710 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
711 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
712 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
713 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
714 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
715 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
716 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
717 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
718 /* LPPHY */
719 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
720 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
721 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
722 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
723 /* ACPHY */
724 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"},
725 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"},
726 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"},
727 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"},
728 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"},
729 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5ga2"},
730 {PHY_TYPE_NULL, 0, 0, ""}
731 };
732
733 typedef struct {
734 uint16 phy_type;
735 uint16 bandrange;
736 const char *vars;
737 } povars_t;
738
739 static const povars_t povars[] = {
740 /* NPHY */
741 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
742 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
743 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
744 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
745 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
746 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
747 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
748 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
749 {PHY_TYPE_NULL, 0, ""}
750 };
751
752 typedef struct {
753 uint8 tag; /* Broadcom subtag name */
754 uint32 revmask; /* Supported cis_sromrev */
755 uint8 len; /* Length field of the tuple, note that it includes the
756 * subtag name (1 byte): 1 + tuple content length
757 */
758 const char *params;
759 } cis_tuple_t;
760
761 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
762 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
763 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
764 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
765
766 static const cis_tuple_t cis_hnbuvars[] = {
767 {OTP_RAW1, 0xffffffff, 0, ""}, /* special case */
768 {OTP_VERS_1, 0xffffffff, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */
769 {OTP_MANFID, 0xffffffff, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */
770 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */
771 {HNBU_UMANFID, 0xffffffff, 8, "8usbmanfid"},
772 {HNBU_SROMREV, 0xffffffff, 2, "1sromrev"},
773 /* NOTE: subdevid is also written to boardtype.
774 * Need to write HNBU_BOARDTYPE to change it if it is different.
775 */
776 {HNBU_CHIPID, 0xffffffff, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
777 {HNBU_BOARDREV, 0xffffffff, 3, "2boardrev"},
778 {HNBU_PAPARMS, 0xffffffff, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
779 {HNBU_AA, 0xffffffff, 3, "1aa2g 1aa5g"},
780 {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */
781 {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"},
782 {HNBU_BOARDFLAGS, 0xffffffff, 13, "4boardflags 4boardflags2 4boardflags3"},
783 {HNBU_LEDS, 0xffffffff, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"},
784 {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"},
785 {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"},
786 {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"},
787 {HNBU_PAPARMS5G, 0xffffffff, 23, "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 "
788 "2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit "
789 "1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"},
790 {HNBU_RDLID, 0xffffffff, 3, "2rdlid"},
791 {HNBU_RSSISMBXA2G, 0xffffffff, 3, "0rssismf2g 0rssismc2g "
792 "0rssisav2g 0bxa2g"}, /* special case */
793 {HNBU_RSSISMBXA5G, 0xffffffff, 3, "0rssismf5g 0rssismc5g "
794 "0rssisav5g 0bxa5g"}, /* special case */
795 {HNBU_XTALFREQ, 0xffffffff, 5, "4xtalfreq"},
796 {HNBU_TRI2G, 0xffffffff, 2, "1tri2g"},
797 {HNBU_TRI5G, 0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"},
798 {HNBU_RXPO2G, 0xffffffff, 2, "1rxpo2g"},
799 {HNBU_RXPO5G, 0xffffffff, 2, "1rxpo5g"},
800 {HNBU_BOARDNUM, 0xffffffff, 3, "2boardnum"},
801 {HNBU_MACADDR, 0xffffffff, 7, "6macaddr"}, /* special case */
802 {HNBU_RDLSN, 0xffffffff, 3, "2rdlsn"},
803 {HNBU_BOARDTYPE, 0xffffffff, 3, "2boardtype"},
804 {HNBU_LEDDC, 0xffffffff, 3, "2leddc"},
805 {HNBU_RDLRNDIS, 0xffffffff, 2, "1rdlndis"},
806 {HNBU_CHAINSWITCH, 0xffffffff, 5, "1txchain 1rxchain 2antswitch"},
807 {HNBU_REGREV, 0xffffffff, 2, "1regrev"},
808 {HNBU_FEM, 0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g "
809 "0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */
810 {HNBU_PAPARMS_C0, 0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
811 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 2pa5gw1a0 2pa5gw2a0 "
812 "2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"},
813 {HNBU_PAPARMS_C1, 0x000007fe, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
814 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 2pa5gw1a1 2pa5gw2a1 "
815 "2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"},
816 {HNBU_PO_CCKOFDM, 0xffffffff, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
817 "4ofdm5ghpo"},
818 {HNBU_PO_MCS2G, 0xffffffff, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
819 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
820 {HNBU_PO_MCS5GM, 0xffffffff, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
821 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
822 {HNBU_PO_MCS5GLH, 0xffffffff, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
823 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
824 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
825 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
826 {HNBU_CCKFILTTYPE, 0xffffffff, 2, "1cckdigfilttype"},
827 {HNBU_PO_CDD, 0xffffffff, 3, "2cddpo"},
828 {HNBU_PO_STBC, 0xffffffff, 3, "2stbcpo"},
829 {HNBU_PO_40M, 0xffffffff, 3, "2bw40po"},
830 {HNBU_PO_40MDUP, 0xffffffff, 3, "2bwduppo"},
831 {HNBU_RDLRWU, 0xffffffff, 2, "1rdlrwu"},
832 {HNBU_WPS, 0xffffffff, 3, "1wpsgpio 1wpsled"},
833 {HNBU_USBFS, 0xffffffff, 2, "1usbfs"},
834 {HNBU_ELNA2G, 0xffffffff, 2, "1elna2g"},
835 {HNBU_ELNA5G, 0xffffffff, 2, "1elna5g"},
836 {HNBU_CUSTOM1, 0xffffffff, 5, "4customvar1"},
837 {OTP_RAW, 0xffffffff, 0, ""}, /* special case */
838 {HNBU_OFDMPO5G, 0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
839 {HNBU_USBEPNUM, 0xffffffff, 3, "2usbepnum"},
840 {HNBU_CCKBW202GPO, 0xffffffff, 5, "2cckbw202gpo 2cckbw20ul2gpo"},
841 {HNBU_LEGOFDMBW202GPO, 0xffffffff, 9, "4legofdmbw202gpo 4legofdmbw20ul2gp"},
842 {HNBU_LEGOFDMBW205GPO, 0xffffffff, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo "
843 "4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"},
844 {HNBU_MCS2GPO, 0xffffffff, 13, "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo"},
845 {HNBU_MCS5GLPO, 0xffffffff, 13, "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"},
846 {HNBU_MCS5GMPO, 0xffffffff, 13, "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"},
847 {HNBU_MCS5GHPO, 0xffffffff, 13, "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"},
848 {HNBU_MCS32PO, 0xffffffff, 3, "2mcs32po"},
849 {HNBU_LEG40DUPPO, 0xffffffff, 3, "2legofdm40duppo"},
850 {HNBU_TEMPTHRESH, 0xffffffff, 6, "1tempthresh 1periodhyst 1tempoffset 1tempcoropt "
851 "1phycal_tempdelta"},
852 {HNBU_FEM_CFG, 0xfffff800, 5, "2fem_cfg1 2fem_cfg2"},
853 {HNBU_ACPA_C0, 0xfffff800, 41, "2subband5gver 2maxp2ga0 2*3pa2ga0 2rxgainsa0 "
854 "1*4maxp5ga0 2*12pa5ga0"},
855 {HNBU_ACPA_C1, 0xfffff800, 39, "2maxp2ga1 2*3pa2ga1 2rxgainsa1 1*4maxp5ga1 "
856 "2*12pa5ga1"},
857 {HNBU_ACPA_C2, 0xfffff800, 39, "2maxp2ga2 2*3pa2ga2 2rxgainsa2 1*4maxp5ga2 "
858 "2*12pa5ga2"},
859 {HNBU_MEAS_PWR, 0xfffff800, 5, "1measpower 1measpower1 1measpower2 2rawtempsense"},
860 {HNBU_PDOFF, 0xfffff800, 13, "2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 "
861 "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"},
862 {HNBU_ACPPR_2GPO, 0xfffff800, 5, "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo"},
863 {HNBU_ACPPR_5GPO, 0xfffff800, 31, "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo "
864 "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5rlpo 2mcslr5gmpo 2mcslr5ghpo"},
865 {HNBU_ACPPR_SBPO, 0xfffff800, 33, "2sb20in40hrrpo 2sb20in80and160hr5glpo "
866 "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo 2sb20in80and160hr5ghpo "
867 "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo 2sb40and80lr5glpo "
868 "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo 2sb40and80lr5ghpo "
869 "2dot11agduphrpo 2dot11agduplrpo"},
870 {HNBU_NOISELVL, 0xfffff800, 11, "2noiselvl2g 2noiselvl5gl 2noiselvl5gm "
871 "2noiselvl5gh 2noiselvl5gu"},
872 {HNBU_RXGAIN_ERR, 0xfffff800, 11, "2rxgainerr2g 2*4rxgainerr5g"},
873 {HNBU_AGBGA, 0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"},
874 {HNBU_UUID, 0xffffffff, 17, "16uuid"},
875 {0xFF, 0xffffffff, 0, ""}
876 };
877
878 #endif /* _bcmsrom_tbl_h_ */
Tomato firmware and modifications.