allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / cfe / cfe / dev / ns16550.h
blob10ea8c077f5affbca11628a771469326fa4ac576
1 /* *********************************************************************
2 * Broadcom Common Firmware Environment (CFE)
4 * NS16550 Serial Port definitions File: ns16550.h
5 *
6 * This defines the hardware registers of 16550 compatible UARTs
8 *********************************************************************
10 * Copyright 2000,2001,2002,2003
11 * Broadcom Corporation. All rights reserved.
13 * This software is furnished under license and may be used and
14 * copied only in accordance with the following terms and
15 * conditions. Subject to these conditions, you may download,
16 * copy, install, use, modify and distribute modified or unmodified
17 * copies of this software in source and/or binary form. No title
18 * or ownership is transferred hereby.
20 * 1) Any source code used, modified or distributed must reproduce
21 * and retain this copyright notice and list of conditions
22 * as they appear in the source file.
24 * 2) No right is granted to use any trade name, trademark, or
25 * logo of Broadcom Corporation. The "Broadcom Corporation"
26 * name may not be used to endorse or promote products derived
27 * from this software without the prior written permission of
28 * Broadcom Corporation.
30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
42 * THE POSSIBILITY OF SUCH DAMAGE.
43 ********************************************************************* */
46 * NS16550 UART registers
49 #ifndef _NS16550_H_
50 #define _NS16550_H_
52 #ifndef NS16550_HZ
53 #define NS16550_HZ 1843200
54 #endif
57 * NS16550 UART registers
60 /* Register definitions */
62 #ifndef CPU_R32364
63 #define R_UART_DATA 0
64 #define R_UART_IER 1
65 #define R_UART_IIR 2
66 #define R_UART_FIFO R_UART_IIR
67 #define R_UART_CFCR 3
68 #define R_UART_MCR 4
69 #define R_UART_LSR 5
70 #define R_UART_MSR 6
71 #define R_UART_SCR 7
72 #else
73 #define R_UART_DATA (0 << 2)
74 #define R_UART_IER (1 << 2)
75 #define R_UART_IIR (2 << 2)
76 #define R_UART_FIFO R_UART_IIR
77 #define R_UART_CFCR (3 << 2)
78 #define R_UART_MCR (4 << 2)
79 #define R_UART_LSR (5 << 2)
80 #define R_UART_MSR (6 << 2)
81 #define R_UART_SCR (7 << 2)
82 #endif
84 /* 16 bit baud rate divisor (lower byte in UART_DATA, upper in UART_IER) */
85 #define BRTC(base, baud) ((base + (8 * baud)) / (16*(baud)))
87 /* interrupt enable register */
88 #define IER_ERXRDY 0x1 /* int on rx ready */
89 #define IER_ETXRDY 0x2 /* int on tx ready */
90 #define IER_ERLS 0x4 /* int on line status change */
91 #define IER_EMSC 0x8 /* int on modem status change */
93 /* interrupt identification register */
94 #define IIR_IMASK 0xf /* mask */
95 #define IIR_RXTOUT 0xc /* receive timeout */
96 #define IIR_RLS 0x6 /* receive line status */
97 #define IIR_RXRDY 0x4 /* receive ready */
98 #define IIR_TXRDY 0x2 /* transmit ready */
99 #define IIR_NOPEND 0x1 /* nothing */
100 #define IIR_MLSC 0x0 /* modem status */
101 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
103 /* fifo control register */
104 #define FIFO_ENABLE 0x01 /* enable fifo */
105 #define FIFO_RCV_RST 0x02 /* reset receive fifo */
106 #define FIFO_XMT_RST 0x04 /* reset transmit fifo */
107 #define FIFO_DMA_MODE 0x08 /* enable dma mode */
108 #define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
109 #define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
110 #define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
111 #define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
113 /* character format control register */
114 #define CFCR_DLAB 0x80 /* divisor latch */
115 #define CFCR_SBREAK 0x40 /* send break */
116 #define CFCR_PZERO 0x30 /* zero parity */
117 #define CFCR_PONE 0x20 /* one parity */
118 #define CFCR_PEVEN 0x10 /* even parity */
119 #define CFCR_PODD 0x00 /* odd parity */
120 #define CFCR_PENAB 0x08 /* parity enable */
121 #define CFCR_STOPB 0x04 /* 2 stop bits */
122 #define CFCR_8BITS 0x03 /* 8 data bits */
123 #define CFCR_7BITS 0x02 /* 7 data bits */
124 #define CFCR_6BITS 0x01 /* 6 data bits */
125 #define CFCR_5BITS 0x00 /* 5 data bits */
127 /* modem control register */
128 #define MCR_LOOPBACK 0x10 /* loopback */
129 #define MCR_IENABLE 0x08 /* output 2 = int enable */
130 #define MCR_DRS 0x04
131 #define MCR_RTS 0x02 /* enable RTS */
132 #define MCR_DTR 0x01 /* enable DTR */
134 /* line status register */
135 #define LSR_RCV_FIFO 0x80 /* error in receive fifo */
136 #define LSR_TSRE 0x40 /* transmitter empty */
137 #define LSR_TXRDY 0x20 /* transmitter ready */
138 #define LSR_BI 0x10 /* break detected */
139 #define LSR_FE 0x08 /* framing error */
140 #define LSR_PE 0x04 /* parity error */
141 #define LSR_OE 0x02 /* overrun error */
142 #define LSR_RXRDY 0x01 /* receiver ready */
143 #define LSR_RCV_MASK 0x1f
145 /* modem status register */
146 #define MSR_DCD 0x80 /* DCD active */
147 #define MSR_RI 0x40 /* RI active */
148 #define MSR_DSR 0x20 /* DSR active */
149 #define MSR_CTS 0x10 /* CTS active */
150 #define MSR_DDCD 0x08 /* DCD changed */
151 #define MSR_TERI 0x04 /* RI changed */
152 #define MSR_DDSR 0x02 /* DSR changed */
153 #define MSR_DCTS 0x01 /* CTS changed */
155 #endif /* _NS16550_H_ */