release/src-rt-6.x/cfe/cfe/dev/dev_ht7520.c

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  HT7520 (Golem) Bridge Support                    File: dev_ht7520.c
   5     *
   6     *********************************************************************
   7     *
   8     *  Copyright 2002,2003
   9     *  Broadcom Corporation. All rights reserved.
  10     *
  11     *  This software is furnished under license and may be used and
  12     *  copied only in accordance with the following terms and
  13     *  conditions.  Subject to these conditions, you may download,
  14     *  copy, install, use, modify and distribute modified or unmodified
  15     *  copies of this software in source and/or binary form.  No title
  16     *  or ownership is transferred hereby.
  17     *
  18     *  1) Any source code used, modified or distributed must reproduce
  19     *     and retain this copyright notice and list of conditions
  20     *     as they appear in the source file.
  21     *
  22     *  2) No right is granted to use any trade name, trademark, or
  23     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  24     *     name may not be used to endorse or promote products derived
  25     *     from this software without the prior written permission of
  26     *     Broadcom Corporation.
  27     *
  28     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  29     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  30     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  31     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  32     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  33     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  34     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  36     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  37     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  38     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  39     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  40     *     THE POSSIBILITY OF SUCH DAMAGE.
  41     ********************************************************************* */
  42
  43 #include "lib_types.h"
  44 #include "lib_physio.h"
  45
  46 #include "pcireg.h"
  47 #include "pcivar.h"
  48
  49 extern int eoi_implemented;
  50
  51 void ht7520apic_preset (pcitag_t tag);
  52 void ht7520apic_setup (pcitag_t tag);
  53
  54
  55 /* PLX HT7520 (LDT to PCI-X bridge + APIC) specific definitions */
  56
  57 #define PCI_VENDOR_AMD                  0x1022
  58 #define PCI_PRODUCT_PLX_HT7520          0x7450
  59 #define PCI_PRODUCT_PLX_HT7520_APIC     0x7451
  60
  61 /* HT7520 specific registers */
  62
  63 /* APIC configuration registers */
  64
  65 #define APIC_CONTROL_REG                0x0044
  66
  67 #define APIC_CONTROL_OSVISBAR           (1 << 0)
  68 #define APIC_CONTROL_IOAEN              (1 << 1)
  69
  70 #define APIC_BASE_ADDR_REG              0x0048
  71
  72 /* APIC registers in BAR0 memory space */
  73
  74 #define HT7520_APIC_INDEX_REG           0x0000
  75 #define HT7520_APIC_DATA_REG            0x0010
  76
  77 #define APIC_ID_INDEX                   0x00
  78 #define APIC_VERSION_INDEX              0x01
  79 #define APIC_ARBID_INDEX                0x02
  80 #define APIC_RDR_BASE_INDEX             0x10
  81 #define APIC_RDR_LO_INDEX(n)            (APIC_RDR_BASE_INDEX + 2*(n))
  82 #define APIC_RDR_HI_INDEX(n)            (APIC_RDR_BASE_INDEX + 2*(n) + 1)
  83
  84 #define RDR_HI_DEST_SHIFT               (56-32)
  85 #define RDR_HI_DEST_MASK                (0xff << RDR_HI_DEST_SHIFT)
  86 #define RDR_LO_IM                       (1 << 16)
  87 #define RDR_LO_TM                       (1 << 15)
  88 #define RDR_LO_IRR                      (1 << 14)
  89 #define RDR_LO_POL                      (1 << 13)
  90 #define RDR_LO_DS                       (1 << 12)
  91 #define RDR_LO_DM                       (1 << 11)
  92 #define RDR_LO_MT_SHIFT                 8
  93 #define RDR_LO_MT_MASK                  (3 << RDR_LO_MT_SHIFT)
  94 #define RDR_LO_IV_SHIFT                 0
  95 #define RDR_LO_IV_MASK                  (0xff << RDR_LO_IV_SHIFT)
  96
  97 void
  98 ht7520apic_preset (pcitag_t tag)
  99 {
 100     pcireg_t ctrl;
 101
 102     /* For some reason, BAR0 (necessary for setting the interrupt
 103        mapping) is hidden by default; the following makes it
 104        visible. */
 105     ctrl = pci_conf_read(tag, APIC_CONTROL_REG);
 106     ctrl |= APIC_CONTROL_IOAEN | APIC_CONTROL_OSVISBAR;
 107     pci_conf_write(tag, APIC_CONTROL_REG, ctrl);
 108     ctrl = pci_conf_read(tag, APIC_CONTROL_REG);   /* push */
 109 }
 110
 111 void
 112 ht7520apic_setup (pcitag_t tag)
 113 {
 114     int port, bus, device, function;
 115     pcitag_t br_tag;
 116     int secondary;
 117     struct pci_bus *pb;
 118     unsigned offset;
 119     phys_addr_t apic_addr;
 120     uint32_t rdrh, rdrl;
 121     int i;
 122
 123     /* The HT7520 splits the bridge and APIC functionality between two
 124        functions.  The following code depends upon a known
 125        relationship between the bridge and APIC tags, with a temporary
 126        fudge for the simulator.  NB: We assume that the bridge
 127        function has already been initialized. */
 128
 129     pci_break_tag(tag, &port, &bus, &device, &function);
 130
 131 #ifdef _FUNCSIM_
 132     br_tag = pci_make_tag(port, bus, device-2, 0);
 133 #else
 134     br_tag = pci_make_tag(port, bus, device, function-1);
 135 #endif
 136     secondary = (pci_conf_read(br_tag, PPB_BUSINFO_REG) >> 8) & 0xff;
 137     pb = pci_businfo(port, secondary);
 138
 139     /* Set up interrupt mappings. */
 140     pci_map_mem(tag, PCI_MAPREG(0), PCI_MATCH_BITS, &apic_addr);
 141
 142     offset = pb->inta_shift % 4;
 143     for (i = 0; i < 4; i++) {
 144         phys_write32(apic_addr + HT7520_APIC_INDEX_REG, APIC_RDR_HI_INDEX(i));
 145         rdrh = 0x03 << RDR_HI_DEST_SHIFT;        /* CPU 0 + CPU 1 */
 146         phys_write32(apic_addr + HT7520_APIC_DATA_REG, rdrh);
 147         rdrh = phys_read32(apic_addr + HT7520_APIC_DATA_REG);  /* push */
 148
 149         phys_write32(apic_addr + HT7520_APIC_INDEX_REG, APIC_RDR_LO_INDEX(i));
 150         if (eoi_implemented) {
 151             /* Passes >=2 have working EOI. Trigger=Level */
 152             rdrl = (RDR_LO_TM |                      /* Level */
 153                     RDR_LO_POL |                     /* Active Low */
 154                     RDR_LO_DM |                      /* Logical */
 155                     0x0 << RDR_LO_MT_SHIFT |         /* Fixed */
 156                     (56+offset) << RDR_LO_IV_SHIFT); /* Vector */
 157         } else {
 158             /* Pass 1 lacks working EOI. Trigger=Edge.  Note that
 159                LO_POL appears mis-documented for edges.  */
 160             rdrl = (RDR_LO_DM |                      /* Logical */
 161                     0x0 << RDR_LO_MT_SHIFT |         /* Fixed */
 162                     (56+offset) << RDR_LO_IV_SHIFT); /* Vector */
 163         }
 164         phys_write32(apic_addr + HT7520_APIC_DATA_REG, rdrl);
 165         offset = (offset + 1) % 4;
 166     }
 167 }