release/src-rt-6.x/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_l1cache.S

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  L1C initialization                       File: bcmcore_l1cache.S
   5     *
   6     *  This module contains code to initialize the CPU's caches
   7     *
   8     *  Note: all the routines in this module rely on registers only,
   9     *        since DRAM may not be active yet.
  10     *
  11     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  12     *
  13     *********************************************************************
  14     *
  15     *  XX Copyright 2000,2001
  16     *  Broadcom Corporation. All rights reserved.
  17     *
  18     *  BROADCOM PROPRIETARY AND CONFIDENTIAL
  19     *
  20     *  This software is furnished under license and may be used and
  21     *  copied only in accordance with the license.
  22     ********************************************************************* */
  23
  24 #include "sbmips.h"
  25 #include "bsp_config.h"
  26
  27                 .text
  28
  29                 .set push
  30                 .set mips32
  31
  32 /*  *********************************************************************
  33     *  BCMCORE_L1CACHE_INIT()
  34     *
  35     *  Initialize the L1 Cache
  36     *
  37     *  Input parameters:
  38     *      nothing
  39     *
  40     *  Return value:
  41     *      nothing
  42     *
  43     *  Registers used:
  44     *      t0,t1,t2
  45     ********************************************************************* */
  46
  47 LEAF(bcmcore_l1cache_init)
  48
  49         /*
  50          * Size the icache
  51          */
  52
  53                 mfc0    t0,C0_CONFIG,1
  54
  55         /*
  56          * Sets Per Way = 64 << CFG_IS
  57          */
  58
  59                 li      t2,M_CFG_IS
  60                 and     t2,t0
  61                 srl     t2,S_CFG_IS
  62                 li      t1,64
  63                 sll     t1,t2
  64
  65         /*
  66          * Associativity = 1 + CFG_IA
  67          */
  68
  69                 li      t2,M_CFG_IA
  70                 and     t2,t0
  71                 srl     t2,S_CFG_IA
  72                 addiu   t2,1
  73
  74         /*
  75          * Associativity * Sets Per Way
  76          */
  77
  78                 multu   t1,t2
  79                 mflo    t1
  80
  81         /*
  82          * Line Size = 2 << CFG_IL
  83          */
  84
  85                 li      t2,M_CFG_IL
  86                 and     t2,t0
  87                 srl     t2,S_CFG_IL
  88                 li      t0,2
  89                 sll     t2,t0,t2
  90
  91         /*
  92          * Instruction Cache Size =
  93          * Associativity * Line Size * Sets Per Way
  94          */
  95
  96                 multu   t1,t2
  97                 mflo    t0
  98
  99         /*
 100          * Zero the icache
 101          */
 102
 103                 mtc0    zero,C0_TAGLO
 104                 mtc0    zero,C0_TAGHI
 105                 li      t1,K0BASE
 106 1:              sub     t0,t0,t2
 107                 cache   Index_Store_Tag_I,0(t1)
 108                 add     t1,t2
 109                 bne     t0,zero,1b
 110
 111         /*
 112          * Size the dcache
 113          */
 114
 115                 mfc0    t0,C0_CONFIG,1
 116
 117         /*
 118          * Sets Per Way = 64 << CFG_DS
 119          */
 120
 121                 li      t2,M_CFG_DS
 122                 and     t2,t0
 123                 srl     t2,S_CFG_DS
 124                 li      t1,64
 125                 sll     t1,t2
 126
 127
 128         /*
 129          * Associativity = 1 + CFG_DA
 130          */
 131
 132                 li      t2,M_CFG_DA
 133                 and     t2,t0
 134                 srl     t2,S_CFG_DA
 135                 addiu   t2,1
 136
 137         /*
 138          * Associativity * Sets Per Way
 139          */
 140
 141                 multu   t1,t2
 142                 mflo    t1
 143
 144         /*
 145          * Line Size = 2 << CFG_DL
 146          */
 147
 148                 li      t2,M_CFG_DL
 149                 and     t2,t0
 150                 srl     t2,S_CFG_DL
 151                 li      t0,2
 152                 sll     t2,t0,t2
 153
 154         /*
 155          * Data Cache Size =
 156          * Associativity * Line Size * Sets Per Way
 157          */
 158
 159                 multu   t1,t2
 160                 mflo    t0
 161
 162         /*
 163          * Zero the dcache
 164          */
 165
 166                 mfc0    t1,C0_CONFIG
 167                 andi    t1,M_CFG_AR
 168                 beqz    t1,r1           # t1 == 0 if mips32r1
 169
 170                 mtc0    zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
 171                 mtc0    zero,C0_TAGHI,2
 172                 b       2f
 173                 nop
 174
 175 r1:             mtc0    zero,C0_TAGLO
 176                 mtc0    zero,C0_TAGHI
 177
 178 2:              li      t1,K0BASE
 179 1:              sub     t0,t0,t2
 180                 cache   Index_Store_Tag_D,0(t1)
 181                 add     t1,t2
 182                 bne     t0,zero,1b
 183
 184         # Now make K0 cacheable
 185
 186                 mfc0    v0,C0_CONFIG            # get current CONFIG register
 187                 srl     v0,v0,3                 # strip out K0 bits
 188                 sll     v0,v0,3                 # k0 bits now zero
 189                 or      v0,v0,K_CFG_K0COH_CACHEABLE # K0 is cacheable.
 190                 mtc0    v0,C0_CONFIG
 191                 nop
 192
 193                 jr      ra
 194
 195 END(bcmcore_l1cache_init)
 196
 197 /*  *********************************************************************
 198     *  BCMCORE_L1CACHE_INVAL_I()
 199     *
 200     *  Invalidate the entire ICache
 201     *
 202     *  Input parameters:
 203     *      nothing
 204     *
 205     *  Return value:
 206     *      nothing
 207     *
 208     *  Registers used:
 209     *      t0,t1,t2
 210     ********************************************************************* */
 211
 212 LEAF(bcmcore_l1cache_inval_i)
 213
 214         /*
 215          * Size the icache
 216          */
 217
 218                 mfc0    t0,C0_CONFIG,1
 219
 220         /*
 221          * Sets Per Way = 64 << CFG_IS
 222          */
 223
 224                 li      t2,M_CFG_IS
 225                 and     t2,t0
 226                 srl     t2,S_CFG_IS
 227                 li      t1,64
 228                 sll     t1,t2
 229
 230         /*
 231          * Associativity = 1 + CFG_IA
 232          */
 233
 234                 li      t2,M_CFG_IA
 235                 and     t2,t0
 236                 srl     t2,S_CFG_IA
 237                 addiu   t2,1
 238
 239         /*
 240          * Associativity * Sets Per Way
 241          */
 242
 243                 multu   t1,t2
 244                 mflo    t1
 245
 246         /*
 247          * Line Size = 2 << CFG_IL
 248          */
 249
 250                 li      t2,M_CFG_IL
 251                 and     t2,t0
 252                 srl     t2,S_CFG_IL
 253                 li      t0,2
 254                 sll     t2,t0,t2
 255
 256         /*
 257          * Instruction Cache Size =
 258          * Associativity * Line Size * Sets Per Way
 259          */
 260
 261                 multu   t1,t2
 262                 mflo    t0
 263
 264         /*
 265          * Invalidate the icache
 266          */
 267
 268                 mtc0    zero,C0_TAGLO
 269                 mtc0    zero,C0_TAGHI
 270                 li      t1,K0BASE
 271 1:              sub     t0,t0,t2
 272                 cache   Index_Invalidate_I,0(t1)
 273                 add     t1,t2
 274                 bne     t0,zero,1b
 275
 276                 j       ra
 277
 278 END(bcmcore_l1cache_inval_i)
 279
 280 /*  *********************************************************************
 281     *  BCMCORE_L1CACHE_FLUSH_D()
 282     *
 283     *  Flush the entire DCache
 284     *
 285     *  Input parameters:
 286     *      nothing
 287     *
 288     *  Return value:
 289     *      nothing
 290     *
 291     *  Registers used:
 292     *      t0,t1,t2,t3
 293     ********************************************************************* */
 294
 295 LEAF(bcmcore_l1cache_flush_d)
 296
 297         /*
 298          * Size the dcache
 299          */
 300
 301                 mfc0    t0,C0_CONFIG,1
 302
 303         /*
 304          * Sets Per Way = 64 << CFG_DS
 305          */
 306
 307                 li      t2,M_CFG_DS
 308                 and     t2,t0
 309                 srl     t2,S_CFG_DS
 310                 li      t1,64
 311                 sll     t1,t2
 312
 313
 314         /*
 315          * Associativity = 1 + CFG_DA
 316          */
 317
 318                 li      t2,M_CFG_DA
 319                 and     t2,t0
 320                 srl     t2,S_CFG_DA
 321                 addiu   t2,1
 322
 323         /*
 324          * Associativity * Sets Per Way
 325          */
 326
 327                 multu   t1,t2
 328                 mflo    t1
 329
 330         /*
 331          * Line Size = 2 << CFG_DL
 332          */
 333
 334                 li      t2,M_CFG_DL
 335                 and     t2,t0
 336                 srl     t2,S_CFG_DL
 337                 li      t0,2
 338                 sll     t2,t0,t2
 339
 340         /*
 341          * Data Cache Size =
 342          * Associativity * Line Size * Sets Per Way
 343          */
 344
 345                 multu   t1,t2
 346                 mflo    t0
 347
 348         /*
 349          * Flush the dcache
 350          */
 351
 352                 mtc0    zero,C0_TAGLO
 353                 mtc0    zero,C0_TAGHI
 354                 li      t1,K0BASE
 355 1:              sub     t0,t0,t2
 356                 cache   Index_Writeback_Inv_D,0(t1)
 357                 add     t1,t2
 358                 bne     t0,zero,1b
 359
 360                 j       ra
 361
 362 END(bcmcore_l1cache_flush_d)
 363
 364
 365                 .set pop
 366
 367 /*  *********************************************************************
 368     *  End
 369     ********************************************************************* */