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allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / cfe / cfe / arch / mips / common / src / disasm.c
blob23cdb309a587bde546e46899abd3931ea23f3869
1 /* *********************************************************************
2 * Broadcom Common Firmware Environment (CFE)
3 *
4 * MIPS disassembler File: disasm.c
5 *
6 * MIPS disassembler (used by ui_examcmds.c)
7 *
8 * Author: Justin Carlson (carlson@broadcom.com)
9 *
10 *********************************************************************
11 *
12 * Copyright 2000,2001,2002,2003
13 * Broadcom Corporation. All rights reserved.
14 *
15 * This software is furnished under license and may be used and
16 * copied only in accordance with the following terms and
17 * conditions. Subject to these conditions, you may download,
18 * copy, install, use, modify and distribute modified or unmodified
19 * copies of this software in source and/or binary form. No title
20 * or ownership is transferred hereby.
21 *
22 * 1) Any source code used, modified or distributed must reproduce
23 * and retain this copyright notice and list of conditions
24 * as they appear in the source file.
25 *
26 * 2) No right is granted to use any trade name, trademark, or
27 * logo of Broadcom Corporation. The "Broadcom Corporation"
28 * name may not be used to endorse or promote products derived
29 * from this software without the prior written permission of
30 * Broadcom Corporation.
31 *
32 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
33 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
34 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
35 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
36 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
37 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
38 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
40 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
41 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
42 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
43 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
44 * THE POSSIBILITY OF SUCH DAMAGE.
45 ********************************************************************* */
46
47
48 #include "lib_types.h"
49 #include "lib_string.h"
50 #include "disasm.h"
51 #include "lib_printf.h"
52
53 #define UINT64_T(x) ((uint64_t) (x##LL))
54 #define PF_64 "ll"
55 #define PF_32 ""
56 /* These aren't guaranteed to be portable, either */
57 #define SEXT_32(bit, val) \
58 ((((int32_t)(val))<<(31-(bit)))>>(31-(bit)))
59 #define SEXT_64(bit, val) \
60 ((((int64_t)(val))<<(63-(bit)))>>(63-(bit)))
61
62 #define DATASEG __attribute__ ((section(".text")))
63
64
65 #define REGNAME(r) (&_regnames[(r)*5])
66 static const char * const _regnames =
67 "zero\0"
68 "AT\0 "
69 "v0\0 "
70 "v1\0 "
71 "a0\0 "
72 "a1\0 "
73 "a2\0 "
74 "a3\0 "
75 "t0\0 "
76 "t1\0 "
77 "t2\0 "
78 "t3\0 "
79 "t4\0 "
80 "t5\0 "
81 "t6\0 "
82 "t7\0 "
83 "s0\0 "
84 "s1\0 "
85 "s2\0 "
86 "s3\0 "
87 "s4\0 "
88 "s5\0 "
89 "s6\0 "
90 "s7\0 "
91 "t8\0 "
92 "t9\0 "
93 "k0\0 "
94 "k1\0 "
95 "gp\0 "
96 "sp\0 "
97 "fp\0 "
98 "ra\0 ";
99
100 #define CP0REGNAME(r) (&_cp0names[(r)*12])
101 static const char * const _cp0names =
102 "C0_INX\0 "
103 "C0_RAND\0 "
104 "C0_TLBLO0\0 "
105 "C0_TLBLO1\0 "
106
107 "C0_CTEXT\0 "
108 "C0_PGMASK\0 "
109 "C0_WIRED\0 "
110 "C0_reserved\0"
111
112 "C0_BADVADDR\0"
113 "C0_COUNT\0 "
114 "C0_TLBHI\0 "
115 "C0_COMPARE\0 "
116
117 "C0_SR\0 "
118 "C0_CAUSE\0 "
119 "C0_EPC\0 "
120 "C0_PRID\0 "
121
122 "C0_CONFIG\0 "
123 "C0_LLADDR\0 "
124 "C0_WATCHLO\0 "
125 "C0_WATCHHI\0 "
126
127 "C0_XCTEXT\0 "
128 "C0_reserved\0"
129 "C0_reserved\0"
130 "C0_reserved\0"
131
132 "C0_reserved\0"
133 "C0_reserved\0"
134 "C0_reserved\0"
135 "C0_reserved\0"
136
137 "C0_TAGLO\0 "
138 "C0_TAGHI\0 "
139 "C0_ERREPC\0 "
140 "C0_reserved\0";
141
142
143
144 /*
145 * MIPS instruction set disassembly module.
146 */
147
148 typedef enum {
149 DC_RD_RS_RT,
150 DC_RD_RT_RS,
151 DC_RT_RS_SIMM,
152 DC_RT_RS_XIMM,
153 DC_RS_RT_OFS,
154 DC_RS_OFS,
155 DC_RD_RT_SA,
156 DC_RT_UIMM,
157 DC_RD,
158 DC_J,
159 DC_RD_RS,
160 DC_RS_RT,
161 DC_RT_RS,
162 DC_RT_RD_SEL,
163 DC_RT_CR_SEL,
164 DC_RS,
165 DC_RS_SIMM,
166 DC_RT_OFS_BASE,
167 DC_FT_OFS_BASE,
168 DC_FD_IDX_BASE,
169 DC_FS_IDX_BASE,
170 DC_FD_FS_FT,
171 DC_FD_FS_RT,
172 DC_FD_FS,
173 DC_PREF_OFS,
174 DC_PREF_IDX,
175 DC_CC_OFS,
176 DC_FD_FS_CC,
177 DC_RD_RS_CC,
178 DC_FD_FR_FS_FT,
179 DC_FD_FS_FT_RS,
180 DC_CC_FS_FT,
181 DC_BARE,
182 DC_RT_FS,
183 DC_SYSCALL,
184 DC_BREAK,
185 DC_VD_VS_VT_VEC,
186 DC_VD_VS_VT,
187 DC_VS_VT,
188 DC_VS_VT_VEC,
189 DC_VD_VS_VT_RS,
190 DC_VD_VS_VT_IMM,
191 DC_VD_VT,
192 DC_VD,
193 DC_VS,
194 DC_DEREF,
195 DC_OOPS
196 } DISASM_CLASS;
197
198
199
200
201 /* We're pulling some trickery here. Most of the time, this structure operates
202 exactly as one would expect. The special case, when type == DC_DREF,
203 means name points to a byte that is an index into a dereferencing array. */
204
205 /*
206 * To make matters worse, the whole module has been coded to reduce the
207 * number of relocations present, so we don't actually store pointers
208 * in the dereferencing array. Instead, we store fixed-width strings
209 * and use digits to represent indicies into the deref array.
210 *
211 * This is all to make more things fit in the relocatable version,
212 * since every initialized pointer goes into our small data segment.
213 */
214
215 typedef struct {
216 char name[15];
217 char type;
218 } disasm_t;
219
220 typedef struct {
221 const disasm_t *ptr;
222 int shift;
223 uint32_t mask;
224 } disasm_deref_t;
225
226 /* Forward declaration of deref array, we need this for the disasm_t definitions */
227
228
229 extern const disasm_deref_t disasm_deref[];
230
231 static const disasm_t disasm_normal[64] DATASEG =
232 {{"$1" , DC_DEREF },
233 {"$2" , DC_DEREF },
234 {"j" , DC_J },
235 {"jal" , DC_J },
236 {"beq" , DC_RS_RT_OFS },
237 {"bne" , DC_RS_RT_OFS },
238 {"blez" , DC_RS_OFS },
239 {"bgtz" , DC_RS_OFS },
240 {"addi" , DC_RT_RS_SIMM },
241 {"addiu" , DC_RT_RS_SIMM },
242 {"slti" , DC_RT_RS_SIMM },
243 {"sltiu" , DC_RT_RS_SIMM },
244 {"andi" , DC_RT_RS_XIMM },
245 {"ori" , DC_RT_RS_XIMM },
246 {"xori" , DC_RT_RS_XIMM },
247 {"lui" , DC_RT_UIMM },
248 {"$4" , DC_DEREF },
249 {"$6" , DC_DEREF },
250 {"invalid" , DC_BARE },
251 {"$15" , DC_DEREF },
252 {"beql" , DC_RS_RT_OFS },
253 {"bnel" , DC_RS_RT_OFS },
254 {"blezl" , DC_RS_OFS },
255 {"bgtzl" , DC_RS_OFS },
256 {"daddi" , DC_RT_RS_SIMM },
257 {"daddiu" , DC_RT_RS_SIMM },
258 {"ldl" , DC_RT_OFS_BASE },
259 {"ldr" , DC_RT_OFS_BASE },
260 {"$3" , DC_DEREF },
261 {"invalid" , DC_BARE },
262 {"$18" , DC_DEREF },
263 {"invalid" , DC_BARE },
264 {"lb" , DC_RT_OFS_BASE },
265 {"lh" , DC_RT_OFS_BASE },
266 {"lwl" , DC_RT_OFS_BASE },
267 {"lw" , DC_RT_OFS_BASE },
268 {"lbu" , DC_RT_OFS_BASE },
269 {"lhu" , DC_RT_OFS_BASE },
270 {"lwr" , DC_RT_OFS_BASE },
271 {"lwu" , DC_RT_OFS_BASE },
272 {"sb" , DC_RT_OFS_BASE },
273 {"sh" , DC_RT_OFS_BASE },
274 {"swl" , DC_RT_OFS_BASE },
275 {"sw" , DC_RT_OFS_BASE },
276 {"sdl" , DC_RT_OFS_BASE },
277 {"sdr" , DC_RT_OFS_BASE },
278 {"swr" , DC_RT_OFS_BASE },
279 {"cache" , DC_BARE },
280 {"ll" , DC_RT_OFS_BASE },
281 {"lwc1" , DC_FT_OFS_BASE },
282 {"invalid" , DC_BARE },
283 {"pref" , DC_PREF_OFS },
284 {"lld" , DC_RT_OFS_BASE },
285 {"ldc1" , DC_FT_OFS_BASE },
286 {"invalid" , DC_BARE },
287 {"ld" , DC_RT_OFS_BASE },
288 {"sc" , DC_RT_OFS_BASE },
289 {"swc1" , DC_FT_OFS_BASE },
290 {"invalid" , DC_BARE },
291 {"invalid" , DC_BARE },
292 {"scd" , DC_RT_OFS_BASE },
293 {"sdc1" , DC_FT_OFS_BASE },
294 {"invalid" , DC_BARE },
295 {"sd" , DC_RT_OFS_BASE }};
296
297 static const disasm_t disasm_special[64] DATASEG =
298 {{"sll" , DC_RD_RT_SA },
299 {"$16" , DC_DEREF },
300 {"srl" , DC_RD_RT_SA },
301 {"sra" , DC_RD_RT_SA },
302 {"sllv" , DC_RD_RT_RS },
303 {"invalid" , DC_BARE },
304 {"srlv" , DC_RD_RT_RS },
305 {"srav" , DC_RD_RT_RS },
306 {"jr" , DC_RS },
307 {"jalr" , DC_RD_RS },
308 {"movz" , DC_RD_RS_RT },
309 {"movn" , DC_RD_RS_RT },
310 {"syscall" , DC_SYSCALL },
311 {"break" , DC_BREAK },
312 {"invalid" , DC_BARE },
313 {"sync" , DC_BARE },
314 {"mfhi" , DC_RD },
315 {"mthi" , DC_RS },
316 {"mflo" , DC_RD },
317 {"mtlo" , DC_RS },
318 {"dsllv" , DC_RD_RT_RS },
319 {"invalid" , DC_BARE },
320 {"dsrlv" , DC_RD_RT_RS },
321 {"dsrav" , DC_RD_RT_RS },
322 {"mult" , DC_RS_RT },
323 {"multu" , DC_RS_RT },
324 {"div" , DC_RS_RT },
325 {"divu" , DC_RS_RT },
326 {"dmult" , DC_RS_RT },
327 {"dmultu" , DC_RS_RT },
328 {"ddiv" , DC_RS_RT },
329 {"ddivu" , DC_RS_RT },
330 {"add" , DC_RD_RS_RT },
331 {"addu" , DC_RD_RS_RT },
332 {"sub" , DC_RD_RS_RT },
333 {"subu" , DC_RD_RS_RT },
334 {"and" , DC_RD_RS_RT },
335 {"or" , DC_RD_RS_RT },
336 {"xor" , DC_RD_RS_RT },
337 {"nor" , DC_RD_RS_RT },
338 {"invalid" , DC_BARE },
339 {"invalid" , DC_BARE },
340 {"slt" , DC_RD_RS_RT },
341 {"sltu" , DC_RD_RS_RT },
342 {"dadd" , DC_RD_RS_RT },
343 {"daddu" , DC_RD_RS_RT },
344 {"dsub" , DC_RD_RS_RT },
345 {"dsubu" , DC_RD_RS_RT },
346 {"tge" , DC_RS_RT },
347 {"tgeu" , DC_RS_RT },
348 {"tlt" , DC_RS_RT },
349 {"tltu" , DC_RS_RT },
350 {"teq" , DC_RS_RT },
351 {"invalid" , DC_BARE },
352 {"tne" , DC_RS_RT },
353 {"invalid" , DC_BARE },
354 {"dsll" , DC_RD_RT_SA },
355 {"invalid" , DC_BARE },
356 {"dsrl" , DC_RD_RT_SA },
357 {"dsra" , DC_RD_RT_SA },
358 {"dsll32" , DC_RD_RT_SA },
359 {"invalid" , DC_BARE },
360 {"dsrl32" , DC_RD_RT_SA },
361 {"dsra32" , DC_RD_RT_SA }};
362
363 static const disasm_t disasm_movci[2] DATASEG =
364 {{"movf" , DC_RD_RS_CC },
365 {"movt" , DC_RD_RS_CC }};
366
367 static const disasm_t disasm_regimm[32] DATASEG =
368 {{"bltz" , DC_RS_OFS },
369 {"bgez" , DC_RS_OFS },
370 {"bltzl" , DC_RS_OFS },
371 {"bgezl" , DC_RS_OFS },
372 {"invalid" , DC_BARE },
373 {"invalid" , DC_BARE },
374 {"invalid" , DC_BARE },
375 {"invalid" , DC_BARE },
376 {"tgei" , DC_RS_SIMM },
377 {"tgeiu" , DC_RS_SIMM },
378 {"tlti" , DC_RS_SIMM },
379 {"tltiu" , DC_RS_SIMM },
380 {"teqi" , DC_RS_SIMM },
381 {"invalid" , DC_BARE },
382 {"tnei" , DC_RS_SIMM },
383 {"invalid" , DC_BARE },
384 {"bltzal" , DC_RS_OFS },
385 {"bgezal" , DC_RS_OFS },
386 {"bltzall" , DC_RS_OFS },
387 {"bgezall" , DC_RS_OFS },
388 {"invalid" , DC_BARE },
389 {"invalid" , DC_BARE },
390 {"invalid" , DC_BARE },
391 {"invalid" , DC_BARE },
392 {"invalid" , DC_BARE },
393 {"invalid" , DC_BARE },
394 {"invalid" , DC_BARE },
395 {"invalid" , DC_BARE },
396 {"invalid" , DC_BARE },
397 {"invalid" , DC_BARE },
398 {"invalid" , DC_BARE },
399 {"invalid" , DC_BARE }};
400
401 static const disasm_t disasm_spec2[64] DATASEG =
402 {{"madd" , DC_RS_RT },
403 {"maddu" , DC_RS_RT },
404 {"mul" , DC_RD_RS_RT },
405 {"invalid" , DC_BARE },
406 {"msub" , DC_RS_RT },
407 {"msubu" , DC_RS_RT },
408 {"invalid" , DC_BARE },
409 {"invalid" , DC_BARE },
410 {"invalid" , DC_BARE },
411 {"invalid" , DC_BARE },
412 {"invalid" , DC_BARE },
413 {"invalid" , DC_BARE },
414 {"invalid" , DC_BARE },
415 {"invalid" , DC_BARE },
416 {"invalid" , DC_BARE },
417 {"invalid" , DC_BARE },
418 {"invalid" , DC_BARE },
419 {"invalid" , DC_BARE },
420 {"invalid" , DC_BARE },
421 {"invalid" , DC_BARE },
422 {"invalid" , DC_BARE },
423 {"invalid" , DC_BARE },
424 {"invalid" , DC_BARE },
425 {"invalid" , DC_BARE },
426 {"invalid" , DC_BARE },
427 {"invalid" , DC_BARE },
428 {"invalid" , DC_BARE },
429 {"invalid" , DC_BARE },
430 {"invalid" , DC_BARE },
431 {"invalid" , DC_BARE },
432 {"invalid" , DC_BARE },
433 {"invalid" , DC_BARE },
434 {"clz" , DC_RT_RS },
435 {"clo" , DC_RT_RS },
436 {"invalid" , DC_BARE },
437 {"invalid" , DC_BARE },
438 {"dclz" , DC_RT_RS },
439 {"dclo" , DC_RT_RS },
440 {"invalid" , DC_BARE },
441 {"invalid" , DC_BARE },
442 {"invalid" , DC_BARE },
443 {"invalid" , DC_BARE },
444 {"invalid" , DC_BARE },
445 {"invalid" , DC_BARE },
446 {"invalid" , DC_BARE },
447 {"invalid" , DC_BARE },
448 {"invalid" , DC_BARE },
449 {"invalid" , DC_BARE },
450 {"invalid" , DC_BARE },
451 {"invalid" , DC_BARE },
452 {"invalid" , DC_BARE },
453 {"invalid" , DC_BARE },
454 {"invalid" , DC_BARE },
455 {"invalid" , DC_BARE },
456 {"invalid" , DC_BARE },
457 {"invalid" , DC_BARE },
458 {"invalid" , DC_BARE },
459 {"invalid" , DC_BARE },
460 {"invalid" , DC_BARE },
461 {"invalid" , DC_BARE },
462 {"invalid" , DC_BARE },
463 {"invalid" , DC_BARE },
464 {"invalid" , DC_BARE },
465 {"sdbbp" , DC_BARE }};
466
467 static const disasm_t disasm_cop0[32] DATASEG =
468 {{"mfc0@1" , DC_RT_CR_SEL },
469 {"dmfc0@1" , DC_RT_CR_SEL },
470 {"invalid" , DC_BARE },
471 {"invalid" , DC_BARE },
472 {"mtc0@1" , DC_RT_CR_SEL },
473 {"dmtc0@1" , DC_RT_CR_SEL },
474 {"invalid" , DC_BARE },
475 {"invalid" , DC_BARE },
476 {"invalid" , DC_BARE },
477 {"invalid" , DC_BARE },
478 {"invalid" , DC_BARE },
479 {"invalid" , DC_BARE },
480 {"invalid" , DC_BARE },
481 {"invalid" , DC_BARE },
482 {"invalid" , DC_BARE },
483 {"invalid" , DC_BARE },
484 {"$5" , DC_DEREF },
485 {"$5" , DC_DEREF },
486 {"$5" , DC_DEREF },
487 {"$5" , DC_DEREF },
488 {"$5" , DC_DEREF },
489 {"$5" , DC_DEREF },
490 {"$5" , DC_DEREF },
491 {"$5" , DC_DEREF },
492 {"$5" , DC_DEREF },
493 {"$5" , DC_DEREF },
494 {"$5" , DC_DEREF },
495 {"$5" , DC_DEREF },
496 {"$5" , DC_DEREF },
497 {"$5" , DC_DEREF },
498 {"$5" , DC_DEREF },
499 {"$5" , DC_DEREF }};
500
501 static const disasm_t disasm_cop0_c0[64] DATASEG =
502 {{"invalid" , DC_BARE },
503 {"tlbr" , DC_BARE },
504 {"tlbwi" , DC_BARE },
505 {"invalid" , DC_BARE },
506 {"invalid" , DC_BARE },
507 {"invalid" , DC_BARE },
508 {"tlbwr" , DC_BARE },
509 {"invalid" , DC_BARE },
510 {"tlbp" , DC_BARE },
511 {"invalid" , DC_BARE },
512 {"invalid" , DC_BARE },
513 {"invalid" , DC_BARE },
514 {"invalid" , DC_BARE },
515 {"invalid" , DC_BARE },
516 {"invalid" , DC_BARE },
517 {"invalid" , DC_BARE },
518 {"invalid" , DC_BARE },
519 {"invalid" , DC_BARE },
520 {"invalid" , DC_BARE },
521 {"invalid" , DC_BARE },
522 {"invalid" , DC_BARE },
523 {"invalid" , DC_BARE },
524 {"invalid" , DC_BARE },
525 {"invalid" , DC_BARE },
526 {"eret" , DC_BARE },
527 {"invalid" , DC_BARE },
528 {"invalid" , DC_BARE },
529 {"invalid" , DC_BARE },
530 {"invalid" , DC_BARE },
531 {"invalid" , DC_BARE },
532 {"invalid" , DC_BARE },
533 {"deret" , DC_BARE },
534 {"wait" , DC_BARE },
535 {"invalid" , DC_BARE },
536 {"invalid" , DC_BARE },
537 {"invalid" , DC_BARE },
538 {"invalid" , DC_BARE },
539 {"invalid" , DC_BARE },
540 {"invalid" , DC_BARE },
541 {"invalid" , DC_BARE },
542 {"invalid" , DC_BARE },
543 {"invalid" , DC_BARE },
544 {"invalid" , DC_BARE },
545 {"invalid" , DC_BARE },
546 {"invalid" , DC_BARE },
547 {"invalid" , DC_BARE },
548 {"invalid" , DC_BARE },
549 {"invalid" , DC_BARE },
550 {"invalid" , DC_BARE },
551 {"invalid" , DC_BARE },
552 {"invalid" , DC_BARE },
553 {"invalid" , DC_BARE },
554 {"invalid" , DC_BARE },
555 {"invalid" , DC_BARE },
556 {"invalid" , DC_BARE },
557 {"invalid" , DC_BARE },
558 {"invalid" , DC_BARE },
559 {"invalid" , DC_BARE },
560 {"invalid" , DC_BARE },
561 {"invalid" , DC_BARE },
562 {"invalid" , DC_BARE },
563 {"invalid" , DC_BARE },
564 {"invalid" , DC_BARE },
565 {"invalid" , DC_BARE }};
566
567 static const disasm_t disasm_cop1[32] DATASEG =
568 {{"mfc1" , DC_RT_FS },
569 {"dmfc1" , DC_RT_FS },
570 {"cfc1" , DC_RT_FS },
571 {"invalid" , DC_BARE },
572 {"mtc1" , DC_RT_FS },
573 {"dmtc1" , DC_RT_FS },
574 {"ctc1" , DC_RT_FS },
575 {"invalid" , DC_BARE },
576 {"$17" , DC_DEREF },
577 {"$36" , DC_DEREF },
578 {"$37" , DC_DEREF },
579 {"invalid" , DC_BARE },
580 {"invalid" , DC_BARE },
581 {"invalid" , DC_BARE },
582 {"invalid" , DC_BARE },
583 {"invalid" , DC_BARE },
584 {"$7" , DC_DEREF },
585 {"$9" , DC_DEREF },
586 {"invalid" , DC_BARE },
587 {"invalid" , DC_BARE },
588 {"$11" , DC_DEREF },
589 {"$12" , DC_DEREF },
590 {"$13" , DC_DEREF },
591 {"invalid" , DC_BARE },
592 {"invalid" , DC_BARE },
593 {"invalid" , DC_BARE },
594 {"invalid" , DC_BARE },
595 {"invalid" , DC_BARE },
596 {"invalid" , DC_BARE },
597 {"invalid" , DC_BARE },
598 {"invalid" , DC_BARE },
599 {"invalid" , DC_BARE }};
600
601 static const disasm_t disasm_cop1_bc1[4] DATASEG =
602 {{"bc1f" , DC_CC_OFS },
603 {"bc1t" , DC_CC_OFS },
604 {"bc1fl" , DC_CC_OFS },
605 {"bc1tl" , DC_CC_OFS },
606 };
607
608 static const disasm_t disasm_cop1_bc1any2[2] DATASEG =
609 {{"bc1any2f" , DC_CC_OFS },
610 {"bc1any2t" , DC_CC_OFS },
611 };
612
613 static const disasm_t disasm_cop1_bc1any4[2] DATASEG =
614 {{"bc1any4f" , DC_CC_OFS },
615 {"bc1any4t" , DC_CC_OFS },
616 };
617
618 static const disasm_t disasm_cop1_s[64] DATASEG =
619 {{"add.s" , DC_FD_FS_FT },
620 {"sub.s" , DC_FD_FS_FT },
621 {"mul.s" , DC_FD_FS_FT },
622 {"div.s" , DC_FD_FS_FT },
623 {"sqrt.s" , DC_FD_FS },
624 {"abs.s" , DC_FD_FS },
625 {"mov.s" , DC_FD_FS },
626 {"neg.s" , DC_FD_FS },
627 {"round.l.s" , DC_FD_FS },
628 {"trunc.l.s" , DC_FD_FS },
629 {"ceil.l.s" , DC_FD_FS },
630 {"floor.l.s" , DC_FD_FS },
631 {"round.w.s" , DC_FD_FS },
632 {"trunc.w.s" , DC_FD_FS },
633 {"ceil.w.s" , DC_FD_FS },
634 {"floor.w.s" , DC_FD_FS },
635 {"invalid" , DC_BARE },
636 {"$8" , DC_DEREF },
637 {"movz.s" , DC_FD_FS_RT },
638 {"movn.s" , DC_FD_FS_RT },
639 {"invalid" , DC_BARE },
640 {"recip.s" , DC_FD_FS },
641 {"rsqrt.s" , DC_FD_FS },
642 {"invalid" , DC_BARE },
643 {"invalid" , DC_BARE },
644 {"invalid" , DC_BARE },
645 {"invalid" , DC_BARE },
646 {"invalid" , DC_BARE },
647 {"recip2.s" , DC_FD_FS_FT },
648 {"recip1.s" , DC_FD_FS },
649 {"rsqrt1.s" , DC_FD_FS },
650 {"rsqrt2.s" , DC_FD_FS_FT },
651 {"invalid" , DC_BARE },
652 {"cvt.d.s" , DC_FD_FS },
653 {"invalid" , DC_BARE },
654 {"invalid" , DC_BARE },
655 {"cvt.w.s" , DC_FD_FS },
656 {"cvt.l.s" , DC_FD_FS },
657 {"cvt.ps.s" , DC_FD_FS_FT },
658 {"invalid" , DC_BARE },
659 {"invalid" , DC_BARE },
660 {"invalid" , DC_BARE },
661 {"invalid" , DC_BARE },
662 {"invalid" , DC_BARE },
663 {"invalid" , DC_BARE },
664 {"invalid" , DC_BARE },
665 {"invalid" , DC_BARE },
666 {"invalid" , DC_BARE },
667 {"$38" , DC_DEREF },
668 {"$39" , DC_DEREF },
669 {"$40" , DC_DEREF },
670 {"$41" , DC_DEREF },
671 {"$42" , DC_DEREF },
672 {"$43" , DC_DEREF },
673 {"$44" , DC_DEREF },
674 {"$45" , DC_DEREF },
675 {"$46" , DC_DEREF },
676 {"$47" , DC_DEREF },
677 {"$48" , DC_DEREF },
678 {"$49" , DC_DEREF },
679 {"$50" , DC_DEREF },
680 {"$51" , DC_DEREF },
681 {"$52" , DC_DEREF },
682 {"$53" , DC_DEREF }};
683
684 static const disasm_t disasm_cop1_s_mvcf[2] DATASEG =
685 {{"movf.s" , DC_FD_FS_CC },
686 {"movt.s" , DC_FD_FS_CC }};
687
688 static const disasm_t disasm_cop1_d[64] DATASEG =
689 {{"add.d" , DC_FD_FS_FT },
690 {"sub.d" , DC_FD_FS_FT },
691 {"mul.d" , DC_FD_FS_FT },
692 {"div.d" , DC_FD_FS_FT },
693 {"sqrt.d" , DC_FD_FS },
694 {"abs.d" , DC_FD_FS },
695 {"mov.d" , DC_FD_FS },
696 {"neg.d" , DC_FD_FS },
697 {"round.l.d" , DC_FD_FS },
698 {"trunc.l.d" , DC_FD_FS },
699 {"ceil.l.d" , DC_FD_FS },
700 {"floor.l.d" , DC_FD_FS },
701 {"round.w.d" , DC_FD_FS },
702 {"trunc.w.d" , DC_FD_FS },
703 {"ceil.w.d" , DC_FD_FS },
704 {"floor.w.d" , DC_FD_FS },
705 {"invalid" , DC_BARE },
706 {"$10" , DC_DEREF },
707 {"movz.d" , DC_FD_FS_RT },
708 {"movn.d" , DC_FD_FS_RT },
709 {"invalid" , DC_BARE },
710 {"recip.d" , DC_FD_FS },
711 {"rsqrt.d" , DC_FD_FS },
712 {"invalid" , DC_BARE },
713 {"invalid" , DC_BARE },
714 {"invalid" , DC_BARE },
715 {"invalid" , DC_BARE },
716 {"invalid" , DC_BARE },
717 {"recip2.d" , DC_FD_FS_FT },
718 {"recip1.d" , DC_FD_FS },
719 {"rsqrt1.d" , DC_FD_FS },
720 {"rsqrt2.d" , DC_FD_FS_FT },
721 {"cvt.s.d" , DC_FD_FS },
722 {"invalid" , DC_BARE },
723 {"invalid" , DC_BARE },
724 {"invalid" , DC_BARE },
725 {"cvt.w.d" , DC_FD_FS },
726 {"cvt.l.d" , DC_FD_FS },
727 {"invalid" , DC_BARE },
728 {"invalid" , DC_BARE },
729 {"invalid" , DC_BARE },
730 {"invalid" , DC_BARE },
731 {"invalid" , DC_BARE },
732 {"invalid" , DC_BARE },
733 {"invalid" , DC_BARE },
734 {"invalid" , DC_BARE },
735 {"invalid" , DC_BARE },
736 {"invalid" , DC_BARE },
737 {"$54" , DC_DEREF },
738 {"$55" , DC_DEREF },
739 {"$56" , DC_DEREF },
740 {"$57" , DC_DEREF },
741 {"$58" , DC_DEREF },
742 {"$59" , DC_DEREF },
743 {"$60" , DC_DEREF },
744 {"$61" , DC_DEREF },
745 {"$62" , DC_DEREF },
746 {"$63" , DC_DEREF },
747 {"$64" , DC_DEREF },
748 {"$65" , DC_DEREF },
749 {"$66" , DC_DEREF },
750 {"$67" , DC_DEREF },
751 {"$68" , DC_DEREF },
752 {"$69" , DC_DEREF }};
753
754 static const disasm_t disasm_cop1_d_mvcf[2] DATASEG =
755 {{"movf.d" , DC_FD_FS_CC },
756 {"movt.d" , DC_FD_FS_CC }};
757
758 static const disasm_t disasm_cop1_w[64] DATASEG =
759 {{"invalid" , DC_BARE },
760 {"invalid" , DC_BARE },
761 {"invalid" , DC_BARE },
762 {"invalid" , DC_BARE },
763 {"invalid" , DC_BARE },
764 {"invalid" , DC_BARE },
765 {"invalid" , DC_BARE },
766 {"invalid" , DC_BARE },
767 {"invalid" , DC_BARE },
768 {"invalid" , DC_BARE },
769 {"invalid" , DC_BARE },
770 {"invalid" , DC_BARE },
771 {"invalid" , DC_BARE },
772 {"invalid" , DC_BARE },
773 {"invalid" , DC_BARE },
774 {"invalid" , DC_BARE },
775 {"invalid" , DC_BARE },
776 {"invalid" , DC_BARE },
777 {"invalid" , DC_BARE },
778 {"invalid" , DC_BARE },
779 {"invalid" , DC_BARE },
780 {"invalid" , DC_BARE },
781 {"invalid" , DC_BARE },
782 {"invalid" , DC_BARE },
783 {"invalid" , DC_BARE },
784 {"invalid" , DC_BARE },
785 {"invalid" , DC_BARE },
786 {"invalid" , DC_BARE },
787 {"invalid" , DC_BARE },
788 {"invalid" , DC_BARE },
789 {"invalid" , DC_BARE },
790 {"invalid" , DC_BARE },
791 {"cvt.s.w" , DC_FD_FS },
792 {"cvt.d.w" , DC_FD_FS },
793 {"invalid" , DC_BARE },
794 {"invalid" , DC_BARE },
795 {"invalid" , DC_BARE },
796 {"invalid" , DC_BARE },
797 {"cvt.ps.pw" , DC_FD_FS },
798 {"invalid" , DC_BARE },
799 {"invalid" , DC_BARE },
800 {"invalid" , DC_BARE },
801 {"invalid" , DC_BARE },
802 {"invalid" , DC_BARE },
803 {"invalid" , DC_BARE },
804 {"invalid" , DC_BARE },
805 {"invalid" , DC_BARE },
806 {"invalid" , DC_BARE },
807 {"invalid" , DC_BARE },
808 {"invalid" , DC_BARE },
809 {"invalid" , DC_BARE },
810 {"invalid" , DC_BARE },
811 {"invalid" , DC_BARE },
812 {"invalid" , DC_BARE },
813 {"invalid" , DC_BARE },
814 {"invalid" , DC_BARE },
815 {"invalid" , DC_BARE },
816 {"invalid" , DC_BARE },
817 {"invalid" , DC_BARE },
818 {"invalid" , DC_BARE },
819 {"invalid" , DC_BARE },
820 {"invalid" , DC_BARE },
821 {"invalid" , DC_BARE },
822 {"invalid" , DC_BARE }};
823
824 static const disasm_t disasm_cop1_l[64] DATASEG =
825 {{"invalid" , DC_BARE },
826 {"invalid" , DC_BARE },
827 {"invalid" , DC_BARE },
828 {"invalid" , DC_BARE },
829 {"invalid" , DC_BARE },
830 {"invalid" , DC_BARE },
831 {"invalid" , DC_BARE },
832 {"invalid" , DC_BARE },
833 {"invalid" , DC_BARE },
834 {"invalid" , DC_BARE },
835 {"invalid" , DC_BARE },
836 {"invalid" , DC_BARE },
837 {"invalid" , DC_BARE },
838 {"invalid" , DC_BARE },
839 {"invalid" , DC_BARE },
840 {"invalid" , DC_BARE },
841 {"invalid" , DC_BARE },
842 {"invalid" , DC_BARE },
843 {"invalid" , DC_BARE },
844 {"invalid" , DC_BARE },
845 {"invalid" , DC_BARE },
846 {"invalid" , DC_BARE },
847 {"invalid" , DC_BARE },
848 {"invalid" , DC_BARE },
849 {"invalid" , DC_BARE },
850 {"invalid" , DC_BARE },
851 {"invalid" , DC_BARE },
852 {"invalid" , DC_BARE },
853 {"invalid" , DC_BARE },
854 {"invalid" , DC_BARE },
855 {"invalid" , DC_BARE },
856 {"invalid" , DC_BARE },
857 {"cvt.s.l" , DC_FD_FS },
858 {"cvt.d.l" , DC_FD_FS },
859 {"invalid" , DC_BARE },
860 {"invalid" , DC_BARE },
861 {"invalid" , DC_BARE },
862 {"invalid" , DC_BARE },
863 {"invalid" , DC_BARE },
864 {"invalid" , DC_BARE },
865 {"invalid" , DC_BARE },
866 {"invalid" , DC_BARE },
867 {"invalid" , DC_BARE },
868 {"invalid" , DC_BARE },
869 {"invalid" , DC_BARE },
870 {"invalid" , DC_BARE },
871 {"invalid" , DC_BARE },
872 {"invalid" , DC_BARE },
873 {"invalid" , DC_BARE },
874 {"invalid" , DC_BARE },
875 {"invalid" , DC_BARE },
876 {"invalid" , DC_BARE },
877 {"invalid" , DC_BARE },
878 {"invalid" , DC_BARE },
879 {"invalid" , DC_BARE },
880 {"invalid" , DC_BARE },
881 {"invalid" , DC_BARE },
882 {"invalid" , DC_BARE },
883 {"invalid" , DC_BARE },
884 {"invalid" , DC_BARE },
885 {"invalid" , DC_BARE },
886 {"invalid" , DC_BARE },
887 {"invalid" , DC_BARE },
888 {"invalid" , DC_BARE }};
889
890 static const disasm_t disasm_cop1_ps[64] DATASEG =
891 {{"add.ps" , DC_FD_FS_FT },
892 {"sub.ps" , DC_FD_FS_FT },
893 {"mul.ps" , DC_FD_FS_FT },
894 {"invalid" , DC_BARE },
895 {"invalid" , DC_BARE },
896 {"abs.ps" , DC_FD_FS },
897 {"mov.ps" , DC_FD_FS },
898 {"neg.ps" , DC_FD_FS },
899 {"invalid" , DC_BARE },
900 {"invalid" , DC_BARE },
901 {"invalid" , DC_BARE },
902 {"invalid" , DC_BARE },
903 {"invalid" , DC_BARE },
904 {"invalid" , DC_BARE },
905 {"invalid" , DC_BARE },
906 {"invalid" , DC_BARE },
907 {"invalid" , DC_BARE },
908 {"$14" , DC_DEREF },
909 {"movz.ps" , DC_FD_FS_RT },
910 {"movn.ps" , DC_FD_FS_RT },
911 {"invalid" , DC_BARE },
912 {"invalid" , DC_BARE },
913 {"invalid" , DC_BARE },
914 {"invalid" , DC_BARE },
915 {"addr.ps" , DC_FD_FS_FT },
916 {"invalid" , DC_BARE },
917 {"mulr.ps" , DC_FD_FS_FT },
918 {"invalid" , DC_BARE },
919 {"recip2.ps" , DC_FD_FS_FT },
920 {"recip1.ps" , DC_FD_FS },
921 {"rsqrt1.ps" , DC_FD_FS },
922 {"rsqrt2.ps" , DC_FD_FS_FT },
923 {"cvt.s.pu" , DC_FD_FS },
924 {"invalid" , DC_BARE },
925 {"invalid" , DC_BARE },
926 {"invalid" , DC_BARE },
927 {"cvt.pw.ps" , DC_FD_FS },
928 {"invalid" , DC_BARE },
929 {"invalid" , DC_BARE },
930 {"invalid" , DC_BARE },
931 {"cvt.s.pl" , DC_FD_FS },
932 {"invalid" , DC_BARE },
933 {"invalid" , DC_BARE },
934 {"invalid" , DC_BARE },
935 {"pll.ps" , DC_FD_FS_FT },
936 {"plu.ps" , DC_FD_FS_FT },
937 {"pul.ps" , DC_FD_FS_FT },
938 {"puu.ps" , DC_FD_FS_FT },
939 {"$70" , DC_DEREF },
940 {"$71" , DC_DEREF },
941 {"$72" , DC_DEREF },
942 {"$73" , DC_DEREF },
943 {"$74" , DC_DEREF },
944 {"$75" , DC_DEREF },
945 {"$76" , DC_DEREF },
946 {"$77" , DC_DEREF },
947 {"$78" , DC_DEREF },
948 {"$79" , DC_DEREF },
949 {"$80" , DC_DEREF },
950 {"$81" , DC_DEREF },
951 {"$82" , DC_DEREF },
952 {"$83" , DC_DEREF },
953 {"$84" , DC_DEREF },
954 {"$85" , DC_DEREF }};
955
956 static const disasm_t disasm_cop1_c_f_s[2] DATASEG =
957 {{"c.f.s" , DC_CC_FS_FT },
958 {"cabs.f.s" , DC_CC_FS_FT }};
959
960 static const disasm_t disasm_cop1_c_un_s[2] DATASEG =
961 {{"c.un.s" , DC_CC_FS_FT },
962 {"cabs.un.s" , DC_CC_FS_FT }};
963
964 static const disasm_t disasm_cop1_c_eq_s[2] DATASEG =
965 {{"c.eq.s" , DC_CC_FS_FT },
966 {"cabs.eq.s" , DC_CC_FS_FT }};
967
968 static const disasm_t disasm_cop1_c_ueq_s[2] DATASEG =
969 {{"c.ueq.s" , DC_CC_FS_FT },
970 {"cabs.ueq.s" , DC_CC_FS_FT }};
971
972 static const disasm_t disasm_cop1_c_olt_s[2] DATASEG =
973 {{"c.olt.s" , DC_CC_FS_FT },
974 {"cabs.olt.s" , DC_CC_FS_FT }};
975
976 static const disasm_t disasm_cop1_c_ult_s[2] DATASEG =
977 {{"c.ult.s" , DC_CC_FS_FT },
978 {"cabs.ult.s" , DC_CC_FS_FT }};
979
980 static const disasm_t disasm_cop1_c_ole_s[2] DATASEG =
981 {{"c.ole.s" , DC_CC_FS_FT },
982 {"cabs.ole.s" , DC_CC_FS_FT }};
983
984 static const disasm_t disasm_cop1_c_ule_s[2] DATASEG =
985 {{"c.ule.s" , DC_CC_FS_FT },
986 {"cabs.ule.s" , DC_CC_FS_FT }};
987
988 static const disasm_t disasm_cop1_c_sf_s[2] DATASEG =
989 {{"c.sf.s" , DC_CC_FS_FT },
990 {"cabs.sf.s" , DC_CC_FS_FT }};
991
992 static const disasm_t disasm_cop1_c_ngle_s[2] DATASEG =
993 {{"c.ngle.s" , DC_CC_FS_FT },
994 {"cabs.ngle.s" , DC_CC_FS_FT }};
995
996 static const disasm_t disasm_cop1_c_seq_s[2] DATASEG =
997 {{"c.seq.s" , DC_CC_FS_FT },
998 {"cabs.seq.s" , DC_CC_FS_FT }};
999
1000 static const disasm_t disasm_cop1_c_ngl_s[2] DATASEG =
1001 {{"c.ngl.s" , DC_CC_FS_FT },
1002 {"cabs.ngl.s" , DC_CC_FS_FT }};
1003
1004 static const disasm_t disasm_cop1_c_lt_s[2] DATASEG =
1005 {{"c.lt.s" , DC_CC_FS_FT },
1006 {"cabs.lt.s" , DC_CC_FS_FT }};
1007
1008 static const disasm_t disasm_cop1_c_nge_s[2] DATASEG =
1009 {{"c.nge.s" , DC_CC_FS_FT },
1010 {"cabs.nge.s" , DC_CC_FS_FT }};
1011
1012 static const disasm_t disasm_cop1_c_le_s[2] DATASEG =
1013 {{"c.le.s" , DC_CC_FS_FT },
1014 {"cabs.le.s" , DC_CC_FS_FT }};
1015
1016 static const disasm_t disasm_cop1_c_ngt_s[2] DATASEG =
1017 {{"c.ngt.s" , DC_CC_FS_FT },
1018 {"cabs.ngt.s" , DC_CC_FS_FT }};
1019
1020 static const disasm_t disasm_cop1_c_f_d[2] DATASEG =
1021 {{"c.f.d" , DC_CC_FS_FT },
1022 {"cabs.f.d" , DC_CC_FS_FT }};
1023
1024 static const disasm_t disasm_cop1_c_un_d[2] DATASEG =
1025 {{"c.un.d" , DC_CC_FS_FT },
1026 {"cabs.un.d" , DC_CC_FS_FT }};
1027
1028 static const disasm_t disasm_cop1_c_eq_d[2] DATASEG =
1029 {{"c.eq.d" , DC_CC_FS_FT },
1030 {"cabs.eq.d" , DC_CC_FS_FT }};
1031
1032 static const disasm_t disasm_cop1_c_ueq_d[2] DATASEG =
1033 {{"c.ueq.d" , DC_CC_FS_FT },
1034 {"cabs.ueq.d" , DC_CC_FS_FT }};
1035
1036 static const disasm_t disasm_cop1_c_olt_d[2] DATASEG =
1037 {{"c.olt.d" , DC_CC_FS_FT },
1038 {"cabs.olt.d" , DC_CC_FS_FT }};
1039
1040 static const disasm_t disasm_cop1_c_ult_d[2] DATASEG =
1041 {{"c.ult.d" , DC_CC_FS_FT },
1042 {"cabs.ult.d" , DC_CC_FS_FT }};
1043
1044 static const disasm_t disasm_cop1_c_ole_d[2] DATASEG =
1045 {{"c.ole.d" , DC_CC_FS_FT },
1046 {"cabs.ole.d" , DC_CC_FS_FT }};
1047
1048 static const disasm_t disasm_cop1_c_ule_d[2] DATASEG =
1049 {{"c.ule.d" , DC_CC_FS_FT },
1050 {"cabs.ule.d" , DC_CC_FS_FT }};
1051
1052 static const disasm_t disasm_cop1_c_sf_d[2] DATASEG =
1053 {{"c.sf.d" , DC_CC_FS_FT },
1054 {"cabs.sf.d" , DC_CC_FS_FT }};
1055
1056 static const disasm_t disasm_cop1_c_ngle_d[2] DATASEG =
1057 {{"c.ngle.d" , DC_CC_FS_FT },
1058 {"cabs.ngle.d" , DC_CC_FS_FT }};
1059
1060 static const disasm_t disasm_cop1_c_seq_d[2] DATASEG =
1061 {{"c.seq.d" , DC_CC_FS_FT },
1062 {"cabs.seq.d" , DC_CC_FS_FT }};
1063
1064 static const disasm_t disasm_cop1_c_ngl_d[2] DATASEG =
1065 {{"c.ngl.d" , DC_CC_FS_FT },
1066 {"cabs.ngl.d" , DC_CC_FS_FT }};
1067
1068 static const disasm_t disasm_cop1_c_lt_d[2] DATASEG =
1069 {{"c.lt.d" , DC_CC_FS_FT },
1070 {"cabs.lt.d" , DC_CC_FS_FT }};
1071
1072 static const disasm_t disasm_cop1_c_nge_d[2] DATASEG =
1073 {{"c.nge.d" , DC_CC_FS_FT },
1074 {"cabs.nge.d" , DC_CC_FS_FT }};
1075
1076 static const disasm_t disasm_cop1_c_le_d[2] DATASEG =
1077 {{"c.le.d" , DC_CC_FS_FT },
1078 {"cabs.le.d" , DC_CC_FS_FT }};
1079
1080 static const disasm_t disasm_cop1_c_ngt_d[2] DATASEG =
1081 {{"c.ngt.d" , DC_CC_FS_FT },
1082 {"cabs.ngt.d" , DC_CC_FS_FT }};
1083
1084 static const disasm_t disasm_cop1_c_f_ps[2] DATASEG =
1085 {{"c.f.ps" , DC_CC_FS_FT },
1086 {"cabs.f.ps" , DC_CC_FS_FT }};
1087
1088 static const disasm_t disasm_cop1_c_un_ps[2] DATASEG =
1089 {{"c.un.ps" , DC_CC_FS_FT },
1090 {"cabs.un.ps" , DC_CC_FS_FT }};
1091
1092 static const disasm_t disasm_cop1_c_eq_ps[2] DATASEG =
1093 {{"c.eq.ps" , DC_CC_FS_FT },
1094 {"cabs.eq.ps" , DC_CC_FS_FT }};
1095
1096 static const disasm_t disasm_cop1_c_ueq_ps[2] DATASEG =
1097 {{"c.ueq.ps" , DC_CC_FS_FT },
1098 {"cabs.ueq.ps" , DC_CC_FS_FT }};
1099
1100 static const disasm_t disasm_cop1_c_olt_ps[2] DATASEG =
1101 {{"c.olt.ps" , DC_CC_FS_FT },
1102 {"cabs.olt.ps" , DC_CC_FS_FT }};
1103
1104 static const disasm_t disasm_cop1_c_ult_ps[2] DATASEG =
1105 {{"c.ult.ps" , DC_CC_FS_FT },
1106 {"cabs.ult.ps" , DC_CC_FS_FT }};
1107
1108 static const disasm_t disasm_cop1_c_ole_ps[2] DATASEG =
1109 {{"c.ole.ps" , DC_CC_FS_FT },
1110 {"cabs.ole.ps" , DC_CC_FS_FT }};
1111
1112 static const disasm_t disasm_cop1_c_ule_ps[2] DATASEG =
1113 {{"c.ule.ps" , DC_CC_FS_FT },
1114 {"cabs.ule.ps" , DC_CC_FS_FT }};
1115
1116 static const disasm_t disasm_cop1_c_sf_ps[2] DATASEG =
1117 {{"c.sf.ps" , DC_CC_FS_FT },
1118 {"cabs.sf.ps" , DC_CC_FS_FT }};
1119
1120 static const disasm_t disasm_cop1_c_ngle_ps[2] DATASEG =
1121 {{"c.ngle.ps" , DC_CC_FS_FT },
1122 {"cabs.ngle.ps" , DC_CC_FS_FT }};
1123
1124 static const disasm_t disasm_cop1_c_seq_ps[2] DATASEG =
1125 {{"c.seq.ps" , DC_CC_FS_FT },
1126 {"cabs.seq.ps" , DC_CC_FS_FT }};
1127
1128 static const disasm_t disasm_cop1_c_ngl_ps[2] DATASEG =
1129 {{"c.ngl.ps" , DC_CC_FS_FT },
1130 {"cabs.ngl.ps" , DC_CC_FS_FT }};
1131
1132 static const disasm_t disasm_cop1_c_lt_ps[2] DATASEG =
1133 {{"c.lt.ps" , DC_CC_FS_FT },
1134 {"cabs.lt.ps" , DC_CC_FS_FT }};
1135
1136 static const disasm_t disasm_cop1_c_nge_ps[2] DATASEG =
1137 {{"c.nge.ps" , DC_CC_FS_FT },
1138 {"cabs.nge.ps" , DC_CC_FS_FT }};
1139
1140 static const disasm_t disasm_cop1_c_le_ps[2] DATASEG =
1141 {{"c.le.ps" , DC_CC_FS_FT },
1142 {"cabs.le.ps" , DC_CC_FS_FT }};
1143
1144 static const disasm_t disasm_cop1_c_ngt_ps[2] DATASEG =
1145 {{"c.ngt.ps" , DC_CC_FS_FT },
1146 {"cabs.ngt.ps" , DC_CC_FS_FT }};
1147
1148 static const disasm_t disasm_cop1_ps_mvcf[2] DATASEG =
1149 {{"movf.ps" , DC_FD_FS_CC },
1150 {"movt.ps" , DC_FD_FS_CC }};
1151
1152 static const disasm_t disasm_cop1x[64] DATASEG =
1153 {{"lwxc1" , DC_FD_IDX_BASE },
1154 {"ldxc1" , DC_FD_IDX_BASE },
1155 {"invalid" , DC_BARE },
1156 {"invalid" , DC_BARE },
1157 {"invalid" , DC_BARE },
1158 {"luxc1" , DC_FD_IDX_BASE },
1159 {"invalid" , DC_BARE },
1160 {"invalid" , DC_BARE },
1161 {"swxc1" , DC_FS_IDX_BASE },
1162 {"sdxc1" , DC_FS_IDX_BASE },
1163 {"invalid" , DC_BARE },
1164 {"invalid" , DC_BARE },
1165 {"invalid" , DC_BARE },
1166 {"suxc1" , DC_FS_IDX_BASE },
1167 {"invalid" , DC_BARE },
1168 {"prefx" , DC_PREF_IDX },
1169 {"invalid" , DC_BARE },
1170 {"invalid" , DC_BARE },
1171 {"invalid" , DC_BARE },
1172 {"invalid" , DC_BARE },
1173 {"invalid" , DC_BARE },
1174 {"invalid" , DC_BARE },
1175 {"invalid" , DC_BARE },
1176 {"invalid" , DC_BARE },
1177 {"invalid" , DC_BARE },
1178 {"invalid" , DC_BARE },
1179 {"invalid" , DC_BARE },
1180 {"invalid" , DC_BARE },
1181 {"invalid" , DC_BARE },
1182 {"invalid" , DC_BARE },
1183 {"alnv.ps" , DC_FD_FS_FT_RS },
1184 {"invalid" , DC_BARE },
1185 {"madd.s" , DC_FD_FR_FS_FT },
1186 {"madd.d" , DC_FD_FR_FS_FT },
1187 {"invalid" , DC_BARE },
1188 {"invalid" , DC_BARE },
1189 {"invalid" , DC_BARE },
1190 {"invalid" , DC_BARE },
1191 {"madd.ps" , DC_FD_FR_FS_FT },
1192 {"invalid" , DC_BARE },
1193 {"msub.s" , DC_FD_FR_FS_FT },
1194 {"msub.d" , DC_FD_FR_FS_FT },
1195 {"invalid" , DC_BARE },
1196 {"invalid" , DC_BARE },
1197 {"invalid" , DC_BARE },
1198 {"invalid" , DC_BARE },
1199 {"msub.ps" , DC_FD_FR_FS_FT },
1200 {"invalid" , DC_BARE },
1201 {"nmadd.s" , DC_FD_FR_FS_FT },
1202 {"nmadd.d" , DC_FD_FR_FS_FT },
1203 {"invalid" , DC_BARE },
1204 {"invalid" , DC_BARE },
1205 {"invalid" , DC_BARE },
1206 {"invalid" , DC_BARE },
1207 {"nmadd.ps" , DC_FD_FR_FS_FT },
1208 {"invalid" , DC_BARE },
1209 {"nmsub.s" , DC_FD_FR_FS_FT },
1210 {"nmsub.d" , DC_FD_FR_FS_FT },
1211 {"invalid" , DC_BARE },
1212 {"invalid" , DC_BARE },
1213 {"invalid" , DC_BARE },
1214 {"invalid" , DC_BARE },
1215 {"nmsub.ps" , DC_FD_FR_FS_FT },
1216 {"invalid" , DC_BARE }};
1217
1218 static const disasm_t disasm_mdmx[8] DATASEG =
1219 {{ "$20" , DC_DEREF },
1220 { "$19" , DC_DEREF },
1221 { "$20" , DC_DEREF },
1222 { "$33" , DC_DEREF },
1223 { "$20" , DC_DEREF },
1224 { "$19" , DC_DEREF },
1225 { "$20" , DC_DEREF },
1226 { "$33" , DC_DEREF },
1227 };
1228
1229 static const disasm_t disasm_mdmx_qh[64] DATASEG =
1230 {{ "msgn.qh" , DC_VD_VS_VT_VEC},
1231 { "c.eq.qh" , DC_VS_VT_VEC },
1232 { "pickf.qh" , DC_VD_VS_VT_VEC},
1233 { "pickt.qh" , DC_VD_VS_VT_VEC},
1234 { "c.lt.qh" , DC_VS_VT_VEC },
1235 { "c.le.qh" , DC_VS_VT_VEC },
1236 { "min.qh" , DC_VD_VS_VT_VEC},
1237 { "max.qh" , DC_VD_VS_VT_VEC},
1238
1239 { "invalid" , DC_BARE },
1240 { "invalid" , DC_BARE },
1241 { "sub.qh" , DC_VD_VS_VT_VEC},
1242 { "add.qh" , DC_VD_VS_VT_VEC},
1243 { "and.qh" , DC_VD_VS_VT_VEC},
1244 { "xor.qh" , DC_VD_VS_VT_VEC},
1245 { "or.qh" , DC_VD_VS_VT_VEC},
1246 { "nor.qh" , DC_VD_VS_VT_VEC},
1247
1248 { "sll.qh" , DC_VD_VS_VT_VEC},
1249 { "invalid" , DC_BARE },
1250 { "srl.qh" , DC_VD_VS_VT_VEC},
1251 { "sra.qh" , DC_VD_VS_VT_VEC},
1252 { "invalid" , DC_BARE },
1253 { "invalid" , DC_BARE },
1254 { "invalid" , DC_BARE },
1255 { "invalid" , DC_BARE },
1256
1257 { "alni.ob" , DC_VD_VS_VT_IMM},
1258 { "alnv.ob" , DC_VD_VS_VT_RS },
1259 { "alni.qh" , DC_VD_VS_VT_IMM},
1260 { "alnv.qh" , DC_VD_VS_VT_RS },
1261 { "invalid" , DC_BARE },
1262 { "invalid" , DC_BARE },
1263 { "invalid" , DC_BARE },
1264 { "$34" , DC_DEREF },
1265
1266 { "rzu.qh" , DC_VD_VT },
1267 { "rnau.qh" , DC_VD_VT },
1268 { "rneu.qh" , DC_VD_VT },
1269 { "invalid" , DC_BARE },
1270 { "rzs.qh" , DC_VD_VT },
1271 { "rnas.qh" , DC_VD_VT },
1272 { "rnes.qh" , DC_VD_VT },
1273 { "invalid" , DC_BARE },
1274
1275 { "invalid" , DC_BARE },
1276 { "invalid" , DC_BARE },
1277 { "invalid" , DC_BARE },
1278 { "invalid" , DC_BARE },
1279 { "invalid" , DC_BARE },
1280 { "invalid" , DC_BARE },
1281 { "invalid" , DC_BARE },
1282 { "invalid" , DC_BARE },
1283
1284 { "mul.qh" , DC_VD_VS_VT_VEC},
1285 { "invalid" , DC_BARE },
1286 { "$21" , DC_DEREF },
1287 { "$22" , DC_DEREF },
1288 { "invalid" , DC_BARE },
1289 { "invalid" , DC_BARE },
1290 { "$23" , DC_DEREF },
1291 { "$24" , DC_DEREF },
1292
1293 { "invalid" , DC_BARE },
1294 { "invalid" , DC_BARE },
1295 { "invalid" , DC_BARE },
1296 { "invalid" , DC_BARE },
1297 { "invalid" , DC_BARE },
1298 { "invalid" , DC_BARE },
1299 { "$25" , DC_DEREF },
1300 { "$26" , DC_DEREF },
1301 };
1302
1303 static const disasm_t disasm_mdmx_ob[64] DATASEG =
1304 {{ "invalid" , DC_BARE },
1305 { "c.eq.ob" , DC_VS_VT_VEC },
1306 { "pickf.ob" , DC_VD_VS_VT_VEC},
1307 { "pickt.ob" , DC_VD_VS_VT_VEC},
1308 { "c.lt.ob" , DC_VS_VT_VEC },
1309 { "c.le.ob" , DC_VS_VT_VEC },
1310 { "min.ob" , DC_VD_VS_VT_VEC},
1311 { "max.ob" , DC_VD_VS_VT_VEC},
1312
1313 { "invalid" , DC_BARE },
1314 { "invalid" , DC_BARE },
1315 { "sub.ob" , DC_VD_VS_VT_VEC},
1316 { "add.ob" , DC_VD_VS_VT_VEC},
1317 { "and.ob" , DC_VD_VS_VT_VEC},
1318 { "xor.ob" , DC_VD_VS_VT_VEC},
1319 { "or.ob" , DC_VD_VS_VT_VEC},
1320 { "nor.ob" , DC_VD_VS_VT_VEC},
1321
1322 { "sll.ob" , DC_VD_VS_VT_VEC},
1323 { "invalid" , DC_BARE },
1324 { "srl.ob" , DC_VD_VS_VT_VEC},
1325 { "invalid" , DC_BARE },
1326 { "invalid" , DC_BARE },
1327 { "invalid" , DC_BARE },
1328 { "invalid" , DC_BARE },
1329 { "invalid" , DC_BARE },
1330
1331 { "alni.ob" , DC_VD_VS_VT_IMM},
1332 { "alnv.ob" , DC_VD_VS_VT_RS },
1333 { "alni.qh" , DC_VD_VS_VT_IMM},
1334 { "alnv.qh" , DC_VD_VS_VT_RS },
1335 { "invalid" , DC_BARE },
1336 { "invalid" , DC_BARE },
1337 { "invalid" , DC_BARE },
1338 { "$35" , DC_DEREF },
1339
1340 { "rzu.ob" , DC_VD_VT },
1341 { "rnau.ob" , DC_VD_VT },
1342 { "rneu.ob" , DC_VD_VT },
1343 { "invalid" , DC_BARE },
1344 { "invalid" , DC_BARE },
1345 { "invalid" , DC_BARE },
1346 { "invalid" , DC_BARE },
1347 { "invalid" , DC_BARE },
1348
1349 { "invalid" , DC_BARE },
1350 { "invalid" , DC_BARE },
1351 { "invalid" , DC_BARE },
1352 { "invalid" , DC_BARE },
1353 { "invalid" , DC_BARE },
1354 { "invalid" , DC_BARE },
1355 { "invalid" , DC_BARE },
1356 { "invalid" , DC_BARE },
1357
1358 { "mul.ob" , DC_VD_VS_VT_VEC},
1359 { "invalid" , DC_BARE },
1360 { "$27" , DC_DEREF },
1361 { "$28" , DC_DEREF },
1362 { "invalid" , DC_BARE },
1363 { "invalid" , DC_BARE },
1364 { "$29" , DC_DEREF },
1365 { "$30" , DC_DEREF },
1366
1367 { "invalid" , DC_BARE },
1368 { "invalid" , DC_BARE },
1369 { "invalid" , DC_BARE },
1370 { "invalid" , DC_BARE },
1371 { "invalid" , DC_BARE },
1372 { "invalid" , DC_BARE },
1373 { "$31" , DC_DEREF },
1374 { "$32" , DC_DEREF },
1375 };
1376
1377 static const disasm_t disasm_mdmx_alni[64] DATASEG =
1378 {{ "invalid" , DC_BARE },
1379 { "invalid" , DC_BARE },
1380 { "invalid" , DC_BARE },
1381 { "invalid" , DC_BARE },
1382 { "invalid" , DC_BARE },
1383 { "invalid" , DC_BARE },
1384 { "invalid" , DC_BARE },
1385 { "invalid" , DC_BARE },
1386
1387 { "invalid" , DC_BARE },
1388 { "invalid" , DC_BARE },
1389 { "invalid" , DC_BARE },
1390 { "invalid" , DC_BARE },
1391 { "invalid" , DC_BARE },
1392 { "invalid" , DC_BARE },
1393 { "invalid" , DC_BARE },
1394 { "invalid" , DC_BARE },
1395
1396 { "invalid" , DC_BARE },
1397 { "invalid" , DC_BARE },
1398 { "invalid" , DC_BARE },
1399 { "invalid" , DC_BARE },
1400 { "invalid" , DC_BARE },
1401 { "invalid" , DC_BARE },
1402 { "invalid" , DC_BARE },
1403 { "invalid" , DC_BARE },
1404
1405 { "alni.ob" , DC_VD_VS_VT_IMM},
1406 { "alnv.ob" , DC_VD_VS_VT_RS },
1407 { "alni.qh" , DC_VD_VS_VT_IMM},
1408 { "alnv.qh" , DC_VD_VS_VT_RS },
1409 { "invalid" , DC_BARE },
1410 { "invalid" , DC_BARE },
1411 { "invalid" , DC_BARE },
1412 { "invalid" , DC_BARE },
1413
1414 { "invalid" , DC_BARE },
1415 { "invalid" , DC_BARE },
1416 { "invalid" , DC_BARE },
1417 { "invalid" , DC_BARE },
1418 { "invalid" , DC_BARE },
1419 { "invalid" , DC_BARE },
1420 { "invalid" , DC_BARE },
1421 { "invalid" , DC_BARE },
1422
1423 { "invalid" , DC_BARE },
1424 { "invalid" , DC_BARE },
1425 { "invalid" , DC_BARE },
1426 { "invalid" , DC_BARE },
1427 { "invalid" , DC_BARE },
1428 { "invalid" , DC_BARE },
1429 { "invalid" , DC_BARE },
1430 { "invalid" , DC_BARE },
1431
1432 { "invalid" , DC_BARE },
1433 { "invalid" , DC_BARE },
1434 { "invalid" , DC_BARE },
1435 { "invalid" , DC_BARE },
1436 { "invalid" , DC_BARE },
1437 { "invalid" , DC_BARE },
1438 { "invalid" , DC_BARE },
1439 { "invalid" , DC_BARE },
1440
1441 { "invalid" , DC_BARE },
1442 { "invalid" , DC_BARE },
1443 { "invalid" , DC_BARE },
1444 { "invalid" , DC_BARE },
1445 { "invalid" , DC_BARE },
1446 { "invalid" , DC_BARE },
1447 { "invalid" , DC_BARE },
1448 { "invalid" , DC_BARE },
1449 };
1450
1451 static const disasm_t disasm_mdmx_muls_qh[2] DATASEG =
1452 {{ "muls.qh" , DC_VS_VT_VEC },
1453 { "mulsl.qh" , DC_VS_VT_VEC },
1454 };
1455
1456 static const disasm_t disasm_mdmx_mul_qh[2] DATASEG =
1457 {{ "mula.qh" , DC_VS_VT_VEC },
1458 { "mull.qh" , DC_VS_VT_VEC },
1459 };
1460
1461 static const disasm_t disasm_mdmx_sub_qh[2] DATASEG =
1462 {{ "suba.qh" , DC_VS_VT_VEC },
1463 { "subl.qh" , DC_VS_VT_VEC },
1464 };
1465
1466 static const disasm_t disasm_mdmx_add_qh[2] DATASEG =
1467 {{ "adda.qh" , DC_VS_VT_VEC },
1468 { "addl.qh" , DC_VS_VT_VEC },
1469 };
1470
1471 static const disasm_t disasm_mdmx_wac_qh[4] DATASEG =
1472 {{ "wacl.qh" , DC_VS_VT },
1473 { "invalid" , DC_BARE },
1474 { "wach.qh" , DC_VS },
1475 { "invalid" , DC_BARE },
1476 };
1477
1478 static const disasm_t disasm_mdmx_rac_qh[4] DATASEG =
1479 {{ "racl.qh" , DC_VD },
1480 { "racm.qh" , DC_VD },
1481 { "rach.qh" , DC_VD },
1482 { "invalid" , DC_BARE },
1483 };
1484
1485 static const disasm_t disasm_mdmx_muls_ob[2] DATASEG =
1486 {{ "muls.ob" , DC_VS_VT_VEC },
1487 { "mulsl.ob" , DC_VS_VT_VEC },
1488 };
1489
1490 static const disasm_t disasm_mdmx_mul_ob[2] DATASEG =
1491 {{ "mula.ob" , DC_VS_VT_VEC },
1492 { "mull.ob" , DC_VS_VT_VEC },
1493 };
1494
1495 static const disasm_t disasm_mdmx_sub_ob[2] DATASEG =
1496 {{ "suba.ob" , DC_VS_VT_VEC },
1497 { "subl.ob" , DC_VS_VT_VEC },
1498 };
1499
1500 static const disasm_t disasm_mdmx_add_ob[2] DATASEG =
1501 {{ "adda.ob" , DC_VS_VT_VEC },
1502 { "addl.ob" , DC_VS_VT_VEC },
1503 };
1504
1505 static const disasm_t disasm_mdmx_wac_ob[4] DATASEG =
1506 {{ "wacl.ob" , DC_VS_VT },
1507 { "invalid" , DC_BARE },
1508 { "wach.ob" , DC_VS },
1509 { "invalid" , DC_BARE },
1510 };
1511
1512 static const disasm_t disasm_mdmx_rac_ob[4] DATASEG =
1513 {{ "racl.ob" , DC_VD },
1514 { "racm.ob" , DC_VD },
1515 { "rach.ob" , DC_VD },
1516 { "invalid" , DC_BARE },
1517 };
1518
1519 static const disasm_t disasm_mdmx_shfl_ob[16] DATASEG =
1520 {{ "shfl.upsl.ob" , DC_VD_VS_VT },
1521 { "shfl.pach.ob" , DC_VD_VS_VT },
1522 { "shfl.mixh.ob" , DC_VD_VS_VT },
1523 { "shfl.mixl.ob" , DC_VD_VS_VT },
1524 { "invalid" , DC_BARE },
1525 { "invalid" , DC_BARE },
1526 { "invalid" , DC_BARE },
1527 { "invalid" , DC_BARE },
1528 { "invalid" , DC_BARE },
1529 { "invalid" , DC_BARE },
1530 { "invalid" , DC_BARE },
1531 { "invalid" , DC_BARE },
1532 { "invalid" , DC_BARE },
1533 { "invalid" , DC_BARE },
1534 { "invalid" , DC_BARE },
1535 { "invalid" , DC_BARE },
1536 };
1537
1538 static const disasm_t disasm_mdmx_shfl_qh[8] DATASEG =
1539 {{ "shfl.bfla.qh" , DC_VD_VS_VT },
1540 { "shfl.pach.qh" , DC_VD_VS_VT },
1541 { "shfl.mixh.qh" , DC_VD_VS_VT },
1542 { "shfl.mixl.qh" , DC_VD_VS_VT },
1543 { "shfl.repa.qh" , DC_VD_VS_VT },
1544 { "shfl.repb.qh" , DC_VD_VS_VT },
1545 { "invalid" , DC_BARE },
1546 { "invalid" , DC_BARE },
1547 };
1548
1549
1550
1551 const disasm_deref_t disasm_deref[] =
1552 /* Disasm array shft msk */
1553 {{ disasm_normal , 26, 0x3f }, /* 0 */
1554 { disasm_special , 0, 0x3f }, /* 1 */
1555 { disasm_regimm , 16, 0x1f }, /* 2 */
1556 { disasm_spec2 , 0, 0x3f }, /* 3 */
1557 { disasm_cop0 , 21, 0x1f }, /* 4 */
1558 { disasm_cop0_c0 , 0, 0x3f }, /* 5 */
1559 { disasm_cop1 , 21, 0x1f }, /* 6 */
1560 { disasm_cop1_s , 0, 0x3f }, /* 7 */
1561 { disasm_cop1_s_mvcf , 16, 0x1 }, /* 8 */
1562 { disasm_cop1_d , 0, 0x3f }, /* 9 */
1563 { disasm_cop1_d_mvcf , 16, 0x1 }, /* 10 */
1564 { disasm_cop1_w , 0, 0x3f }, /* 11 */
1565 { disasm_cop1_l , 0, 0x3f }, /* 12 */
1566 { disasm_cop1_ps , 0, 0x3f }, /* 13 */
1567 { disasm_cop1_ps_mvcf, 16, 0x1 }, /* 14 */
1568 { disasm_cop1x , 0, 0x3f }, /* 15 */
1569 { disasm_movci , 16, 0x1 }, /* 16 */
1570 { disasm_cop1_bc1 , 16, 0x3 }, /* 17 */
1571 { disasm_mdmx , 21, 0x7 }, /* 18 */
1572 { disasm_mdmx_qh , 0, 0x3f }, /* 19 */
1573 { disasm_mdmx_ob , 0, 0x3f }, /* 20 */
1574 { disasm_mdmx_muls_qh, 10, 0x1 }, /* 21 */
1575 { disasm_mdmx_mul_qh , 10, 0x1 }, /* 22 */
1576 { disasm_mdmx_sub_qh , 10, 0x1 }, /* 23 */
1577 { disasm_mdmx_add_qh , 10, 0x1 }, /* 24 */
1578 { disasm_mdmx_wac_qh , 24, 0x3 }, /* 25 */
1579 { disasm_mdmx_rac_qh , 24, 0x3 }, /* 26 */
1580 { disasm_mdmx_muls_ob, 10, 0x1 }, /* 27 */
1581 { disasm_mdmx_mul_ob , 10, 0x1 }, /* 28 */
1582 { disasm_mdmx_sub_ob , 10, 0x1 }, /* 29 */
1583 { disasm_mdmx_add_ob , 10, 0x1 }, /* 30 */
1584 { disasm_mdmx_wac_ob , 24, 0x3 }, /* 31 */
1585 { disasm_mdmx_rac_ob , 24, 0x3 }, /* 32 */
1586 { disasm_mdmx_alni , 0, 0x3f }, /* 33 */
1587 { disasm_mdmx_shfl_ob, 22, 0xf }, /* 34 */
1588 { disasm_mdmx_shfl_qh, 23, 0x7 }, /* 35 */
1589 { disasm_cop1_bc1any2, 16, 0x1 }, /* 36 */
1590 { disasm_cop1_bc1any4, 16, 0x1 }, /* 37 */
1591 { disasm_cop1_c_f_s , 6, 0x1 }, /* 38 */
1592 { disasm_cop1_c_un_s , 6, 0x1 }, /* 39 */
1593 { disasm_cop1_c_eq_s , 6, 0x1 }, /* 40 */
1594 { disasm_cop1_c_ueq_s, 6, 0x1 }, /* 41 */
1595 { disasm_cop1_c_olt_s, 6, 0x1 }, /* 42 */
1596 { disasm_cop1_c_ult_s, 6, 0x1 }, /* 43 */
1597 { disasm_cop1_c_ole_s, 6, 0x1 }, /* 44 */
1598 { disasm_cop1_c_ule_s, 6, 0x1 }, /* 45 */
1599 { disasm_cop1_c_sf_s , 6, 0x1 }, /* 46 */
1600 { disasm_cop1_c_ngle_s, 6, 0x1 }, /* 47 */
1601 { disasm_cop1_c_seq_s, 6, 0x1 }, /* 48 */
1602 { disasm_cop1_c_ngl_s, 6, 0x1 }, /* 49 */
1603 { disasm_cop1_c_lt_s , 6, 0x1 }, /* 50 */
1604 { disasm_cop1_c_nge_s, 6, 0x1 }, /* 51 */
1605 { disasm_cop1_c_le_s , 6, 0x1 }, /* 52 */
1606 { disasm_cop1_c_ngt_s, 6, 0x1 }, /* 53 */
1607 { disasm_cop1_c_f_d , 6, 0x1 }, /* 54 */
1608 { disasm_cop1_c_un_d , 6, 0x1 }, /* 55 */
1609 { disasm_cop1_c_eq_d , 6, 0x1 }, /* 56 */
1610 { disasm_cop1_c_ueq_d, 6, 0x1 }, /* 57 */
1611 { disasm_cop1_c_olt_d, 6, 0x1 }, /* 58 */
1612 { disasm_cop1_c_ult_d, 6, 0x1 }, /* 59 */
1613 { disasm_cop1_c_ole_d, 6, 0x1 }, /* 60 */
1614 { disasm_cop1_c_ule_d, 6, 0x1 }, /* 61 */
1615 { disasm_cop1_c_sf_d , 6, 0x1 }, /* 62 */
1616 { disasm_cop1_c_ngle_d, 6, 0x1 }, /* 63 */
1617 { disasm_cop1_c_seq_d, 6, 0x1 }, /* 64 */
1618 { disasm_cop1_c_ngl_d, 6, 0x1 }, /* 65 */
1619 { disasm_cop1_c_lt_d , 6, 0x1 }, /* 66 */
1620 { disasm_cop1_c_nge_d, 6, 0x1 }, /* 67 */
1621 { disasm_cop1_c_le_d , 6, 0x1 }, /* 68 */
1622 { disasm_cop1_c_ngt_d, 6, 0x1 }, /* 69 */
1623 { disasm_cop1_c_f_ps , 6, 0x1 }, /* 70 */
1624 { disasm_cop1_c_un_ps, 6, 0x1 }, /* 71 */
1625 { disasm_cop1_c_eq_ps, 6, 0x1 }, /* 72 */
1626 { disasm_cop1_c_ueq_ps, 6, 0x1 }, /* 73 */
1627 { disasm_cop1_c_olt_ps, 6, 0x1 }, /* 74 */
1628 { disasm_cop1_c_ult_ps, 6, 0x1 }, /* 75 */
1629 { disasm_cop1_c_ole_ps, 6, 0x1 }, /* 76 */
1630 { disasm_cop1_c_ule_ps, 6, 0x1 }, /* 77 */
1631 { disasm_cop1_c_sf_ps, 6, 0x1 }, /* 78 */
1632 { disasm_cop1_c_ngle_ps, 6, 0x1 }, /* 79 */
1633 { disasm_cop1_c_seq_ps, 6, 0x1 }, /* 80 */
1634 { disasm_cop1_c_ngl_ps, 6, 0x1 }, /* 81 */
1635 { disasm_cop1_c_lt_ps, 6, 0x1 }, /* 82 */
1636 { disasm_cop1_c_nge_ps, 6, 0x1 }, /* 83 */
1637 { disasm_cop1_c_le_ps, 6, 0x1 }, /* 84 */
1638 { disasm_cop1_c_ngt_ps, 6, 0x1 }, /* 85 */
1639 };
1640
1641 #define PREFHINT(x) (&pref_hints[(x)*9])
1642 static char *pref_hints =
1643 "load \0"
1644 "store \0"
1645 "reserved\0"
1646 "reserved\0"
1647
1648 "ld_strm \0"
1649 "st_strm \0"
1650 "ld_retn \0"
1651 "st_retn \0"
1652
1653 "reserved\0"
1654 "reserved\0"
1655 "reserved\0"
1656 "reserved\0"
1657
1658 "reserved\0"
1659 "reserved\0"
1660 "reserved\0"
1661 "reserved\0"
1662
1663 "reserved\0"
1664 "reserved\0"
1665 "reserved\0"
1666 "reserved\0"
1667
1668 "reserved\0"
1669 "reserved\0"
1670 "reserved\0"
1671 "reserved\0"
1672
1673 "reserved\0"
1674 "wb_inval\0"
1675 "reserved\0"
1676 "reserved\0"
1677
1678 "reserved\0"
1679 "reserved\0"
1680 "reserved\0"
1681 "reserved\0";
1682
1683
1684 static int snprintf(char *buf,int len,const char *templat,...)
1685 {
1686 va_list marker;
1687 int count;
1688
1689 va_start(marker,templat);
1690 count = xvsprintf(buf,templat,marker);
1691 va_end(marker);
1692
1693 return count;
1694 }
1695
1696 static const disasm_t *get_disasm_field(uint32_t inst)
1697 {
1698 const disasm_deref_t *tmp = &disasm_deref[0];
1699 const disasm_t *rec;
1700 do {
1701 rec = &(tmp->ptr[(inst>>tmp->shift) & tmp->mask]);
1702 tmp = &disasm_deref[atoi(&(rec->name[1]))];
1703 } while (rec->type == DC_DEREF);
1704 return rec;
1705 }
1706
1707 char *disasm_inst_name(uint32_t inst)
1708 {
1709 return (char *)(get_disasm_field(inst)->name);
1710 }
1711
1712 void disasm_inst(char *buf, int buf_size, uint32_t inst, uint64_t pc)
1713 {
1714 const disasm_t *tmp;
1715 char instname[32];
1716 int commentmode = 0;
1717 char *x;
1718
1719 tmp = get_disasm_field(inst);
1720
1721 strcpy(instname,(char *) tmp->name);
1722
1723 if ((x = strchr(instname,'@'))) {
1724 *x++ = 0;
1725 commentmode = atoi(x);
1726 }
1727
1728 switch (tmp->type) {
1729 case DC_RD_RS_RT:
1730 snprintf(buf, buf_size, "%-8s %s,%s,%s",
1731 instname,
1732 REGNAME((inst>>11) & 0x1f),
1733 REGNAME((inst>>21) & 0x1f),
1734 REGNAME((inst>>16) & 0x1f));
1735 break;
1736 case DC_RD_RT_RS:
1737 snprintf(buf, buf_size, "%-8s %s,%s,%s",
1738 instname,
1739 REGNAME((inst>>11) & 0x1f),
1740 REGNAME((inst>>16) & 0x1f),
1741 REGNAME((inst>>21) & 0x1f));
1742 break;
1743 case DC_RT_RS_SIMM:
1744 snprintf(buf, buf_size, "%-8s %s,%s,#%" PF_32 "d",
1745 instname,
1746 REGNAME((inst>>16) & 0x1f),
1747 REGNAME((inst>>21) & 0x1f),
1748 SEXT_32(15, inst & 0xffff));
1749 break;
1750 case DC_RT_RS_XIMM:
1751 snprintf(buf, buf_size, "%-8s %s,%s,#0x%" PF_32 "x",
1752 instname,
1753 REGNAME((inst>>16) & 0x1f),
1754 REGNAME((inst>>21) & 0x1f),
1755 inst & 0xffff);
1756 break;
1757 case DC_RS_RT_OFS:
1758 snprintf(buf, buf_size, "%-8s %s,%s,0x%" PF_64 "x",
1759 instname,
1760 REGNAME((inst>>21) & 0x1f),
1761 REGNAME((inst>>16) & 0x1f),
1762 pc + 4 + (SEXT_64(15, inst & 0xffff)<<2));
1763 break;
1764 case DC_RS_OFS:
1765 snprintf(buf, buf_size, "%-8s %s,0x%" PF_64 "x",
1766 instname,
1767 REGNAME((inst>>21) & 0x1f),
1768 pc + 4 + (SEXT_64(16, inst & 0xffff)<<2));
1769 break;
1770 case DC_RD_RT_SA:
1771 snprintf(buf, buf_size, "%-8s %s,%s,#%d",
1772 instname,
1773 REGNAME((inst>>11) & 0x1f),
1774 REGNAME((inst>>16) & 0x1f),
1775 (inst>>6) & 0x1f);
1776 break;
1777 case DC_RT_UIMM:
1778 snprintf(buf, buf_size, "%-8s %s,#%d",
1779 instname,
1780 REGNAME((inst>>16) & 0x1f),
1781 inst & 0xffff);
1782 break;
1783 case DC_RD:
1784 snprintf(buf, buf_size, "%-8s %s",
1785 instname,
1786 REGNAME((inst>>11) & 0x1f));
1787 break;
1788 case DC_J:
1789 snprintf(buf, buf_size, "%-8s 0x%" PF_64 "x",
1790 instname,
1791 (pc & UINT64_T(0xfffffffff0000000)) | ((inst & 0x3ffffff)<<2));
1792 break;
1793 case DC_RD_RS:
1794 snprintf(buf, buf_size, "%-8s %s,%s",
1795 instname,
1796 REGNAME((inst>>11) & 0x1f),
1797 REGNAME((inst>>21) & 0x1f));
1798 break;
1799 case DC_RS_RT:
1800 snprintf(buf, buf_size, "%-8s %s,%s",
1801 instname,
1802 REGNAME((inst>>21) & 0x1f),
1803 REGNAME((inst>>16) & 0x1f));
1804 break;
1805 case DC_RT_RS:
1806 snprintf(buf, buf_size, "%-8s %s,%s",
1807 instname,
1808 REGNAME((inst>>16) & 0x1f),
1809 REGNAME((inst>>21) & 0x1f));
1810 break;
1811 case DC_RT_RD_SEL:
1812 snprintf(buf, buf_size, "%-8s %s,%s,#%d",
1813 instname,
1814 REGNAME((inst>>16) & 0x1f),
1815 REGNAME((inst>>11) & 0x1f),
1816 inst & 0x3);
1817 break;
1818 case DC_RT_CR_SEL:
1819 snprintf(buf, buf_size, "%-8s %s,%d,#%d",
1820 instname,
1821 REGNAME((inst>>16) & 0x1f),
1822 (inst>>11) & 0x1f,
1823 inst & 0x3);
1824 break;
1825 case DC_RS:
1826 snprintf(buf, buf_size, "%-8s %s",
1827 instname,
1828 REGNAME((inst>>21) & 0x1f));
1829 break;
1830 case DC_RS_SIMM:
1831 snprintf(buf, buf_size, "%-8s %s,#%" PF_32 "d",
1832 instname,
1833 REGNAME((inst>>21) & 0x1f),
1834 SEXT_32(15, inst & 0xffff));
1835 break;
1836 case DC_RT_OFS_BASE:
1837 snprintf(buf, buf_size, "%-8s %s,#%" PF_32 "d(%s)",
1838 instname,
1839 REGNAME((inst>>16) & 0x1f),
1840 SEXT_32(15, inst),
1841 REGNAME((inst>>21) & 0x1f));
1842 break;
1843 case DC_FT_OFS_BASE:
1844 snprintf(buf, buf_size, "%-8s f%d,#%" PF_32 "d(%s)",
1845 instname,
1846 (inst>>16) & 0x1f,
1847 SEXT_32(15, inst),
1848 REGNAME((inst>>21) & 0x1f));
1849 break;
1850 case DC_FD_IDX_BASE:
1851 snprintf(buf, buf_size, "%-8s f%d,%s(%s)",
1852 instname,
1853 (inst>>6) & 0x1f,
1854 REGNAME((inst>>16) & 0x1f),
1855 REGNAME((inst>>21) & 0x1f));
1856 break;
1857 case DC_FS_IDX_BASE:
1858 snprintf(buf, buf_size, "%-8s f%d,%s(%s)",
1859 instname,
1860 (inst>>11) & 0x1f,
1861 REGNAME((inst>>16) & 0x1f),
1862 REGNAME((inst>>21) & 0x1f));
1863 break;
1864 case DC_FD_FS_FT:
1865 snprintf(buf, buf_size, "%-8s f%d,f%d,f%d",
1866 instname,
1867 (inst>>6) & 0x1f,
1868 (inst>>11) & 0x1f,
1869 (inst>>16) & 0x1f);
1870 break;
1871 case DC_FD_FS_RT:
1872 snprintf(buf, buf_size, "%-8s f%d,f%d,%s",
1873 instname,
1874 (inst>>6) & 0x1f,
1875 (inst>>11) & 0x1f,
1876 REGNAME((inst>>16) & 0x1f));
1877 break;
1878 case DC_FD_FS:
1879 snprintf(buf, buf_size, "%-8s f%d,f%d",
1880 instname,
1881 (inst>>6)&0x1f,
1882 (inst>>11)&0x1f);
1883 break;
1884 case DC_PREF_OFS:
1885 snprintf(buf, buf_size, "%-8s #%" PF_32 "d(%s) /* %s */",
1886 instname,
1887 SEXT_32(15, inst & 0xffff),
1888 REGNAME((inst>>21) & 0x1f),
1889 PREFHINT((inst>>16) & 0x1f));
1890 break;
1891 case DC_PREF_IDX:
1892 snprintf(buf, buf_size, "%-8s %s(%s) /* %s */",
1893 instname,
1894 REGNAME((inst>>16) & 0x1f),
1895 REGNAME((inst>>21) & 0x1f),
1896 PREFHINT((inst>>16) & 0x1f));
1897 break;
1898 case DC_CC_OFS:
1899 snprintf(buf, buf_size, "%-8s %d,0x%" PF_64 "x",
1900 instname,
1901 (inst>>18) & 0x7,
1902 pc + 4 + (SEXT_64(15, inst & 0xffff)<<2));
1903 break;
1904 case DC_RD_RS_CC:
1905 snprintf(buf, buf_size, "%-8s %s,%s,%d",
1906 instname,
1907 REGNAME((inst>>11) & 0x1f),
1908 REGNAME((inst>>21) & 0x1f),
1909 (inst>>18) & 0x7);
1910 break;
1911 case DC_FD_FS_CC:
1912 snprintf(buf, buf_size, "%-8s f%d,f%d,%d",
1913 instname,
1914 (inst>>6) & 0x1f,
1915 (inst>>11) & 0x1f,
1916 (inst>>18) & 0x7);
1917 break;
1918 case DC_FD_FR_FS_FT:
1919 snprintf(buf, buf_size, "%-8s f%d,f%d,f%d,f%d",
1920 instname,
1921 (inst>>6) & 0x1f,
1922 (inst>>21) & 0x1f,
1923 (inst>>11) & 0x1f,
1924 (inst>>16) & 0x1f);
1925 break;
1926 case DC_FD_FS_FT_RS:
1927 snprintf(buf, buf_size, "%-8s f%d,f%d,f%d,%s",
1928 instname,
1929 (inst>>6) & 0x1f,
1930 (inst>>11) & 0x1f,
1931 (inst>>16) & 0x1f,
1932 REGNAME((inst>>21) & 0x1f));
1933 break;
1934 case DC_CC_FS_FT:
1935 snprintf(buf, buf_size, "%-8s %d,f%d,f%d",
1936 instname,
1937 (inst>>8) & 0x7,
1938 (inst>>11) & 0x1f,
1939 (inst>>16) & 0x1f);
1940 break;
1941 case DC_BARE:
1942 snprintf(buf, buf_size, "%-8s", instname);
1943 break;
1944 case DC_RT_FS:
1945 snprintf(buf, buf_size, "%-8s %s,f%d",
1946 instname,
1947 REGNAME((inst>>16) & 0x1f),
1948 (inst>>11) & 0x1f);
1949 break;
1950 case DC_VS:
1951 snprintf(buf, buf_size, "%-8s $v%d",
1952 instname,
1953 (inst>>11) & 0x1f);
1954 break;
1955 case DC_VD:
1956 snprintf(buf, buf_size, "%-8s $v%d",
1957 instname,
1958 (inst>>6) & 0x1f);
1959 break;
1960 case DC_VD_VT:
1961 snprintf(buf, buf_size, "%-8s $v%d,$v%d",
1962 instname,
1963 (inst>>6) & 0x1f,
1964 (inst>>16) & 0x1f);
1965 break;
1966 case DC_VD_VS_VT_IMM:
1967 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d,#%d",
1968 instname,
1969 (inst>>6) & 0x1f,
1970 (inst>>11) & 0x1f,
1971 (inst>>16) & 0x1f,
1972 (inst>>21) & 0x7);
1973 break;
1974 case DC_VD_VS_VT_RS:
1975 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d,%s",
1976 instname,
1977 (inst>>6) & 0x1f,
1978 (inst>>11) & 0x1f,
1979 (inst>>16) & 0x1f,
1980 REGNAME((inst>>21) & 0x1f));
1981 break;
1982 case DC_VD_VS_VT:
1983 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d",
1984 instname,
1985 (inst>>6) & 0x1f,
1986 (inst>>11) & 0x1f,
1987 (inst>>16) & 0x1f);
1988 break;
1989 case DC_VS_VT:
1990 snprintf(buf, buf_size, "%-8s $v%d,$v%d",
1991 instname,
1992 (inst>>11) & 0x1f,
1993 (inst>>16) & 0x1f);
1994 break;
1995 case DC_VS_VT_VEC:
1996 switch((inst>>24) & 0x3) {
1997 case 0:
1998 case 1:
1999 /* element select */
2000 if ((inst>>21) & 1) {
2001 /* QH */
2002 snprintf(buf, buf_size, "%-8s $v%d,$v%d[%d]",
2003 instname,
2004 (inst>>11) & 0x1f,
2005 (inst>>16) & 0x1f,
2006 (inst>>23) & 0x3);
2007 } else {
2008 /* OB */
2009 snprintf(buf, buf_size, "%-8s $v%d,$v%d[%d]",
2010 instname,
2011 (inst>>11) & 0x1f,
2012 (inst>>16) & 0x1f,
2013 (inst>>22) & 0x7);
2014
2015 }
2016 break;
2017 case 2:
2018 /* Vector select */
2019 snprintf(buf, buf_size, "%-8s $v%d,$v%d",
2020 instname,
2021 (inst>>11) & 0x1f,
2022 (inst>>16) & 0x1f);
2023 break;
2024 case 3:
2025 /* immediate select */
2026 snprintf(buf, buf_size, "%-8s $v%d,$#%d",
2027 instname,
2028 (inst>>11) & 0x1f,
2029 (inst>>16) & 0x1f);
2030 break;
2031 }
2032 break;
2033
2034 case DC_VD_VS_VT_VEC:
2035 switch((inst>>24) & 0x3) {
2036 case 0:
2037 case 1:
2038 /* element select */
2039 if ((inst>>21) & 1) {
2040 /* QH */
2041 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d[%d]",
2042 instname,
2043 (inst>>6) & 0x1f,
2044 (inst>>11) & 0x1f,
2045 (inst>>16) & 0x1f,
2046 (inst>>23) & 0x3);
2047 } else {
2048 /* OB */
2049 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d[%d]",
2050 instname,
2051 (inst>>6) & 0x1f,
2052 (inst>>11) & 0x1f,
2053 (inst>>16) & 0x1f,
2054 (inst>>22) & 0x7);
2055
2056 }
2057 break;
2058 case 2:
2059 /* Vector select */
2060 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$v%d",
2061 instname,
2062 (inst>>6) & 0x1f,
2063 (inst>>11) & 0x1f,
2064 (inst>>16) & 0x1f);
2065 break;
2066 case 3:
2067 /* immediate select */
2068 snprintf(buf, buf_size, "%-8s $v%d,$v%d,$#%d",
2069 instname,
2070 (inst>>6) & 0x1f,
2071 (inst>>11) & 0x1f,
2072 (inst>>16) & 0x1f);
2073 break;
2074 }
2075 break;
2076
2077 case DC_SYSCALL:
2078 snprintf(buf, buf_size, "%-8s #%d",
2079 instname,
2080 (inst>>6) & 0xfffff);
2081 break;
2082 case DC_BREAK:
2083 snprintf(buf, buf_size, "%-8s %d", instname, (inst>>6)&0xfffff);
2084 break;
2085 case DC_OOPS:
2086 snprintf(buf, buf_size, "%s OOPS! FIXME!", instname);
2087 break;
2088 default:
2089 /* Hit something we don't know about...Shouldn't happen. */
2090 break;
2091 }
2092
2093 /*
2094 * Handle comment field
2095 */
2096
2097
2098 switch (commentmode) {
2099 case 1: /* CP0 ops */
2100 if ((inst & 3) == 0) { /* select 0 */
2101 snprintf(buf + strlen(buf),buf_size-strlen(buf)," /* %s */",
2102 CP0REGNAME((inst >> 11) & 0x1f));
2103 }
2104 break;
2105 default:
2106 break;
2107 }
2108
2109 buf[buf_size-1] = 0;
2110
2111 }
Tomato firmware and modifications.