1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * Board-specific initialization File: PT1120_INIT.S
6 * This module contains the assembly-language part of the init
7 * code for this board support package. The routine
8 * "board_earlyinit" lives here.
10 * Author: Mitch Lichtenberg (mpl@broadcom.com)
12 * modification history
13 * --------------------
14 * 01a,27jun02,gtb Ported from ptswarm_init.S.
16 *********************************************************************
19 * Broadcom Corporation. All rights reserved.
21 * This software is furnished under license and may be used and
22 * copied only in accordance with the following terms and
23 * conditions. Subject to these conditions, you may download,
24 * copy, install, use, modify and distribute modified or unmodified
25 * copies of this software in source and/or binary form. No title
26 * or ownership is transferred hereby.
28 * 1) Any source code used, modified or distributed must reproduce
29 * and retain this copyright notice and list of conditions as
30 * they appear in the source file.
32 * 2) No right is granted to use any trade name, trademark, or
33 * logo of Broadcom Corporation. Neither the "Broadcom
34 * Corporation" name nor any trademark or logo of Broadcom
35 * Corporation may be used to endorse or promote products
36 * derived from this software without the prior written
37 * permission of Broadcom Corporation.
39 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
40 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
41 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
42 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
43 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
44 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
47 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
48 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
49 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
50 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
51 * THE POSSIBILITY OF SUCH DAMAGE.
52 ********************************************************************* */
55 #include "sb1250_genbus.h"
56 #include "sb1250_regs.h"
57 #include "sb1250_scd.h"
58 #include "sb1250_mc.h"
59 #include "sb1250_mac.h"
60 #include "bsp_config.h"
62 #include "sb1250_draminit.h"
63 #include "../dev/ns16550.h"
65 #if defined(_PT1120_DIAG_CFG_)
66 #undef SERIAL_PORT_LEDS
67 #define SERIAL_PORT_LEDS
71 /* *********************************************************************
73 ********************************************************************* */
77 #define CALLKSEG1(x) la k0,x ; or k0,K1BASE ; jal k0
79 #define CALLKSEG1(x) jal x
83 /* *********************************************************************
86 * Initialize board registers. This is the earliest
87 * time the BSP gets control. This routine cannot assume that
88 * memory is operational, and therefore all code in this routine
89 * must run from registers only. The $ra register must not
90 * be modified, as it contains the return address.
92 * This routine will be called from uncached space, before
93 * the caches are initialized. If you want to make
94 * subroutine calls from here, you must use the CALLKSEG1 macro.
96 * Among other things, this is where the GPIO registers get
97 * programmed to make on-board LEDs function, or other startup
98 * that has to be done before anything will work.
105 ********************************************************************* */
107 LEAF(board_earlyinit)
110 # Configure the GPIOs
113 # 1, 2, and 5 are interrupts
114 # remainder are input (unused)
117 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
118 li t1,GPIO_OUTPUT_MASK
121 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
122 li t1,GPIO_INTERRUPT_MASK
126 # Turn on the diagnostic LED
128 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
129 li t1,M_GPIO_DEBUG_LED
136 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
137 li t1,LEDS_PHYS >> S_IO_ADDRBASE
138 sd t1,R_IO_EXT_START_ADDR(t0)
140 li t1,LEDS_SIZE-1 /* Needs to be 1 smaller, se UM for details */
141 sd t1,R_IO_EXT_MULT_SIZE(t0)
144 sd t1,R_IO_EXT_TIME_CFG0(t0)
147 sd t1,R_IO_EXT_TIME_CFG1(t0)
150 sd t1,R_IO_EXT_CFG(t0)
153 # Configure the alternate boot ROM
156 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
158 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE
159 sd t1,R_IO_EXT_START_ADDR(t0)
161 li t1,ALT_BOOTROM_SIZE-1
162 sd t1,R_IO_EXT_MULT_SIZE(t0)
164 li t1,ALT_BOOTROM_TIMING0
165 sd t1,R_IO_EXT_TIME_CFG0(t0)
167 li t1,ALT_BOOTROM_TIMING1
168 sd t1,R_IO_EXT_TIME_CFG1(t0)
170 li t1,ALT_BOOTROM_CONFIG
171 sd t1,R_IO_EXT_CFG(t0)
174 # Configure I/O bus for an external UART
177 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(UART_CS))
179 li t1, UART_PHYS >> S_IO_ADDRBASE
180 sd t1,R_IO_EXT_START_ADDR(t0)
183 sd t1,R_IO_EXT_MULT_SIZE(t0)
185 li t1, (UART_TIMING0)
186 sd t1,R_IO_EXT_TIME_CFG0(t0)
188 li t1, (UART_TIMING1)
189 sd t1,R_IO_EXT_TIME_CFG1(t0)
192 sd t1,R_IO_EXT_CFG(t0)
196 #ifdef SERIAL_PORT_LEDS
199 * Initialize the UART well enough to output characters.
201 li t0, PHYS_TO_K1(UART_PHYS)
204 sb t1, R_UART_CFCR(t0)
206 li t1, BRTC(CFG_SERIAL_BAUD_RATE)
207 sb t1, R_UART_DATA(t0)
209 sb t1, R_UART_IER(t0)
212 sb t1, R_UART_CFCR(t0)
214 li t1, (MCR_DTR | MCR_RTS | MCR_IENABLE)
215 sb t1, R_UART_MCR(t0)
218 sb t1, R_UART_IER(t0)
221 sb t1, R_UART_FIFO(t0)
228 li t1, (FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST \
230 sb t1, R_UART_FIFO(t0)
237 /* if (value & MASK) != MASK, write 0 to fifo reg. */
238 lb t1, R_UART_IIR(t0)
239 andi t1, t1, IIR_FIFO_MASK
240 xori t1, t1, IIR_FIFO_MASK
244 sb t1, R_UART_FIFO(t0)
249 * If the CPU is a 1250 or hybrid, certain initialization has
250 * to be done so that the chip can be used like an 112x.
253 /* First, figure out what type of SOC we're on. */
254 ld t1, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
256 bne t3, K_SYS_SOC_TYPE_BCM1250, is_bcm112x
259 * We have a 1250 or hybrid. Initialize registers as appropriate.
263 * If we're not already running as a uniprocessor, get us there.
265 dsrl t1, t1, S_SYS_PART # part number now in t1
267 dsrl t3, t3, 8 # t3 = numcpus
269 ld t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
270 or t4, t4, M_SYS_SB_SOFTRES
271 xor t4, t4, M_SYS_SB_SOFTRES
272 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* clear soft reset */
276 or t4, t4, M_SYS_SB_SOFTRES | M_SYS_UNICPU0
277 sd t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG) /* go unicpu */
287 li t0, PHYS_TO_K1(A_MC_BASE_0)
288 dli t1, V_MC_CONFIG_DEFAULT | M_MC_ECC_DISABLE | \
290 sd t1, R_MC_CONFIG(t0)
291 sd zero, R_MC_CS_START(t0)
292 sd zero, R_MC_CS_END(t0)
293 sd zero, R_MC_CS_INTERLEAVE(t0)
294 sd zero, R_MC_CS_ATTR(t0)
295 sd zero, R_MC_TEST_DATA(t0)
296 sd zero, R_MC_TEST_ECC(t0)
299 * Zero out MAC 2's address register. (This has
300 * undefined value after reset, but OSes may check
301 * it on some parts to see if they should init
302 * the interface. This is a convenient place
306 li t0, PHYS_TO_K1(A_MAC_BASE_2)
307 sd zero, R_MAC_ETHERNET_ADDR(t0)
317 /* *********************************************************************
320 * Return the address of the DRAM information table
326 * v0 - DRAM info table, return 0 to use default table
327 ********************************************************************* */
328 #define _HARDWIRED_MEMORY_TABLE 1
330 #define CFG_DRAM_tROUNDTRIP DRT10(2,0)
331 /* CFG_DRAM_MIN_tMEMCLK must be set to 7. Some DIMMS cause diag failures
332 when the memclk is at 125 MHz but pass at 100 MHz or 133 MHz. Setting to 7 causes
333 memclk to be 133 MHz*/
334 #define CFG_DRAM_MIN_tMEMCLK DRT10(7,0)
335 #define DEVADDR (CFG_DRAM_SMBUS_BASE)
336 #define DEFCHAN (CFG_DRAM_SMBUS_CHANNEL)
339 #define LOADREL(reg,label) \
348 #define LOADREL(reg,label) \
356 #ifdef _HARDWIRED_MEMORY_TABLE
359 move v0,zero # auto configure
367 DRAM_GLOBALS(0) /* no port interleaving */
370 * Memory channel 0: Configure via SMBUS, Automatic Timing
371 * Assumes SMBus device numbers are arranged such
372 * that the first two addresses are CS0,1 and CS2,3 on MC0
373 * and the second two addresses are CS0,1 and CS2,3 on MC1
375 DRAM_CHAN_CFG2(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, CFG_DRAM_tROUNDTRIP, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
379 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+2)
380 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+3)
388 #ifdef SERIAL_PORT_LEDS
389 /* *********************************************************************
390 * BOARD_UART_TXCHAR(x)
392 * Transmit one character out the UART on the GENERIC bus.
395 * a0 - 8 bit character value.
402 ********************************************************************* */
404 LEAF(board_uart_txchar)
406 # Wait until there is space in the transmit buffer.
408 li t0, PHYS_TO_K1(UART_PHYS)
410 1: lb t1, R_UART_LSR(t0)
411 andi t1, t1, LSR_TXRDY
414 # OK, now send a character.
416 sb a0, R_UART_DATA(t0)
422 END(board_uart_txchar)
426 /* *********************************************************************
429 * Set LEDs for boot-time progress indication. Not used if
430 * the board does not have progress LEDs. This routine
431 * must not call any other routines, since it may be invoked
432 * either from KSEG0 or KSEG1 and it may be invoked
433 * whether or not the icache is operational.
436 * a0 - LED value (8 bits per character, 4 characters)
443 ********************************************************************* */
446 #define LED_CHAR0 (32+8*3)
447 #define LED_CHAR1 (32+8*2)
448 #define LED_CHAR2 (32+8*1)
449 #define LED_CHAR3 (32+8*0)
451 #ifdef SERIAL_PORT_LEDS
452 #define OUTPUT_CHAR(offset) \
453 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
454 sb a0, offset(t0) ; \
455 bal board_uart_txchar
457 #define OUTPUT_CHAR(offset) \
458 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
467 #ifdef SERIAL_PORT_LEDS
469 bal board_uart_txchar
474 OUTPUT_CHAR(LED_CHAR0)
477 OUTPUT_CHAR(LED_CHAR1)
480 OUTPUT_CHAR(LED_CHAR2)
483 OUTPUT_CHAR(LED_CHAR3)
485 #ifdef SERIAL_PORT_LEDS
487 bal board_uart_txchar
489 bal board_uart_txchar
491 bal board_uart_txchar
499 /* *********************************************************************
502 * Change the size of the bootrom area.
503 * This routine is called only after CFE has been relocated to DRAM
504 * and is executing from DRAM. After that point, the boot rom
505 * is serving as a flash file storage area. Note: this could be
506 * done in board_earlyinit since we're not changing the base address.
516 ********************************************************************* */
519 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BOOTROM_CS))
522 sd t1,R_IO_EXT_MULT_SIZE(t0)
527 /* *********************************************************************
530 * Change the size of the flash area.
531 * Usually CS1 is the promice, but if it's not, the flash is here.
541 ********************************************************************* */
544 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
547 sd t1,R_IO_EXT_MULT_SIZE(t0)