allow coexistance of N build and AC build.
[tomato.git] / release / src-rt-6.x / cfe / cfe / arch / mips / board / p5064 / include / rtc.h
blob237ddc48e5a85e10368da7d4d10c2d837248e920
1 /*
2 * p5064/rtc.h: PC-style real-time clock register definitions
3 * Copyright (c) 1997 Algorithmics Ltd
4 */
6 /*
7 * RTC Register locations
8 */
9 #define RTC_SEC 0x00 /* seconds */
10 #define RTC_SECALRM 0x01 /* seconds alarm */
11 #define RTC_MIN 0x02 /* minutes */
12 #define RTC_MINALRM 0x03 /* minutes alarm */
13 #define RTC_HRS 0x04 /* hours */
14 #define RTC_HRSALRM 0x05 /* hours alarm */
15 #define RTC_WDAY 0x06 /* week day */
16 #define RTC_DAY 0x07 /* day of month */
17 #define RTC_MONTH 0x08 /* month of year */
18 #define RTC_YEAR 0x09 /* month of year */
19 #define RTC_STATUSA 0x0a /* status register A */
20 #define RTCSA_UIP 0x80 /* update in progress */
21 #define RTCSA_DVMASK 0x70 /* divisor select mask (see below) */
22 #define RTCSA_RSMASK 0x0f /* interrupt rate select mask (see below) */
23 #define RTC_STATUSB 0x0b /* status register B */
24 #define RTCSB_UTI 0x80 /* update transfer inhibit */
25 #define RTCSB_PIE 0x40 /* periodic i/u enable */
26 #define RTCSB_AIE 0x20 /* alarm i/u enable */
27 #define RTCSB_UIE 0x10 /* update cycle i/u enable */
28 #define RTCSB_SQWE 0x08 /* square wave enable */
29 #define RTCSB_BINARY 0x04 /* data format (1=binary, 0=bcd) */
30 #define RTCSB_24HR 0x02 /* hour format (1=24 hour) */
31 #define RTCSB_DSE 0x01 /* daylight savings enable! */
32 #define RTC_INTR 0x0c /* status register C (R) interrupt source */
33 #define RTCIR_INTF 0x80 /* i/u output signal */
34 #define RTCIR_PF 0x40 /* periodic i/u */
35 #define RTCIR_AF 0x20 /* alarm i/u */
36 #define RTCIR_UF 0x10 /* update i/u */
37 #define RTCIR_32KE 0x04 /* enable 32kHz output */
38 #define RTC_STATUSD 0x0d /* status register D (R) Lost Power */
39 #define RTCSD_VRT 0x80 /* clock has valid backup power */
40 #define RTC_CENTURY 0x0e /* current century - increment in Dec 99*/
42 #define RTC_NTODREGS (RTC_CENTURY+1)
44 #define RTC_NVSTART RTC_NTODREGS
45 #define RTC_NVSIZE (128-RTC_NTODREGS)
48 * Time base (divisor select) constants (Control register A)
50 #define RTC_OSC_ON 0x20 /* 32KHz crystal */
51 #define RTC_OSC_32KHz 0x30 /* 32KHz crystal; 32KHz square wave */
52 #define RTC_OSC_NONE 0x60 /* actually, both of these reset */
53 #define RTC_OSC_RESET 0x70
54 #define RTC_DV0_OSC_NONE 0x00 /* PC97307: bank0 oscillator disabled */
55 #define RTC_DV0_OSC_ON 0x20 /* PC97307: bank1 oscillator enabled */
56 #define RTC_DV1_OSC_ON 0x30 /* PC97307: bank2 oscillator enabled */
57 #define RTC_DV2_OSC_ON 0x40 /* PC97307: bank3 oscillator enabled */
58 #define RTC_RATE_MASK 0x0f /* No periodic interrupt */
59 #define RTC_RATE_NONE 0x00 /* No periodic interrupt */
60 #define RTC_RATE_8192Hz 0x03 /* 122.070 us period */
61 #define RTC_RATE_4096Hz 0x04 /* 244.141 us period */
62 #define RTC_RATE_2048Hz 0x05 /* 488.281 us period */
63 #define RTC_RATE_1024Hz 0x06 /* 976.562 us period */
64 #define RTC_RATE_512Hz 0x07 /* 1.953125 ms period */
65 #define RTC_RATE_256Hz 0x08 /* 3.90625 ms period */
66 #define RTC_RATE_128Hz 0x09 /* 7.8125 ms period */
67 #define RTC_RATE_64Hz 0x0a /* 15.625 ms period */
68 #define RTC_RATE_32Hz 0x0b /* 31.25 ms period */
69 #define RTC_RATE_16Hz 0x0c /* 62.5 ms period */
70 #define RTC_RATE_8Hz 0x0d /* 125 ms period */
71 #define RTC_RATE_4Hz 0x0e /* 250 ms period */
72 #define RTC_RATE_2Hz 0x0f /* 500 ms period */
74 /* PC97037 specific definitions */
76 #define RTC_BANK1_CENTURY 0x48
77 #define RTC_BANK1_URADDR 0x50
78 #define RTC_BANK1_URDATA 0x53
80 #define RTC_BANK2_APCR1 0x40
81 #define RTC_BANK2_APCR2 0x41
82 #define RTC_BANK2_APCSR 0x42
83 #define RTC_BANK2_WDAY_WAKEUP 0x43
84 #define RTC_BANK2_DAY_WAKEUP 0x44
85 #define RTC_BANK2_MONTH_WAKEUP 0x45
86 #define RTC_BANK2_MONTH_YEAR 0x46
87 #define RTC_BANK2_RAMLOCK 0x47
88 #define RTC_BANK2_CENTURY_WAKEUP 0x48
90 #define APCR1_SWITCHOFFDELAY 0x02
91 #define APCR1_LEVELPOR 0x04
92 #define APCR1_CLEARPOR 0x08
93 #define APCR1_MOAP 0x10
94 #define APCR1_SOC 0x20
95 #define APCR1_FAILSAFESTOP 0x40
96 #define APCR1_POWERFAILURE 0x80
99 #ifndef __ASSEMBLER__
100 unsigned int rtc_get (int);
101 unsigned int rtc_set (int, unsigned int);
102 unsigned int rtc_bis (int, unsigned int);
103 unsigned int rtc_bic (int, unsigned int);
105 unsigned int apc_get (int);
106 unsigned int apc_set (int, unsigned int);
107 unsigned int apc_bis (int, unsigned int);
108 unsigned int apc_bic (int, unsigned int);
109 #endif