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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / sound / mips / hal2.c
blob453d343550a880ae2480337a3ab7c055e001959a
1 /*
2 * Driver for A2 audio system used in SGI machines
3 * Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
4 *
5 * Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
6 * was based on code from Ulf Carlsson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/io.h>
28 #include <linux/slab.h>
29
30 #include <asm/sgi/hpc3.h>
31 #include <asm/sgi/ip22.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm-indirect.h>
37 #include <sound/initval.h>
38
39 #include "hal2.h"
40
41 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
42 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
43
44 module_param(index, int, 0444);
45 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
46 module_param(id, charp, 0444);
47 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
48 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
49 MODULE_AUTHOR("Thomas Bogendoerfer");
50 MODULE_LICENSE("GPL");
51
52
53 #define H2_BLOCK_SIZE 1024
54 #define H2_BUF_SIZE 16384
55
56 struct hal2_pbus {
57 struct hpc3_pbus_dmacregs *pbus;
58 int pbusnr;
59 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
60 };
61
62 struct hal2_desc {
63 struct hpc_dma_desc desc;
64 u32 pad; /* padding */
65 };
66
67 struct hal2_codec {
68 struct snd_pcm_indirect pcm_indirect;
69 struct snd_pcm_substream *substream;
70
71 unsigned char *buffer;
72 dma_addr_t buffer_dma;
73 struct hal2_desc *desc;
74 dma_addr_t desc_dma;
75 int desc_count;
76 struct hal2_pbus pbus;
77 int voices; /* mono/stereo */
78 unsigned int sample_rate;
79 unsigned int master; /* Master frequency */
80 unsigned short mod; /* MOD value */
81 unsigned short inc; /* INC value */
82 };
83
84 #define H2_MIX_OUTPUT_ATT 0
85 #define H2_MIX_INPUT_GAIN 1
86
87 struct snd_hal2 {
88 struct snd_card *card;
89
90 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
91 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
92 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
93 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
94
95 struct hal2_codec dac;
96 struct hal2_codec adc;
97 };
98
99 #define H2_INDIRECT_WAIT(regs) while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
100
101 #define H2_READ_ADDR(addr) (addr | (1<<7))
102 #define H2_WRITE_ADDR(addr) (addr)
103
104 static inline u32 hal2_read(u32 *reg)
105 {
106 return __raw_readl(reg);
107 }
108
109 static inline void hal2_write(u32 val, u32 *reg)
110 {
111 __raw_writel(val, reg);
112 }
113
114
115 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
116 {
117 u32 ret;
118 struct hal2_ctl_regs *regs = hal2->ctl_regs;
119
120 hal2_write(H2_READ_ADDR(addr), &regs->iar);
121 H2_INDIRECT_WAIT(regs);
122 ret = hal2_read(&regs->idr0) & 0xffff;
123 hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
124 H2_INDIRECT_WAIT(regs);
125 ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
126 return ret;
127 }
128
129 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
130 {
131 struct hal2_ctl_regs *regs = hal2->ctl_regs;
132
133 hal2_write(val, &regs->idr0);
134 hal2_write(0, &regs->idr1);
135 hal2_write(0, &regs->idr2);
136 hal2_write(0, &regs->idr3);
137 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
138 H2_INDIRECT_WAIT(regs);
139 }
140
141 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
142 {
143 struct hal2_ctl_regs *regs = hal2->ctl_regs;
144
145 hal2_write(val & 0xffff, &regs->idr0);
146 hal2_write(val >> 16, &regs->idr1);
147 hal2_write(0, &regs->idr2);
148 hal2_write(0, &regs->idr3);
149 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
150 H2_INDIRECT_WAIT(regs);
151 }
152
153 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
154 {
155 struct hal2_ctl_regs *regs = hal2->ctl_regs;
156
157 hal2_write(H2_READ_ADDR(addr), &regs->iar);
158 H2_INDIRECT_WAIT(regs);
159 hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
160 hal2_write(0, &regs->idr1);
161 hal2_write(0, &regs->idr2);
162 hal2_write(0, &regs->idr3);
163 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
164 H2_INDIRECT_WAIT(regs);
165 }
166
167 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
168 {
169 struct hal2_ctl_regs *regs = hal2->ctl_regs;
170
171 hal2_write(H2_READ_ADDR(addr), &regs->iar);
172 H2_INDIRECT_WAIT(regs);
173 hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
174 hal2_write(0, &regs->idr1);
175 hal2_write(0, &regs->idr2);
176 hal2_write(0, &regs->idr3);
177 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
178 H2_INDIRECT_WAIT(regs);
179 }
180
181 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
182 struct snd_ctl_elem_info *uinfo)
183 {
184 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
185 uinfo->count = 2;
186 uinfo->value.integer.min = 0;
187 switch ((int)kcontrol->private_value) {
188 case H2_MIX_OUTPUT_ATT:
189 uinfo->value.integer.max = 31;
190 break;
191 case H2_MIX_INPUT_GAIN:
192 uinfo->value.integer.max = 15;
193 break;
194 }
195 return 0;
196 }
197
198 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
200 {
201 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
202 u32 tmp;
203 int l, r;
204
205 switch ((int)kcontrol->private_value) {
206 case H2_MIX_OUTPUT_ATT:
207 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
208 if (tmp & H2I_C2_MUTE) {
209 l = 0;
210 r = 0;
211 } else {
212 l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
213 r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
214 }
215 break;
216 case H2_MIX_INPUT_GAIN:
217 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
218 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
219 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
220 break;
221 }
222 ucontrol->value.integer.value[0] = l;
223 ucontrol->value.integer.value[1] = r;
224
225 return 0;
226 }
227
228 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
229 struct snd_ctl_elem_value *ucontrol)
230 {
231 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
232 u32 old, new;
233 int l, r;
234
235 l = ucontrol->value.integer.value[0];
236 r = ucontrol->value.integer.value[1];
237
238 switch ((int)kcontrol->private_value) {
239 case H2_MIX_OUTPUT_ATT:
240 old = hal2_i_read32(hal2, H2I_DAC_C2);
241 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
242 if (l | r) {
243 l = 31 - l;
244 r = 31 - r;
245 new |= (l << H2I_C2_L_ATT_SHIFT);
246 new |= (r << H2I_C2_R_ATT_SHIFT);
247 } else
248 new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
249 hal2_i_write32(hal2, H2I_DAC_C2, new);
250 break;
251 case H2_MIX_INPUT_GAIN:
252 old = hal2_i_read32(hal2, H2I_ADC_C2);
253 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
254 new |= (l << H2I_C2_L_GAIN_SHIFT);
255 new |= (r << H2I_C2_R_GAIN_SHIFT);
256 hal2_i_write32(hal2, H2I_ADC_C2, new);
257 break;
258 }
259 return old != new;
260 }
261
262 static struct snd_kcontrol_new hal2_ctrl_headphone __devinitdata = {
263 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
264 .name = "Headphone Playback Volume",
265 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
266 .private_value = H2_MIX_OUTPUT_ATT,
267 .info = hal2_gain_info,
268 .get = hal2_gain_get,
269 .put = hal2_gain_put,
270 };
271
272 static struct snd_kcontrol_new hal2_ctrl_mic __devinitdata = {
273 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
274 .name = "Mic Capture Volume",
275 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
276 .private_value = H2_MIX_INPUT_GAIN,
277 .info = hal2_gain_info,
278 .get = hal2_gain_get,
279 .put = hal2_gain_put,
280 };
281
282 static int __devinit hal2_mixer_create(struct snd_hal2 *hal2)
283 {
284 int err;
285
286 /* mute DAC */
287 hal2_i_write32(hal2, H2I_DAC_C2,
288 H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
289 /* mute ADC */
290 hal2_i_write32(hal2, H2I_ADC_C2, 0);
291
292 err = snd_ctl_add(hal2->card,
293 snd_ctl_new1(&hal2_ctrl_headphone, hal2));
294 if (err < 0)
295 return err;
296
297 err = snd_ctl_add(hal2->card,
298 snd_ctl_new1(&hal2_ctrl_mic, hal2));
299 if (err < 0)
300 return err;
301
302 return 0;
303 }
304
305 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
306 {
307 struct snd_hal2 *hal2 = dev_id;
308 irqreturn_t ret = IRQ_NONE;
309
310 /* decide what caused this interrupt */
311 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
312 snd_pcm_period_elapsed(hal2->dac.substream);
313 ret = IRQ_HANDLED;
314 }
315 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
316 snd_pcm_period_elapsed(hal2->adc.substream);
317 ret = IRQ_HANDLED;
318 }
319 return ret;
320 }
321
322 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
323 {
324 unsigned short mod;
325
326 if (44100 % rate < 48000 % rate) {
327 mod = 4 * 44100 / rate;
328 codec->master = 44100;
329 } else {
330 mod = 4 * 48000 / rate;
331 codec->master = 48000;
332 }
333
334 codec->inc = 4;
335 codec->mod = mod;
336 rate = 4 * codec->master / mod;
337
338 return rate;
339 }
340
341 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
342 {
343 unsigned int master = hal2->dac.master;
344 int inc = hal2->dac.inc;
345 int mod = hal2->dac.mod;
346
347 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
348 hal2_i_write32(hal2, H2I_BRES1_C2,
349 ((0xffff & (inc - mod - 1)) << 16) | inc);
350 }
351
352 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
353 {
354 unsigned int master = hal2->adc.master;
355 int inc = hal2->adc.inc;
356 int mod = hal2->adc.mod;
357
358 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
359 hal2_i_write32(hal2, H2I_BRES2_C2,
360 ((0xffff & (inc - mod - 1)) << 16) | inc);
361 }
362
363 static void hal2_setup_dac(struct snd_hal2 *hal2)
364 {
365 unsigned int fifobeg, fifoend, highwater, sample_size;
366 struct hal2_pbus *pbus = &hal2->dac.pbus;
367
368 /* Now we set up some PBUS information. The PBUS needs information about
369 * what portion of the fifo it will use. If it's receiving or
370 * transmitting, and finally whether the stream is little endian or big
371 * endian. The information is written later, on the start call.
372 */
373 sample_size = 2 * hal2->dac.voices;
374 /* Fifo should be set to hold exactly four samples. Highwater mark
375 * should be set to two samples. */
376 highwater = (sample_size * 2) >> 1; /* halfwords */
377 fifobeg = 0; /* playback is first */
378 fifoend = (sample_size * 4) >> 3; /* doublewords */
379 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
380 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
381 /* We disable everything before we do anything at all */
382 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
383 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
384 /* Setup the HAL2 for playback */
385 hal2_set_dac_rate(hal2);
386 /* Set endianess */
387 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
388 /* Set DMA bus */
389 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
390 /* We are using 1st Bresenham clock generator for playback */
391 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
392 | (1 << H2I_C1_CLKID_SHIFT)
393 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
394 }
395
396 static void hal2_setup_adc(struct snd_hal2 *hal2)
397 {
398 unsigned int fifobeg, fifoend, highwater, sample_size;
399 struct hal2_pbus *pbus = &hal2->adc.pbus;
400
401 sample_size = 2 * hal2->adc.voices;
402 highwater = (sample_size * 2) >> 1; /* halfwords */
403 fifobeg = (4 * 4) >> 3; /* record is second */
404 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
405 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
406 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
407 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
408 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
409 /* Setup the HAL2 for record */
410 hal2_set_adc_rate(hal2);
411 /* Set endianess */
412 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
413 /* Set DMA bus */
414 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
415 /* We are using 2nd Bresenham clock generator for record */
416 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
417 | (2 << H2I_C1_CLKID_SHIFT)
418 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
419 }
420
421 static void hal2_start_dac(struct snd_hal2 *hal2)
422 {
423 struct hal2_pbus *pbus = &hal2->dac.pbus;
424
425 pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
426 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
427 /* enable DAC */
428 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
429 }
430
431 static void hal2_start_adc(struct snd_hal2 *hal2)
432 {
433 struct hal2_pbus *pbus = &hal2->adc.pbus;
434
435 pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
436 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
437 /* enable ADC */
438 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
439 }
440
441 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
442 {
443 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
444 /* The HAL2 itself may remain enabled safely */
445 }
446
447 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
448 {
449 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
450 }
451
452 static int hal2_alloc_dmabuf(struct hal2_codec *codec)
453 {
454 struct hal2_desc *desc;
455 dma_addr_t desc_dma, buffer_dma;
456 int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
457 int i;
458
459 codec->buffer = dma_alloc_noncoherent(NULL, H2_BUF_SIZE,
460 &buffer_dma, GFP_KERNEL);
461 if (!codec->buffer)
462 return -ENOMEM;
463 desc = dma_alloc_noncoherent(NULL, count * sizeof(struct hal2_desc),
464 &desc_dma, GFP_KERNEL);
465 if (!desc) {
466 dma_free_noncoherent(NULL, H2_BUF_SIZE,
467 codec->buffer, buffer_dma);
468 return -ENOMEM;
469 }
470 codec->buffer_dma = buffer_dma;
471 codec->desc_dma = desc_dma;
472 codec->desc = desc;
473 for (i = 0; i < count; i++) {
474 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
475 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
476 desc->desc.pnext = (i == count - 1) ?
477 desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
478 desc++;
479 }
480 dma_cache_sync(NULL, codec->desc, count * sizeof(struct hal2_desc),
481 DMA_TO_DEVICE);
482 codec->desc_count = count;
483 return 0;
484 }
485
486 static void hal2_free_dmabuf(struct hal2_codec *codec)
487 {
488 dma_free_noncoherent(NULL, codec->desc_count * sizeof(struct hal2_desc),
489 codec->desc, codec->desc_dma);
490 dma_free_noncoherent(NULL, H2_BUF_SIZE, codec->buffer,
491 codec->buffer_dma);
492 }
493
494 static struct snd_pcm_hardware hal2_pcm_hw = {
495 .info = (SNDRV_PCM_INFO_MMAP |
496 SNDRV_PCM_INFO_MMAP_VALID |
497 SNDRV_PCM_INFO_INTERLEAVED |
498 SNDRV_PCM_INFO_BLOCK_TRANSFER),
499 .formats = SNDRV_PCM_FMTBIT_S16_BE,
500 .rates = SNDRV_PCM_RATE_8000_48000,
501 .rate_min = 8000,
502 .rate_max = 48000,
503 .channels_min = 2,
504 .channels_max = 2,
505 .buffer_bytes_max = 65536,
506 .period_bytes_min = 1024,
507 .period_bytes_max = 65536,
508 .periods_min = 2,
509 .periods_max = 1024,
510 };
511
512 static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
513 struct snd_pcm_hw_params *params)
514 {
515 int err;
516
517 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
518 if (err < 0)
519 return err;
520
521 return 0;
522 }
523
524 static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
525 {
526 return snd_pcm_lib_free_pages(substream);
527 }
528
529 static int hal2_playback_open(struct snd_pcm_substream *substream)
530 {
531 struct snd_pcm_runtime *runtime = substream->runtime;
532 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
533 int err;
534
535 runtime->hw = hal2_pcm_hw;
536
537 err = hal2_alloc_dmabuf(&hal2->dac);
538 if (err)
539 return err;
540 return 0;
541 }
542
543 static int hal2_playback_close(struct snd_pcm_substream *substream)
544 {
545 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
546
547 hal2_free_dmabuf(&hal2->dac);
548 return 0;
549 }
550
551 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
552 {
553 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
554 struct snd_pcm_runtime *runtime = substream->runtime;
555 struct hal2_codec *dac = &hal2->dac;
556
557 dac->voices = runtime->channels;
558 dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
559 memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
560 dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
561 dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
562 dac->substream = substream;
563 hal2_setup_dac(hal2);
564 return 0;
565 }
566
567 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
568 {
569 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
570
571 switch (cmd) {
572 case SNDRV_PCM_TRIGGER_START:
573 hal2->dac.pcm_indirect.hw_io = hal2->dac.buffer_dma;
574 hal2->dac.pcm_indirect.hw_data = 0;
575 substream->ops->ack(substream);
576 hal2_start_dac(hal2);
577 break;
578 case SNDRV_PCM_TRIGGER_STOP:
579 hal2_stop_dac(hal2);
580 break;
581 default:
582 return -EINVAL;
583 }
584 return 0;
585 }
586
587 static snd_pcm_uframes_t
588 hal2_playback_pointer(struct snd_pcm_substream *substream)
589 {
590 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
591 struct hal2_codec *dac = &hal2->dac;
592
593 return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
594 dac->pbus.pbus->pbdma_bptr);
595 }
596
597 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
598 struct snd_pcm_indirect *rec, size_t bytes)
599 {
600 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
601 unsigned char *buf = hal2->dac.buffer + rec->hw_data;
602
603 memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
604 dma_cache_sync(NULL, buf, bytes, DMA_TO_DEVICE);
605
606 }
607
608 static int hal2_playback_ack(struct snd_pcm_substream *substream)
609 {
610 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
611 struct hal2_codec *dac = &hal2->dac;
612
613 dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
614 snd_pcm_indirect_playback_transfer(substream,
615 &dac->pcm_indirect,
616 hal2_playback_transfer);
617 return 0;
618 }
619
620 static int hal2_capture_open(struct snd_pcm_substream *substream)
621 {
622 struct snd_pcm_runtime *runtime = substream->runtime;
623 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
624 struct hal2_codec *adc = &hal2->adc;
625 int err;
626
627 runtime->hw = hal2_pcm_hw;
628
629 err = hal2_alloc_dmabuf(adc);
630 if (err)
631 return err;
632 return 0;
633 }
634
635 static int hal2_capture_close(struct snd_pcm_substream *substream)
636 {
637 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
638
639 hal2_free_dmabuf(&hal2->adc);
640 return 0;
641 }
642
643 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
644 {
645 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
646 struct snd_pcm_runtime *runtime = substream->runtime;
647 struct hal2_codec *adc = &hal2->adc;
648
649 adc->voices = runtime->channels;
650 adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
651 memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
652 adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
653 adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
654 adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
655 adc->substream = substream;
656 hal2_setup_adc(hal2);
657 return 0;
658 }
659
660 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
661 {
662 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
663
664 switch (cmd) {
665 case SNDRV_PCM_TRIGGER_START:
666 hal2->adc.pcm_indirect.hw_io = hal2->adc.buffer_dma;
667 hal2->adc.pcm_indirect.hw_data = 0;
668 printk(KERN_DEBUG "buffer_dma %x\n", hal2->adc.buffer_dma);
669 hal2_start_adc(hal2);
670 break;
671 case SNDRV_PCM_TRIGGER_STOP:
672 hal2_stop_adc(hal2);
673 break;
674 default:
675 return -EINVAL;
676 }
677 return 0;
678 }
679
680 static snd_pcm_uframes_t
681 hal2_capture_pointer(struct snd_pcm_substream *substream)
682 {
683 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
684 struct hal2_codec *adc = &hal2->adc;
685
686 return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
687 adc->pbus.pbus->pbdma_bptr);
688 }
689
690 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
691 struct snd_pcm_indirect *rec, size_t bytes)
692 {
693 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
694 unsigned char *buf = hal2->adc.buffer + rec->hw_data;
695
696 dma_cache_sync(NULL, buf, bytes, DMA_FROM_DEVICE);
697 memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
698 }
699
700 static int hal2_capture_ack(struct snd_pcm_substream *substream)
701 {
702 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
703 struct hal2_codec *adc = &hal2->adc;
704
705 snd_pcm_indirect_capture_transfer(substream,
706 &adc->pcm_indirect,
707 hal2_capture_transfer);
708 return 0;
709 }
710
711 static struct snd_pcm_ops hal2_playback_ops = {
712 .open = hal2_playback_open,
713 .close = hal2_playback_close,
714 .ioctl = snd_pcm_lib_ioctl,
715 .hw_params = hal2_pcm_hw_params,
716 .hw_free = hal2_pcm_hw_free,
717 .prepare = hal2_playback_prepare,
718 .trigger = hal2_playback_trigger,
719 .pointer = hal2_playback_pointer,
720 .ack = hal2_playback_ack,
721 };
722
723 static struct snd_pcm_ops hal2_capture_ops = {
724 .open = hal2_capture_open,
725 .close = hal2_capture_close,
726 .ioctl = snd_pcm_lib_ioctl,
727 .hw_params = hal2_pcm_hw_params,
728 .hw_free = hal2_pcm_hw_free,
729 .prepare = hal2_capture_prepare,
730 .trigger = hal2_capture_trigger,
731 .pointer = hal2_capture_pointer,
732 .ack = hal2_capture_ack,
733 };
734
735 static int __devinit hal2_pcm_create(struct snd_hal2 *hal2)
736 {
737 struct snd_pcm *pcm;
738 int err;
739
740 /* create first pcm device with one outputs and one input */
741 err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
742 if (err < 0)
743 return err;
744
745 pcm->private_data = hal2;
746 strcpy(pcm->name, "SGI HAL2");
747
748 /* set operators */
749 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
750 &hal2_playback_ops);
751 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
752 &hal2_capture_ops);
753 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
754 snd_dma_continuous_data(GFP_KERNEL),
755 0, 1024 * 1024);
756
757 return 0;
758 }
759
760 static int hal2_dev_free(struct snd_device *device)
761 {
762 struct snd_hal2 *hal2 = device->device_data;
763
764 free_irq(SGI_HPCDMA_IRQ, hal2);
765 kfree(hal2);
766 return 0;
767 }
768
769 static struct snd_device_ops hal2_ops = {
770 .dev_free = hal2_dev_free,
771 };
772
773 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
774 int index)
775 {
776 codec->pbus.pbusnr = index;
777 codec->pbus.pbus = &hpc3->pbdma[index];
778 }
779
780 static int hal2_detect(struct snd_hal2 *hal2)
781 {
782 unsigned short board, major, minor;
783 unsigned short rev;
784
785 /* reset HAL2 */
786 hal2_write(0, &hal2->ctl_regs->isr);
787
788 /* release reset */
789 hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
790 &hal2->ctl_regs->isr);
791
792
793 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
794 rev = hal2_read(&hal2->ctl_regs->rev);
795 if (rev & H2_REV_AUDIO_PRESENT)
796 return -ENODEV;
797
798 board = (rev & H2_REV_BOARD_M) >> 12;
799 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
800 minor = (rev & H2_REV_MINOR_CHIP_M);
801
802 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
803 board, major, minor);
804
805 return 0;
806 }
807
808 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
809 {
810 struct snd_hal2 *hal2;
811 struct hpc3_regs *hpc3 = hpc3c0;
812 int err;
813
814 hal2 = kzalloc(sizeof(struct snd_hal2), GFP_KERNEL);
815 if (!hal2)
816 return -ENOMEM;
817
818 hal2->card = card;
819
820 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
821 "SGI HAL2", hal2)) {
822 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
823 kfree(hal2);
824 return -EAGAIN;
825 }
826
827 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
828 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
829 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
830 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
831
832 if (hal2_detect(hal2) < 0) {
833 kfree(hal2);
834 return -ENODEV;
835 }
836
837 hal2_init_codec(&hal2->dac, hpc3, 0);
838 hal2_init_codec(&hal2->adc, hpc3, 1);
839
840 /*
841 * All DMA channel interfaces in HAL2 are designed to operate with
842 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
843 * in D5. HAL2 is a 16-bit device which can accept both big and little
844 * endian format. It assumes that even address bytes are on high
845 * portion of PBUS (15:8) and assumes that HPC3 is programmed to
846 * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
847 */
848 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
849 (2 << HPC3_DMACFG_D4R_SHIFT) | \
850 (2 << HPC3_DMACFG_D5R_SHIFT) | \
851 (0 << HPC3_DMACFG_D3W_SHIFT) | \
852 (2 << HPC3_DMACFG_D4W_SHIFT) | \
853 (2 << HPC3_DMACFG_D5W_SHIFT) | \
854 HPC3_DMACFG_DS16 | \
855 HPC3_DMACFG_EVENHI | \
856 HPC3_DMACFG_RTIME | \
857 (8 << HPC3_DMACFG_BURST_SHIFT) | \
858 HPC3_DMACFG_DRQLIVE)
859 /*
860 * Ignore what's mentioned in the specification and write value which
861 * works in The Real World (TM)
862 */
863 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
864 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
865
866 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
867 if (err < 0) {
868 free_irq(SGI_HPCDMA_IRQ, hal2);
869 kfree(hal2);
870 return err;
871 }
872 *rchip = hal2;
873 return 0;
874 }
875
876 static int __devinit hal2_probe(struct platform_device *pdev)
877 {
878 struct snd_card *card;
879 struct snd_hal2 *chip;
880 int err;
881
882 err = snd_card_create(index, id, THIS_MODULE, 0, &card);
883 if (err < 0)
884 return err;
885
886 err = hal2_create(card, &chip);
887 if (err < 0) {
888 snd_card_free(card);
889 return err;
890 }
891 snd_card_set_dev(card, &pdev->dev);
892
893 err = hal2_pcm_create(chip);
894 if (err < 0) {
895 snd_card_free(card);
896 return err;
897 }
898 err = hal2_mixer_create(chip);
899 if (err < 0) {
900 snd_card_free(card);
901 return err;
902 }
903
904 strcpy(card->driver, "SGI HAL2 Audio");
905 strcpy(card->shortname, "SGI HAL2 Audio");
906 sprintf(card->longname, "%s irq %i",
907 card->shortname,
908 SGI_HPCDMA_IRQ);
909
910 err = snd_card_register(card);
911 if (err < 0) {
912 snd_card_free(card);
913 return err;
914 }
915 platform_set_drvdata(pdev, card);
916 return 0;
917 }
918
919 static int __devexit hal2_remove(struct platform_device *pdev)
920 {
921 struct snd_card *card = platform_get_drvdata(pdev);
922
923 snd_card_free(card);
924 platform_set_drvdata(pdev, NULL);
925 return 0;
926 }
927
928 static struct platform_driver hal2_driver = {
929 .probe = hal2_probe,
930 .remove = __devexit_p(hal2_remove),
931 .driver = {
932 .name = "sgihal2",
933 .owner = THIS_MODULE,
934 }
935 };
936
937 static int __init alsa_card_hal2_init(void)
938 {
939 return platform_driver_register(&hal2_driver);
940 }
941
942 static void __exit alsa_card_hal2_exit(void)
943 {
944 platform_driver_unregister(&hal2_driver);
945 }
946
947 module_init(alsa_card_hal2_init);
948 module_exit(alsa_card_hal2_exit);
Tomato firmware and modifications.