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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / include / sound / cs46xx_dsp_scb_types.h
blobdb6e4116e4cc840a8c4683ea8b332484cf35a06f
1 /*
2 * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 *
21 * NOTE: comments are copy/paste from cwcemb80.lst
22 * provided by Tom Woller at Cirrus (my only
23 * documentation about the SP OS running inside
24 * the DSP)
25 */
26
27 #ifndef __CS46XX_DSP_SCB_TYPES_H__
28 #define __CS46XX_DSP_SCB_TYPES_H__
29
30 #include <asm/byteorder.h>
31
32 #ifndef ___DSP_DUAL_16BIT_ALLOC
33 #if defined(__LITTLE_ENDIAN)
34 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 a; u16 b;
35 #elif defined(__BIG_ENDIAN)
36 #define ___DSP_DUAL_16BIT_ALLOC(a,b) u16 b; u16 a;
37 #else
38 #error Not __LITTLE_ENDIAN and not __BIG_ENDIAN, then what ???
39 #endif
40 #endif
41
42 /* This structs are used internally by the SP */
43
44 struct dsp_basic_dma_req {
45 /* DMA Requestor Word 0 (DCW) fields:
46
47 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
48 _______________________________________________________________________________________
49 |S| SBT |D| DBT |wb|wb| | | LS | SS |Opt|Do|SSG|DSG| | | | | | | Dword |
50 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
51 */
52 u32 dcw; /* DMA Control Word */
53 u32 dmw; /* DMA Mode Word */
54 u32 saw; /* Source Address Word */
55 u32 daw; /* Destination Address Word */
56 };
57
58 struct dsp_scatter_gather_ext {
59 u32 npaw; /* Next-Page Address Word */
60
61 /* DMA Requestor Word 5 (NPCW) fields:
62
63 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
64 _________________________________________________________________________________________
65 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
66 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
67 */
68 u32 npcw; /* Next-Page Control Word */
69 u32 lbaw; /* Loop-Begin Address Word */
70 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
71 u32 sgaw; /* Scatter/Gather Address Word */
72 };
73
74 struct dsp_volume_control {
75 ___DSP_DUAL_16BIT_ALLOC(
76 rightTarg, /* Target volume for left & right channels */
77 leftTarg
78 )
79 ___DSP_DUAL_16BIT_ALLOC(
80 rightVol, /* Current left & right channel volumes */
81 leftVol
82 )
83 };
84
85 /* Generic stream control block (SCB) structure definition */
86 struct dsp_generic_scb {
87 /* For streaming I/O, the DSP should never alter any words in the DMA
88 requestor or the scatter/gather extension. Only ad hoc DMA request
89 streams are free to alter the requestor (currently only occur in the
90 DOS-based MIDI controller and in debugger-inserted code).
91
92 If an SCB does not have any associated DMA requestor, these 9 ints
93 may be freed for use by other tasks, but the pointer to the SCB must
94 still be such that the insOrd:nextSCB appear at offset 9 from the
95 SCB pointer.
96
97 Basic (non scatter/gather) DMA requestor (4 ints)
98 */
99
100 /* Initialized by the host, only modified by DMA
101 R/O for the DSP task */
102 struct dsp_basic_dma_req basic_req; /* Optional */
103
104 /* Scatter/gather DMA requestor extension (5 ints)
105 Initialized by the host, only modified by DMA
106 DSP task never needs to even read these.
107 */
108 struct dsp_scatter_gather_ext sg_ext; /* Optional */
109
110 /* Sublist pointer & next stream control block (SCB) link.
111 Initialized & modified by the host R/O for the DSP task
112 */
113 ___DSP_DUAL_16BIT_ALLOC(
114 next_scb, /* REQUIRED */
115 sub_list_ptr /* REQUIRED */
116 )
117
118 /* Pointer to this tasks parameter block & stream function pointer
119 Initialized by the host R/O for the DSP task */
120 ___DSP_DUAL_16BIT_ALLOC(
121 entry_point, /* REQUIRED */
122 this_spb /* REQUIRED */
123 )
124
125 /* rsConfig register for stream buffer (rsDMA reg.
126 is loaded from basicReq.daw for incoming streams, or
127 basicReq.saw, for outgoing streams)
128
129 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
130 ______________________________________________________________________________
131 |DMA |D|maxDMAsize| streamNum|dir|p| | | | | | |ds |shr 1|rev Cy | mod |
132 |prio |_|__________|__________|___|_|__|__|__|__|_|_|___|_____|_______|_______|
133 31 30 29 [28:24] [23:16] 15 14 13 12 11 10 9 8 7 6 5 4 [3:0]
134
135
136 Initialized by the host R/O for the DSP task
137 */
138 u32 strm_rs_config; /* REQUIRED */
139 //
140 /* On mixer input streams: indicates mixer input stream configuration
141 On Tees, this is copied from the stream being snooped
142
143 Stream sample pointer & MAC-unit mode for this stream
144
145 Initialized by the host Updated by the DSP task
146 */
147 u32 strm_buf_ptr; /* REQUIRED */
148
149 /* On mixer input streams: points to next mixer input and is updated by the
150 mixer subroutine in the "parent" DSP task
151 (least-significant 16 bits are preserved, unused)
152
153 On Tees, the pointer is copied from the stream being snooped on
154 initialization, and, subsequently, it is copied into the
155 stream being snooped.
156
157 On wavetable/3D voices: the strmBufPtr will use all 32 bits to allow for
158 fractional phase accumulation
159
160 Fractional increment per output sample in the input sample buffer
161
162 (Not used on mixer input streams & redefined on Tees)
163 On wavetable/3D voices: this 32-bit word specifies the integer.fractional
164 increment per output sample.
165 */
166 u32 strmPhiIncr;
167
168
169 /* Standard stereo volume control
170 Initialized by the host (host updates target volumes)
171
172 Current volumes update by the DSP task
173 On mixer input streams: required & updated by the mixer subroutine in the
174 "parent" DSP task
175
176 On Tees, both current & target volumes are copied up on initialization,
177 and, subsequently, the target volume is copied up while the current
178 volume is copied down.
179
180 These two 32-bit words are redefined for wavetable & 3-D voices.
181 */
182 struct dsp_volume_control vol_ctrl_t; /* Optional */
183 };
184
185
186 struct dsp_spos_control_block {
187 /* WARNING: Certain items in this structure are modified by the host
188 Any dword that can be modified by the host, must not be
189 modified by the SP as the host can only do atomic dword
190 writes, and to do otherwise, even a read modify write,
191 may lead to corrupted data on the SP.
192
193 This rule does not apply to one off boot time initialisation prior to starting the SP
194 */
195
196
197 ___DSP_DUAL_16BIT_ALLOC(
198 /* First element on the Hyper forground task tree */
199 hfg_tree_root_ptr, /* HOST */
200 /* First 3 dwords are written by the host and read-only on the DSP */
201 hfg_stack_base /* HOST */
202 )
203
204 ___DSP_DUAL_16BIT_ALLOC(
205 /* Point to this data structure to enable easy access */
206 spos_cb_ptr, /* SP */
207 prev_task_tree_ptr /* SP && HOST */
208 )
209
210 ___DSP_DUAL_16BIT_ALLOC(
211 /* Currently Unused */
212 xxinterval_timer_period,
213 /* Enable extension of SPOS data structure */
214 HFGSPB_ptr
215 )
216
217
218 ___DSP_DUAL_16BIT_ALLOC(
219 xxnum_HFG_ticks_thisInterval,
220 /* Modified by the DSP */
221 xxnum_tntervals
222 )
223
224
225 /* Set by DSP upon encountering a trap (breakpoint) or a spurious
226 interrupt. The host must clear this dword after reading it
227 upon receiving spInt1. */
228 ___DSP_DUAL_16BIT_ALLOC(
229 spurious_int_flag, /* (Host & SP) Nature of the spurious interrupt */
230 trap_flag /* (Host & SP) Nature of detected Trap */
231 )
232
233 ___DSP_DUAL_16BIT_ALLOC(
234 unused2,
235 invalid_IP_flag /* (Host & SP ) Indicate detection of invalid instruction pointer */
236 )
237
238 ___DSP_DUAL_16BIT_ALLOC(
239 /* pointer to forground task tree header for use in next task search */
240 fg_task_tree_hdr_ptr, /* HOST */
241 /* Data structure for controlling synchronous link update */
242 hfg_sync_update_ptr /* HOST */
243 )
244
245 ___DSP_DUAL_16BIT_ALLOC(
246 begin_foreground_FCNT, /* SP */
247 /* Place holder for holding sleep timing */
248 last_FCNT_before_sleep /* SP */
249 )
250
251 ___DSP_DUAL_16BIT_ALLOC(
252 unused7, /* SP */
253 next_task_treePtr /* SP */
254 )
255
256 u32 unused5;
257
258 ___DSP_DUAL_16BIT_ALLOC(
259 active_flags, /* SP */
260 /* State flags, used to assist control of execution of Hyper Forground */
261 HFG_flags /* SP */
262 )
263
264 ___DSP_DUAL_16BIT_ALLOC(
265 unused9,
266 unused8
267 )
268
269 /* Space for saving enough context so that we can set up enough
270 to save some more context.
271 */
272 u32 rFE_save_for_invalid_IP;
273 u32 r32_save_for_spurious_int;
274 u32 r32_save_for_trap;
275 u32 r32_save_for_HFG;
276 };
277
278 /* SPB for MIX_TO_OSTREAM algorithm family */
279 struct dsp_mix2_ostream_spb
280 {
281 /* 16b.16b integer.frac approximation to the
282 number of 3 sample triplets to output each
283 frame. (approximation must be floor, to
284 insure that the fractional error is always
285 positive)
286 */
287 u32 outTripletsPerFrame;
288
289 /* 16b.16b integer.frac accumulated number of
290 output triplets since the start of group
291 */
292 u32 accumOutTriplets;
293 };
294
295 /* SCB for Timing master algorithm */
296 struct dsp_timing_master_scb {
297 /* First 12 dwords from generic_scb_t */
298 struct dsp_basic_dma_req basic_req; /* Optional */
299 struct dsp_scatter_gather_ext sg_ext; /* Optional */
300 ___DSP_DUAL_16BIT_ALLOC(
301 next_scb, /* REQUIRED */
302 sub_list_ptr /* REQUIRED */
303 )
304
305 ___DSP_DUAL_16BIT_ALLOC(
306 entry_point, /* REQUIRED */
307 this_spb /* REQUIRED */
308 )
309
310 ___DSP_DUAL_16BIT_ALLOC(
311 reserved,
312 extra_sample_accum
313 )
314
315
316 ___DSP_DUAL_16BIT_ALLOC(
317 codec_FIFO_syncd,
318 codec_FIFO_ptr
319 )
320
321 /* Init. 8000:0005 for 44.1k
322 8000:0001 for 48k
323 hi: Fractional sample accumulator 0.16b
324 lo: Number of frames remaining to be
325 processed in the current group of
326 frames
327 */
328 ___DSP_DUAL_16BIT_ALLOC(
329 frac_samp_accum_qm1,
330 TM_frms_left_in_group
331 )
332
333 /* Init. 0001:0005 for 44.1k
334 0000:0001 for 48k
335 hi: Fractional sample correction factor 0.16b
336 to be added every frameGroupLength frames
337 to correct for truncation error in
338 nsamp_per_frm_q15
339 lo: Number of frames in the group
340 */
341 ___DSP_DUAL_16BIT_ALLOC(
342 frac_samp_correction_qm1,
343 TM_frm_group_length
344 )
345
346 /* Init. 44.1k*65536/8k = 0x00058333 for 44.1k
347 48k*65536/8k = 0x00060000 for 48k
348 16b.16b integer.frac approximation to the
349 number of samples to output each frame.
350 (approximation must be floor, to insure */
351 u32 nsamp_per_frm_q15;
352 };
353
354 /* SCB for CODEC output algorithm */
355 struct dsp_codec_output_scb {
356 /* First 13 dwords from generic_scb_t */
357 struct dsp_basic_dma_req basic_req; /* Optional */
358 struct dsp_scatter_gather_ext sg_ext; /* Optional */
359 ___DSP_DUAL_16BIT_ALLOC(
360 next_scb, /* REQUIRED */
361 sub_list_ptr /* REQUIRED */
362 )
363
364 ___DSP_DUAL_16BIT_ALLOC(
365 entry_point, /* REQUIRED */
366 this_spb /* REQUIRED */
367 )
368
369 u32 strm_rs_config; /* REQUIRED */
370
371 u32 strm_buf_ptr; /* REQUIRED */
372
373 /* NOTE: The CODEC output task reads samples from the first task on its
374 sublist at the stream buffer pointer (init. to lag DMA destination
375 address word). After the required number of samples is transferred,
376 the CODEC output task advances sub_list_ptr->strm_buf_ptr past the samples
377 consumed.
378 */
379
380 /* Init. 0000:0010 for SDout
381 0060:0010 for SDout2
382 0080:0010 for SDout3
383 hi: Base IO address of FIFO to which
384 the left-channel samples are to
385 be written.
386 lo: Displacement for the base IO
387 address for left-channel to obtain
388 the base IO address for the FIFO
389 to which the right-channel samples
390 are to be written.
391 */
392 ___DSP_DUAL_16BIT_ALLOC(
393 left_chan_base_IO_addr,
394 right_chan_IO_disp
395 )
396
397
398 /* Init: 0x0080:0004 for non-AC-97
399 Init: 0x0080:0000 for AC-97
400 hi: Exponential volume change rate
401 for input stream
402 lo: Positive shift count to shift the
403 16-bit input sample to obtain the
404 32-bit output word
405 */
406 ___DSP_DUAL_16BIT_ALLOC(
407 CO_scale_shift_count,
408 CO_exp_vol_change_rate
409 )
410
411 /* Pointer to SCB at end of input chain */
412 ___DSP_DUAL_16BIT_ALLOC(
413 reserved,
414 last_sub_ptr
415 )
416 };
417
418 /* SCB for CODEC input algorithm */
419 struct dsp_codec_input_scb {
420 /* First 13 dwords from generic_scb_t */
421 struct dsp_basic_dma_req basic_req; /* Optional */
422 struct dsp_scatter_gather_ext sg_ext; /* Optional */
423 ___DSP_DUAL_16BIT_ALLOC(
424 next_scb, /* REQUIRED */
425 sub_list_ptr /* REQUIRED */
426 )
427
428 ___DSP_DUAL_16BIT_ALLOC(
429 entry_point, /* REQUIRED */
430 this_spb /* REQUIRED */
431 )
432
433 u32 strm_rs_config; /* REQUIRED */
434 u32 strm_buf_ptr; /* REQUIRED */
435
436 /* NOTE: The CODEC input task reads samples from the hardware FIFO
437 sublist at the DMA source address word (sub_list_ptr->basic_req.saw).
438 After the required number of samples is transferred, the CODEC
439 output task advances sub_list_ptr->basic_req.saw past the samples
440 consumed. SPuD must initialize the sub_list_ptr->basic_req.saw
441 to point half-way around from the initial sub_list_ptr->strm_nuf_ptr
442 to allow for lag/lead.
443 */
444
445 /* Init. 0000:0010 for SDout
446 0060:0010 for SDout2
447 0080:0010 for SDout3
448 hi: Base IO address of FIFO to which
449 the left-channel samples are to
450 be written.
451 lo: Displacement for the base IO
452 address for left-channel to obtain
453 the base IO address for the FIFO
454 to which the right-channel samples
455 are to be written.
456 */
457 ___DSP_DUAL_16BIT_ALLOC(
458 rightChanINdisp,
459 left_chan_base_IN_addr
460 )
461 /* Init. ?:fffc
462 lo: Negative shift count to shift the
463 32-bit input dword to obtain the
464 16-bit sample msb-aligned (count
465 is negative to shift left)
466 */
467 ___DSP_DUAL_16BIT_ALLOC(
468 scaleShiftCount,
469 reserver1
470 )
471
472 u32 reserved2;
473 };
474
475
476 struct dsp_pcm_serial_input_scb {
477 /* First 13 dwords from generic_scb_t */
478 struct dsp_basic_dma_req basic_req; /* Optional */
479 struct dsp_scatter_gather_ext sg_ext; /* Optional */
480 ___DSP_DUAL_16BIT_ALLOC(
481 next_scb, /* REQUIRED */
482 sub_list_ptr /* REQUIRED */
483 )
484
485 ___DSP_DUAL_16BIT_ALLOC(
486 entry_point, /* REQUIRED */
487 this_spb /* REQUIRED */
488 )
489
490 u32 strm_buf_ptr; /* REQUIRED */
491 u32 strm_rs_config; /* REQUIRED */
492
493 /* Init. Ptr to CODEC input SCB
494 hi: Pointer to the SCB containing the
495 input buffer to which CODEC input
496 samples are written
497 lo: Flag indicating the link to the CODEC
498 input task is to be initialized
499 */
500 ___DSP_DUAL_16BIT_ALLOC(
501 init_codec_input_link,
502 codec_input_buf_scb
503 )
504
505 /* Initialized by the host (host updates target volumes) */
506 struct dsp_volume_control psi_vol_ctrl;
507
508 };
509
510 struct dsp_src_task_scb {
511 ___DSP_DUAL_16BIT_ALLOC(
512 frames_left_in_gof,
513 gofs_left_in_sec
514 )
515
516 ___DSP_DUAL_16BIT_ALLOC(
517 const2_thirds,
518 num_extra_tnput_samples
519 )
520
521 ___DSP_DUAL_16BIT_ALLOC(
522 cor_per_gof,
523 correction_per_sec
524 )
525
526 ___DSP_DUAL_16BIT_ALLOC(
527 output_buf_producer_ptr,
528 junk_DMA_MID
529 )
530
531 ___DSP_DUAL_16BIT_ALLOC(
532 gof_length,
533 gofs_per_sec
534 )
535
536 u32 input_buf_strm_config;
537
538 ___DSP_DUAL_16BIT_ALLOC(
539 reserved_for_SRC_use,
540 input_buf_consumer_ptr
541 )
542
543 u32 accum_phi;
544
545 ___DSP_DUAL_16BIT_ALLOC(
546 exp_src_vol_change_rate,
547 input_buf_producer_ptr
548 )
549
550 ___DSP_DUAL_16BIT_ALLOC(
551 src_next_scb,
552 src_sub_list_ptr
553 )
554
555 ___DSP_DUAL_16BIT_ALLOC(
556 src_entry_point,
557 src_this_sbp
558 )
559
560 u32 src_strm_rs_config;
561 u32 src_strm_buf_ptr;
562
563 u32 phiIncr6int_26frac;
564
565 struct dsp_volume_control src_vol_ctrl;
566 };
567
568 struct dsp_decimate_by_pow2_scb {
569 /* decimationFactor = 2, 4, or 8 (larger factors waste too much memory
570 when compared to cascading decimators)
571 */
572 ___DSP_DUAL_16BIT_ALLOC(
573 dec2_coef_base_ptr,
574 dec2_coef_increment
575 )
576
577 /* coefIncrement = 128 / decimationFactor (for our ROM filter)
578 coefBasePtr = 0x8000 (for our ROM filter)
579 */
580 ___DSP_DUAL_16BIT_ALLOC(
581 dec2_in_samples_per_out_triplet,
582 dec2_extra_in_samples
583 )
584 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
585 inSamplesPerOutTriplet = 3 * decimationFactor
586 */
587
588 ___DSP_DUAL_16BIT_ALLOC(
589 dec2_const2_thirds,
590 dec2_half_num_taps_mp5
591 )
592 /* halfNumTapsM5: (1/2 number of taps in decimation filter) minus 5
593 const2thirds: constant 2/3 in 16Q0 format (sign.15)
594 */
595
596 ___DSP_DUAL_16BIT_ALLOC(
597 dec2_output_buf_producer_ptr,
598 dec2_junkdma_mid
599 )
600
601 u32 dec2_reserved2;
602
603 u32 dec2_input_nuf_strm_config;
604 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
605 (buffer size = decimationFactor * 32 dwords)
606 */
607
608 ___DSP_DUAL_16BIT_ALLOC(
609 dec2_phi_incr,
610 dec2_input_buf_consumer_ptr
611 )
612 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter)
613 phiIncr = decimationFactor * 4
614 */
615
616 u32 dec2_reserved3;
617
618 ___DSP_DUAL_16BIT_ALLOC(
619 dec2_exp_vol_change_rate,
620 dec2_input_buf_producer_ptr
621 )
622 /* inputBufProducerPtr: Input buffer write pointer
623 expVolChangeRate: Exponential volume change rate for possible
624 future mixer on input streams
625 */
626
627 ___DSP_DUAL_16BIT_ALLOC(
628 dec2_next_scb,
629 dec2_sub_list_ptr
630 )
631
632 ___DSP_DUAL_16BIT_ALLOC(
633 dec2_entry_point,
634 dec2_this_spb
635 )
636
637 u32 dec2_strm_rs_config;
638 u32 dec2_strm_buf_ptr;
639
640 u32 dec2_reserved4;
641
642 struct dsp_volume_control dec2_vol_ctrl; /* Not used! */
643 };
644
645 struct dsp_vari_decimate_scb {
646 ___DSP_DUAL_16BIT_ALLOC(
647 vdec_frames_left_in_gof,
648 vdec_gofs_left_in_sec
649 )
650
651 ___DSP_DUAL_16BIT_ALLOC(
652 vdec_const2_thirds,
653 vdec_extra_in_samples
654 )
655 /* extraInSamples: # of accumulated, unused input samples (init. to 0)
656 const2thirds: constant 2/3 in 16Q0 format (sign.15) */
657
658 ___DSP_DUAL_16BIT_ALLOC(
659 vdec_cor_per_gof,
660 vdec_correction_per_sec
661 )
662
663 ___DSP_DUAL_16BIT_ALLOC(
664 vdec_output_buf_producer_ptr,
665 vdec_input_buf_consumer_ptr
666 )
667 /* inputBufConsumerPtr: Input buffer read pointer (into SRC filter) */
668 ___DSP_DUAL_16BIT_ALLOC(
669 vdec_gof_length,
670 vdec_gofs_per_sec
671 )
672
673 u32 vdec_input_buf_strm_config;
674 /* inputBufStrmConfig: rsConfig for the input buffer to the decimator
675 (buffer size = 64 dwords) */
676 u32 vdec_coef_increment;
677 /* coefIncrement = - 128.0 / decimationFactor (as a 32Q15 number) */
678
679 u32 vdec_accumphi;
680 /* accumPhi: accumulated fractional phase increment (6.26) */
681
682 ___DSP_DUAL_16BIT_ALLOC(
683 vdec_exp_vol_change_rate,
684 vdec_input_buf_producer_ptr
685 )
686 /* inputBufProducerPtr: Input buffer write pointer
687 expVolChangeRate: Exponential volume change rate for possible
688 future mixer on input streams */
689
690 ___DSP_DUAL_16BIT_ALLOC(
691 vdec_next_scb,
692 vdec_sub_list_ptr
693 )
694
695 ___DSP_DUAL_16BIT_ALLOC(
696 vdec_entry_point,
697 vdec_this_spb
698 )
699
700 u32 vdec_strm_rs_config;
701 u32 vdec_strm_buf_ptr;
702
703 u32 vdec_phi_incr_6int_26frac;
704
705 struct dsp_volume_control vdec_vol_ctrl;
706 };
707
708
709 /* SCB for MIX_TO_OSTREAM algorithm family */
710 struct dsp_mix2_ostream_scb {
711 /* First 13 dwords from generic_scb_t */
712 struct dsp_basic_dma_req basic_req; /* Optional */
713 struct dsp_scatter_gather_ext sg_ext; /* Optional */
714 ___DSP_DUAL_16BIT_ALLOC(
715 next_scb, /* REQUIRED */
716 sub_list_ptr /* REQUIRED */
717 )
718
719 ___DSP_DUAL_16BIT_ALLOC(
720 entry_point, /* REQUIRED */
721 this_spb /* REQUIRED */
722 )
723
724 u32 strm_rs_config; /* REQUIRED */
725 u32 strm_buf_ptr; /* REQUIRED */
726
727
728 /* hi: Number of mixed-down input triplets
729 computed since start of group
730 lo: Number of frames remaining to be
731 processed in the current group of
732 frames
733 */
734 ___DSP_DUAL_16BIT_ALLOC(
735 frames_left_in_group,
736 accum_input_triplets
737 )
738
739 /* hi: Exponential volume change rate
740 for mixer on input streams
741 lo: Number of frames in the group
742 */
743 ___DSP_DUAL_16BIT_ALLOC(
744 frame_group_length,
745 exp_vol_change_rate
746 )
747
748 ___DSP_DUAL_16BIT_ALLOC(
749 const_FFFF,
750 const_zero
751 )
752 };
753
754
755 /* SCB for S16_MIX algorithm */
756 struct dsp_mix_only_scb {
757 /* First 13 dwords from generic_scb_t */
758 struct dsp_basic_dma_req basic_req; /* Optional */
759 struct dsp_scatter_gather_ext sg_ext; /* Optional */
760 ___DSP_DUAL_16BIT_ALLOC(
761 next_scb, /* REQUIRED */
762 sub_list_ptr /* REQUIRED */
763 )
764
765 ___DSP_DUAL_16BIT_ALLOC(
766 entry_point, /* REQUIRED */
767 this_spb /* REQUIRED */
768 )
769
770 u32 strm_rs_config; /* REQUIRED */
771 u32 strm_buf_ptr; /* REQUIRED */
772
773 u32 reserved;
774 struct dsp_volume_control vol_ctrl;
775 };
776
777 /* SCB for the async. CODEC input algorithm */
778 struct dsp_async_codec_input_scb {
779 u32 io_free2;
780
781 u32 io_current_total;
782 u32 io_previous_total;
783
784 u16 io_count;
785 u16 io_count_limit;
786
787 u16 o_fifo_base_addr;
788 u16 ost_mo_format;
789
790 u32 ostrm_rs_config;
791 u32 ostrm_buf_ptr;
792
793 ___DSP_DUAL_16BIT_ALLOC(
794 io_sclks_per_lr_clk,
795 io_io_enable
796 )
797
798 u32 io_free4;
799
800 ___DSP_DUAL_16BIT_ALLOC(
801 io_next_scb,
802 io_sub_list_ptr
803 )
804
805 ___DSP_DUAL_16BIT_ALLOC(
806 io_entry_point,
807 io_this_spb
808 )
809
810 u32 istrm_rs_config;
811 u32 istrm_buf_ptr;
812
813 /* Init. 0000:8042: for ASER1
814 0000:8044: for ASER2 */
815 ___DSP_DUAL_16BIT_ALLOC(
816 io_stat_reg_addr,
817 iofifo_pointer
818 )
819
820 /* Init 1 stero:100 ASER1
821 Init 0 mono:110 ASER2
822 */
823 ___DSP_DUAL_16BIT_ALLOC(
824 ififo_base_addr,
825 ist_mo_format
826 )
827
828 u32 i_free;
829 };
830
831
832 /* SCB for the SP/DIF CODEC input and output */
833 struct dsp_spdifiscb {
834 ___DSP_DUAL_16BIT_ALLOC(
835 status_ptr,
836 status_start_ptr
837 )
838
839 u32 current_total;
840 u32 previous_total;
841
842 ___DSP_DUAL_16BIT_ALLOC(
843 count,
844 count_limit
845 )
846
847 u32 status_data;
848
849 ___DSP_DUAL_16BIT_ALLOC(
850 status,
851 free4
852 )
853
854 u32 free3;
855
856 ___DSP_DUAL_16BIT_ALLOC(
857 free2,
858 bit_count
859 )
860
861 u32 temp_status;
862
863 ___DSP_DUAL_16BIT_ALLOC(
864 next_SCB,
865 sub_list_ptr
866 )
867
868 ___DSP_DUAL_16BIT_ALLOC(
869 entry_point,
870 this_spb
871 )
872
873 u32 strm_rs_config;
874 u32 strm_buf_ptr;
875
876 ___DSP_DUAL_16BIT_ALLOC(
877 stat_reg_addr,
878 fifo_pointer
879 )
880
881 ___DSP_DUAL_16BIT_ALLOC(
882 fifo_base_addr,
883 st_mo_format
884 )
885
886 u32 free1;
887 };
888
889
890 /* SCB for the SP/DIF CODEC input and output */
891 struct dsp_spdifoscb {
892
893 u32 free2;
894
895 u32 free3[4];
896
897 /* Need to be here for compatibility with AsynchFGTxCode */
898 u32 strm_rs_config;
899
900 u32 strm_buf_ptr;
901
902 ___DSP_DUAL_16BIT_ALLOC(
903 status,
904 free5
905 )
906
907 u32 free4;
908
909 ___DSP_DUAL_16BIT_ALLOC(
910 next_scb,
911 sub_list_ptr
912 )
913
914 ___DSP_DUAL_16BIT_ALLOC(
915 entry_point,
916 this_spb
917 )
918
919 u32 free6[2];
920
921 ___DSP_DUAL_16BIT_ALLOC(
922 stat_reg_addr,
923 fifo_pointer
924 )
925
926 ___DSP_DUAL_16BIT_ALLOC(
927 fifo_base_addr,
928 st_mo_format
929 )
930
931 u32 free1;
932 };
933
934
935 struct dsp_asynch_fg_rx_scb {
936 ___DSP_DUAL_16BIT_ALLOC(
937 bot_buf_mask,
938 buf_Mask
939 )
940
941 ___DSP_DUAL_16BIT_ALLOC(
942 max,
943 min
944 )
945
946 ___DSP_DUAL_16BIT_ALLOC(
947 old_producer_pointer,
948 hfg_scb_ptr
949 )
950
951 ___DSP_DUAL_16BIT_ALLOC(
952 delta,
953 adjust_count
954 )
955
956 u32 unused2[5];
957
958 ___DSP_DUAL_16BIT_ALLOC(
959 sibling_ptr,
960 child_ptr
961 )
962
963 ___DSP_DUAL_16BIT_ALLOC(
964 code_ptr,
965 this_ptr
966 )
967
968 u32 strm_rs_config;
969
970 u32 strm_buf_ptr;
971
972 u32 unused_phi_incr;
973
974 ___DSP_DUAL_16BIT_ALLOC(
975 right_targ,
976 left_targ
977 )
978
979 ___DSP_DUAL_16BIT_ALLOC(
980 right_vol,
981 left_vol
982 )
983 };
984
985
986 struct dsp_asynch_fg_tx_scb {
987 ___DSP_DUAL_16BIT_ALLOC(
988 not_buf_mask,
989 buf_mask
990 )
991
992 ___DSP_DUAL_16BIT_ALLOC(
993 max,
994 min
995 )
996
997 ___DSP_DUAL_16BIT_ALLOC(
998 unused1,
999 hfg_scb_ptr
1000 )
1001
1002 ___DSP_DUAL_16BIT_ALLOC(
1003 delta,
1004 adjust_count
1005 )
1006
1007 u32 accum_phi;
1008
1009 ___DSP_DUAL_16BIT_ALLOC(
1010 unused2,
1011 const_one_third
1012 )
1013
1014 u32 unused3[3];
1015
1016 ___DSP_DUAL_16BIT_ALLOC(
1017 sibling_ptr,
1018 child_ptr
1019 )
1020
1021 ___DSP_DUAL_16BIT_ALLOC(
1022 codePtr,
1023 this_ptr
1024 )
1025
1026 u32 strm_rs_config;
1027
1028 u32 strm_buf_ptr;
1029
1030 u32 phi_incr;
1031
1032 ___DSP_DUAL_16BIT_ALLOC(
1033 unused_right_targ,
1034 unused_left_targ
1035 )
1036
1037 ___DSP_DUAL_16BIT_ALLOC(
1038 unused_right_vol,
1039 unused_left_vol
1040 )
1041 };
1042
1043
1044 struct dsp_output_snoop_scb {
1045 /* First 13 dwords from generic_scb_t */
1046 struct dsp_basic_dma_req basic_req; /* Optional */
1047 struct dsp_scatter_gather_ext sg_ext; /* Optional */
1048 ___DSP_DUAL_16BIT_ALLOC(
1049 next_scb, /* REQUIRED */
1050 sub_list_ptr /* REQUIRED */
1051 )
1052
1053 ___DSP_DUAL_16BIT_ALLOC(
1054 entry_point, /* REQUIRED */
1055 this_spb /* REQUIRED */
1056 )
1057
1058 u32 strm_rs_config; /* REQUIRED */
1059 u32 strm_buf_ptr; /* REQUIRED */
1060
1061 ___DSP_DUAL_16BIT_ALLOC(
1062 init_snoop_input_link,
1063 snoop_child_input_scb
1064 )
1065
1066 u32 snoop_input_buf_ptr;
1067
1068 ___DSP_DUAL_16BIT_ALLOC(
1069 reserved,
1070 input_scb
1071 )
1072 };
1073
1074 struct dsp_spio_write_scb {
1075 ___DSP_DUAL_16BIT_ALLOC(
1076 address1,
1077 address2
1078 )
1079
1080 u32 data1;
1081
1082 u32 data2;
1083
1084 ___DSP_DUAL_16BIT_ALLOC(
1085 address3,
1086 address4
1087 )
1088
1089 u32 data3;
1090
1091 u32 data4;
1092
1093 ___DSP_DUAL_16BIT_ALLOC(
1094 unused1,
1095 data_ptr
1096 )
1097
1098 u32 unused2[2];
1099
1100 ___DSP_DUAL_16BIT_ALLOC(
1101 sibling_ptr,
1102 child_ptr
1103 )
1104
1105 ___DSP_DUAL_16BIT_ALLOC(
1106 entry_point,
1107 this_ptr
1108 )
1109
1110 u32 unused3[5];
1111 };
1112
1113 struct dsp_magic_snoop_task {
1114 u32 i0;
1115 u32 i1;
1116
1117 u32 strm_buf_ptr1;
1118
1119 u16 i2;
1120 u16 snoop_scb;
1121
1122 u32 i3;
1123 u32 i4;
1124 u32 i5;
1125 u32 i6;
1126
1127 u32 i7;
1128
1129 ___DSP_DUAL_16BIT_ALLOC(
1130 next_scb,
1131 sub_list_ptr
1132 )
1133
1134 ___DSP_DUAL_16BIT_ALLOC(
1135 entry_point,
1136 this_ptr
1137 )
1138
1139 u32 strm_buf_config;
1140 u32 strm_buf_ptr2;
1141
1142 u32 i8;
1143
1144 struct dsp_volume_control vdec_vol_ctrl;
1145 };
1146
1147
1148 struct dsp_filter_scb {
1149 ___DSP_DUAL_16BIT_ALLOC(
1150 a0_right, /* 0x00 */
1151 a0_left
1152 )
1153 ___DSP_DUAL_16BIT_ALLOC(
1154 a1_right, /* 0x01 */
1155 a1_left
1156 )
1157 ___DSP_DUAL_16BIT_ALLOC(
1158 a2_right, /* 0x02 */
1159 a2_left
1160 )
1161 ___DSP_DUAL_16BIT_ALLOC(
1162 output_buf_ptr, /* 0x03 */
1163 init
1164 )
1165
1166 ___DSP_DUAL_16BIT_ALLOC(
1167 filter_unused3, /* 0x04 */
1168 filter_unused2
1169 )
1170
1171 u32 prev_sample_output1; /* 0x05 */
1172 u32 prev_sample_output2; /* 0x06 */
1173 u32 prev_sample_input1; /* 0x07 */
1174 u32 prev_sample_input2; /* 0x08 */
1175
1176 ___DSP_DUAL_16BIT_ALLOC(
1177 next_scb_ptr, /* 0x09 */
1178 sub_list_ptr
1179 )
1180
1181 ___DSP_DUAL_16BIT_ALLOC(
1182 entry_point, /* 0x0A */
1183 spb_ptr
1184 )
1185
1186 u32 strm_rs_config; /* 0x0B */
1187 u32 strm_buf_ptr; /* 0x0C */
1188
1189 ___DSP_DUAL_16BIT_ALLOC(
1190 b0_right, /* 0x0D */
1191 b0_left
1192 )
1193 ___DSP_DUAL_16BIT_ALLOC(
1194 b1_right, /* 0x0E */
1195 b1_left
1196 )
1197 ___DSP_DUAL_16BIT_ALLOC(
1198 b2_right, /* 0x0F */
1199 b2_left
1200 )
1201 };
1202 #endif /* __DSP_SCB_TYPES_H__ */
Tomato firmware and modifications.