2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
10 #include <linux/irq.h>
11 #include <linux/slab.h>
13 static void urb_free_priv (struct ohci_hcd
*hc
, urb_priv_t
*urb_priv
)
15 int last
= urb_priv
->length
- 1;
21 for (i
= 0; i
<= last
; i
++) {
22 td
= urb_priv
->td
[i
];
28 list_del (&urb_priv
->pending
);
32 /*-------------------------------------------------------------------------*/
35 * URB goes back to driver, and isn't reissued.
36 * It's completely gone from HC data structures.
37 * PRECONDITION: ohci lock held, irqs blocked.
40 finish_urb(struct ohci_hcd
*ohci
, struct urb
*urb
, int status
)
41 __releases(ohci
->lock
)
42 __acquires(ohci
->lock
)
44 // ASSERT (urb->hcpriv != 0);
46 urb_free_priv (ohci
, urb
->hcpriv
);
47 if (likely(status
== -EINPROGRESS
))
50 switch (usb_pipetype (urb
->pipe
)) {
51 case PIPE_ISOCHRONOUS
:
52 ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
--;
53 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
54 if (quirk_amdiso(ohci
))
56 if (quirk_amdprefetch(ohci
))
57 sb800_prefetch(ohci
, 0);
61 ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
--;
65 #ifdef OHCI_VERBOSE_DEBUG
66 urb_print(urb
, "RET", usb_pipeout (urb
->pipe
), status
);
69 /* urb->complete() can reenter this HCD */
70 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci
), urb
);
71 spin_unlock (&ohci
->lock
);
72 usb_hcd_giveback_urb(ohci_to_hcd(ohci
), urb
, status
);
73 spin_lock (&ohci
->lock
);
75 /* stop periodic dma if it's not needed */
76 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0
77 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0) {
78 ohci
->hc_control
&= ~(OHCI_CTRL_PLE
|OHCI_CTRL_IE
);
79 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
84 /*-------------------------------------------------------------------------*
85 * ED handling functions
86 *-------------------------------------------------------------------------*/
88 /* search for the right schedule branch to use for a periodic ed.
89 * does some load balancing; returns the branch, or negative errno.
91 static int balance (struct ohci_hcd
*ohci
, int interval
, int load
)
93 int i
, branch
= -ENOSPC
;
95 /* iso periods can be huge; iso tds specify frame numbers */
96 if (interval
> NUM_INTS
)
99 /* search for the least loaded schedule branch of that period
100 * that has enough bandwidth left unreserved.
102 for (i
= 0; i
< interval
; i
++) {
103 if (branch
< 0 || ohci
->load
[branch
] > ohci
->load
[i
]) {
106 /* usb 1.1 says 90% of one frame */
107 for (j
= i
; j
< NUM_INTS
; j
+= interval
) {
108 if ((ohci
->load
[j
] + load
) > 900)
119 /*-------------------------------------------------------------------------*/
121 /* both iso and interrupt requests have periods; this routine puts them
122 * into the schedule tree in the apppropriate place. most iso devices use
123 * 1msec periods, but that's not required.
125 static void periodic_link (struct ohci_hcd
*ohci
, struct ed
*ed
)
129 ohci_vdbg (ohci
, "link %sed %p branch %d [%dus.], interval %d\n",
130 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
131 ed
, ed
->branch
, ed
->load
, ed
->interval
);
133 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
134 struct ed
**prev
= &ohci
->periodic
[i
];
135 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
136 struct ed
*here
= *prev
;
138 /* sorting each branch by period (slow before fast)
139 * lets us share the faster parts of the tree.
140 * (plus maybe: put interrupt eds before iso)
142 while (here
&& ed
!= here
) {
143 if (ed
->interval
> here
->interval
)
145 prev
= &here
->ed_next
;
146 prev_p
= &here
->hwNextED
;
152 ed
->hwNextED
= *prev_p
;
155 *prev_p
= cpu_to_hc32(ohci
, ed
->dma
);
158 ohci
->load
[i
] += ed
->load
;
160 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
+= ed
->load
/ ed
->interval
;
163 /* link an ed into one of the HC chains */
165 static int ed_schedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
173 if (quirk_zfmicro(ohci
)
174 && (ed
->type
== PIPE_INTERRUPT
)
175 && !(ohci
->eds_scheduled
++))
176 mod_timer(&ohci
->unlink_watchdog
, round_jiffies(jiffies
+ HZ
));
179 /* we care about rm_list when setting CLE/BLE in case the HC was at
180 * work on some TD when CLE/BLE was turned off, and isn't quiesced
181 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
183 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
184 * periodic ones are singly linked (ed_next). that's because the
185 * periodic schedule encodes a tree like figure 3-5 in the ohci
186 * spec: each qh can have several "previous" nodes, and the tree
187 * doesn't have unused/idle descriptors.
191 if (ohci
->ed_controltail
== NULL
) {
192 WARN_ON (ohci
->hc_control
& OHCI_CTRL_CLE
);
193 ohci_writel (ohci
, ed
->dma
,
194 &ohci
->regs
->ed_controlhead
);
196 ohci
->ed_controltail
->ed_next
= ed
;
197 ohci
->ed_controltail
->hwNextED
= cpu_to_hc32 (ohci
,
200 ed
->ed_prev
= ohci
->ed_controltail
;
201 if (!ohci
->ed_controltail
&& !ohci
->ed_rm_list
) {
203 ohci
->hc_control
|= OHCI_CTRL_CLE
;
204 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlcurrent
);
205 ohci_writel (ohci
, ohci
->hc_control
,
206 &ohci
->regs
->control
);
208 ohci
->ed_controltail
= ed
;
212 if (ohci
->ed_bulktail
== NULL
) {
213 WARN_ON (ohci
->hc_control
& OHCI_CTRL_BLE
);
214 ohci_writel (ohci
, ed
->dma
, &ohci
->regs
->ed_bulkhead
);
216 ohci
->ed_bulktail
->ed_next
= ed
;
217 ohci
->ed_bulktail
->hwNextED
= cpu_to_hc32 (ohci
,
220 ed
->ed_prev
= ohci
->ed_bulktail
;
221 if (!ohci
->ed_bulktail
&& !ohci
->ed_rm_list
) {
223 ohci
->hc_control
|= OHCI_CTRL_BLE
;
224 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkcurrent
);
225 ohci_writel (ohci
, ohci
->hc_control
,
226 &ohci
->regs
->control
);
228 ohci
->ed_bulktail
= ed
;
231 // case PIPE_INTERRUPT:
232 // case PIPE_ISOCHRONOUS:
234 branch
= balance (ohci
, ed
->interval
, ed
->load
);
237 "ERR %d, interval %d msecs, load %d\n",
238 branch
, ed
->interval
, ed
->load
);
242 periodic_link (ohci
, ed
);
245 /* the HC may not see the schedule updates yet, but if it does
246 * then they'll be properly ordered.
251 /*-------------------------------------------------------------------------*/
253 /* scan the periodic table to find and unlink this ED */
254 static void periodic_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
258 for (i
= ed
->branch
; i
< NUM_INTS
; i
+= ed
->interval
) {
260 struct ed
**prev
= &ohci
->periodic
[i
];
261 __hc32
*prev_p
= &ohci
->hcca
->int_table
[i
];
263 while (*prev
&& (temp
= *prev
) != ed
) {
264 prev_p
= &temp
->hwNextED
;
265 prev
= &temp
->ed_next
;
268 *prev_p
= ed
->hwNextED
;
271 ohci
->load
[i
] -= ed
->load
;
273 ohci_to_hcd(ohci
)->self
.bandwidth_allocated
-= ed
->load
/ ed
->interval
;
275 ohci_vdbg (ohci
, "unlink %sed %p branch %d [%dus.], interval %d\n",
276 (ed
->hwINFO
& cpu_to_hc32 (ohci
, ED_ISO
)) ? "iso " : "",
277 ed
, ed
->branch
, ed
->load
, ed
->interval
);
280 /* unlink an ed from one of the HC chains.
281 * just the link to the ed is unlinked.
282 * the link from the ed still points to another operational ed or 0
283 * so the HC can eventually finish the processing of the unlinked ed
284 * (assuming it already started that, which needn't be true).
286 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
287 * it won't. ED_SKIP means the HC will finish its current transaction,
288 * but won't start anything new. The TD queue may still grow; device
289 * drivers don't know about this HCD-internal state.
291 * When the HC can't see the ED, something changes ED_UNLINK to one of:
293 * - ED_OPER: when there's any request queued, the ED gets rescheduled
294 * immediately. HC should be working on them.
296 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
297 * to care about this ED; safe to disable the endpoint.
299 * When finish_unlinks() runs later, after SOF interrupt, it will often
300 * complete one or more URB unlinks before making that state change.
302 static void ed_deschedule (struct ohci_hcd
*ohci
, struct ed
*ed
)
304 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
306 ed
->state
= ED_UNLINK
;
308 /* To deschedule something from the control or bulk list, just
309 * clear CLE/BLE and wait. There's no safe way to scrub out list
310 * head/current registers until later, and "later" isn't very
311 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
312 * the HC is reading the ED queues (while we modify them).
314 * For now, ed_schedule() is "later". It might be good paranoia
315 * to scrub those registers in finish_unlinks(), in case of bugs
316 * that make the HC try to use them.
320 /* remove ED from the HC's list: */
321 if (ed
->ed_prev
== NULL
) {
323 ohci
->hc_control
&= ~OHCI_CTRL_CLE
;
324 ohci_writel (ohci
, ohci
->hc_control
,
325 &ohci
->regs
->control
);
326 // a ohci_readl() later syncs CLE with the HC
329 hc32_to_cpup (ohci
, &ed
->hwNextED
),
330 &ohci
->regs
->ed_controlhead
);
332 ed
->ed_prev
->ed_next
= ed
->ed_next
;
333 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
335 /* remove ED from the HCD's list: */
336 if (ohci
->ed_controltail
== ed
) {
337 ohci
->ed_controltail
= ed
->ed_prev
;
338 if (ohci
->ed_controltail
)
339 ohci
->ed_controltail
->ed_next
= NULL
;
340 } else if (ed
->ed_next
) {
341 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
346 /* remove ED from the HC's list: */
347 if (ed
->ed_prev
== NULL
) {
349 ohci
->hc_control
&= ~OHCI_CTRL_BLE
;
350 ohci_writel (ohci
, ohci
->hc_control
,
351 &ohci
->regs
->control
);
352 // a ohci_readl() later syncs BLE with the HC
355 hc32_to_cpup (ohci
, &ed
->hwNextED
),
356 &ohci
->regs
->ed_bulkhead
);
358 ed
->ed_prev
->ed_next
= ed
->ed_next
;
359 ed
->ed_prev
->hwNextED
= ed
->hwNextED
;
361 /* remove ED from the HCD's list: */
362 if (ohci
->ed_bulktail
== ed
) {
363 ohci
->ed_bulktail
= ed
->ed_prev
;
364 if (ohci
->ed_bulktail
)
365 ohci
->ed_bulktail
->ed_next
= NULL
;
366 } else if (ed
->ed_next
) {
367 ed
->ed_next
->ed_prev
= ed
->ed_prev
;
371 // case PIPE_INTERRUPT:
372 // case PIPE_ISOCHRONOUS:
374 periodic_unlink (ohci
, ed
);
380 /*-------------------------------------------------------------------------*/
382 /* get and maybe (re)init an endpoint. init _should_ be done only as part
383 * of enumeration, usb_set_configuration() or usb_set_interface().
385 static struct ed
*ed_get (
386 struct ohci_hcd
*ohci
,
387 struct usb_host_endpoint
*ep
,
388 struct usb_device
*udev
,
395 spin_lock_irqsave (&ohci
->lock
, flags
);
397 if (!(ed
= ep
->hcpriv
)) {
402 ed
= ed_alloc (ohci
, GFP_ATOMIC
);
408 /* dummy td; end of td list for ed */
409 td
= td_alloc (ohci
, GFP_ATOMIC
);
417 ed
->hwTailP
= cpu_to_hc32 (ohci
, td
->td_dma
);
418 ed
->hwHeadP
= ed
->hwTailP
; /* ED_C, ED_H zeroed */
421 is_out
= !(ep
->desc
.bEndpointAddress
& USB_DIR_IN
);
423 info
= usb_pipedevice (pipe
);
424 ed
->type
= usb_pipetype(pipe
);
426 info
|= (ep
->desc
.bEndpointAddress
& ~USB_DIR_IN
) << 7;
427 info
|= le16_to_cpu(ep
->desc
.wMaxPacketSize
) << 16;
428 if (udev
->speed
== USB_SPEED_LOW
)
430 /* only control transfers store pids in tds */
431 if (ed
->type
!= PIPE_CONTROL
) {
432 info
|= is_out
? ED_OUT
: ED_IN
;
433 if (ed
->type
!= PIPE_BULK
) {
434 /* periodic transfers... */
435 if (ed
->type
== PIPE_ISOCHRONOUS
)
437 else if (interval
> 32) /* iso can be bigger */
439 ed
->interval
= interval
;
440 ed
->load
= usb_calc_bus_time (
441 udev
->speed
, !is_out
,
442 ed
->type
== PIPE_ISOCHRONOUS
,
443 le16_to_cpu(ep
->desc
.wMaxPacketSize
))
447 ed
->hwINFO
= cpu_to_hc32(ohci
, info
);
453 spin_unlock_irqrestore (&ohci
->lock
, flags
);
457 /*-------------------------------------------------------------------------*/
459 /* request unlinking of an endpoint from an operational HC.
460 * put the ep on the rm_list
461 * real work is done at the next start frame (SF) hardware interrupt
462 * caller guarantees HCD is running, so hardware access is safe,
463 * and that ed->state is ED_OPER
465 static void start_ed_unlink (struct ohci_hcd
*ohci
, struct ed
*ed
)
467 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_DEQUEUE
);
468 ed_deschedule (ohci
, ed
);
470 /* rm_list is just singly linked, for simplicity */
471 ed
->ed_next
= ohci
->ed_rm_list
;
473 ohci
->ed_rm_list
= ed
;
475 /* enable SOF interrupt */
476 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrstatus
);
477 ohci_writel (ohci
, OHCI_INTR_SF
, &ohci
->regs
->intrenable
);
478 // flush those writes, and get latest HCCA contents
479 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
481 /* SF interrupt might get delayed; record the frame counter value that
482 * indicates when the HC isn't looking at it, so concurrent unlinks
483 * behave. frame_no wraps every 2^16 msec, and changes right before
486 ed
->tick
= ohci_frame_no(ohci
) + 1;
490 /*-------------------------------------------------------------------------*
491 * TD handling functions
492 *-------------------------------------------------------------------------*/
494 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
497 td_fill (struct ohci_hcd
*ohci
, u32 info
,
498 dma_addr_t data
, int len
,
499 struct urb
*urb
, int index
)
501 struct td
*td
, *td_pt
;
502 struct urb_priv
*urb_priv
= urb
->hcpriv
;
503 int is_iso
= info
& TD_ISO
;
506 // ASSERT (index < urb_priv->length);
508 /* aim for only one interrupt per urb. mostly applies to control
509 * and iso; other urbs rarely need more than one TD per urb.
510 * this way, only final tds (or ones with an error) cause IRQs.
511 * at least immediately; use DI=6 in case any control request is
512 * tempted to die part way through. (and to force the hc to flush
513 * its donelist soonish, even on unlink paths.)
515 * NOTE: could delay interrupts even for the last TD, and get fewer
516 * interrupts ... increasing per-urb latency by sharing interrupts.
517 * Drivers that queue bulk urbs may request that behavior.
519 if (index
!= (urb_priv
->length
- 1)
520 || (urb
->transfer_flags
& URB_NO_INTERRUPT
))
521 info
|= TD_DI_SET (6);
523 /* use this td as the next dummy */
524 td_pt
= urb_priv
->td
[index
];
526 /* fill the old dummy TD */
527 td
= urb_priv
->td
[index
] = urb_priv
->ed
->dummy
;
528 urb_priv
->ed
->dummy
= td_pt
;
530 td
->ed
= urb_priv
->ed
;
531 td
->next_dl_td
= NULL
;
538 td
->hwINFO
= cpu_to_hc32 (ohci
, info
);
540 td
->hwCBP
= cpu_to_hc32 (ohci
, data
& 0xFFFFF000);
541 *ohci_hwPSWp(ohci
, td
, 0) = cpu_to_hc16 (ohci
,
542 (data
& 0x0FFF) | 0xE000);
543 td
->ed
->last_iso
= info
& 0xffff;
545 td
->hwCBP
= cpu_to_hc32 (ohci
, data
);
548 td
->hwBE
= cpu_to_hc32 (ohci
, data
+ len
- 1);
551 td
->hwNextTD
= cpu_to_hc32 (ohci
, td_pt
->td_dma
);
553 /* append to queue */
554 list_add_tail (&td
->td_list
, &td
->ed
->td_list
);
556 /* hash it for later reverse mapping */
557 hash
= TD_HASH_FUNC (td
->td_dma
);
558 td
->td_hash
= ohci
->td_hash
[hash
];
559 ohci
->td_hash
[hash
] = td
;
561 /* HC might read the TD (or cachelines) right away ... */
563 td
->ed
->hwTailP
= td
->hwNextTD
;
566 /*-------------------------------------------------------------------------*/
568 /* Prepare all TDs of a transfer, and queue them onto the ED.
569 * Caller guarantees HC is active.
570 * Usually the ED is already on the schedule, so TDs might be
571 * processed as soon as they're queued.
573 static void td_submit_urb (
574 struct ohci_hcd
*ohci
,
577 struct urb_priv
*urb_priv
= urb
->hcpriv
;
579 int data_len
= urb
->transfer_buffer_length
;
582 int is_out
= usb_pipeout (urb
->pipe
);
585 /* OHCI handles the bulk/interrupt data toggles itself. We just
586 * use the device toggle bits for resetting, and rely on the fact
587 * that resetting toggle is meaningless if the endpoint is active.
589 if (!usb_gettoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
), is_out
)) {
590 usb_settoggle (urb
->dev
, usb_pipeendpoint (urb
->pipe
),
592 urb_priv
->ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_C
);
595 urb_priv
->td_cnt
= 0;
596 list_add (&urb_priv
->pending
, &ohci
->pending
);
599 data
= urb
->transfer_dma
;
603 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
604 * using TD_CC_GET, as well as by seeing them on the done list.
605 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
607 switch (urb_priv
->ed
->type
) {
609 /* Bulk and interrupt are identical except for where in the schedule
613 /* ... and periodic urbs have extra accounting */
614 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
++ == 0
615 && ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0;
619 ? TD_T_TOGGLE
| TD_CC
| TD_DP_OUT
620 : TD_T_TOGGLE
| TD_CC
| TD_DP_IN
;
621 /* TDs _could_ transfer up to 8K each */
622 while (data_len
> 4096) {
623 td_fill (ohci
, info
, data
, 4096, urb
, cnt
);
628 /* maybe avoid ED halt on final TD short read */
629 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
631 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
);
633 if ((urb
->transfer_flags
& URB_ZERO_PACKET
)
634 && cnt
< urb_priv
->length
) {
635 td_fill (ohci
, info
, 0, 0, urb
, cnt
);
638 /* maybe kickstart bulk list */
639 if (urb_priv
->ed
->type
== PIPE_BULK
) {
641 ohci_writel (ohci
, OHCI_BLF
, &ohci
->regs
->cmdstatus
);
645 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
646 * any DATA phase works normally, and the STATUS ack is special.
649 info
= TD_CC
| TD_DP_SETUP
| TD_T_DATA0
;
650 td_fill (ohci
, info
, urb
->setup_dma
, 8, urb
, cnt
++);
652 info
= TD_CC
| TD_R
| TD_T_DATA1
;
653 info
|= is_out
? TD_DP_OUT
: TD_DP_IN
;
654 /* NOTE: mishandles transfers >8K, some >4K */
655 td_fill (ohci
, info
, data
, data_len
, urb
, cnt
++);
657 info
= (is_out
|| data_len
== 0)
658 ? TD_CC
| TD_DP_IN
| TD_T_DATA1
659 : TD_CC
| TD_DP_OUT
| TD_T_DATA1
;
660 td_fill (ohci
, info
, data
, 0, urb
, cnt
++);
661 /* maybe kickstart control list */
663 ohci_writel (ohci
, OHCI_CLF
, &ohci
->regs
->cmdstatus
);
666 /* ISO has no retransmit, so no toggle; and it uses special TDs.
667 * Each TD could handle multiple consecutive frames (interval 1);
668 * we could often reduce the number of TDs here.
670 case PIPE_ISOCHRONOUS
:
671 for (cnt
= 0; cnt
< urb
->number_of_packets
; cnt
++) {
672 int frame
= urb
->start_frame
;
674 // roll-around ... exotic case (and OHCI has
675 // a 2^16 iso range, vs other HCs max of 2^10)
676 frame
+= cnt
* urb
->interval
;
678 td_fill (ohci
, TD_CC
| TD_ISO
| frame
,
679 data
+ urb
->iso_frame_desc
[cnt
].offset
,
680 urb
->iso_frame_desc
[cnt
].length
, urb
, cnt
);
682 if (ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
== 0) {
683 if (quirk_amdiso(ohci
))
685 if (quirk_amdprefetch(ohci
))
686 sb800_prefetch(ohci
, 1);
688 periodic
= ohci_to_hcd(ohci
)->self
.bandwidth_isoc_reqs
++ == 0
689 && ohci_to_hcd(ohci
)->self
.bandwidth_int_reqs
== 0;
693 /* start periodic dma if needed */
696 ohci
->hc_control
|= OHCI_CTRL_PLE
|OHCI_CTRL_IE
;
697 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
700 // ASSERT (urb_priv->length == cnt);
703 /*-------------------------------------------------------------------------*
704 * Done List handling functions
705 *-------------------------------------------------------------------------*/
707 /* calculate transfer length/status and update the urb */
708 static int td_done(struct ohci_hcd
*ohci
, struct urb
*urb
, struct td
*td
)
710 u32 tdINFO
= hc32_to_cpup (ohci
, &td
->hwINFO
);
712 int status
= -EINPROGRESS
;
714 list_del (&td
->td_list
);
716 /* ISO ... drivers see per-TD length/status */
717 if (tdINFO
& TD_ISO
) {
718 u16 tdPSW
= ohci_hwPSW(ohci
, td
, 0);
721 /* NOTE: assumes FC in tdINFO == 0, and that
722 * only the first of 0..MAXPSW psws is used.
725 cc
= (tdPSW
>> 12) & 0xF;
726 if (tdINFO
& TD_CC
) /* hc didn't touch? */
729 if (usb_pipeout (urb
->pipe
))
730 dlen
= urb
->iso_frame_desc
[td
->index
].length
;
732 /* short reads are always OK for ISO */
733 if (cc
== TD_DATAUNDERRUN
)
735 dlen
= tdPSW
& 0x3ff;
737 urb
->actual_length
+= dlen
;
738 urb
->iso_frame_desc
[td
->index
].actual_length
= dlen
;
739 urb
->iso_frame_desc
[td
->index
].status
= cc_to_error
[cc
];
741 if (cc
!= TD_CC_NOERROR
)
743 "urb %p iso td %p (%d) len %d cc %d\n",
744 urb
, td
, 1 + td
->index
, dlen
, cc
);
746 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
747 * except that "setup" bytes aren't counted and "short" transfers
748 * might not be reported as errors.
751 int type
= usb_pipetype (urb
->pipe
);
752 u32 tdBE
= hc32_to_cpup (ohci
, &td
->hwBE
);
754 cc
= TD_CC_GET (tdINFO
);
756 /* update packet status if needed (short is normally ok) */
757 if (cc
== TD_DATAUNDERRUN
758 && !(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
760 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
761 status
= cc_to_error
[cc
];
763 /* count all non-empty packets except control SETUP packet */
764 if ((type
!= PIPE_CONTROL
|| td
->index
!= 0) && tdBE
!= 0) {
766 urb
->actual_length
+= tdBE
- td
->data_dma
+ 1;
768 urb
->actual_length
+=
769 hc32_to_cpup (ohci
, &td
->hwCBP
)
773 if (cc
!= TD_CC_NOERROR
&& cc
< 0x0E)
775 "urb %p td %p (%d) cc %d, len=%d/%d\n",
776 urb
, td
, 1 + td
->index
, cc
,
778 urb
->transfer_buffer_length
);
783 /*-------------------------------------------------------------------------*/
785 static void ed_halted(struct ohci_hcd
*ohci
, struct td
*td
, int cc
)
787 struct urb
*urb
= td
->urb
;
788 urb_priv_t
*urb_priv
= urb
->hcpriv
;
789 struct ed
*ed
= td
->ed
;
790 struct list_head
*tmp
= td
->td_list
.next
;
791 __hc32 toggle
= ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_C
);
793 /* clear ed halt; this is the td that caused it, but keep it inactive
794 * until its urb->complete() has a chance to clean up.
796 ed
->hwINFO
|= cpu_to_hc32 (ohci
, ED_SKIP
);
798 ed
->hwHeadP
&= ~cpu_to_hc32 (ohci
, ED_H
);
800 /* Get rid of all later tds from this urb. We don't have
801 * to be careful: no errors and nothing was transferred.
802 * Also patch the ed so it looks as if those tds completed normally.
804 while (tmp
!= &ed
->td_list
) {
807 next
= list_entry (tmp
, struct td
, td_list
);
808 tmp
= next
->td_list
.next
;
810 if (next
->urb
!= urb
)
813 /* NOTE: if multi-td control DATA segments get supported,
814 * this urb had one of them, this td wasn't the last td
815 * in that segment (TD_R clear), this ed halted because
816 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
817 * then we need to leave the control STATUS packet queued
821 list_del(&next
->td_list
);
823 ed
->hwHeadP
= next
->hwNextTD
| toggle
;
826 /* help for troubleshooting: report anything that
827 * looks odd ... that doesn't include protocol stalls
828 * (or maybe some other things)
831 case TD_DATAUNDERRUN
:
832 if ((urb
->transfer_flags
& URB_SHORT_NOT_OK
) == 0)
836 if (usb_pipecontrol (urb
->pipe
))
841 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
842 urb
, urb
->dev
->devpath
,
843 usb_pipeendpoint (urb
->pipe
),
844 usb_pipein (urb
->pipe
) ? "in" : "out",
845 hc32_to_cpu (ohci
, td
->hwINFO
),
846 cc
, cc_to_error
[cc
]);
850 /* replies to the request have to be on a FIFO basis so
851 * we unreverse the hc-reversed done-list
853 static struct td
*dl_reverse_done_list (struct ohci_hcd
*ohci
)
856 struct td
*td_rev
= NULL
;
857 struct td
*td
= NULL
;
859 td_dma
= hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
);
860 ohci
->hcca
->done_head
= 0;
863 /* get TD from hc's singly linked list, and
864 * prepend to ours. ed->td_list changes later.
869 td
= dma_to_td (ohci
, td_dma
);
871 ohci_err (ohci
, "bad entry %8x\n", td_dma
);
875 td
->hwINFO
|= cpu_to_hc32 (ohci
, TD_DONE
);
876 cc
= TD_CC_GET (hc32_to_cpup (ohci
, &td
->hwINFO
));
878 /* Non-iso endpoints can halt on error; un-halt,
879 * and dequeue any other TDs from this urb.
880 * No other TD could have caused the halt.
882 if (cc
!= TD_CC_NOERROR
883 && (td
->ed
->hwHeadP
& cpu_to_hc32 (ohci
, ED_H
)))
884 ed_halted(ohci
, td
, cc
);
886 td
->next_dl_td
= td_rev
;
888 td_dma
= hc32_to_cpup (ohci
, &td
->hwNextTD
);
893 /*-------------------------------------------------------------------------*/
895 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
897 finish_unlinks (struct ohci_hcd
*ohci
, u16 tick
)
899 struct ed
*ed
, **last
;
902 for (last
= &ohci
->ed_rm_list
, ed
= *last
; ed
!= NULL
; ed
= *last
) {
903 struct list_head
*entry
, *tmp
;
904 int completed
, modified
;
907 /* only take off EDs that the HC isn't using, accounting for
908 * frame counter wraps and EDs with partially retired TDs
910 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci
)->state
))) {
911 if (tick_before (tick
, ed
->tick
)) {
917 if (!list_empty (&ed
->td_list
)) {
921 td
= list_entry (ed
->td_list
.next
, struct td
,
923 head
= hc32_to_cpu (ohci
, ed
->hwHeadP
) &
926 /* INTR_WDH may need to clean up first */
927 if (td
->td_dma
!= head
) {
928 if (ed
== ohci
->ed_to_check
)
929 ohci
->ed_to_check
= NULL
;
936 /* reentrancy: if we drop the schedule lock, someone might
937 * have modified this list. normally it's just prepending
938 * entries (which we'd ignore), but paranoia won't hurt.
944 /* unlink urbs as requested, but rescan the list after
945 * we call a completion since it might have unlinked
946 * another (earlier) urb
948 * When we get here, the HC doesn't see this ed. But it
949 * must not be rescheduled until all completed URBs have
950 * been given back to the driver.
955 list_for_each_safe (entry
, tmp
, &ed
->td_list
) {
958 urb_priv_t
*urb_priv
;
962 td
= list_entry (entry
, struct td
, td_list
);
964 urb_priv
= td
->urb
->hcpriv
;
966 if (!urb
->unlinked
) {
967 prev
= &td
->hwNextTD
;
971 /* patch pointer hc uses */
972 savebits
= *prev
& ~cpu_to_hc32 (ohci
, TD_MASK
);
973 *prev
= td
->hwNextTD
| savebits
;
975 /* If this was unlinked, the TD may not have been
976 * retired ... so manually save the data toggle.
977 * The controller ignores the value we save for
978 * control and ISO endpoints.
980 tdINFO
= hc32_to_cpup(ohci
, &td
->hwINFO
);
981 if ((tdINFO
& TD_T
) == TD_T_DATA0
)
982 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_C
);
983 else if ((tdINFO
& TD_T
) == TD_T_DATA1
)
984 ed
->hwHeadP
|= cpu_to_hc32(ohci
, ED_C
);
986 /* HC may have partly processed this TD */
987 td_done (ohci
, urb
, td
);
990 /* if URB is done, clean up */
991 if (urb_priv
->td_cnt
== urb_priv
->length
) {
992 modified
= completed
= 1;
993 finish_urb(ohci
, urb
, 0);
996 if (completed
&& !list_empty (&ed
->td_list
))
999 /* ED's now officially unlinked, hc doesn't see */
1000 ed
->state
= ED_IDLE
;
1001 if (quirk_zfmicro(ohci
) && ed
->type
== PIPE_INTERRUPT
)
1002 ohci
->eds_scheduled
--;
1003 ed
->hwHeadP
&= ~cpu_to_hc32(ohci
, ED_H
);
1006 ed
->hwINFO
&= ~cpu_to_hc32 (ohci
, ED_SKIP
| ED_DEQUEUE
);
1008 /* but if there's work queued, reschedule */
1009 if (!list_empty (&ed
->td_list
)) {
1010 if (HC_IS_RUNNING(ohci_to_hcd(ohci
)->state
))
1011 ed_schedule (ohci
, ed
);
1018 /* maybe reenable control and bulk lists */
1019 if (HC_IS_RUNNING(ohci_to_hcd(ohci
)->state
)
1020 && ohci_to_hcd(ohci
)->state
!= HC_STATE_QUIESCING
1021 && !ohci
->ed_rm_list
) {
1022 u32 command
= 0, control
= 0;
1024 if (ohci
->ed_controltail
) {
1025 command
|= OHCI_CLF
;
1026 if (quirk_zfmicro(ohci
))
1028 if (!(ohci
->hc_control
& OHCI_CTRL_CLE
)) {
1029 control
|= OHCI_CTRL_CLE
;
1030 ohci_writel (ohci
, 0,
1031 &ohci
->regs
->ed_controlcurrent
);
1034 if (ohci
->ed_bulktail
) {
1035 command
|= OHCI_BLF
;
1036 if (quirk_zfmicro(ohci
))
1038 if (!(ohci
->hc_control
& OHCI_CTRL_BLE
)) {
1039 control
|= OHCI_CTRL_BLE
;
1040 ohci_writel (ohci
, 0,
1041 &ohci
->regs
->ed_bulkcurrent
);
1045 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1047 ohci
->hc_control
|= control
;
1048 if (quirk_zfmicro(ohci
))
1050 ohci_writel (ohci
, ohci
->hc_control
,
1051 &ohci
->regs
->control
);
1054 if (quirk_zfmicro(ohci
))
1056 ohci_writel (ohci
, command
, &ohci
->regs
->cmdstatus
);
1063 /*-------------------------------------------------------------------------*/
1066 * Used to take back a TD from the host controller. This would normally be
1067 * called from within dl_done_list, however it may be called directly if the
1068 * HC no longer sees the TD and it has not appeared on the donelist (after
1069 * two frames). This bug has been observed on ZF Micro systems.
1071 static void takeback_td(struct ohci_hcd
*ohci
, struct td
*td
)
1073 struct urb
*urb
= td
->urb
;
1074 urb_priv_t
*urb_priv
= urb
->hcpriv
;
1075 struct ed
*ed
= td
->ed
;
1078 /* update URB's length and status from TD */
1079 status
= td_done(ohci
, urb
, td
);
1082 /* If all this urb's TDs are done, call complete() */
1083 if (urb_priv
->td_cnt
== urb_priv
->length
)
1084 finish_urb(ohci
, urb
, status
);
1086 /* clean schedule: unlink EDs that are no longer busy */
1087 if (list_empty(&ed
->td_list
)) {
1088 if (ed
->state
== ED_OPER
)
1089 start_ed_unlink(ohci
, ed
);
1091 /* ... reenabling halted EDs only after fault cleanup */
1092 } else if ((ed
->hwINFO
& cpu_to_hc32(ohci
, ED_SKIP
| ED_DEQUEUE
))
1093 == cpu_to_hc32(ohci
, ED_SKIP
)) {
1094 td
= list_entry(ed
->td_list
.next
, struct td
, td_list
);
1095 if (!(td
->hwINFO
& cpu_to_hc32(ohci
, TD_DONE
))) {
1096 ed
->hwINFO
&= ~cpu_to_hc32(ohci
, ED_SKIP
);
1097 /* ... hc may need waking-up */
1100 ohci_writel(ohci
, OHCI_CLF
,
1101 &ohci
->regs
->cmdstatus
);
1104 ohci_writel(ohci
, OHCI_BLF
,
1105 &ohci
->regs
->cmdstatus
);
1113 * Process normal completions (error or success) and clean the schedules.
1115 * This is the main path for handing urbs back to drivers. The only other
1116 * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1117 * instead of scanning the (re-reversed) donelist as this does. There's
1118 * an abnormal path too, handling a quirk in some Compaq silicon: URBs
1119 * with TDs that appear to be orphaned are directly reclaimed.
1122 dl_done_list (struct ohci_hcd
*ohci
)
1124 struct td
*td
= dl_reverse_done_list (ohci
);
1127 struct td
*td_next
= td
->next_dl_td
;
1128 takeback_td(ohci
, td
);