release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         int                     retval;
  31
  32         /* we expect static quirk code to handle the "extended capabilities"
  33          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  34          */
  35
  36         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  37         retval = pci_set_mwi(pdev);
  38         if (!retval)
  39                 ehci_dbg(ehci, "MWI active\n");
  40
  41         return 0;
  42 }
  43
  44 static int ehci_quirk_amd_hudson(struct ehci_hcd *ehci)
  45 {
  46         struct pci_dev *amd_smbus_dev;
  47         u8 rev = 0;
  48
  49         amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL);
  50         if (amd_smbus_dev) {
  51                 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
  52                 if (rev < 0x40) {
  53                         pci_dev_put(amd_smbus_dev);
  54                         amd_smbus_dev = NULL;
  55                         return 0;
  56                 }
  57         } else {
  58                 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL);
  59                 if (!amd_smbus_dev)
  60                         return 0;
  61                 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev);
  62                 if (rev < 0x11 || rev > 0x18) {
  63                         pci_dev_put(amd_smbus_dev);
  64                         amd_smbus_dev = NULL;
  65                         return 0;
  66                 }
  67         }
  68
  69         if (!amd_nb_dev)
  70                 amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
  71
  72         ehci_info(ehci, "QUIRK: Enable exception for AMD Hudson ASPM\n");
  73
  74         pci_dev_put(amd_smbus_dev);
  75         amd_smbus_dev = NULL;
  76
  77         return 1;
  78 }
  79
  80 /* called during probe() after chip reset completes */
  81 static int ehci_pci_setup(struct usb_hcd *hcd)
  82 {
  83         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  84         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  85         struct pci_dev          *p_smbus;
  86         u8                      rev;
  87         u32                     temp;
  88         int                     retval;
  89
  90         switch (pdev->vendor) {
  91         case PCI_VENDOR_ID_TOSHIBA_2:
  92                 /* celleb's companion chip */
  93                 if (pdev->device == 0x01b5) {
  94 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  95                         ehci->big_endian_mmio = 1;
  96 #else
  97                         ehci_warn(ehci,
  98                                   "unsupported big endian Toshiba quirk\n");
  99 #endif
 100                 }
 101                 break;
 102         }
 103
 104         ehci->caps = hcd->regs;
 105         ehci->regs = hcd->regs +
 106                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
 107
 108         dbg_hcs_params(ehci, "reset");
 109         dbg_hcc_params(ehci, "reset");
 110
 111         /* ehci_init() causes memory for DMA transfers to be
 112          * allocated.  Thus, any vendor-specific workarounds based on
 113          * limiting the type of memory used for DMA transfers must
 114          * happen before ehci_init() is called. */
 115         switch (pdev->vendor) {
 116         case PCI_VENDOR_ID_NVIDIA:
 117                 /* NVidia reports that certain chips don't handle
 118                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 119                  * data buffer, and periodic schedule are normal.)
 120                  */
 121                 switch (pdev->device) {
 122                 case 0x003c:    /* MCP04 */
 123                 case 0x005b:    /* CK804 */
 124                 case 0x00d8:    /* CK8 */
 125                 case 0x00e8:    /* CK8S */
 126                         if (pci_set_consistent_dma_mask(pdev,
 127                                                 DMA_BIT_MASK(31)) < 0)
 128                                 ehci_warn(ehci, "can't enable NVidia "
 129                                         "workaround for >2GB RAM\n");
 130                         break;
 131                 }
 132                 break;
 133         }
 134
 135         /* cache this readonly data; minimize chip reads */
 136         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 137
 138         if (ehci_quirk_amd_hudson(ehci))
 139                 ehci->amd_l1_fix = 1;
 140
 141         retval = ehci_halt(ehci);
 142         if (retval)
 143                 return retval;
 144
 145         /* data structure init */
 146         retval = ehci_init(hcd);
 147         if (retval)
 148                 return retval;
 149
 150         switch (pdev->vendor) {
 151         case PCI_VENDOR_ID_NEC:
 152                 ehci->need_io_watchdog = 0;
 153                 break;
 154         case PCI_VENDOR_ID_INTEL:
 155                 ehci->need_io_watchdog = 0;
 156                 ehci->fs_i_thresh = 1;
 157                 if (pdev->device == 0x27cc) {
 158                         ehci->broken_periodic = 1;
 159                         ehci_info(ehci, "using broken periodic workaround\n");
 160                 }
 161                 if (pdev->device == 0x0806 || pdev->device == 0x0811
 162                                 || pdev->device == 0x0829) {
 163                         ehci_info(ehci, "disable lpm for langwell/penwell\n");
 164                         ehci->has_lpm = 0;
 165                 }
 166                 break;
 167         case PCI_VENDOR_ID_TDI:
 168                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 169                         hcd->has_tt = 1;
 170                         tdi_reset(ehci);
 171                 }
 172                 break;
 173         case PCI_VENDOR_ID_AMD:
 174                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 175                 if (pdev->device == 0x7463) {
 176                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 177                         retval = -EIO;
 178                         goto done;
 179                 }
 180                 break;
 181         case PCI_VENDOR_ID_NVIDIA:
 182                 switch (pdev->device) {
 183                 /* Some NForce2 chips have problems with selective suspend;
 184                  * fixed in newer silicon.
 185                  */
 186                 case 0x0068:
 187                         if (pdev->revision < 0xa4)
 188                                 ehci->no_selective_suspend = 1;
 189                         break;
 190
 191                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 192                  * fetching device descriptors unless LPM is disabled.
 193                  * There are also intermittent problems enumerating
 194                  * devices with PPCD enabled.
 195                  */
 196                 case 0x0d9d:
 197                         ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
 198                         ehci->has_lpm = 0;
 199                         ehci->has_ppcd = 0;
 200                         ehci->command &= ~CMD_PPCEE;
 201                         break;
 202                 }
 203                 break;
 204         case PCI_VENDOR_ID_VIA:
 205                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 206                         u8 tmp;
 207
 208                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 209                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 210                          * that sleep time use the conventional 10 usec.
 211                          */
 212                         pci_read_config_byte(pdev, 0x4b, &tmp);
 213                         if (tmp & 0x20)
 214                                 break;
 215                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 216                 }
 217                 break;
 218         case PCI_VENDOR_ID_ATI:
 219                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 220                  * which causes usb devices lose response in some cases.
 221                  */
 222                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 223                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 224                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 225                                                  NULL);
 226                         if (!p_smbus)
 227                                 break;
 228                         rev = p_smbus->revision;
 229                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 230                             || (rev == 0x3b)) {
 231                                 u8 tmp;
 232                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 233                                         "freeze workaround\n");
 234                                 pci_read_config_byte(pdev, 0x53, &tmp);
 235                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 236                         }
 237                         pci_dev_put(p_smbus);
 238                 }
 239                 break;
 240         }
 241
 242         /* optional debug port, normally in the first BAR */
 243         temp = pci_find_capability(pdev, 0x0a);
 244         if (temp) {
 245                 pci_read_config_dword(pdev, temp, &temp);
 246                 temp >>= 16;
 247                 if ((temp & (3 << 13)) == (1 << 13)) {
 248                         temp &= 0x1fff;
 249                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 250                         temp = ehci_readl(ehci, &ehci->debug->control);
 251                         ehci_info(ehci, "debug port %d%s\n",
 252                                 HCS_DEBUG_PORT(ehci->hcs_params),
 253                                 (temp & DBGP_ENABLED)
 254                                         ? " IN USE"
 255                                         : "");
 256                         if (!(temp & DBGP_ENABLED))
 257                                 ehci->debug = NULL;
 258                 }
 259         }
 260
 261         ehci_reset(ehci);
 262
 263         /* at least the Genesys GL880S needs fixup here */
 264         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 265         temp &= 0x0f;
 266         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 267                 ehci_dbg(ehci, "bogus port configuration: "
 268                         "cc=%d x pcc=%d < ports=%d\n",
 269                         HCS_N_CC(ehci->hcs_params),
 270                         HCS_N_PCC(ehci->hcs_params),
 271                         HCS_N_PORTS(ehci->hcs_params));
 272
 273                 switch (pdev->vendor) {
 274                 case 0x17a0:            /* GENESYS */
 275                         /* GL880S: should be PORTS=2 */
 276                         temp |= (ehci->hcs_params & ~0xf);
 277                         ehci->hcs_params = temp;
 278                         break;
 279                 case PCI_VENDOR_ID_NVIDIA:
 280                         /* NF4: should be PCC=10 */
 281                         break;
 282                 }
 283         }
 284
 285         /* Serial Bus Release Number is at PCI 0x60 offset */
 286         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 287
 288         /* Keep this around for a while just in case some EHCI
 289          * implementation uses legacy PCI PM support.  This test
 290          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 291          * been triggered by then.
 292          */
 293         if (!device_can_wakeup(&pdev->dev)) {
 294                 u16     port_wake;
 295
 296                 pci_read_config_word(pdev, 0x62, &port_wake);
 297                 if (port_wake & 0x0001) {
 298                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 299                         device_set_wakeup_capable(&pdev->dev, 1);
 300                 }
 301         }
 302
 303 #ifdef  CONFIG_USB_SUSPEND
 304         /* REVISIT: the controller works fine for wakeup iff the root hub
 305          * itself is "globally" suspended, but usbcore currently doesn't
 306          * understand such things.
 307          *
 308          * System suspend currently expects to be able to suspend the entire
 309          * device tree, device-at-a-time.  If we failed selective suspend
 310          * reports, system suspend would fail; so the root hub code must claim
 311          * success.  That's lying to usbcore, and it matters for runtime
 312          * PM scenarios with selective suspend and remote wakeup...
 313          */
 314         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 315                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 316 #endif
 317
 318         ehci_port_power(ehci, 1);
 319         retval = ehci_pci_reinit(ehci, pdev);
 320 done:
 321         return retval;
 322 }
 323
 324 /*-------------------------------------------------------------------------*/
 325
 326 #ifdef  CONFIG_PM
 327
 328 /* suspend/resume, section 4.3 */
 329
 330 /* These routines rely on the PCI bus glue
 331  * to handle powerdown and wakeup, and currently also on
 332  * transceivers that don't need any software attention to set up
 333  * the right sort of wakeup.
 334  * Also they depend on separate root hub suspend/resume.
 335  */
 336
 337 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 338 {
 339         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 340         unsigned long           flags;
 341         int                     rc = 0;
 342
 343         if (time_before(jiffies, ehci->next_statechange))
 344                 msleep(10);
 345
 346         /* Root hub was already suspended. Disable irq emission and
 347          * mark HW unaccessible.  The PM and USB cores make sure that
 348          * the root hub is either suspended or stopped.
 349          */
 350         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 351         spin_lock_irqsave (&ehci->lock, flags);
 352         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 353         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 354
 355         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 356         spin_unlock_irqrestore (&ehci->lock, flags);
 357
 358         // could save FLADJ in case of Vaux power loss
 359         // ... we'd only use it to handle clock skew
 360
 361         return rc;
 362 }
 363
 364 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 365 {
 366         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 367         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 368
 369         // maybe restore FLADJ
 370
 371         if (time_before(jiffies, ehci->next_statechange))
 372                 msleep(100);
 373
 374         /* Mark hardware accessible again as we are out of D3 state by now */
 375         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 376
 377         /* If CF is still set and we aren't resuming from hibernation
 378          * then we maintained PCI Vaux power.
 379          * Just undo the effect of ehci_pci_suspend().
 380          */
 381         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 382                                 !hibernated) {
 383                 int     mask = INTR_MASK;
 384
 385                 ehci_prepare_ports_for_controller_resume(ehci);
 386                 if (!hcd->self.root_hub->do_remote_wakeup)
 387                         mask &= ~STS_PCD;
 388                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 389                 ehci_readl(ehci, &ehci->regs->intr_enable);
 390                 return 0;
 391         }
 392
 393         usb_root_hub_lost_power(hcd->self.root_hub);
 394
 395         /* Else reset, to cope with power loss or flush-to-storage
 396          * style "resume" having let BIOS kick in during reboot.
 397          */
 398         (void) ehci_halt(ehci);
 399         (void) ehci_reset(ehci);
 400         (void) ehci_pci_reinit(ehci, pdev);
 401
 402         /* emptying the schedule aborts any urbs */
 403         spin_lock_irq(&ehci->lock);
 404         if (ehci->reclaim)
 405                 end_unlink_async(ehci);
 406         ehci_work(ehci);
 407         spin_unlock_irq(&ehci->lock);
 408
 409         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 410         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 411         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 412
 413         /* here we "know" root ports should always stay powered */
 414         ehci_port_power(ehci, 1);
 415
 416         hcd->state = HC_STATE_SUSPENDED;
 417         return 0;
 418 }
 419 #endif
 420
 421 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 422 {
 423         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 424         int rc = 0;
 425
 426         if (!udev->parent) /* udev is root hub itself, impossible */
 427                 rc = -1;
 428         /* we only support lpm device connected to root hub yet */
 429         if (ehci->has_lpm && !udev->parent->parent) {
 430                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 431                 if (!rc)
 432                         rc = ehci_lpm_check(ehci, udev->portnum);
 433         }
 434         return rc;
 435 }
 436
 437 static const struct hc_driver ehci_pci_hc_driver = {
 438         .description =          hcd_name,
 439         .product_desc =         "EHCI Host Controller",
 440         .hcd_priv_size =        sizeof(struct ehci_hcd),
 441
 442         /*
 443          * generic hardware linkage
 444          */
 445         .irq =                  ehci_irq,
 446         .flags =                HCD_MEMORY | HCD_USB2,
 447
 448         /*
 449          * basic lifecycle operations
 450          */
 451         .reset =                ehci_pci_setup,
 452         .start =                ehci_run,
 453 #ifdef  CONFIG_PM
 454         .pci_suspend =          ehci_pci_suspend,
 455         .pci_resume =           ehci_pci_resume,
 456 #endif
 457         .stop =                 ehci_stop,
 458         .shutdown =             ehci_shutdown,
 459
 460         /*
 461          * managing i/o requests and associated device resources
 462          */
 463         .urb_enqueue =          ehci_urb_enqueue,
 464         .urb_dequeue =          ehci_urb_dequeue,
 465         .endpoint_disable =     ehci_endpoint_disable,
 466         .endpoint_reset =       ehci_endpoint_reset,
 467
 468         /*
 469          * scheduling support
 470          */
 471         .get_frame_number =     ehci_get_frame,
 472
 473         /*
 474          * root hub support
 475          */
 476         .hub_status_data =      ehci_hub_status_data,
 477         .hub_control =          ehci_hub_control,
 478         .bus_suspend =          ehci_bus_suspend,
 479         .bus_resume =           ehci_bus_resume,
 480         .relinquish_port =      ehci_relinquish_port,
 481         .port_handed_over =     ehci_port_handed_over,
 482
 483         /*
 484          * call back when device connected and addressed
 485          */
 486         .update_device =        ehci_update_device,
 487
 488         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 489 };
 490
 491 /*-------------------------------------------------------------------------*/
 492
 493 /* PCI driver selection metadata; PCI hotplugging uses this */
 494 static const struct pci_device_id pci_ids [] = { {
 495         /* handle any USB 2.0 EHCI controller */
 496         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 497         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 498         },
 499         { /* end: all zeroes */ }
 500 };
 501 MODULE_DEVICE_TABLE(pci, pci_ids);
 502
 503 /* pci driver glue; this is a "new style" PCI driver module */
 504 static struct pci_driver ehci_pci_driver = {
 505         .name =         (char *) hcd_name,
 506         .id_table =     pci_ids,
 507
 508         .probe =        usb_hcd_pci_probe,
 509         .remove =       usb_hcd_pci_remove,
 510         .shutdown =     usb_hcd_pci_shutdown,
 511
 512 #ifdef CONFIG_PM_SLEEP
 513         .driver =       {
 514                 .pm =   &usb_hcd_pci_pm_ops
 515         },
 516 #endif
 517 };