release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/tidspbridge/include/dspbridge/dspioctl.h

   1 /*
   2  * dspioctl.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Bridge driver BRD_IOCtl reserved command definitions.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #ifndef DSPIOCTL_
  20 #define DSPIOCTL_
  21
  22 /* ------------------------------------ Hardware Abstraction Layer */
  23 #include <hw_defs.h>
  24 #include <hw_mmu.h>
  25
  26 /*
  27  * Any IOCTLS at or above this value are reserved for standard Bridge driver
  28  * interfaces.
  29  */
  30 #define BRDIOCTL_RESERVEDBASE       0x8000
  31
  32 #define BRDIOCTL_CHNLREAD           (BRDIOCTL_RESERVEDBASE + 0x10)
  33 #define BRDIOCTL_CHNLWRITE          (BRDIOCTL_RESERVEDBASE + 0x20)
  34 #define BRDIOCTL_GETINTRCOUNT       (BRDIOCTL_RESERVEDBASE + 0x30)
  35 #define BRDIOCTL_RESETINTRCOUNT     (BRDIOCTL_RESERVEDBASE + 0x40)
  36 #define BRDIOCTL_INTERRUPTDSP       (BRDIOCTL_RESERVEDBASE + 0x50)
  37 /* DMMU */
  38 #define BRDIOCTL_SETMMUCONFIG       (BRDIOCTL_RESERVEDBASE + 0x60)
  39 /* PWR */
  40 #define BRDIOCTL_PWRCONTROL         (BRDIOCTL_RESERVEDBASE + 0x70)
  41
  42 /* attention, modifiers:
  43  * Some of these control enumerations are made visible to user for power
  44  * control, so any changes to this list, should also be updated in the user
  45  * header file 'dbdefs.h' ***/
  46 /* These ioctls are reserved for PWR power commands for the DSP */
  47 #define BRDIOCTL_DEEPSLEEP          (BRDIOCTL_PWRCONTROL + 0x0)
  48 #define BRDIOCTL_EMERGENCYSLEEP     (BRDIOCTL_PWRCONTROL + 0x1)
  49 #define BRDIOCTL_WAKEUP             (BRDIOCTL_PWRCONTROL + 0x2)
  50 #define BRDIOCTL_PWRENABLE          (BRDIOCTL_PWRCONTROL + 0x3)
  51 #define BRDIOCTL_PWRDISABLE         (BRDIOCTL_PWRCONTROL + 0x4)
  52 #define BRDIOCTL_CLK_CTRL                   (BRDIOCTL_PWRCONTROL + 0x7)
  53 /* DSP Initiated Hibernate */
  54 #define BRDIOCTL_PWR_HIBERNATE  (BRDIOCTL_PWRCONTROL + 0x8)
  55 #define BRDIOCTL_PRESCALE_NOTIFY (BRDIOCTL_PWRCONTROL + 0x9)
  56 #define BRDIOCTL_POSTSCALE_NOTIFY (BRDIOCTL_PWRCONTROL + 0xA)
  57 #define BRDIOCTL_CONSTRAINT_REQUEST (BRDIOCTL_PWRCONTROL + 0xB)
  58
  59 /* Number of actual DSP-MMU TLB entrries */
  60 #define BRDIOCTL_NUMOFMMUTLB        32
  61
  62 struct bridge_ioctl_extproc {
  63         u32 ul_dsp_va;          /* DSP virtual address */
  64         u32 ul_gpp_pa;          /* GPP physical address */
  65         /* GPP virtual address. __va does not work for ioremapped addresses */
  66         u32 ul_gpp_va;
  67         u32 ul_size;            /* Size of the mapped memory in bytes */
  68         enum hw_endianism_t endianism;
  69         enum hw_mmu_mixed_size_t mixed_mode;
  70         enum hw_element_size_t elem_size;
  71 };
  72
  73 #endif /* DSPIOCTL_ */