release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/tidspbridge/core/_tiomap.h

   1 /*
   2  * _tiomap.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Definitions and types private to this Bridge driver.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #ifndef _TIOMAP_
  20 #define _TIOMAP_
  21
  22 #include <plat/powerdomain.h>
  23 #include <plat/clockdomain.h>
  24 #include <mach-omap2/prm-regbits-34xx.h>
  25 #include <mach-omap2/cm-regbits-34xx.h>
  26 #include <dspbridge/devdefs.h>
  27 #include <hw_defs.h>
  28 #include <dspbridge/dspioctl.h> /* for bridge_ioctl_extproc defn */
  29 #include <dspbridge/sync.h>
  30 #include <dspbridge/clk.h>
  31
  32 struct map_l4_peripheral {
  33         u32 phys_addr;
  34         u32 dsp_virt_addr;
  35 };
  36
  37 #define ARM_MAILBOX_START               0xfffcf000
  38 #define ARM_MAILBOX_LENGTH              0x800
  39
  40 /* New Registers in OMAP3.1 */
  41
  42 #define TESTBLOCK_ID_START              0xfffed400
  43 #define TESTBLOCK_ID_LENGTH             0xff
  44
  45 /* ID Returned by OMAP1510 */
  46 #define TBC_ID_VALUE                    0xB47002F
  47
  48 #define SPACE_LENGTH                    0x2000
  49 #define API_CLKM_DPLL_DMA               0xfffec000
  50 #define ARM_INTERRUPT_OFFSET            0xb00
  51
  52 #define BIOS24XX
  53
  54 #define L4_PERIPHERAL_NULL          0x0
  55 #define DSPVA_PERIPHERAL_NULL       0x0
  56
  57 #define MAX_LOCK_TLB_ENTRIES 15
  58
  59 #define L4_PERIPHERAL_PRM        0x48306000     /*PRM L4 Peripheral */
  60 #define DSPVA_PERIPHERAL_PRM     0x1181e000
  61 #define L4_PERIPHERAL_SCM        0x48002000     /*SCM L4 Peripheral */
  62 #define DSPVA_PERIPHERAL_SCM     0x1181f000
  63 #define L4_PERIPHERAL_MMU        0x5D000000     /*MMU L4 Peripheral */
  64 #define DSPVA_PERIPHERAL_MMU     0x11820000
  65 #define L4_PERIPHERAL_CM        0x48004000      /* Core L4, Clock Management */
  66 #define DSPVA_PERIPHERAL_CM     0x1181c000
  67 #define L4_PERIPHERAL_PER        0x48005000     /*  PER */
  68 #define DSPVA_PERIPHERAL_PER     0x1181d000
  69
  70 #define L4_PERIPHERAL_GPIO1       0x48310000
  71 #define DSPVA_PERIPHERAL_GPIO1    0x11809000
  72 #define L4_PERIPHERAL_GPIO2       0x49050000
  73 #define DSPVA_PERIPHERAL_GPIO2    0x1180a000
  74 #define L4_PERIPHERAL_GPIO3       0x49052000
  75 #define DSPVA_PERIPHERAL_GPIO3    0x1180b000
  76 #define L4_PERIPHERAL_GPIO4       0x49054000
  77 #define DSPVA_PERIPHERAL_GPIO4    0x1180c000
  78 #define L4_PERIPHERAL_GPIO5       0x49056000
  79 #define DSPVA_PERIPHERAL_GPIO5    0x1180d000
  80
  81 #define L4_PERIPHERAL_IVA2WDT      0x49030000
  82 #define DSPVA_PERIPHERAL_IVA2WDT   0x1180e000
  83
  84 #define L4_PERIPHERAL_DISPLAY     0x48050000
  85 #define DSPVA_PERIPHERAL_DISPLAY  0x1180f000
  86
  87 #define L4_PERIPHERAL_SSI         0x48058000
  88 #define DSPVA_PERIPHERAL_SSI      0x11804000
  89 #define L4_PERIPHERAL_GDD         0x48059000
  90 #define DSPVA_PERIPHERAL_GDD      0x11805000
  91 #define L4_PERIPHERAL_SS1         0x4805a000
  92 #define DSPVA_PERIPHERAL_SS1      0x11806000
  93 #define L4_PERIPHERAL_SS2         0x4805b000
  94 #define DSPVA_PERIPHERAL_SS2      0x11807000
  95
  96 #define L4_PERIPHERAL_CAMERA      0x480BC000
  97 #define DSPVA_PERIPHERAL_CAMERA   0x11819000
  98
  99 #define L4_PERIPHERAL_SDMA        0x48056000
 100 #define DSPVA_PERIPHERAL_SDMA     0x11810000    /* 0x1181d000 conflict w/ PER */
 101
 102 #define L4_PERIPHERAL_UART1             0x4806a000
 103 #define DSPVA_PERIPHERAL_UART1          0x11811000
 104 #define L4_PERIPHERAL_UART2             0x4806c000
 105 #define DSPVA_PERIPHERAL_UART2          0x11812000
 106 #define L4_PERIPHERAL_UART3             0x49020000
 107 #define DSPVA_PERIPHERAL_UART3    0x11813000
 108
 109 #define L4_PERIPHERAL_MCBSP1      0x48074000
 110 #define DSPVA_PERIPHERAL_MCBSP1   0x11814000
 111 #define L4_PERIPHERAL_MCBSP2      0x49022000
 112 #define DSPVA_PERIPHERAL_MCBSP2   0x11815000
 113 #define L4_PERIPHERAL_MCBSP3      0x49024000
 114 #define DSPVA_PERIPHERAL_MCBSP3   0x11816000
 115 #define L4_PERIPHERAL_MCBSP4      0x49026000
 116 #define DSPVA_PERIPHERAL_MCBSP4   0x11817000
 117 #define L4_PERIPHERAL_MCBSP5      0x48096000
 118 #define DSPVA_PERIPHERAL_MCBSP5   0x11818000
 119
 120 #define L4_PERIPHERAL_GPTIMER5    0x49038000
 121 #define DSPVA_PERIPHERAL_GPTIMER5 0x11800000
 122 #define L4_PERIPHERAL_GPTIMER6    0x4903a000
 123 #define DSPVA_PERIPHERAL_GPTIMER6 0x11801000
 124 #define L4_PERIPHERAL_GPTIMER7    0x4903c000
 125 #define DSPVA_PERIPHERAL_GPTIMER7 0x11802000
 126 #define L4_PERIPHERAL_GPTIMER8    0x4903e000
 127 #define DSPVA_PERIPHERAL_GPTIMER8 0x11803000
 128
 129 #define L4_PERIPHERAL_SPI1      0x48098000
 130 #define DSPVA_PERIPHERAL_SPI1   0x1181a000
 131 #define L4_PERIPHERAL_SPI2      0x4809a000
 132 #define DSPVA_PERIPHERAL_SPI2   0x1181b000
 133
 134 #define L4_PERIPHERAL_MBOX        0x48094000
 135 #define DSPVA_PERIPHERAL_MBOX     0x11808000
 136
 137 #define PM_GRPSEL_BASE                  0x48307000
 138 #define DSPVA_GRPSEL_BASE               0x11821000
 139
 140 #define L4_PERIPHERAL_SIDETONE_MCBSP2        0x49028000
 141 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP2 0x11824000
 142 #define L4_PERIPHERAL_SIDETONE_MCBSP3        0x4902a000
 143 #define DSPVA_PERIPHERAL_SIDETONE_MCBSP3 0x11825000
 144
 145 /* define a static array with L4 mappings */
 146 static const struct map_l4_peripheral l4_peripheral_table[] = {
 147         {L4_PERIPHERAL_MBOX, DSPVA_PERIPHERAL_MBOX},
 148         {L4_PERIPHERAL_SCM, DSPVA_PERIPHERAL_SCM},
 149         {L4_PERIPHERAL_MMU, DSPVA_PERIPHERAL_MMU},
 150         {L4_PERIPHERAL_GPTIMER5, DSPVA_PERIPHERAL_GPTIMER5},
 151         {L4_PERIPHERAL_GPTIMER6, DSPVA_PERIPHERAL_GPTIMER6},
 152         {L4_PERIPHERAL_GPTIMER7, DSPVA_PERIPHERAL_GPTIMER7},
 153         {L4_PERIPHERAL_GPTIMER8, DSPVA_PERIPHERAL_GPTIMER8},
 154         {L4_PERIPHERAL_GPIO1, DSPVA_PERIPHERAL_GPIO1},
 155         {L4_PERIPHERAL_GPIO2, DSPVA_PERIPHERAL_GPIO2},
 156         {L4_PERIPHERAL_GPIO3, DSPVA_PERIPHERAL_GPIO3},
 157         {L4_PERIPHERAL_GPIO4, DSPVA_PERIPHERAL_GPIO4},
 158         {L4_PERIPHERAL_GPIO5, DSPVA_PERIPHERAL_GPIO5},
 159         {L4_PERIPHERAL_IVA2WDT, DSPVA_PERIPHERAL_IVA2WDT},
 160         {L4_PERIPHERAL_DISPLAY, DSPVA_PERIPHERAL_DISPLAY},
 161         {L4_PERIPHERAL_SSI, DSPVA_PERIPHERAL_SSI},
 162         {L4_PERIPHERAL_GDD, DSPVA_PERIPHERAL_GDD},
 163         {L4_PERIPHERAL_SS1, DSPVA_PERIPHERAL_SS1},
 164         {L4_PERIPHERAL_SS2, DSPVA_PERIPHERAL_SS2},
 165         {L4_PERIPHERAL_UART1, DSPVA_PERIPHERAL_UART1},
 166         {L4_PERIPHERAL_UART2, DSPVA_PERIPHERAL_UART2},
 167         {L4_PERIPHERAL_UART3, DSPVA_PERIPHERAL_UART3},
 168         {L4_PERIPHERAL_MCBSP1, DSPVA_PERIPHERAL_MCBSP1},
 169         {L4_PERIPHERAL_MCBSP2, DSPVA_PERIPHERAL_MCBSP2},
 170         {L4_PERIPHERAL_MCBSP3, DSPVA_PERIPHERAL_MCBSP3},
 171         {L4_PERIPHERAL_MCBSP4, DSPVA_PERIPHERAL_MCBSP4},
 172         {L4_PERIPHERAL_MCBSP5, DSPVA_PERIPHERAL_MCBSP5},
 173         {L4_PERIPHERAL_CAMERA, DSPVA_PERIPHERAL_CAMERA},
 174         {L4_PERIPHERAL_SPI1, DSPVA_PERIPHERAL_SPI1},
 175         {L4_PERIPHERAL_SPI2, DSPVA_PERIPHERAL_SPI2},
 176         {L4_PERIPHERAL_PRM, DSPVA_PERIPHERAL_PRM},
 177         {L4_PERIPHERAL_CM, DSPVA_PERIPHERAL_CM},
 178         {L4_PERIPHERAL_PER, DSPVA_PERIPHERAL_PER},
 179         {PM_GRPSEL_BASE, DSPVA_GRPSEL_BASE},
 180         {L4_PERIPHERAL_SIDETONE_MCBSP2, DSPVA_PERIPHERAL_SIDETONE_MCBSP2},
 181         {L4_PERIPHERAL_SIDETONE_MCBSP3, DSPVA_PERIPHERAL_SIDETONE_MCBSP3},
 182         {L4_PERIPHERAL_NULL, DSPVA_PERIPHERAL_NULL}
 183 };
 184
 185 /*
 186  *   15         10                  0
 187  *   ---------------------------------
 188  *  |0|0|1|0|0|0|c|c|c|i|i|i|i|i|i|i|
 189  *  ---------------------------------
 190  *  |  (class)  | (module specific) |
 191  *
 192  *  where  c -> Externel Clock Command: Clk & Autoidle Disable/Enable
 193  *  i -> External Clock ID Timers 5,6,7,8, McBSP1,2 and WDT3
 194  */
 195
 196 /* MBX_PM_CLK_IDMASK: DSP External clock id mask. */
 197 #define MBX_PM_CLK_IDMASK   0x7F
 198
 199 /* MBX_PM_CLK_CMDSHIFT: DSP External clock command shift. */
 200 #define MBX_PM_CLK_CMDSHIFT 7
 201
 202 /* MBX_PM_CLK_CMDMASK: DSP External clock command mask. */
 203 #define MBX_PM_CLK_CMDMASK 7
 204
 205 /* MBX_PM_MAX_RESOURCES: CORE 1 Clock resources. */
 206 #define MBX_CORE1_RESOURCES 7
 207
 208 /* MBX_PM_MAX_RESOURCES: CORE 2 Clock Resources. */
 209 #define MBX_CORE2_RESOURCES 1
 210
 211 /* MBX_PM_MAX_RESOURCES: TOTAL Clock Reosurces. */
 212 #define MBX_PM_MAX_RESOURCES 11
 213
 214 /*  Power Management Commands */
 215 #define BPWR_DISABLE_CLOCK      0
 216 #define BPWR_ENABLE_CLOCK       1
 217
 218 /* OMAP242x specific resources */
 219 enum bpwr_ext_clock_id {
 220         BPWR_GP_TIMER5 = 0x10,
 221         BPWR_GP_TIMER6,
 222         BPWR_GP_TIMER7,
 223         BPWR_GP_TIMER8,
 224         BPWR_WD_TIMER3,
 225         BPWR_MCBSP1,
 226         BPWR_MCBSP2,
 227         BPWR_MCBSP3,
 228         BPWR_MCBSP4,
 229         BPWR_MCBSP5,
 230         BPWR_SSI = 0x20
 231 };
 232
 233 static const u32 bpwr_clkid[] = {
 234         (u32) BPWR_GP_TIMER5,
 235         (u32) BPWR_GP_TIMER6,
 236         (u32) BPWR_GP_TIMER7,
 237         (u32) BPWR_GP_TIMER8,
 238         (u32) BPWR_WD_TIMER3,
 239         (u32) BPWR_MCBSP1,
 240         (u32) BPWR_MCBSP2,
 241         (u32) BPWR_MCBSP3,
 242         (u32) BPWR_MCBSP4,
 243         (u32) BPWR_MCBSP5,
 244         (u32) BPWR_SSI
 245 };
 246
 247 struct bpwr_clk_t {
 248         u32 clk_id;
 249         enum dsp_clk_id clk;
 250 };
 251
 252 static const struct bpwr_clk_t bpwr_clks[] = {
 253         {(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5},
 254         {(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6},
 255         {(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7},
 256         {(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8},
 257         {(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3},
 258         {(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1},
 259         {(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2},
 260         {(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3},
 261         {(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4},
 262         {(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5},
 263         {(u32) BPWR_SSI, DSP_CLK_SSI}
 264 };
 265
 266 /* Interrupt Register Offsets */
 267 #define INTH_IT_REG_OFFSET              0x00    /* Interrupt register offset */
 268 #define INTH_MASK_IT_REG_OFFSET         0x04    /* Mask Interrupt reg offset */
 269
 270 #define   DSP_MAILBOX1_INT              10
 271 /*
 272  *  Bit definition of  Interrupt  Level  Registers
 273  */
 274
 275 /* Mail Box defines */
 276 #define MB_ARM2DSP1_REG_OFFSET          0x00
 277
 278 #define MB_ARM2DSP1B_REG_OFFSET         0x04
 279
 280 #define MB_DSP2ARM1B_REG_OFFSET         0x0C
 281
 282 #define MB_ARM2DSP1_FLAG_REG_OFFSET     0x18
 283
 284 #define MB_ARM2DSP_FLAG                 0x0001
 285
 286 #define MBOX_ARM2DSP HW_MBOX_ID0
 287 #define MBOX_DSP2ARM HW_MBOX_ID1
 288 #define MBOX_ARM HW_MBOX_U0_ARM
 289 #define MBOX_DSP HW_MBOX_U1_DSP1
 290
 291 #define ENABLE                          true
 292 #define DISABLE                         false
 293
 294 #define HIGH_LEVEL                      true
 295 #define LOW_LEVEL                       false
 296
 297 /* Macro's */
 298 #define CLEAR_BIT(reg, mask)             (reg &= ~mask)
 299 #define SET_BIT(reg, mask)               (reg |= mask)
 300
 301 #define SET_GROUP_BITS16(reg, position, width, value) \
 302         do {\
 303                 reg &= ~((0xFFFF >> (16 - (width))) << (position)) ; \
 304                 reg |= ((value & (0xFFFF >> (16 - (width)))) << (position)); \
 305         } while (0);
 306
 307 #define CLEAR_BIT_INDEX(reg, index)   (reg &= ~(1 << (index)))
 308
 309 /* This Bridge driver's device context: */
 310 struct bridge_dev_context {
 311         struct dev_object *hdev_obj;    /* Handle to Bridge device object. */
 312         u32 dw_dsp_base_addr;   /* Arm's API to DSP virt base addr */
 313         /*
 314          * DSP External memory prog address as seen virtually by the OS on
 315          * the host side.
 316          */
 317         u32 dw_dsp_ext_base_addr;       /* See the comment above */
 318         u32 dw_api_reg_base;    /* API mem map'd registers */
 319         void __iomem *dw_dsp_mmu_base;  /* DSP MMU Mapped registers */
 320         u32 dw_api_clk_base;    /* CLK Registers */
 321         u32 dw_dsp_clk_m2_base; /* DSP Clock Module m2 */
 322         u32 dw_public_rhea;     /* Pub Rhea */
 323         u32 dw_int_addr;        /* MB INTR reg */
 324         u32 dw_tc_endianism;    /* TC Endianism register */
 325         u32 dw_test_base;       /* DSP MMU Mapped registers */
 326         u32 dw_self_loop;       /* Pointer to the selfloop */
 327         u32 dw_dsp_start_add;   /* API Boot vector */
 328         u32 dw_internal_size;   /* Internal memory size */
 329
 330         struct omap_mbox *mbox;         /* Mail box handle */
 331
 332         struct cfg_hostres *resources;  /* Host Resources */
 333
 334         /*
 335          * Processor specific info is set when prog loaded and read from DCD.
 336          * [See bridge_dev_ctrl()]  PROC info contains DSP-MMU TLB entries.
 337          */
 338         /* DMMU TLB entries */
 339         struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];
 340         u32 dw_brd_state;       /* Last known board state. */
 341
 342         /* TC Settings */
 343         bool tc_word_swap_on;   /* Traffic Controller Word Swap */
 344         struct pg_table_attrs *pt_attrs;
 345         u32 dsp_per_clks;
 346 };
 347
 348 /*
 349  * If dsp_debug is true, do not branch to the DSP entry
 350  * point and wait for DSP to boot.
 351  */
 352 extern s32 dsp_debug;
 353
 354 /*
 355  *  ======== sm_interrupt_dsp ========
 356  *  Purpose:
 357  *      Set interrupt value & send an interrupt to the DSP processor(s).
 358  *      This is typicaly used when mailbox interrupt mechanisms allow data
 359  *      to be associated with interrupt such as for OMAP's CMD/DATA regs.
 360  *  Parameters:
 361  *      dev_context:    Handle to Bridge driver defined device info.
 362  *      mb_val:         Value associated with interrupt(e.g. mailbox value).
 363  *  Returns:
 364  *      0:        Interrupt sent;
 365  *      else:           Unable to send interrupt.
 366  *  Requires:
 367  *  Ensures:
 368  */
 369 int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val);
 370
 371 #endif /* _TIOMAP_ */