release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/octeon/cvmx-helper-rgmii.c

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /*
  29  * Functions for RGMII/GMII/MII initialization, configuration,
  30  * and monitoring.
  31  */
  32 #include <asm/octeon/octeon.h>
  33
  34 #include "cvmx-config.h"
  35
  36
  37 #include "cvmx-mdio.h"
  38 #include "cvmx-pko.h"
  39 #include "cvmx-helper.h"
  40 #include "cvmx-helper-board.h"
  41
  42 #include <asm/octeon/cvmx-npi-defs.h>
  43 #include "cvmx-gmxx-defs.h"
  44 #include "cvmx-asxx-defs.h"
  45 #include "cvmx-dbg-defs.h"
  46
  47 void __cvmx_interrupt_gmxx_enable(int interface);
  48 void __cvmx_interrupt_asxx_enable(int block);
  49
  50 /**
  51  * Probe RGMII ports and determine the number present
  52  *
  53  * @interface: Interface to probe
  54  *
  55  * Returns Number of RGMII/GMII/MII ports (0-4).
  56  */
  57 int __cvmx_helper_rgmii_probe(int interface)
  58 {
  59         int num_ports = 0;
  60         union cvmx_gmxx_inf_mode mode;
  61         mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
  62
  63         if (mode.s.type) {
  64                 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
  65                     || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  66                         cvmx_dprintf("ERROR: RGMII initialize called in "
  67                                      "SPI interface\n");
  68                 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
  69                            || OCTEON_IS_MODEL(OCTEON_CN30XX)
  70                            || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  71                         /*
  72                          * On these chips "type" says we're in
  73                          * GMII/MII mode. This limits us to 2 ports
  74                          */
  75                         num_ports = 2;
  76                 } else {
  77                         cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
  78                                      __func__);
  79                 }
  80         } else {
  81                 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
  82                     || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  83                         num_ports = 4;
  84                 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
  85                            || OCTEON_IS_MODEL(OCTEON_CN30XX)
  86                            || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  87                         num_ports = 3;
  88                 } else {
  89                         cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
  90                                      __func__);
  91                 }
  92         }
  93         return num_ports;
  94 }
  95
  96 /**
  97  * Put an RGMII interface in loopback mode. Internal packets sent
  98  * out will be received back again on the same port. Externally
  99  * received packets will echo back out.
 100  *
 101  * @port:   IPD port number to loop.
 102  */
 103 void cvmx_helper_rgmii_internal_loopback(int port)
 104 {
 105         int interface = (port >> 4) & 1;
 106         int index = port & 0xf;
 107         uint64_t tmp;
 108
 109         union cvmx_gmxx_prtx_cfg gmx_cfg;
 110         gmx_cfg.u64 = 0;
 111         gmx_cfg.s.duplex = 1;
 112         gmx_cfg.s.slottime = 1;
 113         gmx_cfg.s.speed = 1;
 114         cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 115         cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 116         cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 117         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 118         tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 119         cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
 120         tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
 121         cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
 122         tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
 123         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
 124         gmx_cfg.s.en = 1;
 125         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 126 }
 127
 128 static int __cvmx_helper_errata_asx_pass1(int interface, int port,
 129                                           int cpu_clock_hz)
 130 {
 131         /* Set hi water mark as per errata GMX-4 */
 132         if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
 133                 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
 134         else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
 135                 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
 136         else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
 137                 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
 138         else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
 139                 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
 140         else
 141                 cvmx_dprintf("Illegal clock frequency (%d). "
 142                         "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
 143         return 0;
 144 }
 145
 146 /**
 147  * Configure all of the ASX, GMX, and PKO regsiters required
 148  * to get RGMII to function on the supplied interface.
 149  *
 150  * @interface: PKO Interface to configure (0 or 1)
 151  *
 152  * Returns Zero on success
 153  */
 154 int __cvmx_helper_rgmii_enable(int interface)
 155 {
 156         int num_ports = cvmx_helper_ports_on_interface(interface);
 157         int port;
 158         struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
 159         union cvmx_gmxx_inf_mode mode;
 160         union cvmx_asxx_tx_prt_en asx_tx;
 161         union cvmx_asxx_rx_prt_en asx_rx;
 162
 163         mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 164
 165         if (mode.s.en == 0)
 166                 return -1;
 167         if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
 168              OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
 169                 /* Ignore SPI interfaces */
 170                 return -1;
 171
 172         /* Configure the ASX registers needed to use the RGMII ports */
 173         asx_tx.u64 = 0;
 174         asx_tx.s.prt_en = cvmx_build_mask(num_ports);
 175         cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
 176
 177         asx_rx.u64 = 0;
 178         asx_rx.s.prt_en = cvmx_build_mask(num_ports);
 179         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
 180
 181         /* Configure the GMX registers needed to use the RGMII ports */
 182         for (port = 0; port < num_ports; port++) {
 183                 /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
 184                    __cvmx_helper_setup_gmx() */
 185
 186                 if (cvmx_octeon_is_pass1())
 187                         __cvmx_helper_errata_asx_pass1(interface, port,
 188                                                        sys_info_ptr->
 189                                                        cpu_clock_hz);
 190                 else {
 191                         /*
 192                          * Configure more flexible RGMII preamble
 193                          * checking. Pass 1 doesn't support this
 194                          * feature.
 195                          */
 196                         union cvmx_gmxx_rxx_frm_ctl frm_ctl;
 197                         frm_ctl.u64 =
 198                             cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
 199                                           (port, interface));
 200                         /* New field, so must be compile time */
 201                         frm_ctl.s.pre_free = 1;
 202                         cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
 203                                        frm_ctl.u64);
 204                 }
 205
 206                 /*
 207                  * Each pause frame transmitted will ask for about 10M
 208                  * bit times before resume.  If buffer space comes
 209                  * available before that time has expired, an XON
 210                  * pause frame (0 time) will be transmitted to restart
 211                  * the flow.
 212                  */
 213                 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
 214                                20000);
 215                 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
 216                                (port, interface), 19000);
 217
 218                 if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 219                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
 220                                        16);
 221                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
 222                                        16);
 223                 } else {
 224                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
 225                                        24);
 226                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
 227                                        24);
 228                 }
 229         }
 230
 231         __cvmx_helper_setup_gmx(interface, num_ports);
 232
 233         /* enable the ports now */
 234         for (port = 0; port < num_ports; port++) {
 235                 union cvmx_gmxx_prtx_cfg gmx_cfg;
 236                 cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port
 237                                           (interface, port));
 238                 gmx_cfg.u64 =
 239                     cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
 240                 gmx_cfg.s.en = 1;
 241                 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
 242                                gmx_cfg.u64);
 243         }
 244         __cvmx_interrupt_asxx_enable(interface);
 245         __cvmx_interrupt_gmxx_enable(interface);
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * Return the link state of an IPD/PKO port as returned by
 252  * auto negotiation. The result of this function may not match
 253  * Octeon's link config if auto negotiation has changed since
 254  * the last call to cvmx_helper_link_set().
 255  *
 256  * @ipd_port: IPD/PKO port to query
 257  *
 258  * Returns Link state
 259  */
 260 cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
 261 {
 262         int interface = cvmx_helper_get_interface_num(ipd_port);
 263         int index = cvmx_helper_get_interface_index_num(ipd_port);
 264         union cvmx_asxx_prt_loop asxx_prt_loop;
 265
 266         asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 267         if (asxx_prt_loop.s.int_loop & (1 << index)) {
 268                 /* Force 1Gbps full duplex on internal loopback */
 269                 cvmx_helper_link_info_t result;
 270                 result.u64 = 0;
 271                 result.s.full_duplex = 1;
 272                 result.s.link_up = 1;
 273                 result.s.speed = 1000;
 274                 return result;
 275         } else
 276                 return __cvmx_helper_board_link_get(ipd_port);
 277 }
 278
 279 /**
 280  * Configure an IPD/PKO port for the specified link state. This
 281  * function does not influence auto negotiation at the PHY level.
 282  * The passed link state must always match the link state returned
 283  * by cvmx_helper_link_get(). It is normally best to use
 284  * cvmx_helper_link_autoconf() instead.
 285  *
 286  * @ipd_port:  IPD/PKO port to configure
 287  * @link_info: The new link state
 288  *
 289  * Returns Zero on success, negative on failure
 290  */
 291 int __cvmx_helper_rgmii_link_set(int ipd_port,
 292                                  cvmx_helper_link_info_t link_info)
 293 {
 294         int result = 0;
 295         int interface = cvmx_helper_get_interface_num(ipd_port);
 296         int index = cvmx_helper_get_interface_index_num(ipd_port);
 297         union cvmx_gmxx_prtx_cfg original_gmx_cfg;
 298         union cvmx_gmxx_prtx_cfg new_gmx_cfg;
 299         union cvmx_pko_mem_queue_qos pko_mem_queue_qos;
 300         union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16];
 301         union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp;
 302         union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save;
 303         int i;
 304
 305         /* Ignore speed sets in the simulator */
 306         if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
 307                 return 0;
 308
 309         /* Read the current settings so we know the current enable state */
 310         original_gmx_cfg.u64 =
 311             cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 312         new_gmx_cfg = original_gmx_cfg;
 313
 314         /* Disable the lowest level RX */
 315         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 316                        cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
 317                                      ~(1 << index));
 318
 319         /* Disable all queues so that TX should become idle */
 320         for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
 321                 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
 322                 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
 323                 pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
 324                 pko_mem_queue_qos.s.pid = ipd_port;
 325                 pko_mem_queue_qos.s.qid = queue;
 326                 pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
 327                 pko_mem_queue_qos.s.qos_mask = 0;
 328                 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
 329         }
 330
 331         /* Disable backpressure */
 332         gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
 333         gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
 334         gmx_tx_ovr_bp.s.bp &= ~(1 << index);
 335         gmx_tx_ovr_bp.s.en |= 1 << index;
 336         cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
 337         cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
 338
 339         /*
 340          * Poll the GMX state machine waiting for it to become
 341          * idle. Preferably we should only change speed when it is
 342          * idle. If it doesn't become idle we will still do the speed
 343          * change, but there is a slight chance that GMX will
 344          * lockup.
 345          */
 346         cvmx_write_csr(CVMX_NPI_DBG_SELECT,
 347                        interface * 0x800 + index * 0x100 + 0x880);
 348         CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7,
 349                         ==, 0, 10000);
 350         CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf,
 351                         ==, 0, 10000);
 352
 353         /* Disable the port before we make any changes */
 354         new_gmx_cfg.s.en = 0;
 355         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 356         cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 357
 358         /* Set full/half duplex */
 359         if (cvmx_octeon_is_pass1())
 360                 /* Half duplex is broken for 38XX Pass 1 */
 361                 new_gmx_cfg.s.duplex = 1;
 362         else if (!link_info.s.link_up)
 363                 /* Force full duplex on down links */
 364                 new_gmx_cfg.s.duplex = 1;
 365         else
 366                 new_gmx_cfg.s.duplex = link_info.s.full_duplex;
 367
 368         /* Set the link speed. Anything unknown is set to 1Gbps */
 369         if (link_info.s.speed == 10) {
 370                 new_gmx_cfg.s.slottime = 0;
 371                 new_gmx_cfg.s.speed = 0;
 372         } else if (link_info.s.speed == 100) {
 373                 new_gmx_cfg.s.slottime = 0;
 374                 new_gmx_cfg.s.speed = 0;
 375         } else {
 376                 new_gmx_cfg.s.slottime = 1;
 377                 new_gmx_cfg.s.speed = 1;
 378         }
 379
 380         /* Adjust the clocks */
 381         if (link_info.s.speed == 10) {
 382                 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
 383                 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
 384                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
 385         } else if (link_info.s.speed == 100) {
 386                 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
 387                 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
 388                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
 389         } else {
 390                 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 391                 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 392                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 393         }
 394
 395         if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 396                 if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) {
 397                         union cvmx_gmxx_inf_mode mode;
 398                         mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 399
 400         /*
 401          * Port  .en  .type  .p0mii  Configuration
 402          * ----  ---  -----  ------  -----------------------------------------
 403          *  X      0     X      X    All links are disabled.
 404          *  0      1     X      0    Port 0 is RGMII
 405          *  0      1     X      1    Port 0 is MII
 406          *  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
 407          *  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
 408          *                           MII port is selected by GMX_PRT1_CFG[SPEED].
 409          */
 410
 411                         /* In MII mode, CLK_CNT = 1. */
 412                         if (((index == 0) && (mode.s.p0mii == 1))
 413                             || ((index != 0) && (mode.s.type == 1))) {
 414                                 cvmx_write_csr(CVMX_GMXX_TXX_CLK
 415                                                (index, interface), 1);
 416                         }
 417                 }
 418         }
 419
 420         /* Do a read to make sure all setup stuff is complete */
 421         cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 422
 423         /* Save the new GMX setting without enabling the port */
 424         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 425
 426         /* Enable the lowest level RX */
 427         cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 428                        cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<
 429                                                                         index));
 430
 431         /* Re-enable the TX path */
 432         for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
 433                 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
 434                 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
 435                 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,
 436                                pko_mem_queue_qos_save[i].u64);
 437         }
 438
 439         /* Restore backpressure */
 440         cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
 441
 442         /* Restore the GMX enable state. Port config is complete */
 443         new_gmx_cfg.s.en = original_gmx_cfg.s.en;
 444         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
 445
 446         return result;
 447 }
 448
 449 /**
 450  * Configure a port for internal and/or external loopback. Internal loopback
 451  * causes packets sent by the port to be received by Octeon. External loopback
 452  * causes packets received from the wire to sent out again.
 453  *
 454  * @ipd_port: IPD/PKO port to loopback.
 455  * @enable_internal:
 456  *                 Non zero if you want internal loopback
 457  * @enable_external:
 458  *                 Non zero if you want external loopback
 459  *
 460  * Returns Zero on success, negative on failure.
 461  */
 462 int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal,
 463                                            int enable_external)
 464 {
 465         int interface = cvmx_helper_get_interface_num(ipd_port);
 466         int index = cvmx_helper_get_interface_index_num(ipd_port);
 467         int original_enable;
 468         union cvmx_gmxx_prtx_cfg gmx_cfg;
 469         union cvmx_asxx_prt_loop asxx_prt_loop;
 470
 471         /* Read the current enable state and save it */
 472         gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 473         original_enable = gmx_cfg.s.en;
 474         /* Force port to be disabled */
 475         gmx_cfg.s.en = 0;
 476         if (enable_internal) {
 477                 /* Force speed if we're doing internal loopback */
 478                 gmx_cfg.s.duplex = 1;
 479                 gmx_cfg.s.slottime = 1;
 480                 gmx_cfg.s.speed = 1;
 481                 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
 482                 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
 483                 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
 484         }
 485         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 486
 487         /* Set the loopback bits */
 488         asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
 489         if (enable_internal)
 490                 asxx_prt_loop.s.int_loop |= 1 << index;
 491         else
 492                 asxx_prt_loop.s.int_loop &= ~(1 << index);
 493         if (enable_external)
 494                 asxx_prt_loop.s.ext_loop |= 1 << index;
 495         else
 496                 asxx_prt_loop.s.ext_loop &= ~(1 << index);
 497         cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
 498
 499         /* Force enables in internal loopback */
 500         if (enable_internal) {
 501                 uint64_t tmp;
 502                 tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
 503                 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface),
 504                                (1 << index) | tmp);
 505                 tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
 506                 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
 507                                (1 << index) | tmp);
 508                 original_enable = 1;
 509         }
 510
 511         /* Restore the enable state */
 512         gmx_cfg.s.en = original_enable;
 513         cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
 514         return 0;
 515 }