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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / serial / 8250_pci.c
blob7d5a8fe9d003f1ad55f03f55775a9d67d1127143
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 */
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
25
26 #include <asm/byteorder.h>
27 #include <asm/io.h>
28
29 #include "8250.h"
30
31 #undef SERIAL_DEBUG_PCI
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static void moan_device(const char *str, struct pci_dev *dev)
62 {
63 printk(KERN_WARNING
64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
68 "modem board to rmk+serial@arm.linux.org.uk.\n",
69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71 }
72
73 static int
74 setup_port(struct serial_private *priv, struct uart_port *port,
75 int bar, int offset, int regshift)
76 {
77 struct pci_dev *dev = priv->dev;
78 unsigned long base, len;
79
80 if (bar >= PCI_NUM_BAR_RESOURCES)
81 return -EINVAL;
82
83 base = pci_resource_start(dev, bar);
84
85 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
86 len = pci_resource_len(dev, bar);
87
88 if (!priv->remapped_bar[bar])
89 priv->remapped_bar[bar] = ioremap_nocache(base, len);
90 if (!priv->remapped_bar[bar])
91 return -ENOMEM;
92
93 port->iotype = UPIO_MEM;
94 port->iobase = 0;
95 port->mapbase = base + offset;
96 port->membase = priv->remapped_bar[bar] + offset;
97 port->regshift = regshift;
98 } else {
99 port->iotype = UPIO_PORT;
100 port->iobase = base + offset;
101 port->mapbase = 0;
102 port->membase = NULL;
103 port->regshift = 0;
104 }
105 return 0;
106 }
107
108 /*
109 * ADDI-DATA GmbH communication cards <info@addi-data.com>
110 */
111 static int addidata_apci7800_setup(struct serial_private *priv,
112 const struct pciserial_board *board,
113 struct uart_port *port, int idx)
114 {
115 unsigned int bar = 0, offset = board->first_offset;
116 bar = FL_GET_BASE(board->flags);
117
118 if (idx < 2) {
119 offset += idx * board->uart_offset;
120 } else if ((idx >= 2) && (idx < 4)) {
121 bar += 1;
122 offset += ((idx - 2) * board->uart_offset);
123 } else if ((idx >= 4) && (idx < 6)) {
124 bar += 2;
125 offset += ((idx - 4) * board->uart_offset);
126 } else if (idx >= 6) {
127 bar += 3;
128 offset += ((idx - 6) * board->uart_offset);
129 }
130
131 return setup_port(priv, port, bar, offset, board->reg_shift);
132 }
133
134 /*
135 * AFAVLAB uses a different mixture of BARs and offsets
136 * Not that ugly ;) -- HW
137 */
138 static int
139 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
140 struct uart_port *port, int idx)
141 {
142 unsigned int bar, offset = board->first_offset;
143
144 bar = FL_GET_BASE(board->flags);
145 if (idx < 4)
146 bar += idx;
147 else {
148 bar = 4;
149 offset += (idx - 4) * board->uart_offset;
150 }
151
152 return setup_port(priv, port, bar, offset, board->reg_shift);
153 }
154
155 /*
156 * HP's Remote Management Console. The Diva chip came in several
157 * different versions. N-class, L2000 and A500 have two Diva chips, each
158 * with 3 UARTs (the third UART on the second chip is unused). Superdome
159 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
160 * one Diva chip, but it has been expanded to 5 UARTs.
161 */
162 static int pci_hp_diva_init(struct pci_dev *dev)
163 {
164 int rc = 0;
165
166 switch (dev->subsystem_device) {
167 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
168 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
169 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
170 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
171 rc = 3;
172 break;
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
174 rc = 2;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
177 rc = 4;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
180 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
181 rc = 1;
182 break;
183 }
184
185 return rc;
186 }
187
188 /*
189 * HP's Diva chip puts the 4th/5th serial port further out, and
190 * some serial ports are supposed to be hidden on certain models.
191 */
192 static int
193 pci_hp_diva_setup(struct serial_private *priv,
194 const struct pciserial_board *board,
195 struct uart_port *port, int idx)
196 {
197 unsigned int offset = board->first_offset;
198 unsigned int bar = FL_GET_BASE(board->flags);
199
200 switch (priv->dev->subsystem_device) {
201 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
202 if (idx == 3)
203 idx++;
204 break;
205 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
206 if (idx > 0)
207 idx++;
208 if (idx > 2)
209 idx++;
210 break;
211 }
212 if (idx > 2)
213 offset = 0x18;
214
215 offset += idx * board->uart_offset;
216
217 return setup_port(priv, port, bar, offset, board->reg_shift);
218 }
219
220 /*
221 * Added for EKF Intel i960 serial boards
222 */
223 static int pci_inteli960ni_init(struct pci_dev *dev)
224 {
225 unsigned long oldval;
226
227 if (!(dev->subsystem_device & 0x1000))
228 return -ENODEV;
229
230 /* is firmware started? */
231 pci_read_config_dword(dev, 0x44, (void *)&oldval);
232 if (oldval == 0x00001000L) { /* RESET value */
233 printk(KERN_DEBUG "Local i960 firmware missing");
234 return -ENODEV;
235 }
236 return 0;
237 }
238
239 /*
240 * Some PCI serial cards using the PLX 9050 PCI interface chip require
241 * that the card interrupt be explicitly enabled or disabled. This
242 * seems to be mainly needed on card using the PLX which also use I/O
243 * mapped memory.
244 */
245 static int pci_plx9050_init(struct pci_dev *dev)
246 {
247 u8 irq_config;
248 void __iomem *p;
249
250 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
251 moan_device("no memory in bar 0", dev);
252 return 0;
253 }
254
255 irq_config = 0x41;
256 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
257 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
258 irq_config = 0x43;
259
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 /*
272 * enable/disable interrupts
273 */
274 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
275 if (p == NULL)
276 return -ENOMEM;
277 writel(irq_config, p + 0x4c);
278
279 /*
280 * Read the register back to ensure that it took effect.
281 */
282 readl(p + 0x4c);
283 iounmap(p);
284
285 return 0;
286 }
287
288 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
289 {
290 u8 __iomem *p;
291
292 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
293 return;
294
295 /*
296 * disable interrupts
297 */
298 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
299 if (p != NULL) {
300 writel(0, p + 0x4c);
301
302 /*
303 * Read the register back to ensure that it took effect.
304 */
305 readl(p + 0x4c);
306 iounmap(p);
307 }
308 }
309
310 #define NI8420_INT_ENABLE_REG 0x38
311 #define NI8420_INT_ENABLE_BIT 0x2000
312
313 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
314 {
315 void __iomem *p;
316 unsigned long base, len;
317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
324 base = pci_resource_start(dev, bar);
325 len = pci_resource_len(dev, bar);
326 p = ioremap_nocache(base, len);
327 if (p == NULL)
328 return;
329
330 /* Disable the CPU Interrupt */
331 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
332 p + NI8420_INT_ENABLE_REG);
333 iounmap(p);
334 }
335
336
337 /* MITE registers */
338 #define MITE_IOWBSR1 0xc4
339 #define MITE_IOWCR1 0xf4
340 #define MITE_LCIMR1 0x08
341 #define MITE_LCIMR2 0x10
342
343 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
344
345 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
346 {
347 void __iomem *p;
348 unsigned long base, len;
349 unsigned int bar = 0;
350
351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
352 moan_device("no memory in bar", dev);
353 return;
354 }
355
356 base = pci_resource_start(dev, bar);
357 len = pci_resource_len(dev, bar);
358 p = ioremap_nocache(base, len);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365 }
366
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368 static int
369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_port *port, int idx)
371 {
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386 }
387
388 /*
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
393 */
394
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
397
398 static int sbs_init(struct pci_dev *dev)
399 {
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416 }
417
418 /*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
422 static void __devexit sbs_exit(struct pci_dev *dev)
423 {
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 if (p != NULL)
428 writeb(0, p + OCT_REG_CR_OFF);
429 iounmap(p);
430 }
431
432 /*
433 * SIIG serial cards have an PCI interface chip which also controls
434 * the UART clocking frequency. Each UART can be clocked independently
435 * (except cards equiped with 4 UARTs) and initial clocking settings
436 * are stored in the EEPROM chip. It can cause problems because this
437 * version of serial driver doesn't support differently clocked UART's
438 * on single PCI card. To prevent this, initialization functions set
439 * high frequency clocking for all UART's on given card. It is safe (I
440 * hope) because it doesn't touch EEPROM settings to prevent conflicts
441 * with other OSes (like M$ DOS).
442 *
443 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
444 *
445 * There is two family of SIIG serial cards with different PCI
446 * interface chip and different configuration methods:
447 * - 10x cards have control registers in IO and/or memory space;
448 * - 20x cards have control registers in standard PCI configuration space.
449 *
450 * Note: all 10x cards have PCI device ids 0x10..
451 * all 20x cards have PCI device ids 0x20..
452 *
453 * There are also Quartet Serial cards which use Oxford Semiconductor
454 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
455 *
456 * Note: some SIIG cards are probed by the parport_serial object.
457 */
458
459 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
460 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
461
462 static int pci_siig10x_init(struct pci_dev *dev)
463 {
464 u16 data;
465 void __iomem *p;
466
467 switch (dev->device & 0xfff8) {
468 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
469 data = 0xffdf;
470 break;
471 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
472 data = 0xf7ff;
473 break;
474 default: /* 1S1P, 4S */
475 data = 0xfffb;
476 break;
477 }
478
479 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
480 if (p == NULL)
481 return -ENOMEM;
482
483 writew(readw(p + 0x28) & data, p + 0x28);
484 readw(p + 0x28);
485 iounmap(p);
486 return 0;
487 }
488
489 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
490 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
491
492 static int pci_siig20x_init(struct pci_dev *dev)
493 {
494 u8 data;
495
496 /* Change clock frequency for the first UART. */
497 pci_read_config_byte(dev, 0x6f, &data);
498 pci_write_config_byte(dev, 0x6f, data & 0xef);
499
500 /* If this card has 2 UART, we have to do the same with second UART. */
501 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
502 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
503 pci_read_config_byte(dev, 0x73, &data);
504 pci_write_config_byte(dev, 0x73, data & 0xef);
505 }
506 return 0;
507 }
508
509 static int pci_siig_init(struct pci_dev *dev)
510 {
511 unsigned int type = dev->device & 0xff00;
512
513 if (type == 0x1000)
514 return pci_siig10x_init(dev);
515 else if (type == 0x2000)
516 return pci_siig20x_init(dev);
517
518 moan_device("Unknown SIIG card", dev);
519 return -ENODEV;
520 }
521
522 static int pci_siig_setup(struct serial_private *priv,
523 const struct pciserial_board *board,
524 struct uart_port *port, int idx)
525 {
526 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
527
528 if (idx > 3) {
529 bar = 4;
530 offset = (idx - 4) * 8;
531 }
532
533 return setup_port(priv, port, bar, offset, 0);
534 }
535
536 /*
537 * Timedia has an explosion of boards, and to avoid the PCI table from
538 * growing *huge*, we use this function to collapse some 70 entries
539 * in the PCI table into one, for sanity's and compactness's sake.
540 */
541 static const unsigned short timedia_single_port[] = {
542 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
543 };
544
545 static const unsigned short timedia_dual_port[] = {
546 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
547 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
548 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
549 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
550 0xD079, 0
551 };
552
553 static const unsigned short timedia_quad_port[] = {
554 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
555 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
556 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
557 0xB157, 0
558 };
559
560 static const unsigned short timedia_eight_port[] = {
561 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
562 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
563 };
564
565 static const struct timedia_struct {
566 int num;
567 const unsigned short *ids;
568 } timedia_data[] = {
569 { 1, timedia_single_port },
570 { 2, timedia_dual_port },
571 { 4, timedia_quad_port },
572 { 8, timedia_eight_port }
573 };
574
575 static int pci_timedia_init(struct pci_dev *dev)
576 {
577 const unsigned short *ids;
578 int i, j;
579
580 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
581 ids = timedia_data[i].ids;
582 for (j = 0; ids[j]; j++)
583 if (dev->subsystem_device == ids[j])
584 return timedia_data[i].num;
585 }
586 return 0;
587 }
588
589 /*
590 * Timedia/SUNIX uses a mixture of BARs and offsets
591 * Ugh, this is ugly as all hell --- TYT
592 */
593 static int
594 pci_timedia_setup(struct serial_private *priv,
595 const struct pciserial_board *board,
596 struct uart_port *port, int idx)
597 {
598 unsigned int bar = 0, offset = board->first_offset;
599
600 switch (idx) {
601 case 0:
602 bar = 0;
603 break;
604 case 1:
605 offset = board->uart_offset;
606 bar = 0;
607 break;
608 case 2:
609 bar = 1;
610 break;
611 case 3:
612 offset = board->uart_offset;
613 /* FALLTHROUGH */
614 case 4: /* BAR 2 */
615 case 5: /* BAR 3 */
616 case 6: /* BAR 4 */
617 case 7: /* BAR 5 */
618 bar = idx - 2;
619 }
620
621 return setup_port(priv, port, bar, offset, board->reg_shift);
622 }
623
624 /*
625 * Some Titan cards are also a little weird
626 */
627 static int
628 titan_400l_800l_setup(struct serial_private *priv,
629 const struct pciserial_board *board,
630 struct uart_port *port, int idx)
631 {
632 unsigned int bar, offset = board->first_offset;
633
634 switch (idx) {
635 case 0:
636 bar = 1;
637 break;
638 case 1:
639 bar = 2;
640 break;
641 default:
642 bar = 4;
643 offset = (idx - 2) * board->uart_offset;
644 }
645
646 return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 static int pci_xircom_init(struct pci_dev *dev)
650 {
651 msleep(100);
652 return 0;
653 }
654
655 static int pci_ni8420_init(struct pci_dev *dev)
656 {
657 void __iomem *p;
658 unsigned long base, len;
659 unsigned int bar = 0;
660
661 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
662 moan_device("no memory in bar", dev);
663 return 0;
664 }
665
666 base = pci_resource_start(dev, bar);
667 len = pci_resource_len(dev, bar);
668 p = ioremap_nocache(base, len);
669 if (p == NULL)
670 return -ENOMEM;
671
672 /* Enable CPU Interrupt */
673 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
674 p + NI8420_INT_ENABLE_REG);
675
676 iounmap(p);
677 return 0;
678 }
679
680 #define MITE_IOWBSR1_WSIZE 0xa
681 #define MITE_IOWBSR1_WIN_OFFSET 0x800
682 #define MITE_IOWBSR1_WENAB (1 << 7)
683 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
684 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
685 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
686
687 static int pci_ni8430_init(struct pci_dev *dev)
688 {
689 void __iomem *p;
690 unsigned long base, len;
691 u32 device_window;
692 unsigned int bar = 0;
693
694 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
695 moan_device("no memory in bar", dev);
696 return 0;
697 }
698
699 base = pci_resource_start(dev, bar);
700 len = pci_resource_len(dev, bar);
701 p = ioremap_nocache(base, len);
702 if (p == NULL)
703 return -ENOMEM;
704
705 /* Set device window address and size in BAR0 */
706 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
707 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
708 writel(device_window, p + MITE_IOWBSR1);
709
710 /* Set window access to go to RAMSEL IO address space */
711 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
712 p + MITE_IOWCR1);
713
714 /* Enable IO Bus Interrupt 0 */
715 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
716
717 /* Enable CPU Interrupt */
718 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
719
720 iounmap(p);
721 return 0;
722 }
723
724 /* UART Port Control Register */
725 #define NI8430_PORTCON 0x0f
726 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
727
728 static int
729 pci_ni8430_setup(struct serial_private *priv,
730 const struct pciserial_board *board,
731 struct uart_port *port, int idx)
732 {
733 void __iomem *p;
734 unsigned long base, len;
735 unsigned int bar, offset = board->first_offset;
736
737 if (idx >= board->num_ports)
738 return 1;
739
740 bar = FL_GET_BASE(board->flags);
741 offset += idx * board->uart_offset;
742
743 base = pci_resource_start(priv->dev, bar);
744 len = pci_resource_len(priv->dev, bar);
745 p = ioremap_nocache(base, len);
746
747 /* enable the transciever */
748 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
749 p + offset + NI8430_PORTCON);
750
751 iounmap(p);
752
753 return setup_port(priv, port, bar, offset, board->reg_shift);
754 }
755
756
757 static int pci_netmos_init(struct pci_dev *dev)
758 {
759 /* subdevice 0x00PS means <P> parallel, <S> serial */
760 unsigned int num_serial = dev->subsystem_device & 0xf;
761
762 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
763 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
764 return 0;
765 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
766 dev->subsystem_device == 0x0299)
767 return 0;
768
769 if (num_serial == 0)
770 return -ENODEV;
771 return num_serial;
772 }
773
774 /*
775 * These chips are available with optionally one parallel port and up to
776 * two serial ports. Unfortunately they all have the same product id.
777 *
778 * Basic configuration is done over a region of 32 I/O ports. The base
779 * ioport is called INTA or INTC, depending on docs/other drivers.
780 *
781 * The region of the 32 I/O ports is configured in POSIO0R...
782 */
783
784 /* registers */
785 #define ITE_887x_MISCR 0x9c
786 #define ITE_887x_INTCBAR 0x78
787 #define ITE_887x_UARTBAR 0x7c
788 #define ITE_887x_PS0BAR 0x10
789 #define ITE_887x_POSIO0 0x60
790
791 /* I/O space size */
792 #define ITE_887x_IOSIZE 32
793 /* I/O space size (bits 26-24; 8 bytes = 011b) */
794 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
795 /* I/O space size (bits 26-24; 32 bytes = 101b) */
796 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
797 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
798 #define ITE_887x_POSIO_SPEED (3 << 29)
799 /* enable IO_Space bit */
800 #define ITE_887x_POSIO_ENABLE (1 << 31)
801
802 static int pci_ite887x_init(struct pci_dev *dev)
803 {
804 /* inta_addr are the configuration addresses of the ITE */
805 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
806 0x200, 0x280, 0 };
807 int ret, i, type;
808 struct resource *iobase = NULL;
809 u32 miscr, uartbar, ioport;
810
811 /* search for the base-ioport */
812 i = 0;
813 while (inta_addr[i] && iobase == NULL) {
814 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
815 "ite887x");
816 if (iobase != NULL) {
817 /* write POSIO0R - speed | size | ioport */
818 pci_write_config_dword(dev, ITE_887x_POSIO0,
819 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
820 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
821 /* write INTCBAR - ioport */
822 pci_write_config_dword(dev, ITE_887x_INTCBAR,
823 inta_addr[i]);
824 ret = inb(inta_addr[i]);
825 if (ret != 0xff) {
826 /* ioport connected */
827 break;
828 }
829 release_region(iobase->start, ITE_887x_IOSIZE);
830 iobase = NULL;
831 }
832 i++;
833 }
834
835 if (!inta_addr[i]) {
836 printk(KERN_ERR "ite887x: could not find iobase\n");
837 return -ENODEV;
838 }
839
840 /* start of undocumented type checking (see parport_pc.c) */
841 type = inb(iobase->start + 0x18) & 0x0f;
842
843 switch (type) {
844 case 0x2: /* ITE8871 (1P) */
845 case 0xa: /* ITE8875 (1P) */
846 ret = 0;
847 break;
848 case 0xe: /* ITE8872 (2S1P) */
849 ret = 2;
850 break;
851 case 0x6: /* ITE8873 (1S) */
852 ret = 1;
853 break;
854 case 0x8: /* ITE8874 (2S) */
855 ret = 2;
856 break;
857 default:
858 moan_device("Unknown ITE887x", dev);
859 ret = -ENODEV;
860 }
861
862 /* configure all serial ports */
863 for (i = 0; i < ret; i++) {
864 /* read the I/O port from the device */
865 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
866 &ioport);
867 ioport &= 0x0000FF00; /* the actual base address */
868 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
869 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
870 ITE_887x_POSIO_IOSIZE_8 | ioport);
871
872 /* write the ioport to the UARTBAR */
873 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
874 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
875 uartbar |= (ioport << (16 * i)); /* set the ioport */
876 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
877
878 /* get current config */
879 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
880 /* disable interrupts (UARTx_Routing[3:0]) */
881 miscr &= ~(0xf << (12 - 4 * i));
882 /* activate the UART (UARTx_En) */
883 miscr |= 1 << (23 - i);
884 /* write new config with activated UART */
885 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
886 }
887
888 if (ret <= 0) {
889 /* the device has no UARTs if we get here */
890 release_region(iobase->start, ITE_887x_IOSIZE);
891 }
892
893 return ret;
894 }
895
896 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
897 {
898 u32 ioport;
899 /* the ioport is bit 0-15 in POSIO0R */
900 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
901 ioport &= 0xffff;
902 release_region(ioport, ITE_887x_IOSIZE);
903 }
904
905 /*
906 * Oxford Semiconductor Inc.
907 * Check that device is part of the Tornado range of devices, then determine
908 * the number of ports available on the device.
909 */
910 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
911 {
912 u8 __iomem *p;
913 unsigned long deviceID;
914 unsigned int number_uarts = 0;
915
916 /* OxSemi Tornado devices are all 0xCxxx */
917 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
918 (dev->device & 0xF000) != 0xC000)
919 return 0;
920
921 p = pci_iomap(dev, 0, 5);
922 if (p == NULL)
923 return -ENOMEM;
924
925 deviceID = ioread32(p);
926 /* Tornado device */
927 if (deviceID == 0x07000200) {
928 number_uarts = ioread8(p + 4);
929 printk(KERN_DEBUG
930 "%d ports detected on Oxford PCI Express device\n",
931 number_uarts);
932 }
933 pci_iounmap(dev, p);
934 return number_uarts;
935 }
936
937 static int
938 pci_default_setup(struct serial_private *priv,
939 const struct pciserial_board *board,
940 struct uart_port *port, int idx)
941 {
942 unsigned int bar, offset = board->first_offset, maxnr;
943
944 bar = FL_GET_BASE(board->flags);
945 if (board->flags & FL_BASE_BARS)
946 bar += idx;
947 else
948 offset += idx * board->uart_offset;
949
950 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
951 (board->reg_shift + 3);
952
953 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
954 return 1;
955
956 return setup_port(priv, port, bar, offset, board->reg_shift);
957 }
958
959 static int skip_tx_en_setup(struct serial_private *priv,
960 const struct pciserial_board *board,
961 struct uart_port *port, int idx)
962 {
963 port->flags |= UPF_NO_TXEN_TEST;
964 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
965 "[%04x:%04x] subsystem [%04x:%04x]\n",
966 priv->dev->vendor,
967 priv->dev->device,
968 priv->dev->subsystem_vendor,
969 priv->dev->subsystem_device);
970
971 return pci_default_setup(priv, board, port, idx);
972 }
973
974 /* This should be in linux/pci_ids.h */
975 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
976 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
977 #define PCI_DEVICE_ID_OCTPRO 0x0001
978 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
979 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
980 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
981 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
982 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
983 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
984 #define PCI_DEVICE_ID_TITAN_200I 0x8028
985 #define PCI_DEVICE_ID_TITAN_400I 0x8048
986 #define PCI_DEVICE_ID_TITAN_800I 0x8088
987 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
988 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
989 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
990 #define PCI_DEVICE_ID_TITAN_100E 0xA010
991 #define PCI_DEVICE_ID_TITAN_200E 0xA012
992 #define PCI_DEVICE_ID_TITAN_400E 0xA013
993 #define PCI_DEVICE_ID_TITAN_800E 0xA014
994 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
995 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
996 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
997
998 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
999 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1000
1001 /*
1002 * Master list of serial port init/setup/exit quirks.
1003 * This does not describe the general nature of the port.
1004 * (ie, baud base, number and location of ports, etc)
1005 *
1006 * This list is ordered alphabetically by vendor then device.
1007 * Specific entries must come before more generic entries.
1008 */
1009 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1010 /*
1011 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1012 */
1013 {
1014 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1015 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1016 .subvendor = PCI_ANY_ID,
1017 .subdevice = PCI_ANY_ID,
1018 .setup = addidata_apci7800_setup,
1019 },
1020 /*
1021 * AFAVLAB cards - these may be called via parport_serial
1022 * It is not clear whether this applies to all products.
1023 */
1024 {
1025 .vendor = PCI_VENDOR_ID_AFAVLAB,
1026 .device = PCI_ANY_ID,
1027 .subvendor = PCI_ANY_ID,
1028 .subdevice = PCI_ANY_ID,
1029 .setup = afavlab_setup,
1030 },
1031 /*
1032 * HP Diva
1033 */
1034 {
1035 .vendor = PCI_VENDOR_ID_HP,
1036 .device = PCI_DEVICE_ID_HP_DIVA,
1037 .subvendor = PCI_ANY_ID,
1038 .subdevice = PCI_ANY_ID,
1039 .init = pci_hp_diva_init,
1040 .setup = pci_hp_diva_setup,
1041 },
1042 /*
1043 * Intel
1044 */
1045 {
1046 .vendor = PCI_VENDOR_ID_INTEL,
1047 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1048 .subvendor = 0xe4bf,
1049 .subdevice = PCI_ANY_ID,
1050 .init = pci_inteli960ni_init,
1051 .setup = pci_default_setup,
1052 },
1053 {
1054 .vendor = PCI_VENDOR_ID_INTEL,
1055 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1056 .subvendor = PCI_ANY_ID,
1057 .subdevice = PCI_ANY_ID,
1058 .setup = skip_tx_en_setup,
1059 },
1060 {
1061 .vendor = PCI_VENDOR_ID_INTEL,
1062 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1063 .subvendor = PCI_ANY_ID,
1064 .subdevice = PCI_ANY_ID,
1065 .setup = skip_tx_en_setup,
1066 },
1067 {
1068 .vendor = PCI_VENDOR_ID_INTEL,
1069 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1070 .subvendor = PCI_ANY_ID,
1071 .subdevice = PCI_ANY_ID,
1072 .setup = skip_tx_en_setup,
1073 },
1074 /*
1075 * ITE
1076 */
1077 {
1078 .vendor = PCI_VENDOR_ID_ITE,
1079 .device = PCI_DEVICE_ID_ITE_8872,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .init = pci_ite887x_init,
1083 .setup = pci_default_setup,
1084 .exit = __devexit_p(pci_ite887x_exit),
1085 },
1086 /*
1087 * National Instruments
1088 */
1089 {
1090 .vendor = PCI_VENDOR_ID_NI,
1091 .device = PCI_DEVICE_ID_NI_PCI23216,
1092 .subvendor = PCI_ANY_ID,
1093 .subdevice = PCI_ANY_ID,
1094 .init = pci_ni8420_init,
1095 .setup = pci_default_setup,
1096 .exit = __devexit_p(pci_ni8420_exit),
1097 },
1098 {
1099 .vendor = PCI_VENDOR_ID_NI,
1100 .device = PCI_DEVICE_ID_NI_PCI2328,
1101 .subvendor = PCI_ANY_ID,
1102 .subdevice = PCI_ANY_ID,
1103 .init = pci_ni8420_init,
1104 .setup = pci_default_setup,
1105 .exit = __devexit_p(pci_ni8420_exit),
1106 },
1107 {
1108 .vendor = PCI_VENDOR_ID_NI,
1109 .device = PCI_DEVICE_ID_NI_PCI2324,
1110 .subvendor = PCI_ANY_ID,
1111 .subdevice = PCI_ANY_ID,
1112 .init = pci_ni8420_init,
1113 .setup = pci_default_setup,
1114 .exit = __devexit_p(pci_ni8420_exit),
1115 },
1116 {
1117 .vendor = PCI_VENDOR_ID_NI,
1118 .device = PCI_DEVICE_ID_NI_PCI2322,
1119 .subvendor = PCI_ANY_ID,
1120 .subdevice = PCI_ANY_ID,
1121 .init = pci_ni8420_init,
1122 .setup = pci_default_setup,
1123 .exit = __devexit_p(pci_ni8420_exit),
1124 },
1125 {
1126 .vendor = PCI_VENDOR_ID_NI,
1127 .device = PCI_DEVICE_ID_NI_PCI2324I,
1128 .subvendor = PCI_ANY_ID,
1129 .subdevice = PCI_ANY_ID,
1130 .init = pci_ni8420_init,
1131 .setup = pci_default_setup,
1132 .exit = __devexit_p(pci_ni8420_exit),
1133 },
1134 {
1135 .vendor = PCI_VENDOR_ID_NI,
1136 .device = PCI_DEVICE_ID_NI_PCI2322I,
1137 .subvendor = PCI_ANY_ID,
1138 .subdevice = PCI_ANY_ID,
1139 .init = pci_ni8420_init,
1140 .setup = pci_default_setup,
1141 .exit = __devexit_p(pci_ni8420_exit),
1142 },
1143 {
1144 .vendor = PCI_VENDOR_ID_NI,
1145 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1146 .subvendor = PCI_ANY_ID,
1147 .subdevice = PCI_ANY_ID,
1148 .init = pci_ni8420_init,
1149 .setup = pci_default_setup,
1150 .exit = __devexit_p(pci_ni8420_exit),
1151 },
1152 {
1153 .vendor = PCI_VENDOR_ID_NI,
1154 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1155 .subvendor = PCI_ANY_ID,
1156 .subdevice = PCI_ANY_ID,
1157 .init = pci_ni8420_init,
1158 .setup = pci_default_setup,
1159 .exit = __devexit_p(pci_ni8420_exit),
1160 },
1161 {
1162 .vendor = PCI_VENDOR_ID_NI,
1163 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1164 .subvendor = PCI_ANY_ID,
1165 .subdevice = PCI_ANY_ID,
1166 .init = pci_ni8420_init,
1167 .setup = pci_default_setup,
1168 .exit = __devexit_p(pci_ni8420_exit),
1169 },
1170 {
1171 .vendor = PCI_VENDOR_ID_NI,
1172 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1173 .subvendor = PCI_ANY_ID,
1174 .subdevice = PCI_ANY_ID,
1175 .init = pci_ni8420_init,
1176 .setup = pci_default_setup,
1177 .exit = __devexit_p(pci_ni8420_exit),
1178 },
1179 {
1180 .vendor = PCI_VENDOR_ID_NI,
1181 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1182 .subvendor = PCI_ANY_ID,
1183 .subdevice = PCI_ANY_ID,
1184 .init = pci_ni8420_init,
1185 .setup = pci_default_setup,
1186 .exit = __devexit_p(pci_ni8420_exit),
1187 },
1188 {
1189 .vendor = PCI_VENDOR_ID_NI,
1190 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1191 .subvendor = PCI_ANY_ID,
1192 .subdevice = PCI_ANY_ID,
1193 .init = pci_ni8420_init,
1194 .setup = pci_default_setup,
1195 .exit = __devexit_p(pci_ni8420_exit),
1196 },
1197 {
1198 .vendor = PCI_VENDOR_ID_NI,
1199 .device = PCI_ANY_ID,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .init = pci_ni8430_init,
1203 .setup = pci_ni8430_setup,
1204 .exit = __devexit_p(pci_ni8430_exit),
1205 },
1206 /*
1207 * Panacom
1208 */
1209 {
1210 .vendor = PCI_VENDOR_ID_PANACOM,
1211 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1212 .subvendor = PCI_ANY_ID,
1213 .subdevice = PCI_ANY_ID,
1214 .init = pci_plx9050_init,
1215 .setup = pci_default_setup,
1216 .exit = __devexit_p(pci_plx9050_exit),
1217 },
1218 {
1219 .vendor = PCI_VENDOR_ID_PANACOM,
1220 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1221 .subvendor = PCI_ANY_ID,
1222 .subdevice = PCI_ANY_ID,
1223 .init = pci_plx9050_init,
1224 .setup = pci_default_setup,
1225 .exit = __devexit_p(pci_plx9050_exit),
1226 },
1227 /*
1228 * PLX
1229 */
1230 {
1231 .vendor = PCI_VENDOR_ID_PLX,
1232 .device = PCI_DEVICE_ID_PLX_9030,
1233 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1234 .subdevice = PCI_ANY_ID,
1235 .setup = pci_default_setup,
1236 },
1237 {
1238 .vendor = PCI_VENDOR_ID_PLX,
1239 .device = PCI_DEVICE_ID_PLX_9050,
1240 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1241 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1242 .init = pci_plx9050_init,
1243 .setup = pci_default_setup,
1244 .exit = __devexit_p(pci_plx9050_exit),
1245 },
1246 {
1247 .vendor = PCI_VENDOR_ID_PLX,
1248 .device = PCI_DEVICE_ID_PLX_9050,
1249 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1250 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1251 .init = pci_plx9050_init,
1252 .setup = pci_default_setup,
1253 .exit = __devexit_p(pci_plx9050_exit),
1254 },
1255 {
1256 .vendor = PCI_VENDOR_ID_PLX,
1257 .device = PCI_DEVICE_ID_PLX_9050,
1258 .subvendor = PCI_VENDOR_ID_PLX,
1259 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1260 .init = pci_plx9050_init,
1261 .setup = pci_default_setup,
1262 .exit = __devexit_p(pci_plx9050_exit),
1263 },
1264 {
1265 .vendor = PCI_VENDOR_ID_PLX,
1266 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1267 .subvendor = PCI_VENDOR_ID_PLX,
1268 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1269 .init = pci_plx9050_init,
1270 .setup = pci_default_setup,
1271 .exit = __devexit_p(pci_plx9050_exit),
1272 },
1273 /*
1274 * SBS Technologies, Inc., PMC-OCTALPRO 232
1275 */
1276 {
1277 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1278 .device = PCI_DEVICE_ID_OCTPRO,
1279 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1280 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1281 .init = sbs_init,
1282 .setup = sbs_setup,
1283 .exit = __devexit_p(sbs_exit),
1284 },
1285 /*
1286 * SBS Technologies, Inc., PMC-OCTALPRO 422
1287 */
1288 {
1289 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1290 .device = PCI_DEVICE_ID_OCTPRO,
1291 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1292 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1293 .init = sbs_init,
1294 .setup = sbs_setup,
1295 .exit = __devexit_p(sbs_exit),
1296 },
1297 /*
1298 * SBS Technologies, Inc., P-Octal 232
1299 */
1300 {
1301 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1302 .device = PCI_DEVICE_ID_OCTPRO,
1303 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1304 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1305 .init = sbs_init,
1306 .setup = sbs_setup,
1307 .exit = __devexit_p(sbs_exit),
1308 },
1309 /*
1310 * SBS Technologies, Inc., P-Octal 422
1311 */
1312 {
1313 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1314 .device = PCI_DEVICE_ID_OCTPRO,
1315 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1316 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1317 .init = sbs_init,
1318 .setup = sbs_setup,
1319 .exit = __devexit_p(sbs_exit),
1320 },
1321 /*
1322 * SIIG cards - these may be called via parport_serial
1323 */
1324 {
1325 .vendor = PCI_VENDOR_ID_SIIG,
1326 .device = PCI_ANY_ID,
1327 .subvendor = PCI_ANY_ID,
1328 .subdevice = PCI_ANY_ID,
1329 .init = pci_siig_init,
1330 .setup = pci_siig_setup,
1331 },
1332 /*
1333 * Titan cards
1334 */
1335 {
1336 .vendor = PCI_VENDOR_ID_TITAN,
1337 .device = PCI_DEVICE_ID_TITAN_400L,
1338 .subvendor = PCI_ANY_ID,
1339 .subdevice = PCI_ANY_ID,
1340 .setup = titan_400l_800l_setup,
1341 },
1342 {
1343 .vendor = PCI_VENDOR_ID_TITAN,
1344 .device = PCI_DEVICE_ID_TITAN_800L,
1345 .subvendor = PCI_ANY_ID,
1346 .subdevice = PCI_ANY_ID,
1347 .setup = titan_400l_800l_setup,
1348 },
1349 /*
1350 * Timedia cards
1351 */
1352 {
1353 .vendor = PCI_VENDOR_ID_TIMEDIA,
1354 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1355 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1356 .subdevice = PCI_ANY_ID,
1357 .init = pci_timedia_init,
1358 .setup = pci_timedia_setup,
1359 },
1360 {
1361 .vendor = PCI_VENDOR_ID_TIMEDIA,
1362 .device = PCI_ANY_ID,
1363 .subvendor = PCI_ANY_ID,
1364 .subdevice = PCI_ANY_ID,
1365 .setup = pci_timedia_setup,
1366 },
1367 /*
1368 * Xircom cards
1369 */
1370 {
1371 .vendor = PCI_VENDOR_ID_XIRCOM,
1372 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1373 .subvendor = PCI_ANY_ID,
1374 .subdevice = PCI_ANY_ID,
1375 .init = pci_xircom_init,
1376 .setup = pci_default_setup,
1377 },
1378 /*
1379 * Netmos cards - these may be called via parport_serial
1380 */
1381 {
1382 .vendor = PCI_VENDOR_ID_NETMOS,
1383 .device = PCI_ANY_ID,
1384 .subvendor = PCI_ANY_ID,
1385 .subdevice = PCI_ANY_ID,
1386 .init = pci_netmos_init,
1387 .setup = pci_default_setup,
1388 },
1389 /*
1390 * For Oxford Semiconductor and Mainpine
1391 */
1392 {
1393 .vendor = PCI_VENDOR_ID_OXSEMI,
1394 .device = PCI_ANY_ID,
1395 .subvendor = PCI_ANY_ID,
1396 .subdevice = PCI_ANY_ID,
1397 .init = pci_oxsemi_tornado_init,
1398 .setup = pci_default_setup,
1399 },
1400 {
1401 .vendor = PCI_VENDOR_ID_MAINPINE,
1402 .device = PCI_ANY_ID,
1403 .subvendor = PCI_ANY_ID,
1404 .subdevice = PCI_ANY_ID,
1405 .init = pci_oxsemi_tornado_init,
1406 .setup = pci_default_setup,
1407 },
1408 /*
1409 * Default "match everything" terminator entry
1410 */
1411 {
1412 .vendor = PCI_ANY_ID,
1413 .device = PCI_ANY_ID,
1414 .subvendor = PCI_ANY_ID,
1415 .subdevice = PCI_ANY_ID,
1416 .setup = pci_default_setup,
1417 }
1418 };
1419
1420 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1421 {
1422 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1423 }
1424
1425 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1426 {
1427 struct pci_serial_quirk *quirk;
1428
1429 for (quirk = pci_serial_quirks; ; quirk++)
1430 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1431 quirk_id_matches(quirk->device, dev->device) &&
1432 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1433 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1434 break;
1435 return quirk;
1436 }
1437
1438 static inline int get_pci_irq(struct pci_dev *dev,
1439 const struct pciserial_board *board)
1440 {
1441 if (board->flags & FL_NOIRQ)
1442 return 0;
1443 else
1444 return dev->irq;
1445 }
1446
1447 /*
1448 * This is the configuration table for all of the PCI serial boards
1449 * which we support. It is directly indexed by the pci_board_num_t enum
1450 * value, which is encoded in the pci_device_id PCI probe table's
1451 * driver_data member.
1452 *
1453 * The makeup of these names are:
1454 * pbn_bn{_bt}_n_baud{_offsetinhex}
1455 *
1456 * bn = PCI BAR number
1457 * bt = Index using PCI BARs
1458 * n = number of serial ports
1459 * baud = baud rate
1460 * offsetinhex = offset for each sequential port (in hex)
1461 *
1462 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1463 *
1464 * Please note: in theory if n = 1, _bt infix should make no difference.
1465 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1466 */
1467 enum pci_board_num_t {
1468 pbn_default = 0,
1469
1470 pbn_b0_1_115200,
1471 pbn_b0_2_115200,
1472 pbn_b0_4_115200,
1473 pbn_b0_5_115200,
1474 pbn_b0_8_115200,
1475
1476 pbn_b0_1_921600,
1477 pbn_b0_2_921600,
1478 pbn_b0_4_921600,
1479
1480 pbn_b0_2_1130000,
1481
1482 pbn_b0_4_1152000,
1483
1484 pbn_b0_2_1843200,
1485 pbn_b0_4_1843200,
1486
1487 pbn_b0_2_1843200_200,
1488 pbn_b0_4_1843200_200,
1489 pbn_b0_8_1843200_200,
1490
1491 pbn_b0_1_4000000,
1492
1493 pbn_b0_bt_1_115200,
1494 pbn_b0_bt_2_115200,
1495 pbn_b0_bt_4_115200,
1496 pbn_b0_bt_8_115200,
1497
1498 pbn_b0_bt_1_460800,
1499 pbn_b0_bt_2_460800,
1500 pbn_b0_bt_4_460800,
1501
1502 pbn_b0_bt_1_921600,
1503 pbn_b0_bt_2_921600,
1504 pbn_b0_bt_4_921600,
1505 pbn_b0_bt_8_921600,
1506
1507 pbn_b1_1_115200,
1508 pbn_b1_2_115200,
1509 pbn_b1_4_115200,
1510 pbn_b1_8_115200,
1511 pbn_b1_16_115200,
1512
1513 pbn_b1_1_921600,
1514 pbn_b1_2_921600,
1515 pbn_b1_4_921600,
1516 pbn_b1_8_921600,
1517
1518 pbn_b1_2_1250000,
1519
1520 pbn_b1_bt_1_115200,
1521 pbn_b1_bt_2_115200,
1522 pbn_b1_bt_4_115200,
1523
1524 pbn_b1_bt_2_921600,
1525
1526 pbn_b1_1_1382400,
1527 pbn_b1_2_1382400,
1528 pbn_b1_4_1382400,
1529 pbn_b1_8_1382400,
1530
1531 pbn_b2_1_115200,
1532 pbn_b2_2_115200,
1533 pbn_b2_4_115200,
1534 pbn_b2_8_115200,
1535
1536 pbn_b2_1_460800,
1537 pbn_b2_4_460800,
1538 pbn_b2_8_460800,
1539 pbn_b2_16_460800,
1540
1541 pbn_b2_1_921600,
1542 pbn_b2_4_921600,
1543 pbn_b2_8_921600,
1544
1545 pbn_b2_8_1152000,
1546
1547 pbn_b2_bt_1_115200,
1548 pbn_b2_bt_2_115200,
1549 pbn_b2_bt_4_115200,
1550
1551 pbn_b2_bt_2_921600,
1552 pbn_b2_bt_4_921600,
1553
1554 pbn_b3_2_115200,
1555 pbn_b3_4_115200,
1556 pbn_b3_8_115200,
1557
1558 pbn_b4_bt_2_921600,
1559 pbn_b4_bt_4_921600,
1560 pbn_b4_bt_8_921600,
1561
1562 /*
1563 * Board-specific versions.
1564 */
1565 pbn_panacom,
1566 pbn_panacom2,
1567 pbn_panacom4,
1568 pbn_exsys_4055,
1569 pbn_plx_romulus,
1570 pbn_oxsemi,
1571 pbn_oxsemi_1_4000000,
1572 pbn_oxsemi_2_4000000,
1573 pbn_oxsemi_4_4000000,
1574 pbn_oxsemi_8_4000000,
1575 pbn_intel_i960,
1576 pbn_sgi_ioc3,
1577 pbn_computone_4,
1578 pbn_computone_6,
1579 pbn_computone_8,
1580 pbn_sbsxrsio,
1581 pbn_exar_XR17C152,
1582 pbn_exar_XR17C154,
1583 pbn_exar_XR17C158,
1584 pbn_exar_ibm_saturn,
1585 pbn_pasemi_1682M,
1586 pbn_ni8430_2,
1587 pbn_ni8430_4,
1588 pbn_ni8430_8,
1589 pbn_ni8430_16,
1590 pbn_ADDIDATA_PCIe_1_3906250,
1591 pbn_ADDIDATA_PCIe_2_3906250,
1592 pbn_ADDIDATA_PCIe_4_3906250,
1593 pbn_ADDIDATA_PCIe_8_3906250,
1594 };
1595
1596 /*
1597 * uart_offset - the space between channels
1598 * reg_shift - describes how the UART registers are mapped
1599 * to PCI memory by the card.
1600 * For example IER register on SBS, Inc. PMC-OctPro is located at
1601 * offset 0x10 from the UART base, while UART_IER is defined as 1
1602 * in include/linux/serial_reg.h,
1603 * see first lines of serial_in() and serial_out() in 8250.c
1604 */
1605
1606 static struct pciserial_board pci_boards[] __devinitdata = {
1607 [pbn_default] = {
1608 .flags = FL_BASE0,
1609 .num_ports = 1,
1610 .base_baud = 115200,
1611 .uart_offset = 8,
1612 },
1613 [pbn_b0_1_115200] = {
1614 .flags = FL_BASE0,
1615 .num_ports = 1,
1616 .base_baud = 115200,
1617 .uart_offset = 8,
1618 },
1619 [pbn_b0_2_115200] = {
1620 .flags = FL_BASE0,
1621 .num_ports = 2,
1622 .base_baud = 115200,
1623 .uart_offset = 8,
1624 },
1625 [pbn_b0_4_115200] = {
1626 .flags = FL_BASE0,
1627 .num_ports = 4,
1628 .base_baud = 115200,
1629 .uart_offset = 8,
1630 },
1631 [pbn_b0_5_115200] = {
1632 .flags = FL_BASE0,
1633 .num_ports = 5,
1634 .base_baud = 115200,
1635 .uart_offset = 8,
1636 },
1637 [pbn_b0_8_115200] = {
1638 .flags = FL_BASE0,
1639 .num_ports = 8,
1640 .base_baud = 115200,
1641 .uart_offset = 8,
1642 },
1643 [pbn_b0_1_921600] = {
1644 .flags = FL_BASE0,
1645 .num_ports = 1,
1646 .base_baud = 921600,
1647 .uart_offset = 8,
1648 },
1649 [pbn_b0_2_921600] = {
1650 .flags = FL_BASE0,
1651 .num_ports = 2,
1652 .base_baud = 921600,
1653 .uart_offset = 8,
1654 },
1655 [pbn_b0_4_921600] = {
1656 .flags = FL_BASE0,
1657 .num_ports = 4,
1658 .base_baud = 921600,
1659 .uart_offset = 8,
1660 },
1661
1662 [pbn_b0_2_1130000] = {
1663 .flags = FL_BASE0,
1664 .num_ports = 2,
1665 .base_baud = 1130000,
1666 .uart_offset = 8,
1667 },
1668
1669 [pbn_b0_4_1152000] = {
1670 .flags = FL_BASE0,
1671 .num_ports = 4,
1672 .base_baud = 1152000,
1673 .uart_offset = 8,
1674 },
1675
1676 [pbn_b0_2_1843200] = {
1677 .flags = FL_BASE0,
1678 .num_ports = 2,
1679 .base_baud = 1843200,
1680 .uart_offset = 8,
1681 },
1682 [pbn_b0_4_1843200] = {
1683 .flags = FL_BASE0,
1684 .num_ports = 4,
1685 .base_baud = 1843200,
1686 .uart_offset = 8,
1687 },
1688
1689 [pbn_b0_2_1843200_200] = {
1690 .flags = FL_BASE0,
1691 .num_ports = 2,
1692 .base_baud = 1843200,
1693 .uart_offset = 0x200,
1694 },
1695 [pbn_b0_4_1843200_200] = {
1696 .flags = FL_BASE0,
1697 .num_ports = 4,
1698 .base_baud = 1843200,
1699 .uart_offset = 0x200,
1700 },
1701 [pbn_b0_8_1843200_200] = {
1702 .flags = FL_BASE0,
1703 .num_ports = 8,
1704 .base_baud = 1843200,
1705 .uart_offset = 0x200,
1706 },
1707 [pbn_b0_1_4000000] = {
1708 .flags = FL_BASE0,
1709 .num_ports = 1,
1710 .base_baud = 4000000,
1711 .uart_offset = 8,
1712 },
1713
1714 [pbn_b0_bt_1_115200] = {
1715 .flags = FL_BASE0|FL_BASE_BARS,
1716 .num_ports = 1,
1717 .base_baud = 115200,
1718 .uart_offset = 8,
1719 },
1720 [pbn_b0_bt_2_115200] = {
1721 .flags = FL_BASE0|FL_BASE_BARS,
1722 .num_ports = 2,
1723 .base_baud = 115200,
1724 .uart_offset = 8,
1725 },
1726 [pbn_b0_bt_4_115200] = {
1727 .flags = FL_BASE0|FL_BASE_BARS,
1728 .num_ports = 4,
1729 .base_baud = 115200,
1730 .uart_offset = 8,
1731 },
1732 [pbn_b0_bt_8_115200] = {
1733 .flags = FL_BASE0|FL_BASE_BARS,
1734 .num_ports = 8,
1735 .base_baud = 115200,
1736 .uart_offset = 8,
1737 },
1738
1739 [pbn_b0_bt_1_460800] = {
1740 .flags = FL_BASE0|FL_BASE_BARS,
1741 .num_ports = 1,
1742 .base_baud = 460800,
1743 .uart_offset = 8,
1744 },
1745 [pbn_b0_bt_2_460800] = {
1746 .flags = FL_BASE0|FL_BASE_BARS,
1747 .num_ports = 2,
1748 .base_baud = 460800,
1749 .uart_offset = 8,
1750 },
1751 [pbn_b0_bt_4_460800] = {
1752 .flags = FL_BASE0|FL_BASE_BARS,
1753 .num_ports = 4,
1754 .base_baud = 460800,
1755 .uart_offset = 8,
1756 },
1757
1758 [pbn_b0_bt_1_921600] = {
1759 .flags = FL_BASE0|FL_BASE_BARS,
1760 .num_ports = 1,
1761 .base_baud = 921600,
1762 .uart_offset = 8,
1763 },
1764 [pbn_b0_bt_2_921600] = {
1765 .flags = FL_BASE0|FL_BASE_BARS,
1766 .num_ports = 2,
1767 .base_baud = 921600,
1768 .uart_offset = 8,
1769 },
1770 [pbn_b0_bt_4_921600] = {
1771 .flags = FL_BASE0|FL_BASE_BARS,
1772 .num_ports = 4,
1773 .base_baud = 921600,
1774 .uart_offset = 8,
1775 },
1776 [pbn_b0_bt_8_921600] = {
1777 .flags = FL_BASE0|FL_BASE_BARS,
1778 .num_ports = 8,
1779 .base_baud = 921600,
1780 .uart_offset = 8,
1781 },
1782
1783 [pbn_b1_1_115200] = {
1784 .flags = FL_BASE1,
1785 .num_ports = 1,
1786 .base_baud = 115200,
1787 .uart_offset = 8,
1788 },
1789 [pbn_b1_2_115200] = {
1790 .flags = FL_BASE1,
1791 .num_ports = 2,
1792 .base_baud = 115200,
1793 .uart_offset = 8,
1794 },
1795 [pbn_b1_4_115200] = {
1796 .flags = FL_BASE1,
1797 .num_ports = 4,
1798 .base_baud = 115200,
1799 .uart_offset = 8,
1800 },
1801 [pbn_b1_8_115200] = {
1802 .flags = FL_BASE1,
1803 .num_ports = 8,
1804 .base_baud = 115200,
1805 .uart_offset = 8,
1806 },
1807 [pbn_b1_16_115200] = {
1808 .flags = FL_BASE1,
1809 .num_ports = 16,
1810 .base_baud = 115200,
1811 .uart_offset = 8,
1812 },
1813
1814 [pbn_b1_1_921600] = {
1815 .flags = FL_BASE1,
1816 .num_ports = 1,
1817 .base_baud = 921600,
1818 .uart_offset = 8,
1819 },
1820 [pbn_b1_2_921600] = {
1821 .flags = FL_BASE1,
1822 .num_ports = 2,
1823 .base_baud = 921600,
1824 .uart_offset = 8,
1825 },
1826 [pbn_b1_4_921600] = {
1827 .flags = FL_BASE1,
1828 .num_ports = 4,
1829 .base_baud = 921600,
1830 .uart_offset = 8,
1831 },
1832 [pbn_b1_8_921600] = {
1833 .flags = FL_BASE1,
1834 .num_ports = 8,
1835 .base_baud = 921600,
1836 .uart_offset = 8,
1837 },
1838 [pbn_b1_2_1250000] = {
1839 .flags = FL_BASE1,
1840 .num_ports = 2,
1841 .base_baud = 1250000,
1842 .uart_offset = 8,
1843 },
1844
1845 [pbn_b1_bt_1_115200] = {
1846 .flags = FL_BASE1|FL_BASE_BARS,
1847 .num_ports = 1,
1848 .base_baud = 115200,
1849 .uart_offset = 8,
1850 },
1851 [pbn_b1_bt_2_115200] = {
1852 .flags = FL_BASE1|FL_BASE_BARS,
1853 .num_ports = 2,
1854 .base_baud = 115200,
1855 .uart_offset = 8,
1856 },
1857 [pbn_b1_bt_4_115200] = {
1858 .flags = FL_BASE1|FL_BASE_BARS,
1859 .num_ports = 4,
1860 .base_baud = 115200,
1861 .uart_offset = 8,
1862 },
1863
1864 [pbn_b1_bt_2_921600] = {
1865 .flags = FL_BASE1|FL_BASE_BARS,
1866 .num_ports = 2,
1867 .base_baud = 921600,
1868 .uart_offset = 8,
1869 },
1870
1871 [pbn_b1_1_1382400] = {
1872 .flags = FL_BASE1,
1873 .num_ports = 1,
1874 .base_baud = 1382400,
1875 .uart_offset = 8,
1876 },
1877 [pbn_b1_2_1382400] = {
1878 .flags = FL_BASE1,
1879 .num_ports = 2,
1880 .base_baud = 1382400,
1881 .uart_offset = 8,
1882 },
1883 [pbn_b1_4_1382400] = {
1884 .flags = FL_BASE1,
1885 .num_ports = 4,
1886 .base_baud = 1382400,
1887 .uart_offset = 8,
1888 },
1889 [pbn_b1_8_1382400] = {
1890 .flags = FL_BASE1,
1891 .num_ports = 8,
1892 .base_baud = 1382400,
1893 .uart_offset = 8,
1894 },
1895
1896 [pbn_b2_1_115200] = {
1897 .flags = FL_BASE2,
1898 .num_ports = 1,
1899 .base_baud = 115200,
1900 .uart_offset = 8,
1901 },
1902 [pbn_b2_2_115200] = {
1903 .flags = FL_BASE2,
1904 .num_ports = 2,
1905 .base_baud = 115200,
1906 .uart_offset = 8,
1907 },
1908 [pbn_b2_4_115200] = {
1909 .flags = FL_BASE2,
1910 .num_ports = 4,
1911 .base_baud = 115200,
1912 .uart_offset = 8,
1913 },
1914 [pbn_b2_8_115200] = {
1915 .flags = FL_BASE2,
1916 .num_ports = 8,
1917 .base_baud = 115200,
1918 .uart_offset = 8,
1919 },
1920
1921 [pbn_b2_1_460800] = {
1922 .flags = FL_BASE2,
1923 .num_ports = 1,
1924 .base_baud = 460800,
1925 .uart_offset = 8,
1926 },
1927 [pbn_b2_4_460800] = {
1928 .flags = FL_BASE2,
1929 .num_ports = 4,
1930 .base_baud = 460800,
1931 .uart_offset = 8,
1932 },
1933 [pbn_b2_8_460800] = {
1934 .flags = FL_BASE2,
1935 .num_ports = 8,
1936 .base_baud = 460800,
1937 .uart_offset = 8,
1938 },
1939 [pbn_b2_16_460800] = {
1940 .flags = FL_BASE2,
1941 .num_ports = 16,
1942 .base_baud = 460800,
1943 .uart_offset = 8,
1944 },
1945
1946 [pbn_b2_1_921600] = {
1947 .flags = FL_BASE2,
1948 .num_ports = 1,
1949 .base_baud = 921600,
1950 .uart_offset = 8,
1951 },
1952 [pbn_b2_4_921600] = {
1953 .flags = FL_BASE2,
1954 .num_ports = 4,
1955 .base_baud = 921600,
1956 .uart_offset = 8,
1957 },
1958 [pbn_b2_8_921600] = {
1959 .flags = FL_BASE2,
1960 .num_ports = 8,
1961 .base_baud = 921600,
1962 .uart_offset = 8,
1963 },
1964
1965 [pbn_b2_8_1152000] = {
1966 .flags = FL_BASE2,
1967 .num_ports = 8,
1968 .base_baud = 1152000,
1969 .uart_offset = 8,
1970 },
1971
1972 [pbn_b2_bt_1_115200] = {
1973 .flags = FL_BASE2|FL_BASE_BARS,
1974 .num_ports = 1,
1975 .base_baud = 115200,
1976 .uart_offset = 8,
1977 },
1978 [pbn_b2_bt_2_115200] = {
1979 .flags = FL_BASE2|FL_BASE_BARS,
1980 .num_ports = 2,
1981 .base_baud = 115200,
1982 .uart_offset = 8,
1983 },
1984 [pbn_b2_bt_4_115200] = {
1985 .flags = FL_BASE2|FL_BASE_BARS,
1986 .num_ports = 4,
1987 .base_baud = 115200,
1988 .uart_offset = 8,
1989 },
1990
1991 [pbn_b2_bt_2_921600] = {
1992 .flags = FL_BASE2|FL_BASE_BARS,
1993 .num_ports = 2,
1994 .base_baud = 921600,
1995 .uart_offset = 8,
1996 },
1997 [pbn_b2_bt_4_921600] = {
1998 .flags = FL_BASE2|FL_BASE_BARS,
1999 .num_ports = 4,
2000 .base_baud = 921600,
2001 .uart_offset = 8,
2002 },
2003
2004 [pbn_b3_2_115200] = {
2005 .flags = FL_BASE3,
2006 .num_ports = 2,
2007 .base_baud = 115200,
2008 .uart_offset = 8,
2009 },
2010 [pbn_b3_4_115200] = {
2011 .flags = FL_BASE3,
2012 .num_ports = 4,
2013 .base_baud = 115200,
2014 .uart_offset = 8,
2015 },
2016 [pbn_b3_8_115200] = {
2017 .flags = FL_BASE3,
2018 .num_ports = 8,
2019 .base_baud = 115200,
2020 .uart_offset = 8,
2021 },
2022
2023 [pbn_b4_bt_2_921600] = {
2024 .flags = FL_BASE4,
2025 .num_ports = 2,
2026 .base_baud = 921600,
2027 .uart_offset = 8,
2028 },
2029 [pbn_b4_bt_4_921600] = {
2030 .flags = FL_BASE4,
2031 .num_ports = 4,
2032 .base_baud = 921600,
2033 .uart_offset = 8,
2034 },
2035 [pbn_b4_bt_8_921600] = {
2036 .flags = FL_BASE4,
2037 .num_ports = 8,
2038 .base_baud = 921600,
2039 .uart_offset = 8,
2040 },
2041
2042 /*
2043 * Entries following this are board-specific.
2044 */
2045
2046 /*
2047 * Panacom - IOMEM
2048 */
2049 [pbn_panacom] = {
2050 .flags = FL_BASE2,
2051 .num_ports = 2,
2052 .base_baud = 921600,
2053 .uart_offset = 0x400,
2054 .reg_shift = 7,
2055 },
2056 [pbn_panacom2] = {
2057 .flags = FL_BASE2|FL_BASE_BARS,
2058 .num_ports = 2,
2059 .base_baud = 921600,
2060 .uart_offset = 0x400,
2061 .reg_shift = 7,
2062 },
2063 [pbn_panacom4] = {
2064 .flags = FL_BASE2|FL_BASE_BARS,
2065 .num_ports = 4,
2066 .base_baud = 921600,
2067 .uart_offset = 0x400,
2068 .reg_shift = 7,
2069 },
2070
2071 [pbn_exsys_4055] = {
2072 .flags = FL_BASE2,
2073 .num_ports = 4,
2074 .base_baud = 115200,
2075 .uart_offset = 8,
2076 },
2077
2078 /* I think this entry is broken - the first_offset looks wrong --rmk */
2079 [pbn_plx_romulus] = {
2080 .flags = FL_BASE2,
2081 .num_ports = 4,
2082 .base_baud = 921600,
2083 .uart_offset = 8 << 2,
2084 .reg_shift = 2,
2085 .first_offset = 0x03,
2086 },
2087
2088 /*
2089 * This board uses the size of PCI Base region 0 to
2090 * signal now many ports are available
2091 */
2092 [pbn_oxsemi] = {
2093 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2094 .num_ports = 32,
2095 .base_baud = 115200,
2096 .uart_offset = 8,
2097 },
2098 [pbn_oxsemi_1_4000000] = {
2099 .flags = FL_BASE0,
2100 .num_ports = 1,
2101 .base_baud = 4000000,
2102 .uart_offset = 0x200,
2103 .first_offset = 0x1000,
2104 },
2105 [pbn_oxsemi_2_4000000] = {
2106 .flags = FL_BASE0,
2107 .num_ports = 2,
2108 .base_baud = 4000000,
2109 .uart_offset = 0x200,
2110 .first_offset = 0x1000,
2111 },
2112 [pbn_oxsemi_4_4000000] = {
2113 .flags = FL_BASE0,
2114 .num_ports = 4,
2115 .base_baud = 4000000,
2116 .uart_offset = 0x200,
2117 .first_offset = 0x1000,
2118 },
2119 [pbn_oxsemi_8_4000000] = {
2120 .flags = FL_BASE0,
2121 .num_ports = 8,
2122 .base_baud = 4000000,
2123 .uart_offset = 0x200,
2124 .first_offset = 0x1000,
2125 },
2126
2127
2128 /*
2129 * EKF addition for i960 Boards form EKF with serial port.
2130 * Max 256 ports.
2131 */
2132 [pbn_intel_i960] = {
2133 .flags = FL_BASE0,
2134 .num_ports = 32,
2135 .base_baud = 921600,
2136 .uart_offset = 8 << 2,
2137 .reg_shift = 2,
2138 .first_offset = 0x10000,
2139 },
2140 [pbn_sgi_ioc3] = {
2141 .flags = FL_BASE0|FL_NOIRQ,
2142 .num_ports = 1,
2143 .base_baud = 458333,
2144 .uart_offset = 8,
2145 .reg_shift = 0,
2146 .first_offset = 0x20178,
2147 },
2148
2149 /*
2150 * Computone - uses IOMEM.
2151 */
2152 [pbn_computone_4] = {
2153 .flags = FL_BASE0,
2154 .num_ports = 4,
2155 .base_baud = 921600,
2156 .uart_offset = 0x40,
2157 .reg_shift = 2,
2158 .first_offset = 0x200,
2159 },
2160 [pbn_computone_6] = {
2161 .flags = FL_BASE0,
2162 .num_ports = 6,
2163 .base_baud = 921600,
2164 .uart_offset = 0x40,
2165 .reg_shift = 2,
2166 .first_offset = 0x200,
2167 },
2168 [pbn_computone_8] = {
2169 .flags = FL_BASE0,
2170 .num_ports = 8,
2171 .base_baud = 921600,
2172 .uart_offset = 0x40,
2173 .reg_shift = 2,
2174 .first_offset = 0x200,
2175 },
2176 [pbn_sbsxrsio] = {
2177 .flags = FL_BASE0,
2178 .num_ports = 8,
2179 .base_baud = 460800,
2180 .uart_offset = 256,
2181 .reg_shift = 4,
2182 },
2183 /*
2184 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2185 * Only basic 16550A support.
2186 * XR17C15[24] are not tested, but they should work.
2187 */
2188 [pbn_exar_XR17C152] = {
2189 .flags = FL_BASE0,
2190 .num_ports = 2,
2191 .base_baud = 921600,
2192 .uart_offset = 0x200,
2193 },
2194 [pbn_exar_XR17C154] = {
2195 .flags = FL_BASE0,
2196 .num_ports = 4,
2197 .base_baud = 921600,
2198 .uart_offset = 0x200,
2199 },
2200 [pbn_exar_XR17C158] = {
2201 .flags = FL_BASE0,
2202 .num_ports = 8,
2203 .base_baud = 921600,
2204 .uart_offset = 0x200,
2205 },
2206 [pbn_exar_ibm_saturn] = {
2207 .flags = FL_BASE0,
2208 .num_ports = 1,
2209 .base_baud = 921600,
2210 .uart_offset = 0x200,
2211 },
2212
2213 /*
2214 * PA Semi PWRficient PA6T-1682M on-chip UART
2215 */
2216 [pbn_pasemi_1682M] = {
2217 .flags = FL_BASE0,
2218 .num_ports = 1,
2219 .base_baud = 8333333,
2220 },
2221 /*
2222 * National Instruments 843x
2223 */
2224 [pbn_ni8430_16] = {
2225 .flags = FL_BASE0,
2226 .num_ports = 16,
2227 .base_baud = 3686400,
2228 .uart_offset = 0x10,
2229 .first_offset = 0x800,
2230 },
2231 [pbn_ni8430_8] = {
2232 .flags = FL_BASE0,
2233 .num_ports = 8,
2234 .base_baud = 3686400,
2235 .uart_offset = 0x10,
2236 .first_offset = 0x800,
2237 },
2238 [pbn_ni8430_4] = {
2239 .flags = FL_BASE0,
2240 .num_ports = 4,
2241 .base_baud = 3686400,
2242 .uart_offset = 0x10,
2243 .first_offset = 0x800,
2244 },
2245 [pbn_ni8430_2] = {
2246 .flags = FL_BASE0,
2247 .num_ports = 2,
2248 .base_baud = 3686400,
2249 .uart_offset = 0x10,
2250 .first_offset = 0x800,
2251 },
2252 /*
2253 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2254 */
2255 [pbn_ADDIDATA_PCIe_1_3906250] = {
2256 .flags = FL_BASE0,
2257 .num_ports = 1,
2258 .base_baud = 3906250,
2259 .uart_offset = 0x200,
2260 .first_offset = 0x1000,
2261 },
2262 [pbn_ADDIDATA_PCIe_2_3906250] = {
2263 .flags = FL_BASE0,
2264 .num_ports = 2,
2265 .base_baud = 3906250,
2266 .uart_offset = 0x200,
2267 .first_offset = 0x1000,
2268 },
2269 [pbn_ADDIDATA_PCIe_4_3906250] = {
2270 .flags = FL_BASE0,
2271 .num_ports = 4,
2272 .base_baud = 3906250,
2273 .uart_offset = 0x200,
2274 .first_offset = 0x1000,
2275 },
2276 [pbn_ADDIDATA_PCIe_8_3906250] = {
2277 .flags = FL_BASE0,
2278 .num_ports = 8,
2279 .base_baud = 3906250,
2280 .uart_offset = 0x200,
2281 .first_offset = 0x1000,
2282 },
2283 };
2284
2285 static const struct pci_device_id softmodem_blacklist[] = {
2286 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2287 };
2288
2289 /*
2290 * Given a complete unknown PCI device, try to use some heuristics to
2291 * guess what the configuration might be, based on the pitiful PCI
2292 * serial specs. Returns 0 on success, 1 on failure.
2293 */
2294 static int __devinit
2295 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2296 {
2297 const struct pci_device_id *blacklist;
2298 int num_iomem, num_port, first_port = -1, i;
2299
2300 /*
2301 * If it is not a communications device or the programming
2302 * interface is greater than 6, give up.
2303 *
2304 * (Should we try to make guesses for multiport serial devices
2305 * later?)
2306 */
2307 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2308 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2309 (dev->class & 0xff) > 6)
2310 return -ENODEV;
2311
2312 /*
2313 * Do not access blacklisted devices that are known not to
2314 * feature serial ports.
2315 */
2316 for (blacklist = softmodem_blacklist;
2317 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2318 blacklist++) {
2319 if (dev->vendor == blacklist->vendor &&
2320 dev->device == blacklist->device)
2321 return -ENODEV;
2322 }
2323
2324 num_iomem = num_port = 0;
2325 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2326 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2327 num_port++;
2328 if (first_port == -1)
2329 first_port = i;
2330 }
2331 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2332 num_iomem++;
2333 }
2334
2335 /*
2336 * If there is 1 or 0 iomem regions, and exactly one port,
2337 * use it. We guess the number of ports based on the IO
2338 * region size.
2339 */
2340 if (num_iomem <= 1 && num_port == 1) {
2341 board->flags = first_port;
2342 board->num_ports = pci_resource_len(dev, first_port) / 8;
2343 return 0;
2344 }
2345
2346 /*
2347 * Now guess if we've got a board which indexes by BARs.
2348 * Each IO BAR should be 8 bytes, and they should follow
2349 * consecutively.
2350 */
2351 first_port = -1;
2352 num_port = 0;
2353 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2354 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2355 pci_resource_len(dev, i) == 8 &&
2356 (first_port == -1 || (first_port + num_port) == i)) {
2357 num_port++;
2358 if (first_port == -1)
2359 first_port = i;
2360 }
2361 }
2362
2363 if (num_port > 1) {
2364 board->flags = first_port | FL_BASE_BARS;
2365 board->num_ports = num_port;
2366 return 0;
2367 }
2368
2369 return -ENODEV;
2370 }
2371
2372 static inline int
2373 serial_pci_matches(const struct pciserial_board *board,
2374 const struct pciserial_board *guessed)
2375 {
2376 return
2377 board->num_ports == guessed->num_ports &&
2378 board->base_baud == guessed->base_baud &&
2379 board->uart_offset == guessed->uart_offset &&
2380 board->reg_shift == guessed->reg_shift &&
2381 board->first_offset == guessed->first_offset;
2382 }
2383
2384 struct serial_private *
2385 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2386 {
2387 struct uart_port serial_port;
2388 struct serial_private *priv;
2389 struct pci_serial_quirk *quirk;
2390 int rc, nr_ports, i;
2391
2392 nr_ports = board->num_ports;
2393
2394 /*
2395 * Find an init and setup quirks.
2396 */
2397 quirk = find_quirk(dev);
2398
2399 /*
2400 * Run the new-style initialization function.
2401 * The initialization function returns:
2402 * <0 - error
2403 * 0 - use board->num_ports
2404 * >0 - number of ports
2405 */
2406 if (quirk->init) {
2407 rc = quirk->init(dev);
2408 if (rc < 0) {
2409 priv = ERR_PTR(rc);
2410 goto err_out;
2411 }
2412 if (rc)
2413 nr_ports = rc;
2414 }
2415
2416 priv = kzalloc(sizeof(struct serial_private) +
2417 sizeof(unsigned int) * nr_ports,
2418 GFP_KERNEL);
2419 if (!priv) {
2420 priv = ERR_PTR(-ENOMEM);
2421 goto err_deinit;
2422 }
2423
2424 priv->dev = dev;
2425 priv->quirk = quirk;
2426
2427 memset(&serial_port, 0, sizeof(struct uart_port));
2428 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2429 serial_port.uartclk = board->base_baud * 16;
2430 serial_port.irq = get_pci_irq(dev, board);
2431 serial_port.dev = &dev->dev;
2432
2433 for (i = 0; i < nr_ports; i++) {
2434 if (quirk->setup(priv, board, &serial_port, i))
2435 break;
2436
2437 #ifdef SERIAL_DEBUG_PCI
2438 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2439 serial_port.iobase, serial_port.irq, serial_port.iotype);
2440 #endif
2441
2442 priv->line[i] = serial8250_register_port(&serial_port);
2443 if (priv->line[i] < 0) {
2444 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2445 break;
2446 }
2447 }
2448 priv->nr = i;
2449 return priv;
2450
2451 err_deinit:
2452 if (quirk->exit)
2453 quirk->exit(dev);
2454 err_out:
2455 return priv;
2456 }
2457 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2458
2459 void pciserial_remove_ports(struct serial_private *priv)
2460 {
2461 struct pci_serial_quirk *quirk;
2462 int i;
2463
2464 for (i = 0; i < priv->nr; i++)
2465 serial8250_unregister_port(priv->line[i]);
2466
2467 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2468 if (priv->remapped_bar[i])
2469 iounmap(priv->remapped_bar[i]);
2470 priv->remapped_bar[i] = NULL;
2471 }
2472
2473 /*
2474 * Find the exit quirks.
2475 */
2476 quirk = find_quirk(priv->dev);
2477 if (quirk->exit)
2478 quirk->exit(priv->dev);
2479
2480 kfree(priv);
2481 }
2482 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2483
2484 void pciserial_suspend_ports(struct serial_private *priv)
2485 {
2486 int i;
2487
2488 for (i = 0; i < priv->nr; i++)
2489 if (priv->line[i] >= 0)
2490 serial8250_suspend_port(priv->line[i]);
2491 }
2492 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2493
2494 void pciserial_resume_ports(struct serial_private *priv)
2495 {
2496 int i;
2497
2498 /*
2499 * Ensure that the board is correctly configured.
2500 */
2501 if (priv->quirk->init)
2502 priv->quirk->init(priv->dev);
2503
2504 for (i = 0; i < priv->nr; i++)
2505 if (priv->line[i] >= 0)
2506 serial8250_resume_port(priv->line[i]);
2507 }
2508 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2509
2510 /*
2511 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2512 * to the arrangement of serial ports on a PCI card.
2513 */
2514 static int __devinit
2515 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2516 {
2517 struct serial_private *priv;
2518 const struct pciserial_board *board;
2519 struct pciserial_board tmp;
2520 int rc;
2521
2522 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2523 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2524 ent->driver_data);
2525 return -EINVAL;
2526 }
2527
2528 board = &pci_boards[ent->driver_data];
2529
2530 rc = pci_enable_device(dev);
2531 if (rc)
2532 return rc;
2533
2534 if (ent->driver_data == pbn_default) {
2535 /*
2536 * Use a copy of the pci_board entry for this;
2537 * avoid changing entries in the table.
2538 */
2539 memcpy(&tmp, board, sizeof(struct pciserial_board));
2540 board = &tmp;
2541
2542 /*
2543 * We matched one of our class entries. Try to
2544 * determine the parameters of this board.
2545 */
2546 rc = serial_pci_guess_board(dev, &tmp);
2547 if (rc)
2548 goto disable;
2549 } else {
2550 /*
2551 * We matched an explicit entry. If we are able to
2552 * detect this boards settings with our heuristic,
2553 * then we no longer need this entry.
2554 */
2555 memcpy(&tmp, &pci_boards[pbn_default],
2556 sizeof(struct pciserial_board));
2557 rc = serial_pci_guess_board(dev, &tmp);
2558 if (rc == 0 && serial_pci_matches(board, &tmp))
2559 moan_device("Redundant entry in serial pci_table.",
2560 dev);
2561 }
2562
2563 priv = pciserial_init_ports(dev, board);
2564 if (!IS_ERR(priv)) {
2565 pci_set_drvdata(dev, priv);
2566 return 0;
2567 }
2568
2569 rc = PTR_ERR(priv);
2570
2571 disable:
2572 pci_disable_device(dev);
2573 return rc;
2574 }
2575
2576 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2577 {
2578 struct serial_private *priv = pci_get_drvdata(dev);
2579
2580 pci_set_drvdata(dev, NULL);
2581
2582 pciserial_remove_ports(priv);
2583
2584 pci_disable_device(dev);
2585 }
2586
2587 #ifdef CONFIG_PM
2588 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2589 {
2590 struct serial_private *priv = pci_get_drvdata(dev);
2591
2592 if (priv)
2593 pciserial_suspend_ports(priv);
2594
2595 pci_save_state(dev);
2596 pci_set_power_state(dev, pci_choose_state(dev, state));
2597 return 0;
2598 }
2599
2600 static int pciserial_resume_one(struct pci_dev *dev)
2601 {
2602 int err;
2603 struct serial_private *priv = pci_get_drvdata(dev);
2604
2605 pci_set_power_state(dev, PCI_D0);
2606 pci_restore_state(dev);
2607
2608 if (priv) {
2609 /*
2610 * The device may have been disabled. Re-enable it.
2611 */
2612 err = pci_enable_device(dev);
2613 if (err)
2614 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2615 pciserial_resume_ports(priv);
2616 }
2617 return 0;
2618 }
2619 #endif
2620
2621 static struct pci_device_id serial_pci_tbl[] = {
2622 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2623 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2624 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2625 pbn_b2_8_921600 },
2626 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2627 PCI_SUBVENDOR_ID_CONNECT_TECH,
2628 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2629 pbn_b1_8_1382400 },
2630 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2631 PCI_SUBVENDOR_ID_CONNECT_TECH,
2632 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2633 pbn_b1_4_1382400 },
2634 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2635 PCI_SUBVENDOR_ID_CONNECT_TECH,
2636 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2637 pbn_b1_2_1382400 },
2638 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2639 PCI_SUBVENDOR_ID_CONNECT_TECH,
2640 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2641 pbn_b1_8_1382400 },
2642 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2643 PCI_SUBVENDOR_ID_CONNECT_TECH,
2644 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2645 pbn_b1_4_1382400 },
2646 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2647 PCI_SUBVENDOR_ID_CONNECT_TECH,
2648 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2649 pbn_b1_2_1382400 },
2650 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2651 PCI_SUBVENDOR_ID_CONNECT_TECH,
2652 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2653 pbn_b1_8_921600 },
2654 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2655 PCI_SUBVENDOR_ID_CONNECT_TECH,
2656 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2657 pbn_b1_8_921600 },
2658 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2659 PCI_SUBVENDOR_ID_CONNECT_TECH,
2660 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2661 pbn_b1_4_921600 },
2662 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2663 PCI_SUBVENDOR_ID_CONNECT_TECH,
2664 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2665 pbn_b1_4_921600 },
2666 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2667 PCI_SUBVENDOR_ID_CONNECT_TECH,
2668 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2669 pbn_b1_2_921600 },
2670 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2671 PCI_SUBVENDOR_ID_CONNECT_TECH,
2672 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2673 pbn_b1_8_921600 },
2674 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2675 PCI_SUBVENDOR_ID_CONNECT_TECH,
2676 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2677 pbn_b1_8_921600 },
2678 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2679 PCI_SUBVENDOR_ID_CONNECT_TECH,
2680 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2681 pbn_b1_4_921600 },
2682 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2683 PCI_SUBVENDOR_ID_CONNECT_TECH,
2684 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2685 pbn_b1_2_1250000 },
2686 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2687 PCI_SUBVENDOR_ID_CONNECT_TECH,
2688 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2689 pbn_b0_2_1843200 },
2690 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2691 PCI_SUBVENDOR_ID_CONNECT_TECH,
2692 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2693 pbn_b0_4_1843200 },
2694 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2695 PCI_VENDOR_ID_AFAVLAB,
2696 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2697 pbn_b0_4_1152000 },
2698 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2699 PCI_SUBVENDOR_ID_CONNECT_TECH,
2700 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2701 pbn_b0_2_1843200_200 },
2702 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2703 PCI_SUBVENDOR_ID_CONNECT_TECH,
2704 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2705 pbn_b0_4_1843200_200 },
2706 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2707 PCI_SUBVENDOR_ID_CONNECT_TECH,
2708 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2709 pbn_b0_8_1843200_200 },
2710 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2711 PCI_SUBVENDOR_ID_CONNECT_TECH,
2712 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2713 pbn_b0_2_1843200_200 },
2714 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2715 PCI_SUBVENDOR_ID_CONNECT_TECH,
2716 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2717 pbn_b0_4_1843200_200 },
2718 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2719 PCI_SUBVENDOR_ID_CONNECT_TECH,
2720 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2721 pbn_b0_8_1843200_200 },
2722 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2723 PCI_SUBVENDOR_ID_CONNECT_TECH,
2724 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2725 pbn_b0_2_1843200_200 },
2726 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2727 PCI_SUBVENDOR_ID_CONNECT_TECH,
2728 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2729 pbn_b0_4_1843200_200 },
2730 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2731 PCI_SUBVENDOR_ID_CONNECT_TECH,
2732 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2733 pbn_b0_8_1843200_200 },
2734 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2735 PCI_SUBVENDOR_ID_CONNECT_TECH,
2736 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2737 pbn_b0_2_1843200_200 },
2738 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2739 PCI_SUBVENDOR_ID_CONNECT_TECH,
2740 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2741 pbn_b0_4_1843200_200 },
2742 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2743 PCI_SUBVENDOR_ID_CONNECT_TECH,
2744 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2745 pbn_b0_8_1843200_200 },
2746 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2747 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2748 0, 0, pbn_exar_ibm_saturn },
2749
2750 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2752 pbn_b2_bt_1_115200 },
2753 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2755 pbn_b2_bt_2_115200 },
2756 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2758 pbn_b2_bt_4_115200 },
2759 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2761 pbn_b2_bt_2_115200 },
2762 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2764 pbn_b2_bt_4_115200 },
2765 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2767 pbn_b2_8_115200 },
2768 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2770 pbn_b2_8_460800 },
2771 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2773 pbn_b2_8_115200 },
2774
2775 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2777 pbn_b2_bt_2_115200 },
2778 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2780 pbn_b2_bt_2_921600 },
2781 /*
2782 * VScom SPCOM800, from sl@s.pl
2783 */
2784 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2786 pbn_b2_8_921600 },
2787 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2789 pbn_b2_4_921600 },
2790 /* Unknown card - subdevice 0x1584 */
2791 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2792 PCI_VENDOR_ID_PLX,
2793 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2794 pbn_b0_4_115200 },
2795 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2796 PCI_SUBVENDOR_ID_KEYSPAN,
2797 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2798 pbn_panacom },
2799 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2801 pbn_panacom4 },
2802 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2804 pbn_panacom2 },
2805 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2806 PCI_VENDOR_ID_ESDGMBH,
2807 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2808 pbn_b2_4_115200 },
2809 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2810 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2811 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2812 pbn_b2_4_460800 },
2813 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2814 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2815 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2816 pbn_b2_8_460800 },
2817 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2818 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2819 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2820 pbn_b2_16_460800 },
2821 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2822 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2823 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2824 pbn_b2_16_460800 },
2825 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2826 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2827 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2828 pbn_b2_4_460800 },
2829 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2830 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2831 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2832 pbn_b2_8_460800 },
2833 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2834 PCI_SUBVENDOR_ID_EXSYS,
2835 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2836 pbn_exsys_4055 },
2837 /*
2838 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2839 * (Exoray@isys.ca)
2840 */
2841 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2842 0x10b5, 0x106a, 0, 0,
2843 pbn_plx_romulus },
2844 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2846 pbn_b1_4_115200 },
2847 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2849 pbn_b1_2_115200 },
2850 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2852 pbn_b1_8_115200 },
2853 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2855 pbn_b1_8_115200 },
2856 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2857 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2858 0, 0,
2859 pbn_b0_4_921600 },
2860 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2861 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2862 0, 0,
2863 pbn_b0_4_1152000 },
2864
2865 /*
2866 * The below card is a little controversial since it is the
2867 * subject of a PCI vendor/device ID clash. (See
2868 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2869 * For now just used the hex ID 0x950a.
2870 */
2871 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2872 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2873 pbn_b0_2_115200 },
2874 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2876 pbn_b0_2_1130000 },
2877 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2878 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2879 pbn_b0_1_921600 },
2880 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882 pbn_b0_4_115200 },
2883 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885 pbn_b0_bt_2_921600 },
2886 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2887 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2888 pbn_b2_8_1152000 },
2889
2890 /*
2891 * Oxford Semiconductor Inc. Tornado PCI express device range.
2892 */
2893 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2895 pbn_b0_1_4000000 },
2896 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2898 pbn_b0_1_4000000 },
2899 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2901 pbn_oxsemi_1_4000000 },
2902 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_oxsemi_1_4000000 },
2905 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_b0_1_4000000 },
2908 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2910 pbn_b0_1_4000000 },
2911 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_oxsemi_1_4000000 },
2914 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_oxsemi_1_4000000 },
2917 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2919 pbn_b0_1_4000000 },
2920 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2922 pbn_b0_1_4000000 },
2923 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2925 pbn_b0_1_4000000 },
2926 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928 pbn_b0_1_4000000 },
2929 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_oxsemi_2_4000000 },
2932 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2934 pbn_oxsemi_2_4000000 },
2935 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2937 pbn_oxsemi_4_4000000 },
2938 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2940 pbn_oxsemi_4_4000000 },
2941 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2943 pbn_oxsemi_8_4000000 },
2944 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2946 pbn_oxsemi_8_4000000 },
2947 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2949 pbn_oxsemi_1_4000000 },
2950 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2952 pbn_oxsemi_1_4000000 },
2953 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2955 pbn_oxsemi_1_4000000 },
2956 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2958 pbn_oxsemi_1_4000000 },
2959 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2961 pbn_oxsemi_1_4000000 },
2962 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2964 pbn_oxsemi_1_4000000 },
2965 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
2966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967 pbn_oxsemi_1_4000000 },
2968 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
2969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970 pbn_oxsemi_1_4000000 },
2971 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973 pbn_oxsemi_1_4000000 },
2974 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_oxsemi_1_4000000 },
2977 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979 pbn_oxsemi_1_4000000 },
2980 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
2981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982 pbn_oxsemi_1_4000000 },
2983 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
2984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2985 pbn_oxsemi_1_4000000 },
2986 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
2987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988 pbn_oxsemi_1_4000000 },
2989 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
2990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2991 pbn_oxsemi_1_4000000 },
2992 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2994 pbn_oxsemi_1_4000000 },
2995 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997 pbn_oxsemi_1_4000000 },
2998 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
2999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3000 pbn_oxsemi_1_4000000 },
3001 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3003 pbn_oxsemi_1_4000000 },
3004 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_oxsemi_1_4000000 },
3007 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3009 pbn_oxsemi_1_4000000 },
3010 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3012 pbn_oxsemi_1_4000000 },
3013 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015 pbn_oxsemi_1_4000000 },
3016 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3018 pbn_oxsemi_1_4000000 },
3019 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021 pbn_oxsemi_1_4000000 },
3022 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024 pbn_oxsemi_1_4000000 },
3025 /*
3026 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3027 */
3028 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3029 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3030 pbn_oxsemi_1_4000000 },
3031 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3032 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3033 pbn_oxsemi_2_4000000 },
3034 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3035 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3036 pbn_oxsemi_4_4000000 },
3037 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3038 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3039 pbn_oxsemi_8_4000000 },
3040 /*
3041 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3042 * from skokodyn@yahoo.com
3043 */
3044 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3045 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3046 pbn_sbsxrsio },
3047 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3048 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3049 pbn_sbsxrsio },
3050 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3051 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3052 pbn_sbsxrsio },
3053 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3054 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3055 pbn_sbsxrsio },
3056
3057 /*
3058 * Digitan DS560-558, from jimd@esoft.com
3059 */
3060 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062 pbn_b1_1_115200 },
3063
3064 /*
3065 * Titan Electronic cards
3066 * The 400L and 800L have a custom setup quirk.
3067 */
3068 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_b0_1_921600 },
3071 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3073 pbn_b0_2_921600 },
3074 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3076 pbn_b0_4_921600 },
3077 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079 pbn_b0_4_921600 },
3080 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082 pbn_b1_1_921600 },
3083 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085 pbn_b1_bt_2_921600 },
3086 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_b0_bt_4_921600 },
3089 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_b0_bt_8_921600 },
3092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094 pbn_b4_bt_2_921600 },
3095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_b4_bt_4_921600 },
3098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_b4_bt_8_921600 },
3101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3103 pbn_b0_4_921600 },
3104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106 pbn_b0_4_921600 },
3107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3109 pbn_b0_4_921600 },
3110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112 pbn_oxsemi_1_4000000 },
3113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_oxsemi_2_4000000 },
3116 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_oxsemi_4_4000000 },
3119 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_oxsemi_8_4000000 },
3122 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_oxsemi_2_4000000 },
3125 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127 pbn_oxsemi_2_4000000 },
3128
3129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131 pbn_b2_1_460800 },
3132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3134 pbn_b2_1_460800 },
3135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137 pbn_b2_1_460800 },
3138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140 pbn_b2_bt_2_921600 },
3141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3143 pbn_b2_bt_2_921600 },
3144 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3146 pbn_b2_bt_2_921600 },
3147 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3149 pbn_b2_bt_4_921600 },
3150 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3152 pbn_b2_bt_4_921600 },
3153 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3155 pbn_b2_bt_4_921600 },
3156 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3158 pbn_b0_1_921600 },
3159 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161 pbn_b0_1_921600 },
3162 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3164 pbn_b0_1_921600 },
3165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167 pbn_b0_bt_2_921600 },
3168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170 pbn_b0_bt_2_921600 },
3171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_b0_bt_2_921600 },
3174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176 pbn_b0_bt_4_921600 },
3177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179 pbn_b0_bt_4_921600 },
3180 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182 pbn_b0_bt_4_921600 },
3183 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185 pbn_b0_bt_8_921600 },
3186 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3188 pbn_b0_bt_8_921600 },
3189 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191 pbn_b0_bt_8_921600 },
3192
3193 /*
3194 * Computone devices submitted by Doug McNash dmcnash@computone.com
3195 */
3196 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3197 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3198 0, 0, pbn_computone_4 },
3199 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3200 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3201 0, 0, pbn_computone_8 },
3202 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3203 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3204 0, 0, pbn_computone_6 },
3205
3206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_oxsemi },
3209 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3210 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3211 pbn_b0_bt_1_921600 },
3212
3213 /*
3214 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3215 */
3216 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_b0_bt_8_115200 },
3219 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_b0_bt_8_115200 },
3222
3223 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225 pbn_b0_bt_2_115200 },
3226 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 pbn_b0_bt_2_115200 },
3229 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231 pbn_b0_bt_2_115200 },
3232 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234 pbn_b0_bt_2_115200 },
3235 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 pbn_b0_bt_2_115200 },
3238 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 pbn_b0_bt_4_460800 },
3241 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243 pbn_b0_bt_4_460800 },
3244 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246 pbn_b0_bt_2_460800 },
3247 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3249 pbn_b0_bt_2_460800 },
3250 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3252 pbn_b0_bt_2_460800 },
3253 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3255 pbn_b0_bt_1_115200 },
3256 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258 pbn_b0_bt_1_460800 },
3259
3260 /*
3261 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3262 * Cards are identified by their subsystem vendor IDs, which
3263 * (in hex) match the model number.
3264 *
3265 * Note that JC140x are RS422/485 cards which require ox950
3266 * ACR = 0x10, and as such are not currently fully supported.
3267 */
3268 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3269 0x1204, 0x0004, 0, 0,
3270 pbn_b0_4_921600 },
3271 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3272 0x1208, 0x0004, 0, 0,
3273 pbn_b0_4_921600 },
3274 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3275 0x1402, 0x0002, 0, 0,
3276 pbn_b0_2_921600 }, */
3277 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3278 0x1404, 0x0004, 0, 0,
3279 pbn_b0_4_921600 }, */
3280 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3281 0x1208, 0x0004, 0, 0,
3282 pbn_b0_4_921600 },
3283
3284 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3285 0x1204, 0x0004, 0, 0,
3286 pbn_b0_4_921600 },
3287 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3288 0x1208, 0x0004, 0, 0,
3289 pbn_b0_4_921600 },
3290 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3291 0x1208, 0x0004, 0, 0,
3292 pbn_b0_4_921600 },
3293 /*
3294 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3295 */
3296 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 pbn_b1_1_1382400 },
3299
3300 /*
3301 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3302 */
3303 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_b1_1_1382400 },
3306
3307 /*
3308 * RAStel 2 port modem, gerg@moreton.com.au
3309 */
3310 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312 pbn_b2_bt_2_115200 },
3313
3314 /*
3315 * EKF addition for i960 Boards form EKF with serial port
3316 */
3317 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3318 0xE4BF, PCI_ANY_ID, 0, 0,
3319 pbn_intel_i960 },
3320
3321 /*
3322 * Xircom Cardbus/Ethernet combos
3323 */
3324 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326 pbn_b0_1_115200 },
3327 /*
3328 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3329 */
3330 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3332 pbn_b0_1_115200 },
3333
3334 /*
3335 * Untested PCI modems, sent in from various folks...
3336 */
3337
3338 /*
3339 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3340 */
3341 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3342 0x1048, 0x1500, 0, 0,
3343 pbn_b1_1_115200 },
3344
3345 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3346 0xFF00, 0, 0, 0,
3347 pbn_sgi_ioc3 },
3348
3349 /*
3350 * HP Diva card
3351 */
3352 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3353 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3354 pbn_b1_1_115200 },
3355 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3357 pbn_b0_5_115200 },
3358 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3360 pbn_b2_1_115200 },
3361
3362 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364 pbn_b3_2_115200 },
3365 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367 pbn_b3_4_115200 },
3368 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_b3_8_115200 },
3371
3372 /*
3373 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3374 */
3375 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3376 PCI_ANY_ID, PCI_ANY_ID,
3377 0,
3378 0, pbn_exar_XR17C152 },
3379 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3380 PCI_ANY_ID, PCI_ANY_ID,
3381 0,
3382 0, pbn_exar_XR17C154 },
3383 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3384 PCI_ANY_ID, PCI_ANY_ID,
3385 0,
3386 0, pbn_exar_XR17C158 },
3387
3388 /*
3389 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3390 */
3391 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b0_1_115200 },
3394 /*
3395 * ITE
3396 */
3397 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3398 PCI_ANY_ID, PCI_ANY_ID,
3399 0, 0,
3400 pbn_b1_bt_1_115200 },
3401
3402 /*
3403 * IntaShield IS-200
3404 */
3405 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3407 pbn_b2_2_115200 },
3408 /*
3409 * IntaShield IS-400
3410 */
3411 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3413 pbn_b2_4_115200 },
3414 /*
3415 * Perle PCI-RAS cards
3416 */
3417 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3418 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3419 0, 0, pbn_b2_4_921600 },
3420 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3421 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3422 0, 0, pbn_b2_8_921600 },
3423
3424 /*
3425 * Mainpine series cards: Fairly standard layout but fools
3426 * parts of the autodetect in some cases and uses otherwise
3427 * unmatched communications subclasses in the PCI Express case
3428 */
3429
3430 { /* RockForceDUO */
3431 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3432 PCI_VENDOR_ID_MAINPINE, 0x0200,
3433 0, 0, pbn_b0_2_115200 },
3434 { /* RockForceQUATRO */
3435 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3436 PCI_VENDOR_ID_MAINPINE, 0x0300,
3437 0, 0, pbn_b0_4_115200 },
3438 { /* RockForceDUO+ */
3439 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3440 PCI_VENDOR_ID_MAINPINE, 0x0400,
3441 0, 0, pbn_b0_2_115200 },
3442 { /* RockForceQUATRO+ */
3443 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3444 PCI_VENDOR_ID_MAINPINE, 0x0500,
3445 0, 0, pbn_b0_4_115200 },
3446 { /* RockForce+ */
3447 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3448 PCI_VENDOR_ID_MAINPINE, 0x0600,
3449 0, 0, pbn_b0_2_115200 },
3450 { /* RockForce+ */
3451 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3452 PCI_VENDOR_ID_MAINPINE, 0x0700,
3453 0, 0, pbn_b0_4_115200 },
3454 { /* RockForceOCTO+ */
3455 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3456 PCI_VENDOR_ID_MAINPINE, 0x0800,
3457 0, 0, pbn_b0_8_115200 },
3458 { /* RockForceDUO+ */
3459 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3460 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3461 0, 0, pbn_b0_2_115200 },
3462 { /* RockForceQUARTRO+ */
3463 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3464 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3465 0, 0, pbn_b0_4_115200 },
3466 { /* RockForceOCTO+ */
3467 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3468 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3469 0, 0, pbn_b0_8_115200 },
3470 { /* RockForceD1 */
3471 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3472 PCI_VENDOR_ID_MAINPINE, 0x2000,
3473 0, 0, pbn_b0_1_115200 },
3474 { /* RockForceF1 */
3475 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3476 PCI_VENDOR_ID_MAINPINE, 0x2100,
3477 0, 0, pbn_b0_1_115200 },
3478 { /* RockForceD2 */
3479 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3480 PCI_VENDOR_ID_MAINPINE, 0x2200,
3481 0, 0, pbn_b0_2_115200 },
3482 { /* RockForceF2 */
3483 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3484 PCI_VENDOR_ID_MAINPINE, 0x2300,
3485 0, 0, pbn_b0_2_115200 },
3486 { /* RockForceD4 */
3487 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3488 PCI_VENDOR_ID_MAINPINE, 0x2400,
3489 0, 0, pbn_b0_4_115200 },
3490 { /* RockForceF4 */
3491 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3492 PCI_VENDOR_ID_MAINPINE, 0x2500,
3493 0, 0, pbn_b0_4_115200 },
3494 { /* RockForceD8 */
3495 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3496 PCI_VENDOR_ID_MAINPINE, 0x2600,
3497 0, 0, pbn_b0_8_115200 },
3498 { /* RockForceF8 */
3499 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3500 PCI_VENDOR_ID_MAINPINE, 0x2700,
3501 0, 0, pbn_b0_8_115200 },
3502 { /* IQ Express D1 */
3503 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3504 PCI_VENDOR_ID_MAINPINE, 0x3000,
3505 0, 0, pbn_b0_1_115200 },
3506 { /* IQ Express F1 */
3507 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3508 PCI_VENDOR_ID_MAINPINE, 0x3100,
3509 0, 0, pbn_b0_1_115200 },
3510 { /* IQ Express D2 */
3511 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3512 PCI_VENDOR_ID_MAINPINE, 0x3200,
3513 0, 0, pbn_b0_2_115200 },
3514 { /* IQ Express F2 */
3515 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3516 PCI_VENDOR_ID_MAINPINE, 0x3300,
3517 0, 0, pbn_b0_2_115200 },
3518 { /* IQ Express D4 */
3519 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3520 PCI_VENDOR_ID_MAINPINE, 0x3400,
3521 0, 0, pbn_b0_4_115200 },
3522 { /* IQ Express F4 */
3523 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3524 PCI_VENDOR_ID_MAINPINE, 0x3500,
3525 0, 0, pbn_b0_4_115200 },
3526 { /* IQ Express D8 */
3527 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3528 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3529 0, 0, pbn_b0_8_115200 },
3530 { /* IQ Express F8 */
3531 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3532 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3533 0, 0, pbn_b0_8_115200 },
3534
3535
3536 /*
3537 * PA Semi PA6T-1682M on-chip UART
3538 */
3539 { PCI_VENDOR_ID_PASEMI, 0xa004,
3540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3541 pbn_pasemi_1682M },
3542
3543 /*
3544 * National Instruments
3545 */
3546 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 pbn_b1_16_115200 },
3549 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551 pbn_b1_8_115200 },
3552 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 pbn_b1_bt_4_115200 },
3555 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 pbn_b1_bt_2_115200 },
3558 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 pbn_b1_bt_4_115200 },
3561 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563 pbn_b1_bt_2_115200 },
3564 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566 pbn_b1_16_115200 },
3567 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3569 pbn_b1_8_115200 },
3570 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3572 pbn_b1_bt_4_115200 },
3573 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3575 pbn_b1_bt_2_115200 },
3576 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3578 pbn_b1_bt_4_115200 },
3579 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3581 pbn_b1_bt_2_115200 },
3582 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3584 pbn_ni8430_2 },
3585 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3587 pbn_ni8430_2 },
3588 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3590 pbn_ni8430_4 },
3591 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3593 pbn_ni8430_4 },
3594 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596 pbn_ni8430_8 },
3597 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3599 pbn_ni8430_8 },
3600 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3602 pbn_ni8430_16 },
3603 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3605 pbn_ni8430_16 },
3606 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3608 pbn_ni8430_2 },
3609 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3611 pbn_ni8430_2 },
3612 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3614 pbn_ni8430_4 },
3615 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_ni8430_4 },
3618
3619 /*
3620 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3621 */
3622 { PCI_VENDOR_ID_ADDIDATA,
3623 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3624 PCI_ANY_ID,
3625 PCI_ANY_ID,
3626 0,
3627 0,
3628 pbn_b0_4_115200 },
3629
3630 { PCI_VENDOR_ID_ADDIDATA,
3631 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3632 PCI_ANY_ID,
3633 PCI_ANY_ID,
3634 0,
3635 0,
3636 pbn_b0_2_115200 },
3637
3638 { PCI_VENDOR_ID_ADDIDATA,
3639 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3640 PCI_ANY_ID,
3641 PCI_ANY_ID,
3642 0,
3643 0,
3644 pbn_b0_1_115200 },
3645
3646 { PCI_VENDOR_ID_ADDIDATA_OLD,
3647 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3648 PCI_ANY_ID,
3649 PCI_ANY_ID,
3650 0,
3651 0,
3652 pbn_b1_8_115200 },
3653
3654 { PCI_VENDOR_ID_ADDIDATA,
3655 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3656 PCI_ANY_ID,
3657 PCI_ANY_ID,
3658 0,
3659 0,
3660 pbn_b0_4_115200 },
3661
3662 { PCI_VENDOR_ID_ADDIDATA,
3663 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3664 PCI_ANY_ID,
3665 PCI_ANY_ID,
3666 0,
3667 0,
3668 pbn_b0_2_115200 },
3669
3670 { PCI_VENDOR_ID_ADDIDATA,
3671 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3672 PCI_ANY_ID,
3673 PCI_ANY_ID,
3674 0,
3675 0,
3676 pbn_b0_1_115200 },
3677
3678 { PCI_VENDOR_ID_ADDIDATA,
3679 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3680 PCI_ANY_ID,
3681 PCI_ANY_ID,
3682 0,
3683 0,
3684 pbn_b0_4_115200 },
3685
3686 { PCI_VENDOR_ID_ADDIDATA,
3687 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3688 PCI_ANY_ID,
3689 PCI_ANY_ID,
3690 0,
3691 0,
3692 pbn_b0_2_115200 },
3693
3694 { PCI_VENDOR_ID_ADDIDATA,
3695 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3696 PCI_ANY_ID,
3697 PCI_ANY_ID,
3698 0,
3699 0,
3700 pbn_b0_1_115200 },
3701
3702 { PCI_VENDOR_ID_ADDIDATA,
3703 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3704 PCI_ANY_ID,
3705 PCI_ANY_ID,
3706 0,
3707 0,
3708 pbn_b0_8_115200 },
3709
3710 { PCI_VENDOR_ID_ADDIDATA,
3711 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3712 PCI_ANY_ID,
3713 PCI_ANY_ID,
3714 0,
3715 0,
3716 pbn_ADDIDATA_PCIe_4_3906250 },
3717
3718 { PCI_VENDOR_ID_ADDIDATA,
3719 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3720 PCI_ANY_ID,
3721 PCI_ANY_ID,
3722 0,
3723 0,
3724 pbn_ADDIDATA_PCIe_2_3906250 },
3725
3726 { PCI_VENDOR_ID_ADDIDATA,
3727 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3728 PCI_ANY_ID,
3729 PCI_ANY_ID,
3730 0,
3731 0,
3732 pbn_ADDIDATA_PCIe_1_3906250 },
3733
3734 { PCI_VENDOR_ID_ADDIDATA,
3735 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3736 PCI_ANY_ID,
3737 PCI_ANY_ID,
3738 0,
3739 0,
3740 pbn_ADDIDATA_PCIe_8_3906250 },
3741
3742 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3743 PCI_VENDOR_ID_IBM, 0x0299,
3744 0, 0, pbn_b0_bt_2_115200 },
3745
3746 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3747 0xA000, 0x1000,
3748 0, 0, pbn_b0_1_115200 },
3749
3750 /*
3751 * Best Connectivity PCI Multi I/O cards
3752 */
3753
3754 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3755 0xA000, 0x1000,
3756 0, 0, pbn_b0_1_115200 },
3757
3758 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3759 0xA000, 0x3004,
3760 0, 0, pbn_b0_bt_4_115200 },
3761
3762 /*
3763 * These entries match devices with class COMMUNICATION_SERIAL,
3764 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3765 */
3766 { PCI_ANY_ID, PCI_ANY_ID,
3767 PCI_ANY_ID, PCI_ANY_ID,
3768 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3769 0xffff00, pbn_default },
3770 { PCI_ANY_ID, PCI_ANY_ID,
3771 PCI_ANY_ID, PCI_ANY_ID,
3772 PCI_CLASS_COMMUNICATION_MODEM << 8,
3773 0xffff00, pbn_default },
3774 { PCI_ANY_ID, PCI_ANY_ID,
3775 PCI_ANY_ID, PCI_ANY_ID,
3776 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3777 0xffff00, pbn_default },
3778 { 0, }
3779 };
3780
3781 static struct pci_driver serial_pci_driver = {
3782 .name = "serial",
3783 .probe = pciserial_init_one,
3784 .remove = __devexit_p(pciserial_remove_one),
3785 #ifdef CONFIG_PM
3786 .suspend = pciserial_suspend_one,
3787 .resume = pciserial_resume_one,
3788 #endif
3789 .id_table = serial_pci_tbl,
3790 };
3791
3792 static int __init serial8250_pci_init(void)
3793 {
3794 return pci_register_driver(&serial_pci_driver);
3795 }
3796
3797 static void __exit serial8250_pci_exit(void)
3798 {
3799 pci_unregister_driver(&serial_pci_driver);
3800 }
3801
3802 module_init(serial8250_pci_init);
3803 module_exit(serial8250_pci_exit);
3804
3805 MODULE_LICENSE("GPL");
3806 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3807 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Tomato firmware and modifications.