2 * Copyright (c) 2000-2010 LSI Corporation.
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
9 * mpi2_ioc.h Version: 02.00.14
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
66 * Added two new ReasonCode defines for SAS Device Status
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
84 * Added two new reason codes for SAS Device Status Change
86 * Added new event: SAS PHY Counter.
87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
90 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
91 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
92 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
93 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
94 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
95 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
96 * Added Host Based Discovery Phy Event data.
97 * Added defines for ProductID Product field
98 * (MPI2_FW_HEADER_PID_).
99 * Modified values for SAS ProductID Family
100 * (MPI2_FW_HEADER_PID_FAMILY_).
101 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
102 * Added PowerManagementControl Request structures and
104 * --------------------------------------------------------------------------
110 /*****************************************************************************
114 *****************************************************************************/
116 /****************************************************************************
118 ****************************************************************************/
120 /* IOCInit Request message */
121 typedef struct _MPI2_IOC_INIT_REQUEST
123 U8 WhoInit
; /* 0x00 */
124 U8 Reserved1
; /* 0x01 */
125 U8 ChainOffset
; /* 0x02 */
126 U8 Function
; /* 0x03 */
127 U16 Reserved2
; /* 0x04 */
128 U8 Reserved3
; /* 0x06 */
129 U8 MsgFlags
; /* 0x07 */
132 U16 Reserved4
; /* 0x0A */
133 U16 MsgVersion
; /* 0x0C */
134 U16 HeaderVersion
; /* 0x0E */
135 U32 Reserved5
; /* 0x10 */
136 U16 Reserved6
; /* 0x14 */
137 U8 Reserved7
; /* 0x16 */
138 U8 HostMSIxVectors
; /* 0x17 */
139 U16 Reserved8
; /* 0x18 */
140 U16 SystemRequestFrameSize
; /* 0x1A */
141 U16 ReplyDescriptorPostQueueDepth
; /* 0x1C */
142 U16 ReplyFreeQueueDepth
; /* 0x1E */
143 U32 SenseBufferAddressHigh
; /* 0x20 */
144 U32 SystemReplyAddressHigh
; /* 0x24 */
145 U64 SystemRequestFrameBaseAddress
; /* 0x28 */
146 U64 ReplyDescriptorPostQueueAddress
;/* 0x30 */
147 U64 ReplyFreeQueueAddress
; /* 0x38 */
148 U64 TimeStamp
; /* 0x40 */
149 } MPI2_IOC_INIT_REQUEST
, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST
,
150 Mpi2IOCInitRequest_t
, MPI2_POINTER pMpi2IOCInitRequest_t
;
153 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
154 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
155 #define MPI2_WHOINIT_ROM_BIOS (0x02)
156 #define MPI2_WHOINIT_PCI_PEER (0x03)
157 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
158 #define MPI2_WHOINIT_MANUFACTURER (0x05)
161 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
162 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
163 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
164 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
167 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
168 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
169 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
170 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
172 /* minimum depth for the Reply Descriptor Post Queue */
173 #define MPI2_RDPQ_DEPTH_MIN (16)
176 /* IOCInit Reply message */
177 typedef struct _MPI2_IOC_INIT_REPLY
179 U8 WhoInit
; /* 0x00 */
180 U8 Reserved1
; /* 0x01 */
181 U8 MsgLength
; /* 0x02 */
182 U8 Function
; /* 0x03 */
183 U16 Reserved2
; /* 0x04 */
184 U8 Reserved3
; /* 0x06 */
185 U8 MsgFlags
; /* 0x07 */
188 U16 Reserved4
; /* 0x0A */
189 U16 Reserved5
; /* 0x0C */
190 U16 IOCStatus
; /* 0x0E */
191 U32 IOCLogInfo
; /* 0x10 */
192 } MPI2_IOC_INIT_REPLY
, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY
,
193 Mpi2IOCInitReply_t
, MPI2_POINTER pMpi2IOCInitReply_t
;
196 /****************************************************************************
198 ****************************************************************************/
200 /* IOCFacts Request message */
201 typedef struct _MPI2_IOC_FACTS_REQUEST
203 U16 Reserved1
; /* 0x00 */
204 U8 ChainOffset
; /* 0x02 */
205 U8 Function
; /* 0x03 */
206 U16 Reserved2
; /* 0x04 */
207 U8 Reserved3
; /* 0x06 */
208 U8 MsgFlags
; /* 0x07 */
211 U16 Reserved4
; /* 0x0A */
212 } MPI2_IOC_FACTS_REQUEST
, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST
,
213 Mpi2IOCFactsRequest_t
, MPI2_POINTER pMpi2IOCFactsRequest_t
;
216 /* IOCFacts Reply message */
217 typedef struct _MPI2_IOC_FACTS_REPLY
219 U16 MsgVersion
; /* 0x00 */
220 U8 MsgLength
; /* 0x02 */
221 U8 Function
; /* 0x03 */
222 U16 HeaderVersion
; /* 0x04 */
223 U8 IOCNumber
; /* 0x06 */
224 U8 MsgFlags
; /* 0x07 */
227 U16 Reserved1
; /* 0x0A */
228 U16 IOCExceptions
; /* 0x0C */
229 U16 IOCStatus
; /* 0x0E */
230 U32 IOCLogInfo
; /* 0x10 */
231 U8 MaxChainDepth
; /* 0x14 */
232 U8 WhoInit
; /* 0x15 */
233 U8 NumberOfPorts
; /* 0x16 */
234 U8 MaxMSIxVectors
; /* 0x17 */
235 U16 RequestCredit
; /* 0x18 */
236 U16 ProductID
; /* 0x1A */
237 U32 IOCCapabilities
; /* 0x1C */
238 MPI2_VERSION_UNION FWVersion
; /* 0x20 */
239 U16 IOCRequestFrameSize
; /* 0x24 */
240 U16 Reserved3
; /* 0x26 */
241 U16 MaxInitiators
; /* 0x28 */
242 U16 MaxTargets
; /* 0x2A */
243 U16 MaxSasExpanders
; /* 0x2C */
244 U16 MaxEnclosures
; /* 0x2E */
245 U16 ProtocolFlags
; /* 0x30 */
246 U16 HighPriorityCredit
; /* 0x32 */
247 U16 MaxReplyDescriptorPostQueueDepth
; /* 0x34 */
248 U8 ReplyFrameSize
; /* 0x36 */
249 U8 MaxVolumes
; /* 0x37 */
250 U16 MaxDevHandle
; /* 0x38 */
251 U16 MaxPersistentEntries
; /* 0x3A */
252 U16 MinDevHandle
; /* 0x3C */
253 U16 Reserved4
; /* 0x3E */
254 } MPI2_IOC_FACTS_REPLY
, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY
,
255 Mpi2IOCFactsReply_t
, MPI2_POINTER pMpi2IOCFactsReply_t
;
258 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
259 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
260 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
261 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
264 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
265 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
266 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
267 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
270 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
272 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
273 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
274 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
275 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
276 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
278 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
279 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
280 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
281 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
282 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
284 /* defines for WhoInit field are after the IOCInit Request */
286 /* ProductID field uses MPI2_FW_HEADER_PID_ */
288 /* IOCCapabilities */
289 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
290 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
291 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
292 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
293 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
294 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
295 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
296 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
297 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
298 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
299 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
300 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
301 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
304 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
305 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
308 /****************************************************************************
310 ****************************************************************************/
312 /* PortFacts Request message */
313 typedef struct _MPI2_PORT_FACTS_REQUEST
315 U16 Reserved1
; /* 0x00 */
316 U8 ChainOffset
; /* 0x02 */
317 U8 Function
; /* 0x03 */
318 U16 Reserved2
; /* 0x04 */
319 U8 PortNumber
; /* 0x06 */
320 U8 MsgFlags
; /* 0x07 */
323 U16 Reserved3
; /* 0x0A */
324 } MPI2_PORT_FACTS_REQUEST
, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST
,
325 Mpi2PortFactsRequest_t
, MPI2_POINTER pMpi2PortFactsRequest_t
;
327 /* PortFacts Reply message */
328 typedef struct _MPI2_PORT_FACTS_REPLY
330 U16 Reserved1
; /* 0x00 */
331 U8 MsgLength
; /* 0x02 */
332 U8 Function
; /* 0x03 */
333 U16 Reserved2
; /* 0x04 */
334 U8 PortNumber
; /* 0x06 */
335 U8 MsgFlags
; /* 0x07 */
338 U16 Reserved3
; /* 0x0A */
339 U16 Reserved4
; /* 0x0C */
340 U16 IOCStatus
; /* 0x0E */
341 U32 IOCLogInfo
; /* 0x10 */
342 U8 Reserved5
; /* 0x14 */
343 U8 PortType
; /* 0x15 */
344 U16 Reserved6
; /* 0x16 */
345 U16 MaxPostedCmdBuffers
; /* 0x18 */
346 U16 Reserved7
; /* 0x1A */
347 } MPI2_PORT_FACTS_REPLY
, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY
,
348 Mpi2PortFactsReply_t
, MPI2_POINTER pMpi2PortFactsReply_t
;
350 /* PortType values */
351 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
352 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
353 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
354 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
355 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
358 /****************************************************************************
360 ****************************************************************************/
362 /* PortEnable Request message */
363 typedef struct _MPI2_PORT_ENABLE_REQUEST
365 U16 Reserved1
; /* 0x00 */
366 U8 ChainOffset
; /* 0x02 */
367 U8 Function
; /* 0x03 */
368 U8 Reserved2
; /* 0x04 */
369 U8 PortFlags
; /* 0x05 */
370 U8 Reserved3
; /* 0x06 */
371 U8 MsgFlags
; /* 0x07 */
374 U16 Reserved4
; /* 0x0A */
375 } MPI2_PORT_ENABLE_REQUEST
, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST
,
376 Mpi2PortEnableRequest_t
, MPI2_POINTER pMpi2PortEnableRequest_t
;
379 /* PortEnable Reply message */
380 typedef struct _MPI2_PORT_ENABLE_REPLY
382 U16 Reserved1
; /* 0x00 */
383 U8 MsgLength
; /* 0x02 */
384 U8 Function
; /* 0x03 */
385 U8 Reserved2
; /* 0x04 */
386 U8 PortFlags
; /* 0x05 */
387 U8 Reserved3
; /* 0x06 */
388 U8 MsgFlags
; /* 0x07 */
391 U16 Reserved4
; /* 0x0A */
392 U16 Reserved5
; /* 0x0C */
393 U16 IOCStatus
; /* 0x0E */
394 U32 IOCLogInfo
; /* 0x10 */
395 } MPI2_PORT_ENABLE_REPLY
, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY
,
396 Mpi2PortEnableReply_t
, MPI2_POINTER pMpi2PortEnableReply_t
;
399 /****************************************************************************
400 * EventNotification message
401 ****************************************************************************/
403 /* EventNotification Request message */
404 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
406 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
408 U16 Reserved1
; /* 0x00 */
409 U8 ChainOffset
; /* 0x02 */
410 U8 Function
; /* 0x03 */
411 U16 Reserved2
; /* 0x04 */
412 U8 Reserved3
; /* 0x06 */
413 U8 MsgFlags
; /* 0x07 */
416 U16 Reserved4
; /* 0x0A */
417 U32 Reserved5
; /* 0x0C */
418 U32 Reserved6
; /* 0x10 */
419 U32 EventMasks
[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS
];/* 0x14 */
420 U16 SASBroadcastPrimitiveMasks
; /* 0x24 */
421 U16 Reserved7
; /* 0x26 */
422 U32 Reserved8
; /* 0x28 */
423 } MPI2_EVENT_NOTIFICATION_REQUEST
,
424 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST
,
425 Mpi2EventNotificationRequest_t
, MPI2_POINTER pMpi2EventNotificationRequest_t
;
428 /* EventNotification Reply message */
429 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
431 U16 EventDataLength
; /* 0x00 */
432 U8 MsgLength
; /* 0x02 */
433 U8 Function
; /* 0x03 */
434 U16 Reserved1
; /* 0x04 */
435 U8 AckRequired
; /* 0x06 */
436 U8 MsgFlags
; /* 0x07 */
439 U16 Reserved2
; /* 0x0A */
440 U16 Reserved3
; /* 0x0C */
441 U16 IOCStatus
; /* 0x0E */
442 U32 IOCLogInfo
; /* 0x10 */
443 U16 Event
; /* 0x14 */
444 U16 Reserved4
; /* 0x16 */
445 U32 EventContext
; /* 0x18 */
446 U32 EventData
[1]; /* 0x1C */
447 } MPI2_EVENT_NOTIFICATION_REPLY
, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY
,
448 Mpi2EventNotificationReply_t
, MPI2_POINTER pMpi2EventNotificationReply_t
;
451 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
452 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
455 #define MPI2_EVENT_LOG_DATA (0x0001)
456 #define MPI2_EVENT_STATE_CHANGE (0x0002)
457 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
458 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
459 #define MPI2_EVENT_TASK_SET_FULL (0x000E)
460 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
461 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
462 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
463 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
464 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
465 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
466 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
467 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
468 #define MPI2_EVENT_IR_VOLUME (0x001E)
469 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
470 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
471 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
472 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
473 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
474 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
475 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
478 /* Log Entry Added Event data */
480 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
481 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
483 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
485 U64 TimeStamp
; /* 0x00 */
486 U32 Reserved1
; /* 0x08 */
487 U16 LogSequence
; /* 0x0C */
488 U16 LogEntryQualifier
; /* 0x0E */
491 U16 Reserved2
; /* 0x12 */
492 U8 LogData
[MPI2_EVENT_DATA_LOG_DATA_LENGTH
];/* 0x14 */
493 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED
,
494 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED
,
495 Mpi2EventDataLogEntryAdded_t
, MPI2_POINTER pMpi2EventDataLogEntryAdded_t
;
497 /* GPIO Interrupt Event data */
499 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
{
500 U8 GPIONum
; /* 0x00 */
501 U8 Reserved1
; /* 0x01 */
502 U16 Reserved2
; /* 0x02 */
503 } MPI2_EVENT_DATA_GPIO_INTERRUPT
,
504 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT
,
505 Mpi2EventDataGpioInterrupt_t
, MPI2_POINTER pMpi2EventDataGpioInterrupt_t
;
507 /* Hard Reset Received Event data */
509 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
511 U8 Reserved1
; /* 0x00 */
513 U16 Reserved2
; /* 0x02 */
514 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED
,
515 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED
,
516 Mpi2EventDataHardResetReceived_t
,
517 MPI2_POINTER pMpi2EventDataHardResetReceived_t
;
519 /* Task Set Full Event data */
521 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
523 U16 DevHandle
; /* 0x00 */
524 U16 CurrentDepth
; /* 0x02 */
525 } MPI2_EVENT_DATA_TASK_SET_FULL
, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL
,
526 Mpi2EventDataTaskSetFull_t
, MPI2_POINTER pMpi2EventDataTaskSetFull_t
;
529 /* SAS Device Status Change Event data */
531 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
533 U16 TaskTag
; /* 0x00 */
534 U8 ReasonCode
; /* 0x02 */
535 U8 Reserved1
; /* 0x03 */
538 U16 DevHandle
; /* 0x06 */
539 U32 Reserved2
; /* 0x08 */
540 U64 SASAddress
; /* 0x0C */
541 U8 LUN
[8]; /* 0x14 */
542 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
,
543 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
,
544 Mpi2EventDataSasDeviceStatusChange_t
,
545 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t
;
547 /* SAS Device Status Change Event data ReasonCode values */
548 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
549 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
550 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
551 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
552 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
553 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
554 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
555 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
556 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
557 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
558 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
559 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
560 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
563 /* Integrated RAID Operation Status Event data */
565 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
567 U16 VolDevHandle
; /* 0x00 */
568 U16 Reserved1
; /* 0x02 */
569 U8 RAIDOperation
; /* 0x04 */
570 U8 PercentComplete
; /* 0x05 */
571 U16 Reserved2
; /* 0x06 */
572 U32 Resereved3
; /* 0x08 */
573 } MPI2_EVENT_DATA_IR_OPERATION_STATUS
,
574 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS
,
575 Mpi2EventDataIrOperationStatus_t
,
576 MPI2_POINTER pMpi2EventDataIrOperationStatus_t
;
578 /* Integrated RAID Operation Status Event data RAIDOperation values */
579 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
580 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
581 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
582 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
583 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
586 /* Integrated RAID Volume Event data */
588 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
590 U16 VolDevHandle
; /* 0x00 */
591 U8 ReasonCode
; /* 0x02 */
592 U8 Reserved1
; /* 0x03 */
593 U32 NewValue
; /* 0x04 */
594 U32 PreviousValue
; /* 0x08 */
595 } MPI2_EVENT_DATA_IR_VOLUME
, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME
,
596 Mpi2EventDataIrVolume_t
, MPI2_POINTER pMpi2EventDataIrVolume_t
;
598 /* Integrated RAID Volume Event data ReasonCode values */
599 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
600 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
601 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
604 /* Integrated RAID Physical Disk Event data */
606 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
608 U16 Reserved1
; /* 0x00 */
609 U8 ReasonCode
; /* 0x02 */
610 U8 PhysDiskNum
; /* 0x03 */
611 U16 PhysDiskDevHandle
; /* 0x04 */
612 U16 Reserved2
; /* 0x06 */
614 U16 EnclosureHandle
; /* 0x0A */
615 U32 NewValue
; /* 0x0C */
616 U32 PreviousValue
; /* 0x10 */
617 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK
,
618 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK
,
619 Mpi2EventDataIrPhysicalDisk_t
, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t
;
621 /* Integrated RAID Physical Disk Event data ReasonCode values */
622 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
623 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
624 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
627 /* Integrated RAID Configuration Change List Event data */
630 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
631 * one and check NumElements at runtime.
633 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
634 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
637 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
639 U16 ElementFlags
; /* 0x00 */
640 U16 VolDevHandle
; /* 0x02 */
641 U8 ReasonCode
; /* 0x04 */
642 U8 PhysDiskNum
; /* 0x05 */
643 U16 PhysDiskDevHandle
; /* 0x06 */
644 } MPI2_EVENT_IR_CONFIG_ELEMENT
, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT
,
645 Mpi2EventIrConfigElement_t
, MPI2_POINTER pMpi2EventIrConfigElement_t
;
647 /* IR Configuration Change List Event data ElementFlags values */
648 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
649 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
650 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
651 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
653 /* IR Configuration Change List Event data ReasonCode values */
654 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
655 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
656 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
657 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
658 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
659 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
660 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
661 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
662 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
664 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
666 U8 NumElements
; /* 0x00 */
667 U8 Reserved1
; /* 0x01 */
668 U8 Reserved2
; /* 0x02 */
669 U8 ConfigNum
; /* 0x03 */
670 U32 Flags
; /* 0x04 */
671 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement
[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
]; /* 0x08 */
672 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
,
673 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
,
674 Mpi2EventDataIrConfigChangeList_t
,
675 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t
;
677 /* IR Configuration Change List Event data Flags values */
678 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
681 /* SAS Discovery Event data */
683 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
686 U8 ReasonCode
; /* 0x01 */
687 U8 PhysicalPort
; /* 0x02 */
688 U8 Reserved1
; /* 0x03 */
689 U32 DiscoveryStatus
; /* 0x04 */
690 } MPI2_EVENT_DATA_SAS_DISCOVERY
,
691 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY
,
692 Mpi2EventDataSasDiscovery_t
, MPI2_POINTER pMpi2EventDataSasDiscovery_t
;
694 /* SAS Discovery Event data Flags values */
695 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
696 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
698 /* SAS Discovery Event data ReasonCode values */
699 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
700 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
702 /* SAS Discovery Event data DiscoveryStatus values */
703 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
704 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
705 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
706 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
707 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
708 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
709 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
710 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
711 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
712 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
713 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
714 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
715 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
716 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
717 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
718 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
719 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
720 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
721 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
722 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
725 /* SAS Broadcast Primitive Event data */
727 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
729 U8 PhyNum
; /* 0x00 */
731 U8 PortWidth
; /* 0x02 */
732 U8 Primitive
; /* 0x03 */
733 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
,
734 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
,
735 Mpi2EventDataSasBroadcastPrimitive_t
,
736 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t
;
738 /* defines for the Primitive field */
739 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
740 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
741 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
742 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
743 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
744 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
745 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
746 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
749 /* SAS Initiator Device Status Change Event data */
751 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
753 U8 ReasonCode
; /* 0x00 */
754 U8 PhysicalPort
; /* 0x01 */
755 U16 DevHandle
; /* 0x02 */
756 U64 SASAddress
; /* 0x04 */
757 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
,
758 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
,
759 Mpi2EventDataSasInitDevStatusChange_t
,
760 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t
;
762 /* SAS Initiator Device Status Change event ReasonCode values */
763 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
764 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
767 /* SAS Initiator Device Table Overflow Event data */
769 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
771 U16 MaxInit
; /* 0x00 */
772 U16 CurrentInit
; /* 0x02 */
773 U64 SASAddress
; /* 0x04 */
774 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
,
775 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
,
776 Mpi2EventDataSasInitTableOverflow_t
,
777 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t
;
780 /* SAS Topology Change List Event data */
783 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
784 * one and check NumEntries at runtime.
786 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
787 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
790 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
792 U16 AttachedDevHandle
; /* 0x00 */
793 U8 LinkRate
; /* 0x02 */
794 U8 PhyStatus
; /* 0x03 */
795 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY
, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY
,
796 Mpi2EventSasTopoPhyEntry_t
, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t
;
798 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
800 U16 EnclosureHandle
; /* 0x00 */
801 U16 ExpanderDevHandle
; /* 0x02 */
802 U8 NumPhys
; /* 0x04 */
803 U8 Reserved1
; /* 0x05 */
804 U16 Reserved2
; /* 0x06 */
805 U8 NumEntries
; /* 0x08 */
806 U8 StartPhyNum
; /* 0x09 */
807 U8 ExpStatus
; /* 0x0A */
808 U8 PhysicalPort
; /* 0x0B */
809 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY
[MPI2_EVENT_SAS_TOPO_PHY_COUNT
]; /* 0x0C*/
810 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
,
811 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
,
812 Mpi2EventDataSasTopologyChangeList_t
,
813 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t
;
815 /* values for the ExpStatus field */
816 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
817 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
818 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
819 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
820 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
822 /* defines for the LinkRate field */
823 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
824 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
825 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
826 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
828 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
829 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
830 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
831 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
832 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
833 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
834 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
835 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
836 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
838 /* values for the PhyStatus field */
839 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
840 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
841 /* values for the PhyStatus ReasonCode sub-field */
842 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
843 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
844 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
845 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
846 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
847 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
850 /* SAS Enclosure Device Status Change Event data */
852 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
854 U16 EnclosureHandle
; /* 0x00 */
855 U8 ReasonCode
; /* 0x02 */
856 U8 PhysicalPort
; /* 0x03 */
857 U64 EnclosureLogicalID
; /* 0x04 */
858 U16 NumSlots
; /* 0x0C */
859 U16 StartSlot
; /* 0x0E */
860 U32 PhyBits
; /* 0x10 */
861 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
,
862 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
,
863 Mpi2EventDataSasEnclDevStatusChange_t
,
864 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t
;
866 /* SAS Enclosure Device Status Change event ReasonCode values */
867 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
868 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
871 /* SAS PHY Counter Event data */
873 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
{
874 U64 TimeStamp
; /* 0x00 */
875 U32 Reserved1
; /* 0x08 */
876 U8 PhyEventCode
; /* 0x0C */
877 U8 PhyNum
; /* 0x0D */
878 U16 Reserved2
; /* 0x0E */
879 U32 PhyEventInfo
; /* 0x10 */
880 U8 CounterType
; /* 0x14 */
881 U8 ThresholdWindow
; /* 0x15 */
882 U8 TimeUnits
; /* 0x16 */
883 U8 Reserved3
; /* 0x17 */
884 U32 EventThreshold
; /* 0x18 */
885 U16 ThresholdFlags
; /* 0x1C */
886 U16 Reserved4
; /* 0x1E */
887 } MPI2_EVENT_DATA_SAS_PHY_COUNTER
,
888 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER
,
889 Mpi2EventDataSasPhyCounter_t
, MPI2_POINTER pMpi2EventDataSasPhyCounter_t
;
891 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
893 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
895 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
897 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
898 * ThresholdFlags field
902 /* SAS Quiesce Event data */
904 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
{
905 U8 ReasonCode
; /* 0x00 */
906 U8 Reserved1
; /* 0x01 */
907 U16 Reserved2
; /* 0x02 */
908 U32 Reserved3
; /* 0x04 */
909 } MPI2_EVENT_DATA_SAS_QUIESCE
,
910 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE
,
911 Mpi2EventDataSasQuiesce_t
, MPI2_POINTER pMpi2EventDataSasQuiesce_t
;
913 /* SAS Quiesce Event data ReasonCode values */
914 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
915 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
918 /* Host Based Discovery Phy Event data */
920 typedef struct _MPI2_EVENT_HBD_PHY_SAS
{
922 U8 NegotiatedLinkRate
; /* 0x01 */
923 U8 PhyNum
; /* 0x02 */
924 U8 PhysicalPort
; /* 0x03 */
925 U32 Reserved1
; /* 0x04 */
926 U8 InitialFrame
[28]; /* 0x08 */
927 } MPI2_EVENT_HBD_PHY_SAS
, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS
,
928 Mpi2EventHbdPhySas_t
, MPI2_POINTER pMpi2EventHbdPhySas_t
;
930 /* values for the Flags field */
931 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
932 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
934 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
935 * the NegotiatedLinkRate field */
937 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
{
938 MPI2_EVENT_HBD_PHY_SAS Sas
;
939 } MPI2_EVENT_HBD_DESCRIPTOR
, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR
,
940 Mpi2EventHbdDescriptor_t
, MPI2_POINTER pMpi2EventHbdDescriptor_t
;
942 typedef struct _MPI2_EVENT_DATA_HBD_PHY
{
943 U8 DescriptorType
; /* 0x00 */
944 U8 Reserved1
; /* 0x01 */
945 U16 Reserved2
; /* 0x02 */
946 U32 Reserved3
; /* 0x04 */
947 MPI2_EVENT_HBD_DESCRIPTOR Descriptor
; /* 0x08 */
948 } MPI2_EVENT_DATA_HBD_PHY
, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY
,
949 Mpi2EventDataHbdPhy_t
, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t
;
951 /* values for the DescriptorType field */
952 #define MPI2_EVENT_HBD_DT_SAS (0x01)
956 /****************************************************************************
958 ****************************************************************************/
960 /* EventAck Request message */
961 typedef struct _MPI2_EVENT_ACK_REQUEST
963 U16 Reserved1
; /* 0x00 */
964 U8 ChainOffset
; /* 0x02 */
965 U8 Function
; /* 0x03 */
966 U16 Reserved2
; /* 0x04 */
967 U8 Reserved3
; /* 0x06 */
968 U8 MsgFlags
; /* 0x07 */
971 U16 Reserved4
; /* 0x0A */
972 U16 Event
; /* 0x0C */
973 U16 Reserved5
; /* 0x0E */
974 U32 EventContext
; /* 0x10 */
975 } MPI2_EVENT_ACK_REQUEST
, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST
,
976 Mpi2EventAckRequest_t
, MPI2_POINTER pMpi2EventAckRequest_t
;
979 /* EventAck Reply message */
980 typedef struct _MPI2_EVENT_ACK_REPLY
982 U16 Reserved1
; /* 0x00 */
983 U8 MsgLength
; /* 0x02 */
984 U8 Function
; /* 0x03 */
985 U16 Reserved2
; /* 0x04 */
986 U8 Reserved3
; /* 0x06 */
987 U8 MsgFlags
; /* 0x07 */
990 U16 Reserved4
; /* 0x0A */
991 U16 Reserved5
; /* 0x0C */
992 U16 IOCStatus
; /* 0x0E */
993 U32 IOCLogInfo
; /* 0x10 */
994 } MPI2_EVENT_ACK_REPLY
, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY
,
995 Mpi2EventAckReply_t
, MPI2_POINTER pMpi2EventAckReply_t
;
998 /****************************************************************************
1000 ****************************************************************************/
1002 /* FWDownload Request message */
1003 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1005 U8 ImageType
; /* 0x00 */
1006 U8 Reserved1
; /* 0x01 */
1007 U8 ChainOffset
; /* 0x02 */
1008 U8 Function
; /* 0x03 */
1009 U16 Reserved2
; /* 0x04 */
1010 U8 Reserved3
; /* 0x06 */
1011 U8 MsgFlags
; /* 0x07 */
1012 U8 VP_ID
; /* 0x08 */
1013 U8 VF_ID
; /* 0x09 */
1014 U16 Reserved4
; /* 0x0A */
1015 U32 TotalImageSize
; /* 0x0C */
1016 U32 Reserved5
; /* 0x10 */
1017 MPI2_MPI_SGE_UNION SGL
; /* 0x14 */
1018 } MPI2_FW_DOWNLOAD_REQUEST
, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST
,
1019 Mpi2FWDownloadRequest
, MPI2_POINTER pMpi2FWDownloadRequest
;
1021 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1023 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1024 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1025 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1026 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1027 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1028 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1029 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1030 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1032 /* FWDownload TransactionContext Element */
1033 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1035 U8 Reserved1
; /* 0x00 */
1036 U8 ContextSize
; /* 0x01 */
1037 U8 DetailsLength
; /* 0x02 */
1038 U8 Flags
; /* 0x03 */
1039 U32 Reserved2
; /* 0x04 */
1040 U32 ImageOffset
; /* 0x08 */
1041 U32 ImageSize
; /* 0x0C */
1042 } MPI2_FW_DOWNLOAD_TCSGE
, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE
,
1043 Mpi2FWDownloadTCSGE_t
, MPI2_POINTER pMpi2FWDownloadTCSGE_t
;
1045 /* FWDownload Reply message */
1046 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1048 U8 ImageType
; /* 0x00 */
1049 U8 Reserved1
; /* 0x01 */
1050 U8 MsgLength
; /* 0x02 */
1051 U8 Function
; /* 0x03 */
1052 U16 Reserved2
; /* 0x04 */
1053 U8 Reserved3
; /* 0x06 */
1054 U8 MsgFlags
; /* 0x07 */
1055 U8 VP_ID
; /* 0x08 */
1056 U8 VF_ID
; /* 0x09 */
1057 U16 Reserved4
; /* 0x0A */
1058 U16 Reserved5
; /* 0x0C */
1059 U16 IOCStatus
; /* 0x0E */
1060 U32 IOCLogInfo
; /* 0x10 */
1061 } MPI2_FW_DOWNLOAD_REPLY
, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY
,
1062 Mpi2FWDownloadReply_t
, MPI2_POINTER pMpi2FWDownloadReply_t
;
1065 /****************************************************************************
1067 ****************************************************************************/
1069 /* FWUpload Request message */
1070 typedef struct _MPI2_FW_UPLOAD_REQUEST
1072 U8 ImageType
; /* 0x00 */
1073 U8 Reserved1
; /* 0x01 */
1074 U8 ChainOffset
; /* 0x02 */
1075 U8 Function
; /* 0x03 */
1076 U16 Reserved2
; /* 0x04 */
1077 U8 Reserved3
; /* 0x06 */
1078 U8 MsgFlags
; /* 0x07 */
1079 U8 VP_ID
; /* 0x08 */
1080 U8 VF_ID
; /* 0x09 */
1081 U16 Reserved4
; /* 0x0A */
1082 U32 Reserved5
; /* 0x0C */
1083 U32 Reserved6
; /* 0x10 */
1084 MPI2_MPI_SGE_UNION SGL
; /* 0x14 */
1085 } MPI2_FW_UPLOAD_REQUEST
, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST
,
1086 Mpi2FWUploadRequest_t
, MPI2_POINTER pMpi2FWUploadRequest_t
;
1088 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1089 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1090 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1091 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1092 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1093 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1094 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1095 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1096 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1097 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1099 typedef struct _MPI2_FW_UPLOAD_TCSGE
1101 U8 Reserved1
; /* 0x00 */
1102 U8 ContextSize
; /* 0x01 */
1103 U8 DetailsLength
; /* 0x02 */
1104 U8 Flags
; /* 0x03 */
1105 U32 Reserved2
; /* 0x04 */
1106 U32 ImageOffset
; /* 0x08 */
1107 U32 ImageSize
; /* 0x0C */
1108 } MPI2_FW_UPLOAD_TCSGE
, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE
,
1109 Mpi2FWUploadTCSGE_t
, MPI2_POINTER pMpi2FWUploadTCSGE_t
;
1111 /* FWUpload Reply message */
1112 typedef struct _MPI2_FW_UPLOAD_REPLY
1114 U8 ImageType
; /* 0x00 */
1115 U8 Reserved1
; /* 0x01 */
1116 U8 MsgLength
; /* 0x02 */
1117 U8 Function
; /* 0x03 */
1118 U16 Reserved2
; /* 0x04 */
1119 U8 Reserved3
; /* 0x06 */
1120 U8 MsgFlags
; /* 0x07 */
1121 U8 VP_ID
; /* 0x08 */
1122 U8 VF_ID
; /* 0x09 */
1123 U16 Reserved4
; /* 0x0A */
1124 U16 Reserved5
; /* 0x0C */
1125 U16 IOCStatus
; /* 0x0E */
1126 U32 IOCLogInfo
; /* 0x10 */
1127 U32 ActualImageSize
; /* 0x14 */
1128 } MPI2_FW_UPLOAD_REPLY
, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY
,
1129 Mpi2FWUploadReply_t
, MPI2_POINTER pMPi2FWUploadReply_t
;
1132 /* FW Image Header */
1133 typedef struct _MPI2_FW_IMAGE_HEADER
1135 U32 Signature
; /* 0x00 */
1136 U32 Signature0
; /* 0x04 */
1137 U32 Signature1
; /* 0x08 */
1138 U32 Signature2
; /* 0x0C */
1139 MPI2_VERSION_UNION MPIVersion
; /* 0x10 */
1140 MPI2_VERSION_UNION FWVersion
; /* 0x14 */
1141 MPI2_VERSION_UNION NVDATAVersion
; /* 0x18 */
1142 MPI2_VERSION_UNION PackageVersion
; /* 0x1C */
1143 U16 VendorID
; /* 0x20 */
1144 U16 ProductID
; /* 0x22 */
1145 U16 ProtocolFlags
; /* 0x24 */
1146 U16 Reserved26
; /* 0x26 */
1147 U32 IOCCapabilities
; /* 0x28 */
1148 U32 ImageSize
; /* 0x2C */
1149 U32 NextImageHeaderOffset
; /* 0x30 */
1150 U32 Checksum
; /* 0x34 */
1151 U32 Reserved38
; /* 0x38 */
1152 U32 Reserved3C
; /* 0x3C */
1153 U32 Reserved40
; /* 0x40 */
1154 U32 Reserved44
; /* 0x44 */
1155 U32 Reserved48
; /* 0x48 */
1156 U32 Reserved4C
; /* 0x4C */
1157 U32 Reserved50
; /* 0x50 */
1158 U32 Reserved54
; /* 0x54 */
1159 U32 Reserved58
; /* 0x58 */
1160 U32 Reserved5C
; /* 0x5C */
1161 U32 Reserved60
; /* 0x60 */
1162 U32 FirmwareVersionNameWhat
; /* 0x64 */
1163 U8 FirmwareVersionName
[32]; /* 0x68 */
1164 U32 VendorNameWhat
; /* 0x88 */
1165 U8 VendorName
[32]; /* 0x8C */
1166 U32 PackageNameWhat
; /* 0x88 */
1167 U8 PackageName
[32]; /* 0x8C */
1168 U32 ReservedD0
; /* 0xD0 */
1169 U32 ReservedD4
; /* 0xD4 */
1170 U32 ReservedD8
; /* 0xD8 */
1171 U32 ReservedDC
; /* 0xDC */
1172 U32 ReservedE0
; /* 0xE0 */
1173 U32 ReservedE4
; /* 0xE4 */
1174 U32 ReservedE8
; /* 0xE8 */
1175 U32 ReservedEC
; /* 0xEC */
1176 U32 ReservedF0
; /* 0xF0 */
1177 U32 ReservedF4
; /* 0xF4 */
1178 U32 ReservedF8
; /* 0xF8 */
1179 U32 ReservedFC
; /* 0xFC */
1180 } MPI2_FW_IMAGE_HEADER
, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER
,
1181 Mpi2FWImageHeader_t
, MPI2_POINTER pMpi2FWImageHeader_t
;
1183 /* Signature field */
1184 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1185 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1186 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1188 /* Signature0 field */
1189 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1190 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1192 /* Signature1 field */
1193 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1194 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1196 /* Signature2 field */
1197 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1198 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1201 /* defines for using the ProductID field */
1202 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1203 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1205 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1206 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1207 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1208 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1211 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1213 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1214 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1216 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1218 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1221 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1222 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1223 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1225 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1227 #define MPI2_FW_HEADER_SIZE (0x100)
1230 /* Extended Image Header */
1231 typedef struct _MPI2_EXT_IMAGE_HEADER
1234 U8 ImageType
; /* 0x00 */
1235 U8 Reserved1
; /* 0x01 */
1236 U16 Reserved2
; /* 0x02 */
1237 U32 Checksum
; /* 0x04 */
1238 U32 ImageSize
; /* 0x08 */
1239 U32 NextImageHeaderOffset
; /* 0x0C */
1240 U32 PackageVersion
; /* 0x10 */
1241 U32 Reserved3
; /* 0x14 */
1242 U32 Reserved4
; /* 0x18 */
1243 U32 Reserved5
; /* 0x1C */
1244 U8 IdentifyString
[32]; /* 0x20 */
1245 } MPI2_EXT_IMAGE_HEADER
, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER
,
1246 Mpi2ExtImageHeader_t
, MPI2_POINTER pMpi2ExtImageHeader_t
;
1248 /* useful offsets */
1249 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1250 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1251 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1253 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1255 /* defines for the ImageType field */
1256 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1257 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1258 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1259 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1260 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1261 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1262 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1263 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1265 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1269 /* FLASH Layout Extended Image Data */
1272 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1273 * one and check RegionsPerLayout at runtime.
1275 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1276 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1280 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1281 * one and check NumberOfLayouts at runtime.
1283 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1284 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1287 typedef struct _MPI2_FLASH_REGION
1289 U8 RegionType
; /* 0x00 */
1290 U8 Reserved1
; /* 0x01 */
1291 U16 Reserved2
; /* 0x02 */
1292 U32 RegionOffset
; /* 0x04 */
1293 U32 RegionSize
; /* 0x08 */
1294 U32 Reserved3
; /* 0x0C */
1295 } MPI2_FLASH_REGION
, MPI2_POINTER PTR_MPI2_FLASH_REGION
,
1296 Mpi2FlashRegion_t
, MPI2_POINTER pMpi2FlashRegion_t
;
1298 typedef struct _MPI2_FLASH_LAYOUT
1300 U32 FlashSize
; /* 0x00 */
1301 U32 Reserved1
; /* 0x04 */
1302 U32 Reserved2
; /* 0x08 */
1303 U32 Reserved3
; /* 0x0C */
1304 MPI2_FLASH_REGION Region
[MPI2_FLASH_NUMBER_OF_REGIONS
];/* 0x10 */
1305 } MPI2_FLASH_LAYOUT
, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT
,
1306 Mpi2FlashLayout_t
, MPI2_POINTER pMpi2FlashLayout_t
;
1308 typedef struct _MPI2_FLASH_LAYOUT_DATA
1310 U8 ImageRevision
; /* 0x00 */
1311 U8 Reserved1
; /* 0x01 */
1312 U8 SizeOfRegion
; /* 0x02 */
1313 U8 Reserved2
; /* 0x03 */
1314 U16 NumberOfLayouts
; /* 0x04 */
1315 U16 RegionsPerLayout
; /* 0x06 */
1316 U16 MinimumSectorAlignment
; /* 0x08 */
1317 U16 Reserved3
; /* 0x0A */
1318 U32 Reserved4
; /* 0x0C */
1319 MPI2_FLASH_LAYOUT Layout
[MPI2_FLASH_NUMBER_OF_LAYOUTS
];/* 0x10 */
1320 } MPI2_FLASH_LAYOUT_DATA
, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA
,
1321 Mpi2FlashLayoutData_t
, MPI2_POINTER pMpi2FlashLayoutData_t
;
1323 /* defines for the RegionType field */
1324 #define MPI2_FLASH_REGION_UNUSED (0x00)
1325 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1326 #define MPI2_FLASH_REGION_BIOS (0x02)
1327 #define MPI2_FLASH_REGION_NVDATA (0x03)
1328 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1329 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1330 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1331 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1332 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1333 #define MPI2_FLASH_REGION_INIT (0x0A)
1336 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1340 /* Supported Devices Extended Image Data */
1343 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1344 * one and check NumberOfDevices at runtime.
1346 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1347 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1350 typedef struct _MPI2_SUPPORTED_DEVICE
1352 U16 DeviceID
; /* 0x00 */
1353 U16 VendorID
; /* 0x02 */
1354 U16 DeviceIDMask
; /* 0x04 */
1355 U16 Reserved1
; /* 0x06 */
1356 U8 LowPCIRev
; /* 0x08 */
1357 U8 HighPCIRev
; /* 0x09 */
1358 U16 Reserved2
; /* 0x0A */
1359 U32 Reserved3
; /* 0x0C */
1360 } MPI2_SUPPORTED_DEVICE
, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE
,
1361 Mpi2SupportedDevice_t
, MPI2_POINTER pMpi2SupportedDevice_t
;
1363 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1365 U8 ImageRevision
; /* 0x00 */
1366 U8 Reserved1
; /* 0x01 */
1367 U8 NumberOfDevices
; /* 0x02 */
1368 U8 Reserved2
; /* 0x03 */
1369 U32 Reserved3
; /* 0x04 */
1370 MPI2_SUPPORTED_DEVICE SupportedDevice
[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
]; /* 0x08 */
1371 } MPI2_SUPPORTED_DEVICES_DATA
, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA
,
1372 Mpi2SupportedDevicesData_t
, MPI2_POINTER pMpi2SupportedDevicesData_t
;
1375 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1378 /* Init Extended Image Data */
1380 typedef struct _MPI2_INIT_IMAGE_FOOTER
1383 U32 BootFlags
; /* 0x00 */
1384 U32 ImageSize
; /* 0x04 */
1385 U32 Signature0
; /* 0x08 */
1386 U32 Signature1
; /* 0x0C */
1387 U32 Signature2
; /* 0x10 */
1388 U32 ResetVector
; /* 0x14 */
1389 } MPI2_INIT_IMAGE_FOOTER
, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER
,
1390 Mpi2InitImageFooter_t
, MPI2_POINTER pMpi2InitImageFooter_t
;
1392 /* defines for the BootFlags field */
1393 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1395 /* defines for the ImageSize field */
1396 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1398 /* defines for the Signature0 field */
1399 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1400 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1402 /* defines for the Signature1 field */
1403 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1404 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1406 /* defines for the Signature2 field */
1407 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1408 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1410 /* Signature fields as individual bytes */
1411 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1412 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1413 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1414 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1416 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1418 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1419 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1421 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1423 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1424 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1426 /* defines for the ResetVector field */
1427 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1430 /****************************************************************************
1431 * PowerManagementControl message
1432 ****************************************************************************/
1434 /* PowerManagementControl Request message */
1435 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
{
1436 U8 Feature
; /* 0x00 */
1437 U8 Reserved1
; /* 0x01 */
1438 U8 ChainOffset
; /* 0x02 */
1439 U8 Function
; /* 0x03 */
1440 U16 Reserved2
; /* 0x04 */
1441 U8 Reserved3
; /* 0x06 */
1442 U8 MsgFlags
; /* 0x07 */
1443 U8 VP_ID
; /* 0x08 */
1444 U8 VF_ID
; /* 0x09 */
1445 U16 Reserved4
; /* 0x0A */
1446 U8 Parameter1
; /* 0x0C */
1447 U8 Parameter2
; /* 0x0D */
1448 U8 Parameter3
; /* 0x0E */
1449 U8 Parameter4
; /* 0x0F */
1450 U32 Reserved5
; /* 0x10 */
1451 U32 Reserved6
; /* 0x14 */
1452 } MPI2_PWR_MGMT_CONTROL_REQUEST
, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST
,
1453 Mpi2PwrMgmtControlRequest_t
, MPI2_POINTER pMpi2PwrMgmtControlRequest_t
;
1455 /* defines for the Feature field */
1456 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1457 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1458 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03)
1459 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1460 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1461 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1463 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1464 /* Parameter1 contains a PHY number */
1465 /* Parameter2 indicates power condition action using these defines */
1466 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1467 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1468 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1469 /* Parameter3 and Parameter4 are reserved */
1471 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1473 /* Parameter1 contains SAS port width modulation group number */
1474 /* Parameter2 indicates IOC action using these defines */
1475 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1476 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1477 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1478 /* Parameter3 indicates desired modulation level using these defines */
1479 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1480 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1481 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1482 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1483 /* Parameter4 is reserved */
1485 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1486 /* Parameter1 indicates desired PCIe link speed using these defines */
1487 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00)
1488 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01)
1489 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02)
1490 /* Parameter2 indicates desired PCIe link width using these defines */
1491 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01)
1492 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02)
1493 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04)
1494 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08)
1495 /* Parameter3 and Parameter4 are reserved */
1497 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1498 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1499 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1500 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1501 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1502 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1503 /* Parameter2, Parameter3, and Parameter4 are reserved */
1506 /* PowerManagementControl Reply message */
1507 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
{
1508 U8 Feature
; /* 0x00 */
1509 U8 Reserved1
; /* 0x01 */
1510 U8 MsgLength
; /* 0x02 */
1511 U8 Function
; /* 0x03 */
1512 U16 Reserved2
; /* 0x04 */
1513 U8 Reserved3
; /* 0x06 */
1514 U8 MsgFlags
; /* 0x07 */
1515 U8 VP_ID
; /* 0x08 */
1516 U8 VF_ID
; /* 0x09 */
1517 U16 Reserved4
; /* 0x0A */
1518 U16 Reserved5
; /* 0x0C */
1519 U16 IOCStatus
; /* 0x0E */
1520 U32 IOCLogInfo
; /* 0x10 */
1521 } MPI2_PWR_MGMT_CONTROL_REPLY
, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY
,
1522 Mpi2PwrMgmtControlReply_t
, MPI2_POINTER pMpi2PwrMgmtControlReply_t
;