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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / scsi / aic7xxx / aic7xxx_core.c
blob67bec2ed5de6411706bfe69b0268db051d1fb208
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
41 */
42
43 #ifdef __linux__
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
47 #else
48 #include <dev/aic7xxx/aic7xxx_osm.h>
49 #include <dev/aic7xxx/aic7xxx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
51 #endif
52
53 /***************************** Lookup Tables **********************************/
54 static const char *const ahc_chip_names[] = {
55 "NONE",
56 "aic7770",
57 "aic7850",
58 "aic7855",
59 "aic7859",
60 "aic7860",
61 "aic7870",
62 "aic7880",
63 "aic7895",
64 "aic7895C",
65 "aic7890/91",
66 "aic7896/97",
67 "aic7892",
68 "aic7899"
69 };
70 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
71
72 /*
73 * Hardware error codes.
74 */
75 struct ahc_hard_error_entry {
76 uint8_t errno;
77 const char *errmesg;
78 };
79
80 static const struct ahc_hard_error_entry ahc_hard_errors[] = {
81 { ILLHADDR, "Illegal Host Access" },
82 { ILLSADDR, "Illegal Sequencer Address referrenced" },
83 { ILLOPCODE, "Illegal Opcode in sequencer program" },
84 { SQPARERR, "Sequencer Parity Error" },
85 { DPARERR, "Data-path Parity Error" },
86 { MPARERR, "Scratch or SCB Memory Parity Error" },
87 { PCIERRSTAT, "PCI Error detected" },
88 { CIOPARERR, "CIOBUS Parity Error" },
89 };
90 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
91
92 static const struct ahc_phase_table_entry ahc_phase_table[] =
93 {
94 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
95 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
96 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
97 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
98 { P_COMMAND, MSG_NOOP, "in Command phase" },
99 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
100 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
101 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
102 { P_BUSFREE, MSG_NOOP, "while idle" },
103 { 0, MSG_NOOP, "in unknown phase" }
104 };
105
106 /*
107 * In most cases we only wish to itterate over real phases, so
108 * exclude the last element from the count.
109 */
110 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
111
112 /*
113 * Valid SCSIRATE values. (p. 3-17)
114 * Provides a mapping of tranfer periods in ns to the proper value to
115 * stick in the scsixfer reg.
116 */
117 static const struct ahc_syncrate ahc_syncrates[] =
118 {
119 /* ultra2 fast/ultra period rate */
120 { 0x42, 0x000, 9, "80.0" },
121 { 0x03, 0x000, 10, "40.0" },
122 { 0x04, 0x000, 11, "33.0" },
123 { 0x05, 0x100, 12, "20.0" },
124 { 0x06, 0x110, 15, "16.0" },
125 { 0x07, 0x120, 18, "13.4" },
126 { 0x08, 0x000, 25, "10.0" },
127 { 0x19, 0x010, 31, "8.0" },
128 { 0x1a, 0x020, 37, "6.67" },
129 { 0x1b, 0x030, 43, "5.7" },
130 { 0x1c, 0x040, 50, "5.0" },
131 { 0x00, 0x050, 56, "4.4" },
132 { 0x00, 0x060, 62, "4.0" },
133 { 0x00, 0x070, 68, "3.6" },
134 { 0x00, 0x000, 0, NULL }
135 };
136
137 /* Our Sequencer Program */
138 #include "aic7xxx_seq.h"
139
140 /**************************** Function Declarations ***************************/
141 static void ahc_force_renegotiation(struct ahc_softc *ahc,
142 struct ahc_devinfo *devinfo);
143 static struct ahc_tmode_tstate*
144 ahc_alloc_tstate(struct ahc_softc *ahc,
145 u_int scsi_id, char channel);
146 #ifdef AHC_TARGET_MODE
147 static void ahc_free_tstate(struct ahc_softc *ahc,
148 u_int scsi_id, char channel, int force);
149 #endif
150 static const struct ahc_syncrate*
151 ahc_devlimited_syncrate(struct ahc_softc *ahc,
152 struct ahc_initiator_tinfo *,
153 u_int *period,
154 u_int *ppr_options,
155 role_t role);
156 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
157 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
158 struct ahc_devinfo *devinfo);
159 static void ahc_scb_devinfo(struct ahc_softc *ahc,
160 struct ahc_devinfo *devinfo,
161 struct scb *scb);
162 static void ahc_assert_atn(struct ahc_softc *ahc);
163 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
164 struct ahc_devinfo *devinfo,
165 struct scb *scb);
166 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
167 struct ahc_devinfo *devinfo);
168 static void ahc_construct_sdtr(struct ahc_softc *ahc,
169 struct ahc_devinfo *devinfo,
170 u_int period, u_int offset);
171 static void ahc_construct_wdtr(struct ahc_softc *ahc,
172 struct ahc_devinfo *devinfo,
173 u_int bus_width);
174 static void ahc_construct_ppr(struct ahc_softc *ahc,
175 struct ahc_devinfo *devinfo,
176 u_int period, u_int offset,
177 u_int bus_width, u_int ppr_options);
178 static void ahc_clear_msg_state(struct ahc_softc *ahc);
179 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
180 static void ahc_handle_message_phase(struct ahc_softc *ahc);
181 typedef enum {
182 AHCMSG_1B,
183 AHCMSG_2B,
184 AHCMSG_EXT
185 } ahc_msgtype;
186 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
187 u_int msgval, int full);
188 static int ahc_parse_msg(struct ahc_softc *ahc,
189 struct ahc_devinfo *devinfo);
190 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
191 struct ahc_devinfo *devinfo);
192 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
193 struct ahc_devinfo *devinfo);
194 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
195 static void ahc_handle_devreset(struct ahc_softc *ahc,
196 struct ahc_devinfo *devinfo,
197 cam_status status, char *message,
198 int verbose_level);
199 #ifdef AHC_TARGET_MODE
200 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
201 struct ahc_devinfo *devinfo,
202 struct scb *scb);
203 #endif
204
205 static bus_dmamap_callback_t ahc_dmamap_cb;
206 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
207 static int ahc_init_scbdata(struct ahc_softc *ahc);
208 static void ahc_fini_scbdata(struct ahc_softc *ahc);
209 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
210 struct scb *prev_scb,
211 struct scb *scb);
212 static int ahc_qinfifo_count(struct ahc_softc *ahc);
213 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
214 u_int prev, u_int scbptr);
215 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
216 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
217 u_int scbpos, u_int prev);
218 static void ahc_reset_current_bus(struct ahc_softc *ahc);
219 #ifdef AHC_DUMP_SEQ
220 static void ahc_dumpseq(struct ahc_softc *ahc);
221 #endif
222 static int ahc_loadseq(struct ahc_softc *ahc);
223 static int ahc_check_patch(struct ahc_softc *ahc,
224 const struct patch **start_patch,
225 u_int start_instr, u_int *skip_addr);
226 static void ahc_download_instr(struct ahc_softc *ahc,
227 u_int instrptr, uint8_t *dconsts);
228 #ifdef AHC_TARGET_MODE
229 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
230 struct ahc_tmode_lstate *lstate,
231 u_int initiator_id,
232 u_int event_type,
233 u_int event_arg);
234 static void ahc_update_scsiid(struct ahc_softc *ahc,
235 u_int targid_mask);
236 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
237 struct target_cmd *cmd);
238 #endif
239
240 static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
241 static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
242 static void ahc_busy_tcl(struct ahc_softc *ahc,
243 u_int tcl, u_int busyid);
244
245 /************************** SCB and SCB queue management **********************/
246 static void ahc_run_untagged_queues(struct ahc_softc *ahc);
247 static void ahc_run_untagged_queue(struct ahc_softc *ahc,
248 struct scb_tailq *queue);
249
250 /****************************** Initialization ********************************/
251 static void ahc_alloc_scbs(struct ahc_softc *ahc);
252 static void ahc_shutdown(void *arg);
253
254 /*************************** Interrupt Services *******************************/
255 static void ahc_clear_intstat(struct ahc_softc *ahc);
256 static void ahc_run_qoutfifo(struct ahc_softc *ahc);
257 #ifdef AHC_TARGET_MODE
258 static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
259 #endif
260 static void ahc_handle_brkadrint(struct ahc_softc *ahc);
261 static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
262 static void ahc_handle_scsiint(struct ahc_softc *ahc,
263 u_int intstat);
264 static void ahc_clear_critical_section(struct ahc_softc *ahc);
265
266 /***************************** Error Recovery *********************************/
267 static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
268 static int ahc_abort_scbs(struct ahc_softc *ahc, int target,
269 char channel, int lun, u_int tag,
270 role_t role, uint32_t status);
271 static void ahc_calc_residual(struct ahc_softc *ahc,
272 struct scb *scb);
273
274 /*********************** Untagged Transaction Routines ************************/
275 static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
276 static inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
277
278 /*
279 * Block our completion routine from starting the next untagged
280 * transaction for this target or target lun.
281 */
282 static inline void
283 ahc_freeze_untagged_queues(struct ahc_softc *ahc)
284 {
285 if ((ahc->flags & AHC_SCB_BTT) == 0)
286 ahc->untagged_queue_lock++;
287 }
288
289 /*
290 * Allow the next untagged transaction for this target or target lun
291 * to be executed. We use a counting semaphore to allow the lock
292 * to be acquired recursively. Once the count drops to zero, the
293 * transaction queues will be run.
294 */
295 static inline void
296 ahc_release_untagged_queues(struct ahc_softc *ahc)
297 {
298 if ((ahc->flags & AHC_SCB_BTT) == 0) {
299 ahc->untagged_queue_lock--;
300 if (ahc->untagged_queue_lock == 0)
301 ahc_run_untagged_queues(ahc);
302 }
303 }
304
305 /************************* Sequencer Execution Control ************************/
306 static void
307 ahc_pause_bug_fix(struct ahc_softc *ahc)
308 {
309 if ((ahc->features & AHC_ULTRA2) != 0)
310 (void)ahc_inb(ahc, CCSCBCTL);
311 }
312
313 /*
314 * Determine whether the sequencer has halted code execution.
315 * Returns non-zero status if the sequencer is stopped.
316 */
317 int
318 ahc_is_paused(struct ahc_softc *ahc)
319 {
320 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
321 }
322
323 /*
324 * Request that the sequencer stop and wait, indefinitely, for it
325 * to stop. The sequencer will only acknowledge that it is paused
326 * once it has reached an instruction boundary and PAUSEDIS is
327 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
328 * for critical sections.
329 */
330 void
331 ahc_pause(struct ahc_softc *ahc)
332 {
333 ahc_outb(ahc, HCNTRL, ahc->pause);
334
335 /*
336 * Since the sequencer can disable pausing in a critical section, we
337 * must loop until it actually stops.
338 */
339 while (ahc_is_paused(ahc) == 0)
340 ;
341
342 ahc_pause_bug_fix(ahc);
343 }
344
345 /*
346 * Allow the sequencer to continue program execution.
347 * We check here to ensure that no additional interrupt
348 * sources that would cause the sequencer to halt have been
349 * asserted. If, for example, a SCSI bus reset is detected
350 * while we are fielding a different, pausing, interrupt type,
351 * we don't want to release the sequencer before going back
352 * into our interrupt handler and dealing with this new
353 * condition.
354 */
355 void
356 ahc_unpause(struct ahc_softc *ahc)
357 {
358 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
359 ahc_outb(ahc, HCNTRL, ahc->unpause);
360 }
361
362 /************************** Memory mapping routines ***************************/
363 static struct ahc_dma_seg *
364 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
365 {
366 int sg_index;
367
368 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
369 /* sg_list_phys points to entry 1, not 0 */
370 sg_index++;
371
372 return (&scb->sg_list[sg_index]);
373 }
374
375 static uint32_t
376 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
377 {
378 int sg_index;
379
380 /* sg_list_phys points to entry 1, not 0 */
381 sg_index = sg - &scb->sg_list[1];
382
383 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
384 }
385
386 static uint32_t
387 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
388 {
389 return (ahc->scb_data->hscb_busaddr
390 + (sizeof(struct hardware_scb) * index));
391 }
392
393 static void
394 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
395 {
396 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
397 ahc->scb_data->hscb_dmamap,
398 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
399 /*len*/sizeof(*scb->hscb), op);
400 }
401
402 void
403 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
404 {
405 if (scb->sg_count == 0)
406 return;
407
408 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
409 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
410 * sizeof(struct ahc_dma_seg),
411 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
412 }
413
414 #ifdef AHC_TARGET_MODE
415 static uint32_t
416 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
417 {
418 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
419 }
420 #endif
421
422 /*********************** Miscelaneous Support Functions ***********************/
423 /*
424 * Determine whether the sequencer reported a residual
425 * for this SCB/transaction.
426 */
427 static void
428 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
429 {
430 uint32_t sgptr;
431
432 sgptr = ahc_le32toh(scb->hscb->sgptr);
433 if ((sgptr & SG_RESID_VALID) != 0)
434 ahc_calc_residual(ahc, scb);
435 }
436
437 /*
438 * Return pointers to the transfer negotiation information
439 * for the specified our_id/remote_id pair.
440 */
441 struct ahc_initiator_tinfo *
442 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
443 u_int remote_id, struct ahc_tmode_tstate **tstate)
444 {
445 /*
446 * Transfer data structures are stored from the perspective
447 * of the target role. Since the parameters for a connection
448 * in the initiator role to a given target are the same as
449 * when the roles are reversed, we pretend we are the target.
450 */
451 if (channel == 'B')
452 our_id += 8;
453 *tstate = ahc->enabled_targets[our_id];
454 return (&(*tstate)->transinfo[remote_id]);
455 }
456
457 uint16_t
458 ahc_inw(struct ahc_softc *ahc, u_int port)
459 {
460 uint16_t r = ahc_inb(ahc, port+1) << 8;
461 return r | ahc_inb(ahc, port);
462 }
463
464 void
465 ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
466 {
467 ahc_outb(ahc, port, value & 0xFF);
468 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
469 }
470
471 uint32_t
472 ahc_inl(struct ahc_softc *ahc, u_int port)
473 {
474 return ((ahc_inb(ahc, port))
475 | (ahc_inb(ahc, port+1) << 8)
476 | (ahc_inb(ahc, port+2) << 16)
477 | (ahc_inb(ahc, port+3) << 24));
478 }
479
480 void
481 ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
482 {
483 ahc_outb(ahc, port, (value) & 0xFF);
484 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
485 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
486 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
487 }
488
489 uint64_t
490 ahc_inq(struct ahc_softc *ahc, u_int port)
491 {
492 return ((ahc_inb(ahc, port))
493 | (ahc_inb(ahc, port+1) << 8)
494 | (ahc_inb(ahc, port+2) << 16)
495 | (ahc_inb(ahc, port+3) << 24)
496 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
497 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
498 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
499 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
500 }
501
502 void
503 ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
504 {
505 ahc_outb(ahc, port, value & 0xFF);
506 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
507 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
508 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
509 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
510 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
511 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
512 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
513 }
514
515 /*
516 * Get a free scb. If there are none, see if we can allocate a new SCB.
517 */
518 struct scb *
519 ahc_get_scb(struct ahc_softc *ahc)
520 {
521 struct scb *scb;
522
523 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
524 ahc_alloc_scbs(ahc);
525 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
526 if (scb == NULL)
527 return (NULL);
528 }
529 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
530 return (scb);
531 }
532
533 /*
534 * Return an SCB resource to the free list.
535 */
536 void
537 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
538 {
539 struct hardware_scb *hscb;
540
541 hscb = scb->hscb;
542 /* Clean up for the next user */
543 ahc->scb_data->scbindex[hscb->tag] = NULL;
544 scb->flags = SCB_FREE;
545 hscb->control = 0;
546
547 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
548
549 /* Notify the OSM that a resource is now available. */
550 ahc_platform_scb_free(ahc, scb);
551 }
552
553 struct scb *
554 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
555 {
556 struct scb* scb;
557
558 scb = ahc->scb_data->scbindex[tag];
559 if (scb != NULL)
560 ahc_sync_scb(ahc, scb,
561 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
562 return (scb);
563 }
564
565 static void
566 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
567 {
568 struct hardware_scb *q_hscb;
569 u_int saved_tag;
570
571 /*
572 * Our queuing method is a bit tricky. The card
573 * knows in advance which HSCB to download, and we
574 * can't disappoint it. To achieve this, the next
575 * SCB to download is saved off in ahc->next_queued_scb.
576 * When we are called to queue "an arbitrary scb",
577 * we copy the contents of the incoming HSCB to the one
578 * the sequencer knows about, swap HSCB pointers and
579 * finally assign the SCB to the tag indexed location
580 * in the scb_array. This makes sure that we can still
581 * locate the correct SCB by SCB_TAG.
582 */
583 q_hscb = ahc->next_queued_scb->hscb;
584 saved_tag = q_hscb->tag;
585 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
586 if ((scb->flags & SCB_CDB32_PTR) != 0) {
587 q_hscb->shared_data.cdb_ptr =
588 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
589 + offsetof(struct hardware_scb, cdb32));
590 }
591 q_hscb->tag = saved_tag;
592 q_hscb->next = scb->hscb->tag;
593
594 /* Now swap HSCB pointers. */
595 ahc->next_queued_scb->hscb = scb->hscb;
596 scb->hscb = q_hscb;
597
598 /* Now define the mapping from tag to SCB in the scbindex */
599 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
600 }
601
602 /*
603 * Tell the sequencer about a new transaction to execute.
604 */
605 void
606 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
607 {
608 ahc_swap_with_next_hscb(ahc, scb);
609
610 if (scb->hscb->tag == SCB_LIST_NULL
611 || scb->hscb->next == SCB_LIST_NULL)
612 panic("Attempt to queue invalid SCB tag %x:%x\n",
613 scb->hscb->tag, scb->hscb->next);
614
615 /*
616 * Setup data "oddness".
617 */
618 scb->hscb->lun &= LID;
619 if (ahc_get_transfer_length(scb) & 0x1)
620 scb->hscb->lun |= SCB_XFERLEN_ODD;
621
622 /*
623 * Keep a history of SCBs we've downloaded in the qinfifo.
624 */
625 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
626
627 /*
628 * Make sure our data is consistent from the
629 * perspective of the adapter.
630 */
631 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
632
633 /* Tell the adapter about the newly queued SCB */
634 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
635 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
636 } else {
637 if ((ahc->features & AHC_AUTOPAUSE) == 0)
638 ahc_pause(ahc);
639 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
640 if ((ahc->features & AHC_AUTOPAUSE) == 0)
641 ahc_unpause(ahc);
642 }
643 }
644
645 struct scsi_sense_data *
646 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
647 {
648 int offset;
649
650 offset = scb - ahc->scb_data->scbarray;
651 return (&ahc->scb_data->sense[offset]);
652 }
653
654 static uint32_t
655 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
656 {
657 int offset;
658
659 offset = scb - ahc->scb_data->scbarray;
660 return (ahc->scb_data->sense_busaddr
661 + (offset * sizeof(struct scsi_sense_data)));
662 }
663
664 /************************** Interrupt Processing ******************************/
665 static void
666 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
667 {
668 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
669 /*offset*/0, /*len*/256, op);
670 }
671
672 static void
673 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
674 {
675 #ifdef AHC_TARGET_MODE
676 if ((ahc->flags & AHC_TARGETROLE) != 0) {
677 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
678 ahc->shared_data_dmamap,
679 ahc_targetcmd_offset(ahc, 0),
680 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
681 op);
682 }
683 #endif
684 }
685
686 /*
687 * See if the firmware has posted any completed commands
688 * into our in-core command complete fifos.
689 */
690 #define AHC_RUN_QOUTFIFO 0x1
691 #define AHC_RUN_TQINFIFO 0x2
692 static u_int
693 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
694 {
695 u_int retval;
696
697 retval = 0;
698 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
699 /*offset*/ahc->qoutfifonext, /*len*/1,
700 BUS_DMASYNC_POSTREAD);
701 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
702 retval |= AHC_RUN_QOUTFIFO;
703 #ifdef AHC_TARGET_MODE
704 if ((ahc->flags & AHC_TARGETROLE) != 0
705 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
706 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
707 ahc->shared_data_dmamap,
708 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
709 /*len*/sizeof(struct target_cmd),
710 BUS_DMASYNC_POSTREAD);
711 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
712 retval |= AHC_RUN_TQINFIFO;
713 }
714 #endif
715 return (retval);
716 }
717
718 /*
719 * Catch an interrupt from the adapter
720 */
721 int
722 ahc_intr(struct ahc_softc *ahc)
723 {
724 u_int intstat;
725
726 if ((ahc->pause & INTEN) == 0) {
727 /*
728 * Our interrupt is not enabled on the chip
729 * and may be disabled for re-entrancy reasons,
730 * so just return. This is likely just a shared
731 * interrupt.
732 */
733 return (0);
734 }
735 /*
736 * Instead of directly reading the interrupt status register,
737 * infer the cause of the interrupt by checking our in-core
738 * completion queues. This avoids a costly PCI bus read in
739 * most cases.
740 */
741 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
742 && (ahc_check_cmdcmpltqueues(ahc) != 0))
743 intstat = CMDCMPLT;
744 else {
745 intstat = ahc_inb(ahc, INTSTAT);
746 }
747
748 if ((intstat & INT_PEND) == 0) {
749 #if AHC_PCI_CONFIG > 0
750 if (ahc->unsolicited_ints > 500) {
751 ahc->unsolicited_ints = 0;
752 if ((ahc->chip & AHC_PCI) != 0
753 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
754 ahc->bus_intr(ahc);
755 }
756 #endif
757 ahc->unsolicited_ints++;
758 return (0);
759 }
760 ahc->unsolicited_ints = 0;
761
762 if (intstat & CMDCMPLT) {
763 ahc_outb(ahc, CLRINT, CLRCMDINT);
764
765 /*
766 * Ensure that the chip sees that we've cleared
767 * this interrupt before we walk the output fifo.
768 * Otherwise, we may, due to posted bus writes,
769 * clear the interrupt after we finish the scan,
770 * and after the sequencer has added new entries
771 * and asserted the interrupt again.
772 */
773 ahc_flush_device_writes(ahc);
774 ahc_run_qoutfifo(ahc);
775 #ifdef AHC_TARGET_MODE
776 if ((ahc->flags & AHC_TARGETROLE) != 0)
777 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
778 #endif
779 }
780
781 /*
782 * Handle statuses that may invalidate our cached
783 * copy of INTSTAT separately.
784 */
785 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
786 /* Hot eject. Do nothing */
787 } else if (intstat & BRKADRINT) {
788 ahc_handle_brkadrint(ahc);
789 } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
790
791 ahc_pause_bug_fix(ahc);
792
793 if ((intstat & SEQINT) != 0)
794 ahc_handle_seqint(ahc, intstat);
795
796 if ((intstat & SCSIINT) != 0)
797 ahc_handle_scsiint(ahc, intstat);
798 }
799 return (1);
800 }
801
802 /************************* Sequencer Execution Control ************************/
803 /*
804 * Restart the sequencer program from address zero
805 */
806 static void
807 ahc_restart(struct ahc_softc *ahc)
808 {
809 uint8_t sblkctl;
810
811 ahc_pause(ahc);
812
813 /* No more pending messages. */
814 ahc_clear_msg_state(ahc);
815
816 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
817 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
818 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
819 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
820 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
821 ahc_outb(ahc, SAVED_LUN, 0xFF);
822
823 /*
824 * Ensure that the sequencer's idea of TQINPOS
825 * matches our own. The sequencer increments TQINPOS
826 * only after it sees a DMA complete and a reset could
827 * occur before the increment leaving the kernel to believe
828 * the command arrived but the sequencer to not.
829 */
830 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
831
832 /* Always allow reselection */
833 ahc_outb(ahc, SCSISEQ,
834 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
835 if ((ahc->features & AHC_CMD_CHAN) != 0) {
836 /* Ensure that no DMA operations are in progress */
837 ahc_outb(ahc, CCSCBCNT, 0);
838 ahc_outb(ahc, CCSGCTL, 0);
839 ahc_outb(ahc, CCSCBCTL, 0);
840 }
841 /*
842 * If we were in the process of DMA'ing SCB data into
843 * an SCB, replace that SCB on the free list. This prevents
844 * an SCB leak.
845 */
846 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
847 ahc_add_curscb_to_free_list(ahc);
848 ahc_outb(ahc, SEQ_FLAGS2,
849 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
850 }
851
852 /*
853 * Clear any pending sequencer interrupt. It is no
854 * longer relevant since we're resetting the Program
855 * Counter.
856 */
857 ahc_outb(ahc, CLRINT, CLRSEQINT);
858
859 ahc_outb(ahc, MWI_RESIDUAL, 0);
860 ahc_outb(ahc, SEQCTL, ahc->seqctl);
861 ahc_outb(ahc, SEQADDR0, 0);
862 ahc_outb(ahc, SEQADDR1, 0);
863
864 /*
865 * Take the LED out of diagnostic mode on PM resume, too
866 */
867 sblkctl = ahc_inb(ahc, SBLKCTL);
868 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
869
870 ahc_unpause(ahc);
871 }
872
873 /************************* Input/Output Queues ********************************/
874 static void
875 ahc_run_qoutfifo(struct ahc_softc *ahc)
876 {
877 struct scb *scb;
878 u_int scb_index;
879
880 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
881 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
882
883 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
884 if ((ahc->qoutfifonext & 0x03) == 0x03) {
885 u_int modnext;
886
887 /*
888 * Clear 32bits of QOUTFIFO at a time
889 * so that we don't clobber an incoming
890 * byte DMA to the array on architectures
891 * that only support 32bit load and store
892 * operations.
893 */
894 modnext = ahc->qoutfifonext & ~0x3;
895 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
896 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
897 ahc->shared_data_dmamap,
898 /*offset*/modnext, /*len*/4,
899 BUS_DMASYNC_PREREAD);
900 }
901 ahc->qoutfifonext++;
902
903 scb = ahc_lookup_scb(ahc, scb_index);
904 if (scb == NULL) {
905 printk("%s: WARNING no command for scb %d "
906 "(cmdcmplt)\nQOUTPOS = %d\n",
907 ahc_name(ahc), scb_index,
908 (ahc->qoutfifonext - 1) & 0xFF);
909 continue;
910 }
911
912 /*
913 * Save off the residual
914 * if there is one.
915 */
916 ahc_update_residual(ahc, scb);
917 ahc_done(ahc, scb);
918 }
919 }
920
921 static void
922 ahc_run_untagged_queues(struct ahc_softc *ahc)
923 {
924 int i;
925
926 for (i = 0; i < 16; i++)
927 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
928 }
929
930 static void
931 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
932 {
933 struct scb *scb;
934
935 if (ahc->untagged_queue_lock != 0)
936 return;
937
938 if ((scb = TAILQ_FIRST(queue)) != NULL
939 && (scb->flags & SCB_ACTIVE) == 0) {
940 scb->flags |= SCB_ACTIVE;
941 ahc_queue_scb(ahc, scb);
942 }
943 }
944
945 /************************* Interrupt Handling *********************************/
946 static void
947 ahc_handle_brkadrint(struct ahc_softc *ahc)
948 {
949 /*
950 * We upset the sequencer :-(
951 * Lookup the error message
952 */
953 int i;
954 int error;
955
956 error = ahc_inb(ahc, ERROR);
957 for (i = 0; error != 1 && i < num_errors; i++)
958 error >>= 1;
959 printk("%s: brkadrint, %s at seqaddr = 0x%x\n",
960 ahc_name(ahc), ahc_hard_errors[i].errmesg,
961 ahc_inb(ahc, SEQADDR0) |
962 (ahc_inb(ahc, SEQADDR1) << 8));
963
964 ahc_dump_card_state(ahc);
965
966 /* Tell everyone that this HBA is no longer available */
967 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
968 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
969 CAM_NO_HBA);
970
971 /* Disable all interrupt sources by resetting the controller */
972 ahc_shutdown(ahc);
973 }
974
975 static void
976 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
977 {
978 struct scb *scb;
979 struct ahc_devinfo devinfo;
980
981 ahc_fetch_devinfo(ahc, &devinfo);
982
983 /*
984 * Clear the upper byte that holds SEQINT status
985 * codes and clear the SEQINT bit. We will unpause
986 * the sequencer, if appropriate, after servicing
987 * the request.
988 */
989 ahc_outb(ahc, CLRINT, CLRSEQINT);
990 switch (intstat & SEQINT_MASK) {
991 case BAD_STATUS:
992 {
993 u_int scb_index;
994 struct hardware_scb *hscb;
995
996 /*
997 * Set the default return value to 0 (don't
998 * send sense). The sense code will change
999 * this if needed.
1000 */
1001 ahc_outb(ahc, RETURN_1, 0);
1002
1003 /*
1004 * The sequencer will notify us when a command
1005 * has an error that would be of interest to
1006 * the kernel. This allows us to leave the sequencer
1007 * running in the common case of command completes
1008 * without error. The sequencer will already have
1009 * dma'd the SCB back up to us, so we can reference
1010 * the in kernel copy directly.
1011 */
1012 scb_index = ahc_inb(ahc, SCB_TAG);
1013 scb = ahc_lookup_scb(ahc, scb_index);
1014 if (scb == NULL) {
1015 ahc_print_devinfo(ahc, &devinfo);
1016 printk("ahc_intr - referenced scb "
1017 "not valid during seqint 0x%x scb(%d)\n",
1018 intstat, scb_index);
1019 ahc_dump_card_state(ahc);
1020 panic("for safety");
1021 goto unpause;
1022 }
1023
1024 hscb = scb->hscb;
1025
1026 /* Don't want to clobber the original sense code */
1027 if ((scb->flags & SCB_SENSE) != 0) {
1028 /*
1029 * Clear the SCB_SENSE Flag and have
1030 * the sequencer do a normal command
1031 * complete.
1032 */
1033 scb->flags &= ~SCB_SENSE;
1034 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1035 break;
1036 }
1037 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
1038 /* Freeze the queue until the client sees the error. */
1039 ahc_freeze_devq(ahc, scb);
1040 ahc_freeze_scb(scb);
1041 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
1042 switch (hscb->shared_data.status.scsi_status) {
1043 case SCSI_STATUS_OK:
1044 printk("%s: Interrupted for staus of 0???\n",
1045 ahc_name(ahc));
1046 break;
1047 case SCSI_STATUS_CMD_TERMINATED:
1048 case SCSI_STATUS_CHECK_COND:
1049 {
1050 struct ahc_dma_seg *sg;
1051 struct scsi_sense *sc;
1052 struct ahc_initiator_tinfo *targ_info;
1053 struct ahc_tmode_tstate *tstate;
1054 struct ahc_transinfo *tinfo;
1055 #ifdef AHC_DEBUG
1056 if (ahc_debug & AHC_SHOW_SENSE) {
1057 ahc_print_path(ahc, scb);
1058 printk("SCB %d: requests Check Status\n",
1059 scb->hscb->tag);
1060 }
1061 #endif
1062
1063 if (ahc_perform_autosense(scb) == 0)
1064 break;
1065
1066 targ_info = ahc_fetch_transinfo(ahc,
1067 devinfo.channel,
1068 devinfo.our_scsiid,
1069 devinfo.target,
1070 &tstate);
1071 tinfo = &targ_info->curr;
1072 sg = scb->sg_list;
1073 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
1074 /*
1075 * Save off the residual if there is one.
1076 */
1077 ahc_update_residual(ahc, scb);
1078 #ifdef AHC_DEBUG
1079 if (ahc_debug & AHC_SHOW_SENSE) {
1080 ahc_print_path(ahc, scb);
1081 printk("Sending Sense\n");
1082 }
1083 #endif
1084 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
1085 sg->len = ahc_get_sense_bufsize(ahc, scb);
1086 sg->len |= AHC_DMA_LAST_SEG;
1087
1088 /* Fixup byte order */
1089 sg->addr = ahc_htole32(sg->addr);
1090 sg->len = ahc_htole32(sg->len);
1091
1092 sc->opcode = REQUEST_SENSE;
1093 sc->byte2 = 0;
1094 if (tinfo->protocol_version <= SCSI_REV_2
1095 && SCB_GET_LUN(scb) < 8)
1096 sc->byte2 = SCB_GET_LUN(scb) << 5;
1097 sc->unused[0] = 0;
1098 sc->unused[1] = 0;
1099 sc->length = sg->len;
1100 sc->control = 0;
1101
1102 /*
1103 * We can't allow the target to disconnect.
1104 * This will be an untagged transaction and
1105 * having the target disconnect will make this
1106 * transaction indestinguishable from outstanding
1107 * tagged transactions.
1108 */
1109 hscb->control = 0;
1110
1111 /*
1112 * This request sense could be because the
1113 * the device lost power or in some other
1114 * way has lost our transfer negotiations.
1115 * Renegotiate if appropriate. Unit attention
1116 * errors will be reported before any data
1117 * phases occur.
1118 */
1119 if (ahc_get_residual(scb)
1120 == ahc_get_transfer_length(scb)) {
1121 ahc_update_neg_request(ahc, &devinfo,
1122 tstate, targ_info,
1123 AHC_NEG_IF_NON_ASYNC);
1124 }
1125 if (tstate->auto_negotiate & devinfo.target_mask) {
1126 hscb->control |= MK_MESSAGE;
1127 scb->flags &= ~SCB_NEGOTIATE;
1128 scb->flags |= SCB_AUTO_NEGOTIATE;
1129 }
1130 hscb->cdb_len = sizeof(*sc);
1131 hscb->dataptr = sg->addr;
1132 hscb->datacnt = sg->len;
1133 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
1134 hscb->sgptr = ahc_htole32(hscb->sgptr);
1135 scb->sg_count = 1;
1136 scb->flags |= SCB_SENSE;
1137 ahc_qinfifo_requeue_tail(ahc, scb);
1138 ahc_outb(ahc, RETURN_1, SEND_SENSE);
1139 /*
1140 * Ensure we have enough time to actually
1141 * retrieve the sense.
1142 */
1143 ahc_scb_timer_reset(scb, 5 * 1000000);
1144 break;
1145 }
1146 default:
1147 break;
1148 }
1149 break;
1150 }
1151 case NO_MATCH:
1152 {
1153 /* Ensure we don't leave the selection hardware on */
1154 ahc_outb(ahc, SCSISEQ,
1155 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1156
1157 printk("%s:%c:%d: no active SCB for reconnecting "
1158 "target - issuing BUS DEVICE RESET\n",
1159 ahc_name(ahc), devinfo.channel, devinfo.target);
1160 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1161 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1162 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1163 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1164 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1165 "SINDEX == 0x%x\n",
1166 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1167 ahc_index_busy_tcl(ahc,
1168 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1169 ahc_inb(ahc, SAVED_LUN))),
1170 ahc_inb(ahc, SINDEX));
1171 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1172 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1173 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1174 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1175 ahc_inb(ahc, SCB_CONTROL));
1176 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1177 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1178 printk("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
1179 printk("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
1180 ahc_dump_card_state(ahc);
1181 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
1182 ahc->msgout_len = 1;
1183 ahc->msgout_index = 0;
1184 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1185 ahc_outb(ahc, MSG_OUT, HOST_MSG);
1186 ahc_assert_atn(ahc);
1187 break;
1188 }
1189 case SEND_REJECT:
1190 {
1191 u_int rejbyte = ahc_inb(ahc, ACCUM);
1192 printk("%s:%c:%d: Warning - unknown message received from "
1193 "target (0x%x). Rejecting\n",
1194 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
1195 break;
1196 }
1197 case PROTO_VIOLATION:
1198 {
1199 ahc_handle_proto_violation(ahc);
1200 break;
1201 }
1202 case IGN_WIDE_RES:
1203 ahc_handle_ign_wide_residue(ahc, &devinfo);
1204 break;
1205 case PDATA_REINIT:
1206 ahc_reinitialize_dataptrs(ahc);
1207 break;
1208 case BAD_PHASE:
1209 {
1210 u_int lastphase;
1211
1212 lastphase = ahc_inb(ahc, LASTPHASE);
1213 printk("%s:%c:%d: unknown scsi bus phase %x, "
1214 "lastphase = 0x%x. Attempting to continue\n",
1215 ahc_name(ahc), devinfo.channel, devinfo.target,
1216 lastphase, ahc_inb(ahc, SCSISIGI));
1217 break;
1218 }
1219 case MISSED_BUSFREE:
1220 {
1221 u_int lastphase;
1222
1223 lastphase = ahc_inb(ahc, LASTPHASE);
1224 printk("%s:%c:%d: Missed busfree. "
1225 "Lastphase = 0x%x, Curphase = 0x%x\n",
1226 ahc_name(ahc), devinfo.channel, devinfo.target,
1227 lastphase, ahc_inb(ahc, SCSISIGI));
1228 ahc_restart(ahc);
1229 return;
1230 }
1231 case HOST_MSG_LOOP:
1232 {
1233 /*
1234 * The sequencer has encountered a message phase
1235 * that requires host assistance for completion.
1236 * While handling the message phase(s), we will be
1237 * notified by the sequencer after each byte is
1238 * transfered so we can track bus phase changes.
1239 *
1240 * If this is the first time we've seen a HOST_MSG_LOOP
1241 * interrupt, initialize the state of the host message
1242 * loop.
1243 */
1244 if (ahc->msg_type == MSG_TYPE_NONE) {
1245 struct scb *scb;
1246 u_int scb_index;
1247 u_int bus_phase;
1248
1249 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1250 if (bus_phase != P_MESGIN
1251 && bus_phase != P_MESGOUT) {
1252 printk("ahc_intr: HOST_MSG_LOOP bad "
1253 "phase 0x%x\n",
1254 bus_phase);
1255 /*
1256 * Probably transitioned to bus free before
1257 * we got here. Just punt the message.
1258 */
1259 ahc_clear_intstat(ahc);
1260 ahc_restart(ahc);
1261 return;
1262 }
1263
1264 scb_index = ahc_inb(ahc, SCB_TAG);
1265 scb = ahc_lookup_scb(ahc, scb_index);
1266 if (devinfo.role == ROLE_INITIATOR) {
1267 if (bus_phase == P_MESGOUT) {
1268 if (scb == NULL)
1269 panic("HOST_MSG_LOOP with "
1270 "invalid SCB %x\n",
1271 scb_index);
1272
1273 ahc_setup_initiator_msgout(ahc,
1274 &devinfo,
1275 scb);
1276 } else {
1277 ahc->msg_type =
1278 MSG_TYPE_INITIATOR_MSGIN;
1279 ahc->msgin_index = 0;
1280 }
1281 }
1282 #ifdef AHC_TARGET_MODE
1283 else {
1284 if (bus_phase == P_MESGOUT) {
1285 ahc->msg_type =
1286 MSG_TYPE_TARGET_MSGOUT;
1287 ahc->msgin_index = 0;
1288 }
1289 else
1290 ahc_setup_target_msgin(ahc,
1291 &devinfo,
1292 scb);
1293 }
1294 #endif
1295 }
1296
1297 ahc_handle_message_phase(ahc);
1298 break;
1299 }
1300 case PERR_DETECTED:
1301 {
1302 /*
1303 * If we've cleared the parity error interrupt
1304 * but the sequencer still believes that SCSIPERR
1305 * is true, it must be that the parity error is
1306 * for the currently presented byte on the bus,
1307 * and we are not in a phase (data-in) where we will
1308 * eventually ack this byte. Ack the byte and
1309 * throw it away in the hope that the target will
1310 * take us to message out to deliver the appropriate
1311 * error message.
1312 */
1313 if ((intstat & SCSIINT) == 0
1314 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
1315
1316 if ((ahc->features & AHC_DT) == 0) {
1317 u_int curphase;
1318
1319 /*
1320 * The hardware will only let you ack bytes
1321 * if the expected phase in SCSISIGO matches
1322 * the current phase. Make sure this is
1323 * currently the case.
1324 */
1325 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1326 ahc_outb(ahc, LASTPHASE, curphase);
1327 ahc_outb(ahc, SCSISIGO, curphase);
1328 }
1329 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
1330 int wait;
1331
1332 /*
1333 * In a data phase. Faster to bitbucket
1334 * the data than to individually ack each
1335 * byte. This is also the only strategy
1336 * that will work with AUTOACK enabled.
1337 */
1338 ahc_outb(ahc, SXFRCTL1,
1339 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
1340 wait = 5000;
1341 while (--wait != 0) {
1342 if ((ahc_inb(ahc, SCSISIGI)
1343 & (CDI|MSGI)) != 0)
1344 break;
1345 ahc_delay(100);
1346 }
1347 ahc_outb(ahc, SXFRCTL1,
1348 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
1349 if (wait == 0) {
1350 struct scb *scb;
1351 u_int scb_index;
1352
1353 ahc_print_devinfo(ahc, &devinfo);
1354 printk("Unable to clear parity error. "
1355 "Resetting bus.\n");
1356 scb_index = ahc_inb(ahc, SCB_TAG);
1357 scb = ahc_lookup_scb(ahc, scb_index);
1358 if (scb != NULL)
1359 ahc_set_transaction_status(scb,
1360 CAM_UNCOR_PARITY);
1361 ahc_reset_channel(ahc, devinfo.channel,
1362 /*init reset*/TRUE);
1363 }
1364 } else {
1365 ahc_inb(ahc, SCSIDATL);
1366 }
1367 }
1368 break;
1369 }
1370 case DATA_OVERRUN:
1371 {
1372 /*
1373 * When the sequencer detects an overrun, it
1374 * places the controller in "BITBUCKET" mode
1375 * and allows the target to complete its transfer.
1376 * Unfortunately, none of the counters get updated
1377 * when the controller is in this mode, so we have
1378 * no way of knowing how large the overrun was.
1379 */
1380 u_int scbindex = ahc_inb(ahc, SCB_TAG);
1381 u_int lastphase = ahc_inb(ahc, LASTPHASE);
1382 u_int i;
1383
1384 scb = ahc_lookup_scb(ahc, scbindex);
1385 for (i = 0; i < num_phases; i++) {
1386 if (lastphase == ahc_phase_table[i].phase)
1387 break;
1388 }
1389 ahc_print_path(ahc, scb);
1390 printk("data overrun detected %s."
1391 " Tag == 0x%x.\n",
1392 ahc_phase_table[i].phasemsg,
1393 scb->hscb->tag);
1394 ahc_print_path(ahc, scb);
1395 printk("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
1396 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
1397 ahc_get_transfer_length(scb), scb->sg_count);
1398 if (scb->sg_count > 0) {
1399 for (i = 0; i < scb->sg_count; i++) {
1400
1401 printk("sg[%d] - Addr 0x%x%x : Length %d\n",
1402 i,
1403 (ahc_le32toh(scb->sg_list[i].len) >> 24
1404 & SG_HIGH_ADDR_BITS),
1405 ahc_le32toh(scb->sg_list[i].addr),
1406 ahc_le32toh(scb->sg_list[i].len)
1407 & AHC_SG_LEN_MASK);
1408 }
1409 }
1410 /*
1411 * Set this and it will take effect when the
1412 * target does a command complete.
1413 */
1414 ahc_freeze_devq(ahc, scb);
1415 if ((scb->flags & SCB_SENSE) == 0) {
1416 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1417 } else {
1418 scb->flags &= ~SCB_SENSE;
1419 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1420 }
1421 ahc_freeze_scb(scb);
1422
1423 if ((ahc->features & AHC_ULTRA2) != 0) {
1424 /*
1425 * Clear the channel in case we return
1426 * to data phase later.
1427 */
1428 ahc_outb(ahc, SXFRCTL0,
1429 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1430 ahc_outb(ahc, SXFRCTL0,
1431 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1432 }
1433 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1434 u_int dscommand1;
1435
1436 /* Ensure HHADDR is 0 for future DMA operations. */
1437 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
1438 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
1439 ahc_outb(ahc, HADDR, 0);
1440 ahc_outb(ahc, DSCOMMAND1, dscommand1);
1441 }
1442 break;
1443 }
1444 case MKMSG_FAILED:
1445 {
1446 u_int scbindex;
1447
1448 printk("%s:%c:%d:%d: Attempt to issue message failed\n",
1449 ahc_name(ahc), devinfo.channel, devinfo.target,
1450 devinfo.lun);
1451 scbindex = ahc_inb(ahc, SCB_TAG);
1452 scb = ahc_lookup_scb(ahc, scbindex);
1453 if (scb != NULL
1454 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1455 /*
1456 * Ensure that we didn't put a second instance of this
1457 * SCB into the QINFIFO.
1458 */
1459 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
1460 SCB_GET_CHANNEL(ahc, scb),
1461 SCB_GET_LUN(scb), scb->hscb->tag,
1462 ROLE_INITIATOR, /*status*/0,
1463 SEARCH_REMOVE);
1464 break;
1465 }
1466 case NO_FREE_SCB:
1467 {
1468 printk("%s: No free or disconnected SCBs\n", ahc_name(ahc));
1469 ahc_dump_card_state(ahc);
1470 panic("for safety");
1471 break;
1472 }
1473 case SCB_MISMATCH:
1474 {
1475 u_int scbptr;
1476
1477 scbptr = ahc_inb(ahc, SCBPTR);
1478 printk("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
1479 scbptr, ahc_inb(ahc, ARG_1),
1480 ahc->scb_data->hscbs[scbptr].tag);
1481 ahc_dump_card_state(ahc);
1482 panic("for saftey");
1483 break;
1484 }
1485 case OUT_OF_RANGE:
1486 {
1487 printk("%s: BTT calculation out of range\n", ahc_name(ahc));
1488 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1489 "ARG_1 == 0x%x ACCUM = 0x%x\n",
1490 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1491 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1492 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1493 "SINDEX == 0x%x\n, A == 0x%x\n",
1494 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1495 ahc_index_busy_tcl(ahc,
1496 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1497 ahc_inb(ahc, SAVED_LUN))),
1498 ahc_inb(ahc, SINDEX),
1499 ahc_inb(ahc, ACCUM));
1500 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1501 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1502 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1503 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1504 ahc_inb(ahc, SCB_CONTROL));
1505 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1506 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1507 ahc_dump_card_state(ahc);
1508 panic("for safety");
1509 break;
1510 }
1511 default:
1512 printk("ahc_intr: seqint, "
1513 "intstat == 0x%x, scsisigi = 0x%x\n",
1514 intstat, ahc_inb(ahc, SCSISIGI));
1515 break;
1516 }
1517 unpause:
1518 /*
1519 * The sequencer is paused immediately on
1520 * a SEQINT, so we should restart it when
1521 * we're done.
1522 */
1523 ahc_unpause(ahc);
1524 }
1525
1526 static void
1527 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
1528 {
1529 u_int scb_index;
1530 u_int status0;
1531 u_int status;
1532 struct scb *scb;
1533 char cur_channel;
1534 char intr_channel;
1535
1536 if ((ahc->features & AHC_TWIN) != 0
1537 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
1538 cur_channel = 'B';
1539 else
1540 cur_channel = 'A';
1541 intr_channel = cur_channel;
1542
1543 if ((ahc->features & AHC_ULTRA2) != 0)
1544 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
1545 else
1546 status0 = 0;
1547 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1548 if (status == 0 && status0 == 0) {
1549 if ((ahc->features & AHC_TWIN) != 0) {
1550 /* Try the other channel */
1551 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1552 status = ahc_inb(ahc, SSTAT1)
1553 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1554 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1555 }
1556 if (status == 0) {
1557 printk("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1558 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1559 ahc_unpause(ahc);
1560 return;
1561 }
1562 }
1563
1564 /* Make sure the sequencer is in a safe location. */
1565 ahc_clear_critical_section(ahc);
1566
1567 scb_index = ahc_inb(ahc, SCB_TAG);
1568 scb = ahc_lookup_scb(ahc, scb_index);
1569 if (scb != NULL
1570 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1571 scb = NULL;
1572
1573 if ((ahc->features & AHC_ULTRA2) != 0
1574 && (status0 & IOERR) != 0) {
1575 int now_lvd;
1576
1577 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1578 printk("%s: Transceiver State Has Changed to %s mode\n",
1579 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1580 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1581 /*
1582 * When transitioning to SE mode, the reset line
1583 * glitches, triggering an arbitration bug in some
1584 * Ultra2 controllers. This bug is cleared when we
1585 * assert the reset line. Since a reset glitch has
1586 * already occurred with this transition and a
1587 * transceiver state change is handled just like
1588 * a bus reset anyway, asserting the reset line
1589 * ourselves is safe.
1590 */
1591 ahc_reset_channel(ahc, intr_channel,
1592 /*Initiate Reset*/now_lvd == 0);
1593 } else if ((status & SCSIRSTI) != 0) {
1594 printk("%s: Someone reset channel %c\n",
1595 ahc_name(ahc), intr_channel);
1596 if (intr_channel != cur_channel)
1597 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1598 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1599 } else if ((status & SCSIPERR) != 0) {
1600 /*
1601 * Determine the bus phase and queue an appropriate message.
1602 * SCSIPERR is latched true as soon as a parity error
1603 * occurs. If the sequencer acked the transfer that
1604 * caused the parity error and the currently presented
1605 * transfer on the bus has correct parity, SCSIPERR will
1606 * be cleared by CLRSCSIPERR. Use this to determine if
1607 * we should look at the last phase the sequencer recorded,
1608 * or the current phase presented on the bus.
1609 */
1610 struct ahc_devinfo devinfo;
1611 u_int mesg_out;
1612 u_int curphase;
1613 u_int errorphase;
1614 u_int lastphase;
1615 u_int scsirate;
1616 u_int i;
1617 u_int sstat2;
1618 int silent;
1619
1620 lastphase = ahc_inb(ahc, LASTPHASE);
1621 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1622 sstat2 = ahc_inb(ahc, SSTAT2);
1623 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1624 /*
1625 * For all phases save DATA, the sequencer won't
1626 * automatically ack a byte that has a parity error
1627 * in it. So the only way that the current phase
1628 * could be 'data-in' is if the parity error is for
1629 * an already acked byte in the data phase. During
1630 * synchronous data-in transfers, we may actually
1631 * ack bytes before latching the current phase in
1632 * LASTPHASE, leading to the discrepancy between
1633 * curphase and lastphase.
1634 */
1635 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1636 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1637 errorphase = curphase;
1638 else
1639 errorphase = lastphase;
1640
1641 for (i = 0; i < num_phases; i++) {
1642 if (errorphase == ahc_phase_table[i].phase)
1643 break;
1644 }
1645 mesg_out = ahc_phase_table[i].mesg_out;
1646 silent = FALSE;
1647 if (scb != NULL) {
1648 if (SCB_IS_SILENT(scb))
1649 silent = TRUE;
1650 else
1651 ahc_print_path(ahc, scb);
1652 scb->flags |= SCB_TRANSMISSION_ERROR;
1653 } else
1654 printk("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1655 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1656 scsirate = ahc_inb(ahc, SCSIRATE);
1657 if (silent == FALSE) {
1658 printk("parity error detected %s. "
1659 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1660 ahc_phase_table[i].phasemsg,
1661 ahc_inw(ahc, SEQADDR0),
1662 scsirate);
1663 if ((ahc->features & AHC_DT) != 0) {
1664 if ((sstat2 & CRCVALERR) != 0)
1665 printk("\tCRC Value Mismatch\n");
1666 if ((sstat2 & CRCENDERR) != 0)
1667 printk("\tNo terminal CRC packet "
1668 "recevied\n");
1669 if ((sstat2 & CRCREQERR) != 0)
1670 printk("\tIllegal CRC packet "
1671 "request\n");
1672 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1673 printk("\tUnexpected %sDT Data Phase\n",
1674 (scsirate & SINGLE_EDGE)
1675 ? "" : "non-");
1676 }
1677 }
1678
1679 if ((ahc->features & AHC_DT) != 0
1680 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1681 /*
1682 * This error applies regardless of
1683 * data direction, so ignore the value
1684 * in the phase table.
1685 */
1686 mesg_out = MSG_INITIATOR_DET_ERR;
1687 }
1688
1689 /*
1690 * We've set the hardware to assert ATN if we
1691 * get a parity error on "in" phases, so all we
1692 * need to do is stuff the message buffer with
1693 * the appropriate message. "In" phases have set
1694 * mesg_out to something other than MSG_NOP.
1695 */
1696 if (mesg_out != MSG_NOOP) {
1697 if (ahc->msg_type != MSG_TYPE_NONE)
1698 ahc->send_msg_perror = TRUE;
1699 else
1700 ahc_outb(ahc, MSG_OUT, mesg_out);
1701 }
1702 /*
1703 * Force a renegotiation with this target just in
1704 * case we are out of sync for some external reason
1705 * unknown (or unreported) by the target.
1706 */
1707 ahc_fetch_devinfo(ahc, &devinfo);
1708 ahc_force_renegotiation(ahc, &devinfo);
1709
1710 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1711 ahc_unpause(ahc);
1712 } else if ((status & SELTO) != 0) {
1713 u_int scbptr;
1714
1715 /* Stop the selection */
1716 ahc_outb(ahc, SCSISEQ, 0);
1717
1718 /* No more pending messages */
1719 ahc_clear_msg_state(ahc);
1720
1721 /* Clear interrupt state */
1722 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1723 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1724
1725 /*
1726 * Although the driver does not care about the
1727 * 'Selection in Progress' status bit, the busy
1728 * LED does. SELINGO is only cleared by a successfull
1729 * selection, so we must manually clear it to insure
1730 * the LED turns off just incase no future successful
1731 * selections occur (e.g. no devices on the bus).
1732 */
1733 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1734
1735 scbptr = ahc_inb(ahc, WAITING_SCBH);
1736 ahc_outb(ahc, SCBPTR, scbptr);
1737 scb_index = ahc_inb(ahc, SCB_TAG);
1738
1739 scb = ahc_lookup_scb(ahc, scb_index);
1740 if (scb == NULL) {
1741 printk("%s: ahc_intr - referenced scb not "
1742 "valid during SELTO scb(%d, %d)\n",
1743 ahc_name(ahc), scbptr, scb_index);
1744 ahc_dump_card_state(ahc);
1745 } else {
1746 struct ahc_devinfo devinfo;
1747 #ifdef AHC_DEBUG
1748 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1749 ahc_print_path(ahc, scb);
1750 printk("Saw Selection Timeout for SCB 0x%x\n",
1751 scb_index);
1752 }
1753 #endif
1754 ahc_scb_devinfo(ahc, &devinfo, scb);
1755 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1756 ahc_freeze_devq(ahc, scb);
1757
1758 /*
1759 * Cancel any pending transactions on the device
1760 * now that it seems to be missing. This will
1761 * also revert us to async/narrow transfers until
1762 * we can renegotiate with the device.
1763 */
1764 ahc_handle_devreset(ahc, &devinfo,
1765 CAM_SEL_TIMEOUT,
1766 "Selection Timeout",
1767 /*verbose_level*/1);
1768 }
1769 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1770 ahc_restart(ahc);
1771 } else if ((status & BUSFREE) != 0
1772 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1773 struct ahc_devinfo devinfo;
1774 u_int lastphase;
1775 u_int saved_scsiid;
1776 u_int saved_lun;
1777 u_int target;
1778 u_int initiator_role_id;
1779 char channel;
1780 int printerror;
1781
1782 /*
1783 * Clear our selection hardware as soon as possible.
1784 * We may have an entry in the waiting Q for this target,
1785 * that is affected by this busfree and we don't want to
1786 * go about selecting the target while we handle the event.
1787 */
1788 ahc_outb(ahc, SCSISEQ,
1789 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1790
1791 /*
1792 * Disable busfree interrupts and clear the busfree
1793 * interrupt status. We do this here so that several
1794 * bus transactions occur prior to clearing the SCSIINT
1795 * latch. It can take a bit for the clearing to take effect.
1796 */
1797 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1798 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1799
1800 /*
1801 * Look at what phase we were last in.
1802 * If its message out, chances are pretty good
1803 * that the busfree was in response to one of
1804 * our abort requests.
1805 */
1806 lastphase = ahc_inb(ahc, LASTPHASE);
1807 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1808 saved_lun = ahc_inb(ahc, SAVED_LUN);
1809 target = SCSIID_TARGET(ahc, saved_scsiid);
1810 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1811 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1812 ahc_compile_devinfo(&devinfo, initiator_role_id,
1813 target, saved_lun, channel, ROLE_INITIATOR);
1814 printerror = 1;
1815
1816 if (lastphase == P_MESGOUT) {
1817 u_int tag;
1818
1819 tag = SCB_LIST_NULL;
1820 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1821 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1822 if (ahc->msgout_buf[ahc->msgout_index - 1]
1823 == MSG_ABORT_TAG)
1824 tag = scb->hscb->tag;
1825 ahc_print_path(ahc, scb);
1826 printk("SCB %d - Abort%s Completed.\n",
1827 scb->hscb->tag, tag == SCB_LIST_NULL ?
1828 "" : " Tag");
1829 ahc_abort_scbs(ahc, target, channel,
1830 saved_lun, tag,
1831 ROLE_INITIATOR,
1832 CAM_REQ_ABORTED);
1833 printerror = 0;
1834 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1835 MSG_BUS_DEV_RESET, TRUE)) {
1836 #ifdef __FreeBSD__
1837 /*
1838 * Don't mark the user's request for this BDR
1839 * as completing with CAM_BDR_SENT. CAM3
1840 * specifies CAM_REQ_CMP.
1841 */
1842 if (scb != NULL
1843 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1844 && ahc_match_scb(ahc, scb, target, channel,
1845 CAM_LUN_WILDCARD,
1846 SCB_LIST_NULL,
1847 ROLE_INITIATOR)) {
1848 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1849 }
1850 #endif
1851 ahc_compile_devinfo(&devinfo,
1852 initiator_role_id,
1853 target,
1854 CAM_LUN_WILDCARD,
1855 channel,
1856 ROLE_INITIATOR);
1857 ahc_handle_devreset(ahc, &devinfo,
1858 CAM_BDR_SENT,
1859 "Bus Device Reset",
1860 /*verbose_level*/0);
1861 printerror = 0;
1862 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1863 MSG_EXT_PPR, FALSE)) {
1864 struct ahc_initiator_tinfo *tinfo;
1865 struct ahc_tmode_tstate *tstate;
1866
1867 /*
1868 * PPR Rejected. Try non-ppr negotiation
1869 * and retry command.
1870 */
1871 tinfo = ahc_fetch_transinfo(ahc,
1872 devinfo.channel,
1873 devinfo.our_scsiid,
1874 devinfo.target,
1875 &tstate);
1876 tinfo->curr.transport_version = 2;
1877 tinfo->goal.transport_version = 2;
1878 tinfo->goal.ppr_options = 0;
1879 ahc_qinfifo_requeue_tail(ahc, scb);
1880 printerror = 0;
1881 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1882 MSG_EXT_WDTR, FALSE)) {
1883 /*
1884 * Negotiation Rejected. Go-narrow and
1885 * retry command.
1886 */
1887 ahc_set_width(ahc, &devinfo,
1888 MSG_EXT_WDTR_BUS_8_BIT,
1889 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1890 /*paused*/TRUE);
1891 ahc_qinfifo_requeue_tail(ahc, scb);
1892 printerror = 0;
1893 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1894 MSG_EXT_SDTR, FALSE)) {
1895 /*
1896 * Negotiation Rejected. Go-async and
1897 * retry command.
1898 */
1899 ahc_set_syncrate(ahc, &devinfo,
1900 /*syncrate*/NULL,
1901 /*period*/0, /*offset*/0,
1902 /*ppr_options*/0,
1903 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1904 /*paused*/TRUE);
1905 ahc_qinfifo_requeue_tail(ahc, scb);
1906 printerror = 0;
1907 }
1908 }
1909 if (printerror != 0) {
1910 u_int i;
1911
1912 if (scb != NULL) {
1913 u_int tag;
1914
1915 if ((scb->hscb->control & TAG_ENB) != 0)
1916 tag = scb->hscb->tag;
1917 else
1918 tag = SCB_LIST_NULL;
1919 ahc_print_path(ahc, scb);
1920 ahc_abort_scbs(ahc, target, channel,
1921 SCB_GET_LUN(scb), tag,
1922 ROLE_INITIATOR,
1923 CAM_UNEXP_BUSFREE);
1924 } else {
1925 /*
1926 * We had not fully identified this connection,
1927 * so we cannot abort anything.
1928 */
1929 printk("%s: ", ahc_name(ahc));
1930 }
1931 for (i = 0; i < num_phases; i++) {
1932 if (lastphase == ahc_phase_table[i].phase)
1933 break;
1934 }
1935 if (lastphase != P_BUSFREE) {
1936 /*
1937 * Renegotiate with this device at the
1938 * next oportunity just in case this busfree
1939 * is due to a negotiation mismatch with the
1940 * device.
1941 */
1942 ahc_force_renegotiation(ahc, &devinfo);
1943 }
1944 printk("Unexpected busfree %s\n"
1945 "SEQADDR == 0x%x\n",
1946 ahc_phase_table[i].phasemsg,
1947 ahc_inb(ahc, SEQADDR0)
1948 | (ahc_inb(ahc, SEQADDR1) << 8));
1949 }
1950 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1951 ahc_restart(ahc);
1952 } else {
1953 printk("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1954 ahc_name(ahc), status);
1955 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1956 }
1957 }
1958
1959 /*
1960 * Force renegotiation to occur the next time we initiate
1961 * a command to the current device.
1962 */
1963 static void
1964 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1965 {
1966 struct ahc_initiator_tinfo *targ_info;
1967 struct ahc_tmode_tstate *tstate;
1968
1969 targ_info = ahc_fetch_transinfo(ahc,
1970 devinfo->channel,
1971 devinfo->our_scsiid,
1972 devinfo->target,
1973 &tstate);
1974 ahc_update_neg_request(ahc, devinfo, tstate,
1975 targ_info, AHC_NEG_IF_NON_ASYNC);
1976 }
1977
1978 #define AHC_MAX_STEPS 2000
1979 static void
1980 ahc_clear_critical_section(struct ahc_softc *ahc)
1981 {
1982 int stepping;
1983 int steps;
1984 u_int simode0;
1985 u_int simode1;
1986
1987 if (ahc->num_critical_sections == 0)
1988 return;
1989
1990 stepping = FALSE;
1991 steps = 0;
1992 simode0 = 0;
1993 simode1 = 0;
1994 for (;;) {
1995 struct cs *cs;
1996 u_int seqaddr;
1997 u_int i;
1998
1999 seqaddr = ahc_inb(ahc, SEQADDR0)
2000 | (ahc_inb(ahc, SEQADDR1) << 8);
2001
2002 /*
2003 * Seqaddr represents the next instruction to execute,
2004 * so we are really executing the instruction just
2005 * before it.
2006 */
2007 if (seqaddr != 0)
2008 seqaddr -= 1;
2009 cs = ahc->critical_sections;
2010 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
2011
2012 if (cs->begin < seqaddr && cs->end >= seqaddr)
2013 break;
2014 }
2015
2016 if (i == ahc->num_critical_sections)
2017 break;
2018
2019 if (steps > AHC_MAX_STEPS) {
2020 printk("%s: Infinite loop in critical section\n",
2021 ahc_name(ahc));
2022 ahc_dump_card_state(ahc);
2023 panic("critical section loop");
2024 }
2025
2026 steps++;
2027 if (stepping == FALSE) {
2028
2029 /*
2030 * Disable all interrupt sources so that the
2031 * sequencer will not be stuck by a pausing
2032 * interrupt condition while we attempt to
2033 * leave a critical section.
2034 */
2035 simode0 = ahc_inb(ahc, SIMODE0);
2036 ahc_outb(ahc, SIMODE0, 0);
2037 simode1 = ahc_inb(ahc, SIMODE1);
2038 if ((ahc->features & AHC_DT) != 0)
2039 /*
2040 * On DT class controllers, we
2041 * use the enhanced busfree logic.
2042 * Unfortunately we cannot re-enable
2043 * busfree detection within the
2044 * current connection, so we must
2045 * leave it on while single stepping.
2046 */
2047 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
2048 else
2049 ahc_outb(ahc, SIMODE1, 0);
2050 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2051 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
2052 stepping = TRUE;
2053 }
2054 if ((ahc->features & AHC_DT) != 0) {
2055 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
2056 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2057 }
2058 ahc_outb(ahc, HCNTRL, ahc->unpause);
2059 while (!ahc_is_paused(ahc))
2060 ahc_delay(200);
2061 }
2062 if (stepping) {
2063 ahc_outb(ahc, SIMODE0, simode0);
2064 ahc_outb(ahc, SIMODE1, simode1);
2065 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2066 }
2067 }
2068
2069 /*
2070 * Clear any pending interrupt status.
2071 */
2072 static void
2073 ahc_clear_intstat(struct ahc_softc *ahc)
2074 {
2075 /* Clear any interrupt conditions this may have caused */
2076 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2077 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
2078 CLRREQINIT);
2079 ahc_flush_device_writes(ahc);
2080 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
2081 ahc_flush_device_writes(ahc);
2082 ahc_outb(ahc, CLRINT, CLRSCSIINT);
2083 ahc_flush_device_writes(ahc);
2084 }
2085
2086 /**************************** Debugging Routines ******************************/
2087 #ifdef AHC_DEBUG
2088 uint32_t ahc_debug = AHC_DEBUG_OPTS;
2089 #endif
2090
2091
2092 /************************* Transfer Negotiation *******************************/
2093 /*
2094 * Allocate per target mode instance (ID we respond to as a target)
2095 * transfer negotiation data structures.
2096 */
2097 static struct ahc_tmode_tstate *
2098 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
2099 {
2100 struct ahc_tmode_tstate *master_tstate;
2101 struct ahc_tmode_tstate *tstate;
2102 int i;
2103
2104 master_tstate = ahc->enabled_targets[ahc->our_id];
2105 if (channel == 'B') {
2106 scsi_id += 8;
2107 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
2108 }
2109 if (ahc->enabled_targets[scsi_id] != NULL
2110 && ahc->enabled_targets[scsi_id] != master_tstate)
2111 panic("%s: ahc_alloc_tstate - Target already allocated",
2112 ahc_name(ahc));
2113 tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC);
2114 if (tstate == NULL)
2115 return (NULL);
2116
2117 /*
2118 * If we have allocated a master tstate, copy user settings from
2119 * the master tstate (taken from SRAM or the EEPROM) for this
2120 * channel, but reset our current and goal settings to async/narrow
2121 * until an initiator talks to us.
2122 */
2123 if (master_tstate != NULL) {
2124 memcpy(tstate, master_tstate, sizeof(*tstate));
2125 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2126 tstate->ultraenb = 0;
2127 for (i = 0; i < AHC_NUM_TARGETS; i++) {
2128 memset(&tstate->transinfo[i].curr, 0,
2129 sizeof(tstate->transinfo[i].curr));
2130 memset(&tstate->transinfo[i].goal, 0,
2131 sizeof(tstate->transinfo[i].goal));
2132 }
2133 } else
2134 memset(tstate, 0, sizeof(*tstate));
2135 ahc->enabled_targets[scsi_id] = tstate;
2136 return (tstate);
2137 }
2138
2139 #ifdef AHC_TARGET_MODE
2140 /*
2141 * Free per target mode instance (ID we respond to as a target)
2142 * transfer negotiation data structures.
2143 */
2144 static void
2145 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
2146 {
2147 struct ahc_tmode_tstate *tstate;
2148
2149 /*
2150 * Don't clean up our "master" tstate.
2151 * It has our default user settings.
2152 */
2153 if (((channel == 'B' && scsi_id == ahc->our_id_b)
2154 || (channel == 'A' && scsi_id == ahc->our_id))
2155 && force == FALSE)
2156 return;
2157
2158 if (channel == 'B')
2159 scsi_id += 8;
2160 tstate = ahc->enabled_targets[scsi_id];
2161 if (tstate != NULL)
2162 kfree(tstate);
2163 ahc->enabled_targets[scsi_id] = NULL;
2164 }
2165 #endif
2166
2167 /*
2168 * Called when we have an active connection to a target on the bus,
2169 * this function finds the nearest syncrate to the input period limited
2170 * by the capabilities of the bus connectivity of and sync settings for
2171 * the target.
2172 */
2173 const struct ahc_syncrate *
2174 ahc_devlimited_syncrate(struct ahc_softc *ahc,
2175 struct ahc_initiator_tinfo *tinfo,
2176 u_int *period, u_int *ppr_options, role_t role)
2177 {
2178 struct ahc_transinfo *transinfo;
2179 u_int maxsync;
2180
2181 if ((ahc->features & AHC_ULTRA2) != 0) {
2182 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
2183 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
2184 maxsync = AHC_SYNCRATE_DT;
2185 } else {
2186 maxsync = AHC_SYNCRATE_ULTRA;
2187 /* Can't do DT on an SE bus */
2188 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2189 }
2190 } else if ((ahc->features & AHC_ULTRA) != 0) {
2191 maxsync = AHC_SYNCRATE_ULTRA;
2192 } else {
2193 maxsync = AHC_SYNCRATE_FAST;
2194 }
2195 /*
2196 * Never allow a value higher than our current goal
2197 * period otherwise we may allow a target initiated
2198 * negotiation to go above the limit as set by the
2199 * user. In the case of an initiator initiated
2200 * sync negotiation, we limit based on the user
2201 * setting. This allows the system to still accept
2202 * incoming negotiations even if target initiated
2203 * negotiation is not performed.
2204 */
2205 if (role == ROLE_TARGET)
2206 transinfo = &tinfo->user;
2207 else
2208 transinfo = &tinfo->goal;
2209 *ppr_options &= transinfo->ppr_options;
2210 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2211 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
2212 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2213 }
2214 if (transinfo->period == 0) {
2215 *period = 0;
2216 *ppr_options = 0;
2217 return (NULL);
2218 }
2219 *period = max(*period, (u_int)transinfo->period);
2220 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
2221 }
2222
2223 /*
2224 * Look up the valid period to SCSIRATE conversion in our table.
2225 * Return the period and offset that should be sent to the target
2226 * if this was the beginning of an SDTR.
2227 */
2228 const struct ahc_syncrate *
2229 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
2230 u_int *ppr_options, u_int maxsync)
2231 {
2232 const struct ahc_syncrate *syncrate;
2233
2234 if ((ahc->features & AHC_DT) == 0)
2235 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2236
2237 /* Skip all DT only entries if DT is not available */
2238 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2239 && maxsync < AHC_SYNCRATE_ULTRA2)
2240 maxsync = AHC_SYNCRATE_ULTRA2;
2241
2242 /* Now set the maxsync based on the card capabilities
2243 * DT is already done above */
2244 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2245 && maxsync < AHC_SYNCRATE_ULTRA)
2246 maxsync = AHC_SYNCRATE_ULTRA;
2247 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2248 && maxsync < AHC_SYNCRATE_FAST)
2249 maxsync = AHC_SYNCRATE_FAST;
2250
2251 for (syncrate = &ahc_syncrates[maxsync];
2252 syncrate->rate != NULL;
2253 syncrate++) {
2254
2255 /*
2256 * The Ultra2 table doesn't go as low
2257 * as for the Fast/Ultra cards.
2258 */
2259 if ((ahc->features & AHC_ULTRA2) != 0
2260 && (syncrate->sxfr_u2 == 0))
2261 break;
2262
2263 if (*period <= syncrate->period) {
2264 /*
2265 * When responding to a target that requests
2266 * sync, the requested rate may fall between
2267 * two rates that we can output, but still be
2268 * a rate that we can receive. Because of this,
2269 * we want to respond to the target with
2270 * the same rate that it sent to us even
2271 * if the period we use to send data to it
2272 * is lower. Only lower the response period
2273 * if we must.
2274 */
2275 if (syncrate == &ahc_syncrates[maxsync])
2276 *period = syncrate->period;
2277
2278 /*
2279 * At some speeds, we only support
2280 * ST transfers.
2281 */
2282 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
2283 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2284 break;
2285 }
2286 }
2287
2288 if ((*period == 0)
2289 || (syncrate->rate == NULL)
2290 || ((ahc->features & AHC_ULTRA2) != 0
2291 && (syncrate->sxfr_u2 == 0))) {
2292 /* Use asynchronous transfers. */
2293 *period = 0;
2294 syncrate = NULL;
2295 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2296 }
2297 return (syncrate);
2298 }
2299
2300 /*
2301 * Convert from an entry in our syncrate table to the SCSI equivalent
2302 * sync "period" factor.
2303 */
2304 u_int
2305 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
2306 {
2307 const struct ahc_syncrate *syncrate;
2308
2309 if ((ahc->features & AHC_ULTRA2) != 0)
2310 scsirate &= SXFR_ULTRA2;
2311 else
2312 scsirate &= SXFR;
2313
2314 /* now set maxsync based on card capabilities */
2315 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
2316 maxsync = AHC_SYNCRATE_ULTRA2;
2317 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2318 && maxsync < AHC_SYNCRATE_ULTRA)
2319 maxsync = AHC_SYNCRATE_ULTRA;
2320 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2321 && maxsync < AHC_SYNCRATE_FAST)
2322 maxsync = AHC_SYNCRATE_FAST;
2323
2324
2325 syncrate = &ahc_syncrates[maxsync];
2326 while (syncrate->rate != NULL) {
2327
2328 if ((ahc->features & AHC_ULTRA2) != 0) {
2329 if (syncrate->sxfr_u2 == 0)
2330 break;
2331 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
2332 return (syncrate->period);
2333 } else if (scsirate == (syncrate->sxfr & SXFR)) {
2334 return (syncrate->period);
2335 }
2336 syncrate++;
2337 }
2338 return (0); /* async */
2339 }
2340
2341 /*
2342 * Truncate the given synchronous offset to a value the
2343 * current adapter type and syncrate are capable of.
2344 */
2345 static void
2346 ahc_validate_offset(struct ahc_softc *ahc,
2347 struct ahc_initiator_tinfo *tinfo,
2348 const struct ahc_syncrate *syncrate,
2349 u_int *offset, int wide, role_t role)
2350 {
2351 u_int maxoffset;
2352
2353 /* Limit offset to what we can do */
2354 if (syncrate == NULL) {
2355 maxoffset = 0;
2356 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2357 maxoffset = MAX_OFFSET_ULTRA2;
2358 } else {
2359 if (wide)
2360 maxoffset = MAX_OFFSET_16BIT;
2361 else
2362 maxoffset = MAX_OFFSET_8BIT;
2363 }
2364 *offset = min(*offset, maxoffset);
2365 if (tinfo != NULL) {
2366 if (role == ROLE_TARGET)
2367 *offset = min(*offset, (u_int)tinfo->user.offset);
2368 else
2369 *offset = min(*offset, (u_int)tinfo->goal.offset);
2370 }
2371 }
2372
2373 /*
2374 * Truncate the given transfer width parameter to a value the
2375 * current adapter type is capable of.
2376 */
2377 static void
2378 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
2379 u_int *bus_width, role_t role)
2380 {
2381 switch (*bus_width) {
2382 default:
2383 if (ahc->features & AHC_WIDE) {
2384 /* Respond Wide */
2385 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2386 break;
2387 }
2388 /* FALLTHROUGH */
2389 case MSG_EXT_WDTR_BUS_8_BIT:
2390 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2391 break;
2392 }
2393 if (tinfo != NULL) {
2394 if (role == ROLE_TARGET)
2395 *bus_width = min((u_int)tinfo->user.width, *bus_width);
2396 else
2397 *bus_width = min((u_int)tinfo->goal.width, *bus_width);
2398 }
2399 }
2400
2401 /*
2402 * Update the bitmask of targets for which the controller should
2403 * negotiate with at the next convenient oportunity. This currently
2404 * means the next time we send the initial identify messages for
2405 * a new transaction.
2406 */
2407 int
2408 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2409 struct ahc_tmode_tstate *tstate,
2410 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
2411 {
2412 u_int auto_negotiate_orig;
2413
2414 auto_negotiate_orig = tstate->auto_negotiate;
2415 if (neg_type == AHC_NEG_ALWAYS) {
2416 /*
2417 * Force our "current" settings to be
2418 * unknown so that unless a bus reset
2419 * occurs the need to renegotiate is
2420 * recorded persistently.
2421 */
2422 if ((ahc->features & AHC_WIDE) != 0)
2423 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
2424 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
2425 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
2426 }
2427 if (tinfo->curr.period != tinfo->goal.period
2428 || tinfo->curr.width != tinfo->goal.width
2429 || tinfo->curr.offset != tinfo->goal.offset
2430 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2431 || (neg_type == AHC_NEG_IF_NON_ASYNC
2432 && (tinfo->goal.offset != 0
2433 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2434 || tinfo->goal.ppr_options != 0)))
2435 tstate->auto_negotiate |= devinfo->target_mask;
2436 else
2437 tstate->auto_negotiate &= ~devinfo->target_mask;
2438
2439 return (auto_negotiate_orig != tstate->auto_negotiate);
2440 }
2441
2442 /*
2443 * Update the user/goal/curr tables of synchronous negotiation
2444 * parameters as well as, in the case of a current or active update,
2445 * any data structures on the host controller. In the case of an
2446 * active update, the specified target is currently talking to us on
2447 * the bus, so the transfer parameter update must take effect
2448 * immediately.
2449 */
2450 void
2451 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2452 const struct ahc_syncrate *syncrate, u_int period,
2453 u_int offset, u_int ppr_options, u_int type, int paused)
2454 {
2455 struct ahc_initiator_tinfo *tinfo;
2456 struct ahc_tmode_tstate *tstate;
2457 u_int old_period;
2458 u_int old_offset;
2459 u_int old_ppr;
2460 int active;
2461 int update_needed;
2462
2463 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2464 update_needed = 0;
2465
2466 if (syncrate == NULL) {
2467 period = 0;
2468 offset = 0;
2469 }
2470
2471 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2472 devinfo->target, &tstate);
2473
2474 if ((type & AHC_TRANS_USER) != 0) {
2475 tinfo->user.period = period;
2476 tinfo->user.offset = offset;
2477 tinfo->user.ppr_options = ppr_options;
2478 }
2479
2480 if ((type & AHC_TRANS_GOAL) != 0) {
2481 tinfo->goal.period = period;
2482 tinfo->goal.offset = offset;
2483 tinfo->goal.ppr_options = ppr_options;
2484 }
2485
2486 old_period = tinfo->curr.period;
2487 old_offset = tinfo->curr.offset;
2488 old_ppr = tinfo->curr.ppr_options;
2489
2490 if ((type & AHC_TRANS_CUR) != 0
2491 && (old_period != period
2492 || old_offset != offset
2493 || old_ppr != ppr_options)) {
2494 u_int scsirate;
2495
2496 update_needed++;
2497 scsirate = tinfo->scsirate;
2498 if ((ahc->features & AHC_ULTRA2) != 0) {
2499
2500 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
2501 if (syncrate != NULL) {
2502 scsirate |= syncrate->sxfr_u2;
2503 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
2504 scsirate |= ENABLE_CRC;
2505 else
2506 scsirate |= SINGLE_EDGE;
2507 }
2508 } else {
2509
2510 scsirate &= ~(SXFR|SOFS);
2511 /*
2512 * Ensure Ultra mode is set properly for
2513 * this target.
2514 */
2515 tstate->ultraenb &= ~devinfo->target_mask;
2516 if (syncrate != NULL) {
2517 if (syncrate->sxfr & ULTRA_SXFR) {
2518 tstate->ultraenb |=
2519 devinfo->target_mask;
2520 }
2521 scsirate |= syncrate->sxfr & SXFR;
2522 scsirate |= offset & SOFS;
2523 }
2524 if (active) {
2525 u_int sxfrctl0;
2526
2527 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
2528 sxfrctl0 &= ~FAST20;
2529 if (tstate->ultraenb & devinfo->target_mask)
2530 sxfrctl0 |= FAST20;
2531 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
2532 }
2533 }
2534 if (active) {
2535 ahc_outb(ahc, SCSIRATE, scsirate);
2536 if ((ahc->features & AHC_ULTRA2) != 0)
2537 ahc_outb(ahc, SCSIOFFSET, offset);
2538 }
2539
2540 tinfo->scsirate = scsirate;
2541 tinfo->curr.period = period;
2542 tinfo->curr.offset = offset;
2543 tinfo->curr.ppr_options = ppr_options;
2544
2545 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2546 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2547 if (bootverbose) {
2548 if (offset != 0) {
2549 printk("%s: target %d synchronous at %sMHz%s, "
2550 "offset = 0x%x\n", ahc_name(ahc),
2551 devinfo->target, syncrate->rate,
2552 (ppr_options & MSG_EXT_PPR_DT_REQ)
2553 ? " DT" : "", offset);
2554 } else {
2555 printk("%s: target %d using "
2556 "asynchronous transfers\n",
2557 ahc_name(ahc), devinfo->target);
2558 }
2559 }
2560 }
2561
2562 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2563 tinfo, AHC_NEG_TO_GOAL);
2564
2565 if (update_needed)
2566 ahc_update_pending_scbs(ahc);
2567 }
2568
2569 /*
2570 * Update the user/goal/curr tables of wide negotiation
2571 * parameters as well as, in the case of a current or active update,
2572 * any data structures on the host controller. In the case of an
2573 * active update, the specified target is currently talking to us on
2574 * the bus, so the transfer parameter update must take effect
2575 * immediately.
2576 */
2577 void
2578 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2579 u_int width, u_int type, int paused)
2580 {
2581 struct ahc_initiator_tinfo *tinfo;
2582 struct ahc_tmode_tstate *tstate;
2583 u_int oldwidth;
2584 int active;
2585 int update_needed;
2586
2587 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2588 update_needed = 0;
2589 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2590 devinfo->target, &tstate);
2591
2592 if ((type & AHC_TRANS_USER) != 0)
2593 tinfo->user.width = width;
2594
2595 if ((type & AHC_TRANS_GOAL) != 0)
2596 tinfo->goal.width = width;
2597
2598 oldwidth = tinfo->curr.width;
2599 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2600 u_int scsirate;
2601
2602 update_needed++;
2603 scsirate = tinfo->scsirate;
2604 scsirate &= ~WIDEXFER;
2605 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2606 scsirate |= WIDEXFER;
2607
2608 tinfo->scsirate = scsirate;
2609
2610 if (active)
2611 ahc_outb(ahc, SCSIRATE, scsirate);
2612
2613 tinfo->curr.width = width;
2614
2615 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2616 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2617 if (bootverbose) {
2618 printk("%s: target %d using %dbit transfers\n",
2619 ahc_name(ahc), devinfo->target,
2620 8 * (0x01 << width));
2621 }
2622 }
2623
2624 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2625 tinfo, AHC_NEG_TO_GOAL);
2626 if (update_needed)
2627 ahc_update_pending_scbs(ahc);
2628 }
2629
2630 /*
2631 * Update the current state of tagged queuing for a given target.
2632 */
2633 static void
2634 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2635 struct ahc_devinfo *devinfo, ahc_queue_alg alg)
2636 {
2637 struct scsi_device *sdev = cmd->device;
2638
2639 ahc_platform_set_tags(ahc, sdev, devinfo, alg);
2640 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2641 devinfo->lun, AC_TRANSFER_NEG);
2642 }
2643
2644 /*
2645 * When the transfer settings for a connection change, update any
2646 * in-transit SCBs to contain the new data so the hardware will
2647 * be set correctly during future (re)selections.
2648 */
2649 static void
2650 ahc_update_pending_scbs(struct ahc_softc *ahc)
2651 {
2652 struct scb *pending_scb;
2653 int pending_scb_count;
2654 int i;
2655 int paused;
2656 u_int saved_scbptr;
2657
2658 /*
2659 * Traverse the pending SCB list and ensure that all of the
2660 * SCBs there have the proper settings.
2661 */
2662 pending_scb_count = 0;
2663 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2664 struct ahc_devinfo devinfo;
2665 struct hardware_scb *pending_hscb;
2666 struct ahc_initiator_tinfo *tinfo;
2667 struct ahc_tmode_tstate *tstate;
2668
2669 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2670 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2671 devinfo.our_scsiid,
2672 devinfo.target, &tstate);
2673 pending_hscb = pending_scb->hscb;
2674 pending_hscb->control &= ~ULTRAENB;
2675 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2676 pending_hscb->control |= ULTRAENB;
2677 pending_hscb->scsirate = tinfo->scsirate;
2678 pending_hscb->scsioffset = tinfo->curr.offset;
2679 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2680 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2681 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2682 pending_hscb->control &= ~MK_MESSAGE;
2683 }
2684 ahc_sync_scb(ahc, pending_scb,
2685 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2686 pending_scb_count++;
2687 }
2688
2689 if (pending_scb_count == 0)
2690 return;
2691
2692 if (ahc_is_paused(ahc)) {
2693 paused = 1;
2694 } else {
2695 paused = 0;
2696 ahc_pause(ahc);
2697 }
2698
2699 saved_scbptr = ahc_inb(ahc, SCBPTR);
2700 /* Ensure that the hscbs down on the card match the new information */
2701 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2702 struct hardware_scb *pending_hscb;
2703 u_int control;
2704 u_int scb_tag;
2705
2706 ahc_outb(ahc, SCBPTR, i);
2707 scb_tag = ahc_inb(ahc, SCB_TAG);
2708 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2709 if (pending_scb == NULL)
2710 continue;
2711
2712 pending_hscb = pending_scb->hscb;
2713 control = ahc_inb(ahc, SCB_CONTROL);
2714 control &= ~(ULTRAENB|MK_MESSAGE);
2715 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2716 ahc_outb(ahc, SCB_CONTROL, control);
2717 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2718 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2719 }
2720 ahc_outb(ahc, SCBPTR, saved_scbptr);
2721
2722 if (paused == 0)
2723 ahc_unpause(ahc);
2724 }
2725
2726 /**************************** Pathing Information *****************************/
2727 static void
2728 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2729 {
2730 u_int saved_scsiid;
2731 role_t role;
2732 int our_id;
2733
2734 if (ahc_inb(ahc, SSTAT0) & TARGET)
2735 role = ROLE_TARGET;
2736 else
2737 role = ROLE_INITIATOR;
2738
2739 if (role == ROLE_TARGET
2740 && (ahc->features & AHC_MULTI_TID) != 0
2741 && (ahc_inb(ahc, SEQ_FLAGS)
2742 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2743 /* We were selected, so pull our id from TARGIDIN */
2744 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2745 } else if ((ahc->features & AHC_ULTRA2) != 0)
2746 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2747 else
2748 our_id = ahc_inb(ahc, SCSIID) & OID;
2749
2750 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2751 ahc_compile_devinfo(devinfo,
2752 our_id,
2753 SCSIID_TARGET(ahc, saved_scsiid),
2754 ahc_inb(ahc, SAVED_LUN),
2755 SCSIID_CHANNEL(ahc, saved_scsiid),
2756 role);
2757 }
2758
2759 static const struct ahc_phase_table_entry*
2760 ahc_lookup_phase_entry(int phase)
2761 {
2762 const struct ahc_phase_table_entry *entry;
2763 const struct ahc_phase_table_entry *last_entry;
2764
2765 /*
2766 * num_phases doesn't include the default entry which
2767 * will be returned if the phase doesn't match.
2768 */
2769 last_entry = &ahc_phase_table[num_phases];
2770 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2771 if (phase == entry->phase)
2772 break;
2773 }
2774 return (entry);
2775 }
2776
2777 void
2778 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2779 u_int lun, char channel, role_t role)
2780 {
2781 devinfo->our_scsiid = our_id;
2782 devinfo->target = target;
2783 devinfo->lun = lun;
2784 devinfo->target_offset = target;
2785 devinfo->channel = channel;
2786 devinfo->role = role;
2787 if (channel == 'B')
2788 devinfo->target_offset += 8;
2789 devinfo->target_mask = (0x01 << devinfo->target_offset);
2790 }
2791
2792 void
2793 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2794 {
2795 printk("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2796 devinfo->target, devinfo->lun);
2797 }
2798
2799 static void
2800 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2801 struct scb *scb)
2802 {
2803 role_t role;
2804 int our_id;
2805
2806 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2807 role = ROLE_INITIATOR;
2808 if ((scb->flags & SCB_TARGET_SCB) != 0)
2809 role = ROLE_TARGET;
2810 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2811 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2812 }
2813
2814
2815 /************************ Message Phase Processing ****************************/
2816 static void
2817 ahc_assert_atn(struct ahc_softc *ahc)
2818 {
2819 u_int scsisigo;
2820
2821 scsisigo = ATNO;
2822 if ((ahc->features & AHC_DT) == 0)
2823 scsisigo |= ahc_inb(ahc, SCSISIGI);
2824 ahc_outb(ahc, SCSISIGO, scsisigo);
2825 }
2826
2827 /*
2828 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2829 * or enters the initial message out phase, we are interrupted. Fill our
2830 * outgoing message buffer with the appropriate message and beging handing
2831 * the message phase(s) manually.
2832 */
2833 static void
2834 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2835 struct scb *scb)
2836 {
2837 /*
2838 * To facilitate adding multiple messages together,
2839 * each routine should increment the index and len
2840 * variables instead of setting them explicitly.
2841 */
2842 ahc->msgout_index = 0;
2843 ahc->msgout_len = 0;
2844
2845 if ((scb->flags & SCB_DEVICE_RESET) == 0
2846 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2847 u_int identify_msg;
2848
2849 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2850 if ((scb->hscb->control & DISCENB) != 0)
2851 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2852 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2853 ahc->msgout_len++;
2854
2855 if ((scb->hscb->control & TAG_ENB) != 0) {
2856 ahc->msgout_buf[ahc->msgout_index++] =
2857 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2858 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2859 ahc->msgout_len += 2;
2860 }
2861 }
2862
2863 if (scb->flags & SCB_DEVICE_RESET) {
2864 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2865 ahc->msgout_len++;
2866 ahc_print_path(ahc, scb);
2867 printk("Bus Device Reset Message Sent\n");
2868 /*
2869 * Clear our selection hardware in advance of
2870 * the busfree. We may have an entry in the waiting
2871 * Q for this target, and we don't want to go about
2872 * selecting while we handle the busfree and blow it
2873 * away.
2874 */
2875 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2876 } else if ((scb->flags & SCB_ABORT) != 0) {
2877 if ((scb->hscb->control & TAG_ENB) != 0)
2878 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2879 else
2880 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2881 ahc->msgout_len++;
2882 ahc_print_path(ahc, scb);
2883 printk("Abort%s Message Sent\n",
2884 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2885 /*
2886 * Clear our selection hardware in advance of
2887 * the busfree. We may have an entry in the waiting
2888 * Q for this target, and we don't want to go about
2889 * selecting while we handle the busfree and blow it
2890 * away.
2891 */
2892 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2893 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2894 ahc_build_transfer_msg(ahc, devinfo);
2895 } else {
2896 printk("ahc_intr: AWAITING_MSG for an SCB that "
2897 "does not have a waiting message\n");
2898 printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2899 devinfo->target_mask);
2900 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2901 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2902 ahc_inb(ahc, MSG_OUT), scb->flags);
2903 }
2904
2905 /*
2906 * Clear the MK_MESSAGE flag from the SCB so we aren't
2907 * asked to send this message again.
2908 */
2909 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2910 scb->hscb->control &= ~MK_MESSAGE;
2911 ahc->msgout_index = 0;
2912 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2913 }
2914
2915 /*
2916 * Build an appropriate transfer negotiation message for the
2917 * currently active target.
2918 */
2919 static void
2920 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2921 {
2922 /*
2923 * We need to initiate transfer negotiations.
2924 * If our current and goal settings are identical,
2925 * we want to renegotiate due to a check condition.
2926 */
2927 struct ahc_initiator_tinfo *tinfo;
2928 struct ahc_tmode_tstate *tstate;
2929 const struct ahc_syncrate *rate;
2930 int dowide;
2931 int dosync;
2932 int doppr;
2933 u_int period;
2934 u_int ppr_options;
2935 u_int offset;
2936
2937 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2938 devinfo->target, &tstate);
2939 /*
2940 * Filter our period based on the current connection.
2941 * If we can't perform DT transfers on this segment (not in LVD
2942 * mode for instance), then our decision to issue a PPR message
2943 * may change.
2944 */
2945 period = tinfo->goal.period;
2946 offset = tinfo->goal.offset;
2947 ppr_options = tinfo->goal.ppr_options;
2948 /* Target initiated PPR is not allowed in the SCSI spec */
2949 if (devinfo->role == ROLE_TARGET)
2950 ppr_options = 0;
2951 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2952 &ppr_options, devinfo->role);
2953 dowide = tinfo->curr.width != tinfo->goal.width;
2954 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2955 /*
2956 * Only use PPR if we have options that need it, even if the device
2957 * claims to support it. There might be an expander in the way
2958 * that doesn't.
2959 */
2960 doppr = ppr_options != 0;
2961
2962 if (!dowide && !dosync && !doppr) {
2963 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2964 dosync = tinfo->goal.offset != 0;
2965 }
2966
2967 if (!dowide && !dosync && !doppr) {
2968 /*
2969 * Force async with a WDTR message if we have a wide bus,
2970 * or just issue an SDTR with a 0 offset.
2971 */
2972 if ((ahc->features & AHC_WIDE) != 0)
2973 dowide = 1;
2974 else
2975 dosync = 1;
2976
2977 if (bootverbose) {
2978 ahc_print_devinfo(ahc, devinfo);
2979 printk("Ensuring async\n");
2980 }
2981 }
2982
2983 /* Target initiated PPR is not allowed in the SCSI spec */
2984 if (devinfo->role == ROLE_TARGET)
2985 doppr = 0;
2986
2987 /*
2988 * Both the PPR message and SDTR message require the
2989 * goal syncrate to be limited to what the target device
2990 * is capable of handling (based on whether an LVD->SE
2991 * expander is on the bus), so combine these two cases.
2992 * Regardless, guarantee that if we are using WDTR and SDTR
2993 * messages that WDTR comes first.
2994 */
2995 if (doppr || (dosync && !dowide)) {
2996
2997 offset = tinfo->goal.offset;
2998 ahc_validate_offset(ahc, tinfo, rate, &offset,
2999 doppr ? tinfo->goal.width
3000 : tinfo->curr.width,
3001 devinfo->role);
3002 if (doppr) {
3003 ahc_construct_ppr(ahc, devinfo, period, offset,
3004 tinfo->goal.width, ppr_options);
3005 } else {
3006 ahc_construct_sdtr(ahc, devinfo, period, offset);
3007 }
3008 } else {
3009 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
3010 }
3011 }
3012
3013 /*
3014 * Build a synchronous negotiation message in our message
3015 * buffer based on the input parameters.
3016 */
3017 static void
3018 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3019 u_int period, u_int offset)
3020 {
3021 if (offset == 0)
3022 period = AHC_ASYNC_XFER_PERIOD;
3023 ahc->msgout_index += spi_populate_sync_msg(
3024 ahc->msgout_buf + ahc->msgout_index, period, offset);
3025 ahc->msgout_len += 5;
3026 if (bootverbose) {
3027 printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3028 ahc_name(ahc), devinfo->channel, devinfo->target,
3029 devinfo->lun, period, offset);
3030 }
3031 }
3032
3033 /*
3034 * Build a wide negotiation message in our message
3035 * buffer based on the input parameters.
3036 */
3037 static void
3038 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3039 u_int bus_width)
3040 {
3041 ahc->msgout_index += spi_populate_width_msg(
3042 ahc->msgout_buf + ahc->msgout_index, bus_width);
3043 ahc->msgout_len += 4;
3044 if (bootverbose) {
3045 printk("(%s:%c:%d:%d): Sending WDTR %x\n",
3046 ahc_name(ahc), devinfo->channel, devinfo->target,
3047 devinfo->lun, bus_width);
3048 }
3049 }
3050
3051 /*
3052 * Build a parallel protocol request message in our message
3053 * buffer based on the input parameters.
3054 */
3055 static void
3056 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3057 u_int period, u_int offset, u_int bus_width,
3058 u_int ppr_options)
3059 {
3060 if (offset == 0)
3061 period = AHC_ASYNC_XFER_PERIOD;
3062 ahc->msgout_index += spi_populate_ppr_msg(
3063 ahc->msgout_buf + ahc->msgout_index, period, offset,
3064 bus_width, ppr_options);
3065 ahc->msgout_len += 8;
3066 if (bootverbose) {
3067 printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3068 "offset %x, ppr_options %x\n", ahc_name(ahc),
3069 devinfo->channel, devinfo->target, devinfo->lun,
3070 bus_width, period, offset, ppr_options);
3071 }
3072 }
3073
3074 /*
3075 * Clear any active message state.
3076 */
3077 static void
3078 ahc_clear_msg_state(struct ahc_softc *ahc)
3079 {
3080 ahc->msgout_len = 0;
3081 ahc->msgin_index = 0;
3082 ahc->msg_type = MSG_TYPE_NONE;
3083 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
3084 /*
3085 * The target didn't care to respond to our
3086 * message request, so clear ATN.
3087 */
3088 ahc_outb(ahc, CLRSINT1, CLRATNO);
3089 }
3090 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
3091 ahc_outb(ahc, SEQ_FLAGS2,
3092 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3093 }
3094
3095 static void
3096 ahc_handle_proto_violation(struct ahc_softc *ahc)
3097 {
3098 struct ahc_devinfo devinfo;
3099 struct scb *scb;
3100 u_int scbid;
3101 u_int seq_flags;
3102 u_int curphase;
3103 u_int lastphase;
3104 int found;
3105
3106 ahc_fetch_devinfo(ahc, &devinfo);
3107 scbid = ahc_inb(ahc, SCB_TAG);
3108 scb = ahc_lookup_scb(ahc, scbid);
3109 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
3110 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3111 lastphase = ahc_inb(ahc, LASTPHASE);
3112 if ((seq_flags & NOT_IDENTIFIED) != 0) {
3113
3114 /*
3115 * The reconnecting target either did not send an
3116 * identify message, or did, but we didn't find an SCB
3117 * to match.
3118 */
3119 ahc_print_devinfo(ahc, &devinfo);
3120 printk("Target did not send an IDENTIFY message. "
3121 "LASTPHASE = 0x%x.\n", lastphase);
3122 scb = NULL;
3123 } else if (scb == NULL) {
3124 /*
3125 * We don't seem to have an SCB active for this
3126 * transaction. Print an error and reset the bus.
3127 */
3128 ahc_print_devinfo(ahc, &devinfo);
3129 printk("No SCB found during protocol violation\n");
3130 goto proto_violation_reset;
3131 } else {
3132 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
3133 if ((seq_flags & NO_CDB_SENT) != 0) {
3134 ahc_print_path(ahc, scb);
3135 printk("No or incomplete CDB sent to device.\n");
3136 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
3137 /*
3138 * The target never bothered to provide status to
3139 * us prior to completing the command. Since we don't
3140 * know the disposition of this command, we must attempt
3141 * to abort it. Assert ATN and prepare to send an abort
3142 * message.
3143 */
3144 ahc_print_path(ahc, scb);
3145 printk("Completed command without status.\n");
3146 } else {
3147 ahc_print_path(ahc, scb);
3148 printk("Unknown protocol violation.\n");
3149 ahc_dump_card_state(ahc);
3150 }
3151 }
3152 if ((lastphase & ~P_DATAIN_DT) == 0
3153 || lastphase == P_COMMAND) {
3154 proto_violation_reset:
3155 /*
3156 * Target either went directly to data/command
3157 * phase or didn't respond to our ATN.
3158 * The only safe thing to do is to blow
3159 * it away with a bus reset.
3160 */
3161 found = ahc_reset_channel(ahc, 'A', TRUE);
3162 printk("%s: Issued Channel %c Bus Reset. "
3163 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
3164 } else {
3165 /*
3166 * Leave the selection hardware off in case
3167 * this abort attempt will affect yet to
3168 * be sent commands.
3169 */
3170 ahc_outb(ahc, SCSISEQ,
3171 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
3172 ahc_assert_atn(ahc);
3173 ahc_outb(ahc, MSG_OUT, HOST_MSG);
3174 if (scb == NULL) {
3175 ahc_print_devinfo(ahc, &devinfo);
3176 ahc->msgout_buf[0] = MSG_ABORT_TASK;
3177 ahc->msgout_len = 1;
3178 ahc->msgout_index = 0;
3179 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3180 } else {
3181 ahc_print_path(ahc, scb);
3182 scb->flags |= SCB_ABORT;
3183 }
3184 printk("Protocol violation %s. Attempting to abort.\n",
3185 ahc_lookup_phase_entry(curphase)->phasemsg);
3186 }
3187 }
3188
3189 /*
3190 * Manual message loop handler.
3191 */
3192 static void
3193 ahc_handle_message_phase(struct ahc_softc *ahc)
3194 {
3195 struct ahc_devinfo devinfo;
3196 u_int bus_phase;
3197 int end_session;
3198
3199 ahc_fetch_devinfo(ahc, &devinfo);
3200 end_session = FALSE;
3201 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3202
3203 reswitch:
3204 switch (ahc->msg_type) {
3205 case MSG_TYPE_INITIATOR_MSGOUT:
3206 {
3207 int lastbyte;
3208 int phasemis;
3209 int msgdone;
3210
3211 if (ahc->msgout_len == 0)
3212 panic("HOST_MSG_LOOP interrupt with no active message");
3213
3214 #ifdef AHC_DEBUG
3215 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3216 ahc_print_devinfo(ahc, &devinfo);
3217 printk("INITIATOR_MSG_OUT");
3218 }
3219 #endif
3220 phasemis = bus_phase != P_MESGOUT;
3221 if (phasemis) {
3222 #ifdef AHC_DEBUG
3223 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3224 printk(" PHASEMIS %s\n",
3225 ahc_lookup_phase_entry(bus_phase)
3226 ->phasemsg);
3227 }
3228 #endif
3229 if (bus_phase == P_MESGIN) {
3230 /*
3231 * Change gears and see if
3232 * this messages is of interest to
3233 * us or should be passed back to
3234 * the sequencer.
3235 */
3236 ahc_outb(ahc, CLRSINT1, CLRATNO);
3237 ahc->send_msg_perror = FALSE;
3238 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3239 ahc->msgin_index = 0;
3240 goto reswitch;
3241 }
3242 end_session = TRUE;
3243 break;
3244 }
3245
3246 if (ahc->send_msg_perror) {
3247 ahc_outb(ahc, CLRSINT1, CLRATNO);
3248 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3249 #ifdef AHC_DEBUG
3250 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3251 printk(" byte 0x%x\n", ahc->send_msg_perror);
3252 #endif
3253 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
3254 break;
3255 }
3256
3257 msgdone = ahc->msgout_index == ahc->msgout_len;
3258 if (msgdone) {
3259 /*
3260 * The target has requested a retry.
3261 * Re-assert ATN, reset our message index to
3262 * 0, and try again.
3263 */
3264 ahc->msgout_index = 0;
3265 ahc_assert_atn(ahc);
3266 }
3267
3268 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
3269 if (lastbyte) {
3270 /* Last byte is signified by dropping ATN */
3271 ahc_outb(ahc, CLRSINT1, CLRATNO);
3272 }
3273
3274 /*
3275 * Clear our interrupt status and present
3276 * the next byte on the bus.
3277 */
3278 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3279 #ifdef AHC_DEBUG
3280 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3281 printk(" byte 0x%x\n",
3282 ahc->msgout_buf[ahc->msgout_index]);
3283 #endif
3284 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3285 break;
3286 }
3287 case MSG_TYPE_INITIATOR_MSGIN:
3288 {
3289 int phasemis;
3290 int message_done;
3291
3292 #ifdef AHC_DEBUG
3293 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3294 ahc_print_devinfo(ahc, &devinfo);
3295 printk("INITIATOR_MSG_IN");
3296 }
3297 #endif
3298 phasemis = bus_phase != P_MESGIN;
3299 if (phasemis) {
3300 #ifdef AHC_DEBUG
3301 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3302 printk(" PHASEMIS %s\n",
3303 ahc_lookup_phase_entry(bus_phase)
3304 ->phasemsg);
3305 }
3306 #endif
3307 ahc->msgin_index = 0;
3308 if (bus_phase == P_MESGOUT
3309 && (ahc->send_msg_perror == TRUE
3310 || (ahc->msgout_len != 0
3311 && ahc->msgout_index == 0))) {
3312 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3313 goto reswitch;
3314 }
3315 end_session = TRUE;
3316 break;
3317 }
3318
3319 /* Pull the byte in without acking it */
3320 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
3321 #ifdef AHC_DEBUG
3322 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3323 printk(" byte 0x%x\n",
3324 ahc->msgin_buf[ahc->msgin_index]);
3325 #endif
3326
3327 message_done = ahc_parse_msg(ahc, &devinfo);
3328
3329 if (message_done) {
3330 /*
3331 * Clear our incoming message buffer in case there
3332 * is another message following this one.
3333 */
3334 ahc->msgin_index = 0;
3335
3336 /*
3337 * If this message illicited a response,
3338 * assert ATN so the target takes us to the
3339 * message out phase.
3340 */
3341 if (ahc->msgout_len != 0) {
3342 #ifdef AHC_DEBUG
3343 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3344 ahc_print_devinfo(ahc, &devinfo);
3345 printk("Asserting ATN for response\n");
3346 }
3347 #endif
3348 ahc_assert_atn(ahc);
3349 }
3350 } else
3351 ahc->msgin_index++;
3352
3353 if (message_done == MSGLOOP_TERMINATED) {
3354 end_session = TRUE;
3355 } else {
3356 /* Ack the byte */
3357 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3358 ahc_inb(ahc, SCSIDATL);
3359 }
3360 break;
3361 }
3362 case MSG_TYPE_TARGET_MSGIN:
3363 {
3364 int msgdone;
3365 int msgout_request;
3366
3367 if (ahc->msgout_len == 0)
3368 panic("Target MSGIN with no active message");
3369
3370 /*
3371 * If we interrupted a mesgout session, the initiator
3372 * will not know this until our first REQ. So, we
3373 * only honor mesgout requests after we've sent our
3374 * first byte.
3375 */
3376 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
3377 && ahc->msgout_index > 0)
3378 msgout_request = TRUE;
3379 else
3380 msgout_request = FALSE;
3381
3382 if (msgout_request) {
3383
3384 /*
3385 * Change gears and see if
3386 * this messages is of interest to
3387 * us or should be passed back to
3388 * the sequencer.
3389 */
3390 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
3391 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
3392 ahc->msgin_index = 0;
3393 /* Dummy read to REQ for first byte */
3394 ahc_inb(ahc, SCSIDATL);
3395 ahc_outb(ahc, SXFRCTL0,
3396 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3397 break;
3398 }
3399
3400 msgdone = ahc->msgout_index == ahc->msgout_len;
3401 if (msgdone) {
3402 ahc_outb(ahc, SXFRCTL0,
3403 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3404 end_session = TRUE;
3405 break;
3406 }
3407
3408 /*
3409 * Present the next byte on the bus.
3410 */
3411 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3412 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3413 break;
3414 }
3415 case MSG_TYPE_TARGET_MSGOUT:
3416 {
3417 int lastbyte;
3418 int msgdone;
3419
3420 /*
3421 * The initiator signals that this is
3422 * the last byte by dropping ATN.
3423 */
3424 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
3425
3426 /*
3427 * Read the latched byte, but turn off SPIOEN first
3428 * so that we don't inadvertently cause a REQ for the
3429 * next byte.
3430 */
3431 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3432 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
3433 msgdone = ahc_parse_msg(ahc, &devinfo);
3434 if (msgdone == MSGLOOP_TERMINATED) {
3435 /*
3436 * The message is *really* done in that it caused
3437 * us to go to bus free. The sequencer has already
3438 * been reset at this point, so pull the ejection
3439 * handle.
3440 */
3441 return;
3442 }
3443
3444 ahc->msgin_index++;
3445
3446 if (msgdone == MSGLOOP_MSGCOMPLETE) {
3447 ahc->msgin_index = 0;
3448
3449 /*
3450 * If this message illicited a response, transition
3451 * to the Message in phase and send it.
3452 */
3453 if (ahc->msgout_len != 0) {
3454 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
3455 ahc_outb(ahc, SXFRCTL0,
3456 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3457 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3458 ahc->msgin_index = 0;
3459 break;
3460 }
3461 }
3462
3463 if (lastbyte)
3464 end_session = TRUE;
3465 else {
3466 /* Ask for the next byte. */
3467 ahc_outb(ahc, SXFRCTL0,
3468 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3469 }
3470
3471 break;
3472 }
3473 default:
3474 panic("Unknown REQINIT message type");
3475 }
3476
3477 if (end_session) {
3478 ahc_clear_msg_state(ahc);
3479 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3480 } else
3481 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3482 }
3483
3484 /*
3485 * See if we sent a particular extended message to the target.
3486 * If "full" is true, return true only if the target saw the full
3487 * message. If "full" is false, return true if the target saw at
3488 * least the first byte of the message.
3489 */
3490 static int
3491 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3492 {
3493 int found;
3494 u_int index;
3495
3496 found = FALSE;
3497 index = 0;
3498
3499 while (index < ahc->msgout_len) {
3500 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3501 u_int end_index;
3502
3503 end_index = index + 1 + ahc->msgout_buf[index + 1];
3504 if (ahc->msgout_buf[index+2] == msgval
3505 && type == AHCMSG_EXT) {
3506
3507 if (full) {
3508 if (ahc->msgout_index > end_index)
3509 found = TRUE;
3510 } else if (ahc->msgout_index > index)
3511 found = TRUE;
3512 }
3513 index = end_index;
3514 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3515 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3516
3517 /* Skip tag type and tag id or residue param*/
3518 index += 2;
3519 } else {
3520 /* Single byte message */
3521 if (type == AHCMSG_1B
3522 && ahc->msgout_buf[index] == msgval
3523 && ahc->msgout_index > index)
3524 found = TRUE;
3525 index++;
3526 }
3527
3528 if (found)
3529 break;
3530 }
3531 return (found);
3532 }
3533
3534 /*
3535 * Wait for a complete incoming message, parse it, and respond accordingly.
3536 */
3537 static int
3538 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3539 {
3540 struct ahc_initiator_tinfo *tinfo;
3541 struct ahc_tmode_tstate *tstate;
3542 int reject;
3543 int done;
3544 int response;
3545 u_int targ_scsirate;
3546
3547 done = MSGLOOP_IN_PROG;
3548 response = FALSE;
3549 reject = FALSE;
3550 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3551 devinfo->target, &tstate);
3552 targ_scsirate = tinfo->scsirate;
3553
3554 /*
3555 * Parse as much of the message as is available,
3556 * rejecting it if we don't support it. When
3557 * the entire message is available and has been
3558 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3559 * that we have parsed an entire message.
3560 *
3561 * In the case of extended messages, we accept the length
3562 * byte outright and perform more checking once we know the
3563 * extended message type.
3564 */
3565 switch (ahc->msgin_buf[0]) {
3566 case MSG_DISCONNECT:
3567 case MSG_SAVEDATAPOINTER:
3568 case MSG_CMDCOMPLETE:
3569 case MSG_RESTOREPOINTERS:
3570 case MSG_IGN_WIDE_RESIDUE:
3571 /*
3572 * End our message loop as these are messages
3573 * the sequencer handles on its own.
3574 */
3575 done = MSGLOOP_TERMINATED;
3576 break;
3577 case MSG_MESSAGE_REJECT:
3578 response = ahc_handle_msg_reject(ahc, devinfo);
3579 /* FALLTHROUGH */
3580 case MSG_NOOP:
3581 done = MSGLOOP_MSGCOMPLETE;
3582 break;
3583 case MSG_EXTENDED:
3584 {
3585 /* Wait for enough of the message to begin validation */
3586 if (ahc->msgin_index < 2)
3587 break;
3588 switch (ahc->msgin_buf[2]) {
3589 case MSG_EXT_SDTR:
3590 {
3591 const struct ahc_syncrate *syncrate;
3592 u_int period;
3593 u_int ppr_options;
3594 u_int offset;
3595 u_int saved_offset;
3596
3597 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3598 reject = TRUE;
3599 break;
3600 }
3601
3602 /*
3603 * Wait until we have both args before validating
3604 * and acting on this message.
3605 *
3606 * Add one to MSG_EXT_SDTR_LEN to account for
3607 * the extended message preamble.
3608 */
3609 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3610 break;
3611
3612 period = ahc->msgin_buf[3];
3613 ppr_options = 0;
3614 saved_offset = offset = ahc->msgin_buf[4];
3615 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3616 &ppr_options,
3617 devinfo->role);
3618 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3619 targ_scsirate & WIDEXFER,
3620 devinfo->role);
3621 if (bootverbose) {
3622 printk("(%s:%c:%d:%d): Received "
3623 "SDTR period %x, offset %x\n\t"
3624 "Filtered to period %x, offset %x\n",
3625 ahc_name(ahc), devinfo->channel,
3626 devinfo->target, devinfo->lun,
3627 ahc->msgin_buf[3], saved_offset,
3628 period, offset);
3629 }
3630 ahc_set_syncrate(ahc, devinfo,
3631 syncrate, period,
3632 offset, ppr_options,
3633 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3634 /*paused*/TRUE);
3635
3636 /*
3637 * See if we initiated Sync Negotiation
3638 * and didn't have to fall down to async
3639 * transfers.
3640 */
3641 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3642 /* We started it */
3643 if (saved_offset != offset) {
3644 /* Went too low - force async */
3645 reject = TRUE;
3646 }
3647 } else {
3648 /*
3649 * Send our own SDTR in reply
3650 */
3651 if (bootverbose
3652 && devinfo->role == ROLE_INITIATOR) {
3653 printk("(%s:%c:%d:%d): Target "
3654 "Initiated SDTR\n",
3655 ahc_name(ahc), devinfo->channel,
3656 devinfo->target, devinfo->lun);
3657 }
3658 ahc->msgout_index = 0;
3659 ahc->msgout_len = 0;
3660 ahc_construct_sdtr(ahc, devinfo,
3661 period, offset);
3662 ahc->msgout_index = 0;
3663 response = TRUE;
3664 }
3665 done = MSGLOOP_MSGCOMPLETE;
3666 break;
3667 }
3668 case MSG_EXT_WDTR:
3669 {
3670 u_int bus_width;
3671 u_int saved_width;
3672 u_int sending_reply;
3673
3674 sending_reply = FALSE;
3675 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3676 reject = TRUE;
3677 break;
3678 }
3679
3680 /*
3681 * Wait until we have our arg before validating
3682 * and acting on this message.
3683 *
3684 * Add one to MSG_EXT_WDTR_LEN to account for
3685 * the extended message preamble.
3686 */
3687 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3688 break;
3689
3690 bus_width = ahc->msgin_buf[3];
3691 saved_width = bus_width;
3692 ahc_validate_width(ahc, tinfo, &bus_width,
3693 devinfo->role);
3694 if (bootverbose) {
3695 printk("(%s:%c:%d:%d): Received WDTR "
3696 "%x filtered to %x\n",
3697 ahc_name(ahc), devinfo->channel,
3698 devinfo->target, devinfo->lun,
3699 saved_width, bus_width);
3700 }
3701
3702 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3703 /*
3704 * Don't send a WDTR back to the
3705 * target, since we asked first.
3706 * If the width went higher than our
3707 * request, reject it.
3708 */
3709 if (saved_width > bus_width) {
3710 reject = TRUE;
3711 printk("(%s:%c:%d:%d): requested %dBit "
3712 "transfers. Rejecting...\n",
3713 ahc_name(ahc), devinfo->channel,
3714 devinfo->target, devinfo->lun,
3715 8 * (0x01 << bus_width));
3716 bus_width = 0;
3717 }
3718 } else {
3719 /*
3720 * Send our own WDTR in reply
3721 */
3722 if (bootverbose
3723 && devinfo->role == ROLE_INITIATOR) {
3724 printk("(%s:%c:%d:%d): Target "
3725 "Initiated WDTR\n",
3726 ahc_name(ahc), devinfo->channel,
3727 devinfo->target, devinfo->lun);
3728 }
3729 ahc->msgout_index = 0;
3730 ahc->msgout_len = 0;
3731 ahc_construct_wdtr(ahc, devinfo, bus_width);
3732 ahc->msgout_index = 0;
3733 response = TRUE;
3734 sending_reply = TRUE;
3735 }
3736 /*
3737 * After a wide message, we are async, but
3738 * some devices don't seem to honor this portion
3739 * of the spec. Force a renegotiation of the
3740 * sync component of our transfer agreement even
3741 * if our goal is async. By updating our width
3742 * after forcing the negotiation, we avoid
3743 * renegotiating for width.
3744 */
3745 ahc_update_neg_request(ahc, devinfo, tstate,
3746 tinfo, AHC_NEG_ALWAYS);
3747 ahc_set_width(ahc, devinfo, bus_width,
3748 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3749 /*paused*/TRUE);
3750 if (sending_reply == FALSE && reject == FALSE) {
3751
3752 /*
3753 * We will always have an SDTR to send.
3754 */
3755 ahc->msgout_index = 0;
3756 ahc->msgout_len = 0;
3757 ahc_build_transfer_msg(ahc, devinfo);
3758 ahc->msgout_index = 0;
3759 response = TRUE;
3760 }
3761 done = MSGLOOP_MSGCOMPLETE;
3762 break;
3763 }
3764 case MSG_EXT_PPR:
3765 {
3766 const struct ahc_syncrate *syncrate;
3767 u_int period;
3768 u_int offset;
3769 u_int bus_width;
3770 u_int ppr_options;
3771 u_int saved_width;
3772 u_int saved_offset;
3773 u_int saved_ppr_options;
3774
3775 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3776 reject = TRUE;
3777 break;
3778 }
3779
3780 /*
3781 * Wait until we have all args before validating
3782 * and acting on this message.
3783 *
3784 * Add one to MSG_EXT_PPR_LEN to account for
3785 * the extended message preamble.
3786 */
3787 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3788 break;
3789
3790 period = ahc->msgin_buf[3];
3791 offset = ahc->msgin_buf[5];
3792 bus_width = ahc->msgin_buf[6];
3793 saved_width = bus_width;
3794 ppr_options = ahc->msgin_buf[7];
3795 /*
3796 * According to the spec, a DT only
3797 * period factor with no DT option
3798 * set implies async.
3799 */
3800 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3801 && period == 9)
3802 offset = 0;
3803 saved_ppr_options = ppr_options;
3804 saved_offset = offset;
3805
3806 /*
3807 * Mask out any options we don't support
3808 * on any controller. Transfer options are
3809 * only available if we are negotiating wide.
3810 */
3811 ppr_options &= MSG_EXT_PPR_DT_REQ;
3812 if (bus_width == 0)
3813 ppr_options = 0;
3814
3815 ahc_validate_width(ahc, tinfo, &bus_width,
3816 devinfo->role);
3817 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3818 &ppr_options,
3819 devinfo->role);
3820 ahc_validate_offset(ahc, tinfo, syncrate,
3821 &offset, bus_width,
3822 devinfo->role);
3823
3824 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3825 /*
3826 * If we are unable to do any of the
3827 * requested options (we went too low),
3828 * then we'll have to reject the message.
3829 */
3830 if (saved_width > bus_width
3831 || saved_offset != offset
3832 || saved_ppr_options != ppr_options) {
3833 reject = TRUE;
3834 period = 0;
3835 offset = 0;
3836 bus_width = 0;
3837 ppr_options = 0;
3838 syncrate = NULL;
3839 }
3840 } else {
3841 if (devinfo->role != ROLE_TARGET)
3842 printk("(%s:%c:%d:%d): Target "
3843 "Initiated PPR\n",
3844 ahc_name(ahc), devinfo->channel,
3845 devinfo->target, devinfo->lun);
3846 else
3847 printk("(%s:%c:%d:%d): Initiator "
3848 "Initiated PPR\n",
3849 ahc_name(ahc), devinfo->channel,
3850 devinfo->target, devinfo->lun);
3851 ahc->msgout_index = 0;
3852 ahc->msgout_len = 0;
3853 ahc_construct_ppr(ahc, devinfo, period, offset,
3854 bus_width, ppr_options);
3855 ahc->msgout_index = 0;
3856 response = TRUE;
3857 }
3858 if (bootverbose) {
3859 printk("(%s:%c:%d:%d): Received PPR width %x, "
3860 "period %x, offset %x,options %x\n"
3861 "\tFiltered to width %x, period %x, "
3862 "offset %x, options %x\n",
3863 ahc_name(ahc), devinfo->channel,
3864 devinfo->target, devinfo->lun,
3865 saved_width, ahc->msgin_buf[3],
3866 saved_offset, saved_ppr_options,
3867 bus_width, period, offset, ppr_options);
3868 }
3869 ahc_set_width(ahc, devinfo, bus_width,
3870 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3871 /*paused*/TRUE);
3872 ahc_set_syncrate(ahc, devinfo,
3873 syncrate, period,
3874 offset, ppr_options,
3875 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3876 /*paused*/TRUE);
3877 done = MSGLOOP_MSGCOMPLETE;
3878 break;
3879 }
3880 default:
3881 /* Unknown extended message. Reject it. */
3882 reject = TRUE;
3883 break;
3884 }
3885 break;
3886 }
3887 #ifdef AHC_TARGET_MODE
3888 case MSG_BUS_DEV_RESET:
3889 ahc_handle_devreset(ahc, devinfo,
3890 CAM_BDR_SENT,
3891 "Bus Device Reset Received",
3892 /*verbose_level*/0);
3893 ahc_restart(ahc);
3894 done = MSGLOOP_TERMINATED;
3895 break;
3896 case MSG_ABORT_TAG:
3897 case MSG_ABORT:
3898 case MSG_CLEAR_QUEUE:
3899 {
3900 int tag;
3901
3902 /* Target mode messages */
3903 if (devinfo->role != ROLE_TARGET) {
3904 reject = TRUE;
3905 break;
3906 }
3907 tag = SCB_LIST_NULL;
3908 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3909 tag = ahc_inb(ahc, INITIATOR_TAG);
3910 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3911 devinfo->lun, tag, ROLE_TARGET,
3912 CAM_REQ_ABORTED);
3913
3914 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3915 if (tstate != NULL) {
3916 struct ahc_tmode_lstate* lstate;
3917
3918 lstate = tstate->enabled_luns[devinfo->lun];
3919 if (lstate != NULL) {
3920 ahc_queue_lstate_event(ahc, lstate,
3921 devinfo->our_scsiid,
3922 ahc->msgin_buf[0],
3923 /*arg*/tag);
3924 ahc_send_lstate_events(ahc, lstate);
3925 }
3926 }
3927 ahc_restart(ahc);
3928 done = MSGLOOP_TERMINATED;
3929 break;
3930 }
3931 #endif
3932 case MSG_TERM_IO_PROC:
3933 default:
3934 reject = TRUE;
3935 break;
3936 }
3937
3938 if (reject) {
3939 /*
3940 * Setup to reject the message.
3941 */
3942 ahc->msgout_index = 0;
3943 ahc->msgout_len = 1;
3944 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3945 done = MSGLOOP_MSGCOMPLETE;
3946 response = TRUE;
3947 }
3948
3949 if (done != MSGLOOP_IN_PROG && !response)
3950 /* Clear the outgoing message buffer */
3951 ahc->msgout_len = 0;
3952
3953 return (done);
3954 }
3955
3956 /*
3957 * Process a message reject message.
3958 */
3959 static int
3960 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3961 {
3962 /*
3963 * What we care about here is if we had an
3964 * outstanding SDTR or WDTR message for this
3965 * target. If we did, this is a signal that
3966 * the target is refusing negotiation.
3967 */
3968 struct scb *scb;
3969 struct ahc_initiator_tinfo *tinfo;
3970 struct ahc_tmode_tstate *tstate;
3971 u_int scb_index;
3972 u_int last_msg;
3973 int response = 0;
3974
3975 scb_index = ahc_inb(ahc, SCB_TAG);
3976 scb = ahc_lookup_scb(ahc, scb_index);
3977 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3978 devinfo->our_scsiid,
3979 devinfo->target, &tstate);
3980 /* Might be necessary */
3981 last_msg = ahc_inb(ahc, LAST_MSG);
3982
3983 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3984 /*
3985 * Target does not support the PPR message.
3986 * Attempt to negotiate SPI-2 style.
3987 */
3988 if (bootverbose) {
3989 printk("(%s:%c:%d:%d): PPR Rejected. "
3990 "Trying WDTR/SDTR\n",
3991 ahc_name(ahc), devinfo->channel,
3992 devinfo->target, devinfo->lun);
3993 }
3994 tinfo->goal.ppr_options = 0;
3995 tinfo->curr.transport_version = 2;
3996 tinfo->goal.transport_version = 2;
3997 ahc->msgout_index = 0;
3998 ahc->msgout_len = 0;
3999 ahc_build_transfer_msg(ahc, devinfo);
4000 ahc->msgout_index = 0;
4001 response = 1;
4002 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4003
4004 /* note 8bit xfers */
4005 printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4006 "8bit transfers\n", ahc_name(ahc),
4007 devinfo->channel, devinfo->target, devinfo->lun);
4008 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4009 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4010 /*paused*/TRUE);
4011 /*
4012 * No need to clear the sync rate. If the target
4013 * did not accept the command, our syncrate is
4014 * unaffected. If the target started the negotiation,
4015 * but rejected our response, we already cleared the
4016 * sync rate before sending our WDTR.
4017 */
4018 if (tinfo->goal.offset != tinfo->curr.offset) {
4019
4020 /* Start the sync negotiation */
4021 ahc->msgout_index = 0;
4022 ahc->msgout_len = 0;
4023 ahc_build_transfer_msg(ahc, devinfo);
4024 ahc->msgout_index = 0;
4025 response = 1;
4026 }
4027 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4028 /* note asynch xfers and clear flag */
4029 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
4030 /*offset*/0, /*ppr_options*/0,
4031 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4032 /*paused*/TRUE);
4033 printk("(%s:%c:%d:%d): refuses synchronous negotiation. "
4034 "Using asynchronous transfers\n",
4035 ahc_name(ahc), devinfo->channel,
4036 devinfo->target, devinfo->lun);
4037 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4038 int tag_type;
4039 int mask;
4040
4041 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4042
4043 if (tag_type == MSG_SIMPLE_TASK) {
4044 printk("(%s:%c:%d:%d): refuses tagged commands. "
4045 "Performing non-tagged I/O\n", ahc_name(ahc),
4046 devinfo->channel, devinfo->target, devinfo->lun);
4047 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
4048 mask = ~0x23;
4049 } else {
4050 printk("(%s:%c:%d:%d): refuses %s tagged commands. "
4051 "Performing simple queue tagged I/O only\n",
4052 ahc_name(ahc), devinfo->channel, devinfo->target,
4053 devinfo->lun, tag_type == MSG_ORDERED_TASK
4054 ? "ordered" : "head of queue");
4055 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
4056 mask = ~0x03;
4057 }
4058
4059 /*
4060 * Resend the identify for this CCB as the target
4061 * may believe that the selection is invalid otherwise.
4062 */
4063 ahc_outb(ahc, SCB_CONTROL,
4064 ahc_inb(ahc, SCB_CONTROL) & mask);
4065 scb->hscb->control &= mask;
4066 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
4067 /*type*/MSG_SIMPLE_TASK);
4068 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
4069 ahc_assert_atn(ahc);
4070
4071 /*
4072 * This transaction is now at the head of
4073 * the untagged queue for this target.
4074 */
4075 if ((ahc->flags & AHC_SCB_BTT) == 0) {
4076 struct scb_tailq *untagged_q;
4077
4078 untagged_q =
4079 &(ahc->untagged_queues[devinfo->target_offset]);
4080 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
4081 scb->flags |= SCB_UNTAGGEDQ;
4082 }
4083 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4084 scb->hscb->tag);
4085
4086 /*
4087 * Requeue all tagged commands for this target
4088 * currently in our posession so they can be
4089 * converted to untagged commands.
4090 */
4091 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
4092 SCB_GET_CHANNEL(ahc, scb),
4093 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4094 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4095 SEARCH_COMPLETE);
4096 } else {
4097 /*
4098 * Otherwise, we ignore it.
4099 */
4100 printk("%s:%c:%d: Message reject for %x -- ignored\n",
4101 ahc_name(ahc), devinfo->channel, devinfo->target,
4102 last_msg);
4103 }
4104 return (response);
4105 }
4106
4107 /*
4108 * Process an ingnore wide residue message.
4109 */
4110 static void
4111 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4112 {
4113 u_int scb_index;
4114 struct scb *scb;
4115
4116 scb_index = ahc_inb(ahc, SCB_TAG);
4117 scb = ahc_lookup_scb(ahc, scb_index);
4118 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
4119 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
4120 /*
4121 * Ignore the message if we haven't
4122 * seen an appropriate data phase yet.
4123 */
4124 } else {
4125 /*
4126 * If the residual occurred on the last
4127 * transfer and the transfer request was
4128 * expected to end on an odd count, do
4129 * nothing. Otherwise, subtract a byte
4130 * and update the residual count accordingly.
4131 */
4132 uint32_t sgptr;
4133
4134 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4135 if ((sgptr & SG_LIST_NULL) != 0
4136 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
4137 /*
4138 * If the residual occurred on the last
4139 * transfer and the transfer request was
4140 * expected to end on an odd count, do
4141 * nothing.
4142 */
4143 } else {
4144 struct ahc_dma_seg *sg;
4145 uint32_t data_cnt;
4146 uint32_t data_addr;
4147 uint32_t sglen;
4148
4149 /* Pull in all of the sgptr */
4150 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
4151 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
4152
4153 if ((sgptr & SG_LIST_NULL) != 0) {
4154 /*
4155 * The residual data count is not updated
4156 * for the command run to completion case.
4157 * Explicitly zero the count.
4158 */
4159 data_cnt &= ~AHC_SG_LEN_MASK;
4160 }
4161
4162 data_addr = ahc_inl(ahc, SHADDR);
4163
4164 data_cnt += 1;
4165 data_addr -= 1;
4166 sgptr &= SG_PTR_MASK;
4167
4168 sg = ahc_sg_bus_to_virt(scb, sgptr);
4169
4170 /*
4171 * The residual sg ptr points to the next S/G
4172 * to load so we must go back one.
4173 */
4174 sg--;
4175 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
4176 if (sg != scb->sg_list
4177 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
4178
4179 sg--;
4180 sglen = ahc_le32toh(sg->len);
4181 /*
4182 * Preserve High Address and SG_LIST bits
4183 * while setting the count to 1.
4184 */
4185 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
4186 data_addr = ahc_le32toh(sg->addr)
4187 + (sglen & AHC_SG_LEN_MASK) - 1;
4188
4189 /*
4190 * Increment sg so it points to the
4191 * "next" sg.
4192 */
4193 sg++;
4194 sgptr = ahc_sg_virt_to_bus(scb, sg);
4195 }
4196 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
4197 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
4198 /*
4199 * Toggle the "oddness" of the transfer length
4200 * to handle this mid-transfer ignore wide
4201 * residue. This ensures that the oddness is
4202 * correct for subsequent data transfers.
4203 */
4204 ahc_outb(ahc, SCB_LUN,
4205 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
4206 }
4207 }
4208 }
4209
4210
4211 /*
4212 * Reinitialize the data pointers for the active transfer
4213 * based on its current residual.
4214 */
4215 static void
4216 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
4217 {
4218 struct scb *scb;
4219 struct ahc_dma_seg *sg;
4220 u_int scb_index;
4221 uint32_t sgptr;
4222 uint32_t resid;
4223 uint32_t dataptr;
4224
4225 scb_index = ahc_inb(ahc, SCB_TAG);
4226 scb = ahc_lookup_scb(ahc, scb_index);
4227 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
4228 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
4229 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
4230 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4231
4232 sgptr &= SG_PTR_MASK;
4233 sg = ahc_sg_bus_to_virt(scb, sgptr);
4234
4235 /* The residual sg_ptr always points to the next sg */
4236 sg--;
4237
4238 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
4239 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
4240 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
4241
4242 dataptr = ahc_le32toh(sg->addr)
4243 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
4244 - resid;
4245 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
4246 u_int dscommand1;
4247
4248 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
4249 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
4250 ahc_outb(ahc, HADDR,
4251 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
4252 ahc_outb(ahc, DSCOMMAND1, dscommand1);
4253 }
4254 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
4255 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
4256 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
4257 ahc_outb(ahc, HADDR, dataptr);
4258 ahc_outb(ahc, HCNT + 2, resid >> 16);
4259 ahc_outb(ahc, HCNT + 1, resid >> 8);
4260 ahc_outb(ahc, HCNT, resid);
4261 if ((ahc->features & AHC_ULTRA2) == 0) {
4262 ahc_outb(ahc, STCNT + 2, resid >> 16);
4263 ahc_outb(ahc, STCNT + 1, resid >> 8);
4264 ahc_outb(ahc, STCNT, resid);
4265 }
4266 }
4267
4268 /*
4269 * Handle the effects of issuing a bus device reset message.
4270 */
4271 static void
4272 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4273 cam_status status, char *message, int verbose_level)
4274 {
4275 #ifdef AHC_TARGET_MODE
4276 struct ahc_tmode_tstate* tstate;
4277 u_int lun;
4278 #endif
4279 int found;
4280
4281 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
4282 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
4283 status);
4284
4285 #ifdef AHC_TARGET_MODE
4286 /*
4287 * Send an immediate notify ccb to all target mord peripheral
4288 * drivers affected by this action.
4289 */
4290 tstate = ahc->enabled_targets[devinfo->our_scsiid];
4291 if (tstate != NULL) {
4292 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
4293 struct ahc_tmode_lstate* lstate;
4294
4295 lstate = tstate->enabled_luns[lun];
4296 if (lstate == NULL)
4297 continue;
4298
4299 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
4300 MSG_BUS_DEV_RESET, /*arg*/0);
4301 ahc_send_lstate_events(ahc, lstate);
4302 }
4303 }
4304 #endif
4305
4306 /*
4307 * Go back to async/narrow transfers and renegotiate.
4308 */
4309 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4310 AHC_TRANS_CUR, /*paused*/TRUE);
4311 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
4312 /*period*/0, /*offset*/0, /*ppr_options*/0,
4313 AHC_TRANS_CUR, /*paused*/TRUE);
4314
4315 if (status != CAM_SEL_TIMEOUT)
4316 ahc_send_async(ahc, devinfo->channel, devinfo->target,
4317 CAM_LUN_WILDCARD, AC_SENT_BDR);
4318
4319 if (message != NULL
4320 && (verbose_level <= bootverbose))
4321 printk("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
4322 message, devinfo->channel, devinfo->target, found);
4323 }
4324
4325 #ifdef AHC_TARGET_MODE
4326 static void
4327 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4328 struct scb *scb)
4329 {
4330
4331 /*
4332 * To facilitate adding multiple messages together,
4333 * each routine should increment the index and len
4334 * variables instead of setting them explicitly.
4335 */
4336 ahc->msgout_index = 0;
4337 ahc->msgout_len = 0;
4338
4339 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
4340 ahc_build_transfer_msg(ahc, devinfo);
4341 else
4342 panic("ahc_intr: AWAITING target message with no message");
4343
4344 ahc->msgout_index = 0;
4345 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
4346 }
4347 #endif
4348 /**************************** Initialization **********************************/
4349 /*
4350 * Allocate a controller structure for a new device
4351 * and perform initial initializion.
4352 */
4353 struct ahc_softc *
4354 ahc_alloc(void *platform_arg, char *name)
4355 {
4356 struct ahc_softc *ahc;
4357 int i;
4358
4359 #ifndef __FreeBSD__
4360 ahc = kmalloc(sizeof(*ahc), GFP_ATOMIC);
4361 if (!ahc) {
4362 printk("aic7xxx: cannot malloc softc!\n");
4363 kfree(name);
4364 return NULL;
4365 }
4366 #else
4367 ahc = device_get_softc((device_t)platform_arg);
4368 #endif
4369 memset(ahc, 0, sizeof(*ahc));
4370 ahc->seep_config = kmalloc(sizeof(*ahc->seep_config), GFP_ATOMIC);
4371 if (ahc->seep_config == NULL) {
4372 #ifndef __FreeBSD__
4373 kfree(ahc);
4374 #endif
4375 kfree(name);
4376 return (NULL);
4377 }
4378 LIST_INIT(&ahc->pending_scbs);
4379 /* We don't know our unit number until the OSM sets it */
4380 ahc->name = name;
4381 ahc->unit = -1;
4382 ahc->description = NULL;
4383 ahc->channel = 'A';
4384 ahc->channel_b = 'B';
4385 ahc->chip = AHC_NONE;
4386 ahc->features = AHC_FENONE;
4387 ahc->bugs = AHC_BUGNONE;
4388 ahc->flags = AHC_FNONE;
4389 /*
4390 * Default to all error reporting enabled with the
4391 * sequencer operating at its fastest speed.
4392 * The bus attach code may modify this.
4393 */
4394 ahc->seqctl = FASTMODE;
4395
4396 for (i = 0; i < AHC_NUM_TARGETS; i++)
4397 TAILQ_INIT(&ahc->untagged_queues[i]);
4398 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
4399 ahc_free(ahc);
4400 ahc = NULL;
4401 }
4402 return (ahc);
4403 }
4404
4405 int
4406 ahc_softc_init(struct ahc_softc *ahc)
4407 {
4408
4409 /* The IRQMS bit is only valid on VL and EISA chips */
4410 if ((ahc->chip & AHC_PCI) == 0)
4411 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
4412 else
4413 ahc->unpause = 0;
4414 ahc->pause = ahc->unpause | PAUSE;
4415 if (ahc->scb_data == NULL) {
4416 ahc->scb_data = kmalloc(sizeof(*ahc->scb_data), GFP_ATOMIC);
4417 if (ahc->scb_data == NULL)
4418 return (ENOMEM);
4419 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
4420 }
4421
4422 return (0);
4423 }
4424
4425 void
4426 ahc_set_unit(struct ahc_softc *ahc, int unit)
4427 {
4428 ahc->unit = unit;
4429 }
4430
4431 void
4432 ahc_set_name(struct ahc_softc *ahc, char *name)
4433 {
4434 if (ahc->name != NULL)
4435 kfree(ahc->name);
4436 ahc->name = name;
4437 }
4438
4439 void
4440 ahc_free(struct ahc_softc *ahc)
4441 {
4442 int i;
4443
4444 switch (ahc->init_level) {
4445 default:
4446 case 5:
4447 ahc_shutdown(ahc);
4448 /* FALLTHROUGH */
4449 case 4:
4450 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
4451 ahc->shared_data_dmamap);
4452 /* FALLTHROUGH */
4453 case 3:
4454 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4455 ahc->shared_data_dmamap);
4456 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
4457 ahc->shared_data_dmamap);
4458 /* FALLTHROUGH */
4459 case 2:
4460 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4461 case 1:
4462 #ifndef __linux__
4463 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
4464 #endif
4465 break;
4466 case 0:
4467 break;
4468 }
4469
4470 #ifndef __linux__
4471 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
4472 #endif
4473 ahc_platform_free(ahc);
4474 ahc_fini_scbdata(ahc);
4475 for (i = 0; i < AHC_NUM_TARGETS; i++) {
4476 struct ahc_tmode_tstate *tstate;
4477
4478 tstate = ahc->enabled_targets[i];
4479 if (tstate != NULL) {
4480 #ifdef AHC_TARGET_MODE
4481 int j;
4482
4483 for (j = 0; j < AHC_NUM_LUNS; j++) {
4484 struct ahc_tmode_lstate *lstate;
4485
4486 lstate = tstate->enabled_luns[j];
4487 if (lstate != NULL) {
4488 xpt_free_path(lstate->path);
4489 kfree(lstate);
4490 }
4491 }
4492 #endif
4493 kfree(tstate);
4494 }
4495 }
4496 #ifdef AHC_TARGET_MODE
4497 if (ahc->black_hole != NULL) {
4498 xpt_free_path(ahc->black_hole->path);
4499 kfree(ahc->black_hole);
4500 }
4501 #endif
4502 if (ahc->name != NULL)
4503 kfree(ahc->name);
4504 if (ahc->seep_config != NULL)
4505 kfree(ahc->seep_config);
4506 #ifndef __FreeBSD__
4507 kfree(ahc);
4508 #endif
4509 return;
4510 }
4511
4512 static void
4513 ahc_shutdown(void *arg)
4514 {
4515 struct ahc_softc *ahc;
4516 int i;
4517
4518 ahc = (struct ahc_softc *)arg;
4519
4520 /* This will reset most registers to 0, but not all */
4521 ahc_reset(ahc, /*reinit*/FALSE);
4522 ahc_outb(ahc, SCSISEQ, 0);
4523 ahc_outb(ahc, SXFRCTL0, 0);
4524 ahc_outb(ahc, DSPCISTATUS, 0);
4525
4526 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4527 ahc_outb(ahc, i, 0);
4528 }
4529
4530 /*
4531 * Reset the controller and record some information about it
4532 * that is only available just after a reset. If "reinit" is
4533 * non-zero, this reset occured after initial configuration
4534 * and the caller requests that the chip be fully reinitialized
4535 * to a runable state. Chip interrupts are *not* enabled after
4536 * a reinitialization. The caller must enable interrupts via
4537 * ahc_intr_enable().
4538 */
4539 int
4540 ahc_reset(struct ahc_softc *ahc, int reinit)
4541 {
4542 u_int sblkctl;
4543 u_int sxfrctl1_a, sxfrctl1_b;
4544 int error;
4545 int wait;
4546
4547 /*
4548 * Preserve the value of the SXFRCTL1 register for all channels.
4549 * It contains settings that affect termination and we don't want
4550 * to disturb the integrity of the bus.
4551 */
4552 ahc_pause(ahc);
4553 sxfrctl1_b = 0;
4554 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4555 u_int sblkctl;
4556
4557 /*
4558 * Save channel B's settings in case this chip
4559 * is setup for TWIN channel operation.
4560 */
4561 sblkctl = ahc_inb(ahc, SBLKCTL);
4562 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4563 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4564 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4565 }
4566 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4567
4568 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4569
4570 /*
4571 * Ensure that the reset has finished. We delay 1000us
4572 * prior to reading the register to make sure the chip
4573 * has sufficiently completed its reset to handle register
4574 * accesses.
4575 */
4576 wait = 1000;
4577 do {
4578 ahc_delay(1000);
4579 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4580
4581 if (wait == 0) {
4582 printk("%s: WARNING - Failed chip reset! "
4583 "Trying to initialize anyway.\n", ahc_name(ahc));
4584 }
4585 ahc_outb(ahc, HCNTRL, ahc->pause);
4586
4587 /* Determine channel configuration */
4588 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4589 /* No Twin Channel PCI cards */
4590 if ((ahc->chip & AHC_PCI) != 0)
4591 sblkctl &= ~SELBUSB;
4592 switch (sblkctl) {
4593 case 0:
4594 /* Single Narrow Channel */
4595 break;
4596 case 2:
4597 /* Wide Channel */
4598 ahc->features |= AHC_WIDE;
4599 break;
4600 case 8:
4601 /* Twin Channel */
4602 ahc->features |= AHC_TWIN;
4603 break;
4604 default:
4605 printk(" Unsupported adapter type. Ignoring\n");
4606 return(-1);
4607 }
4608
4609 /*
4610 * Reload sxfrctl1.
4611 *
4612 * We must always initialize STPWEN to 1 before we
4613 * restore the saved values. STPWEN is initialized
4614 * to a tri-state condition which can only be cleared
4615 * by turning it on.
4616 */
4617 if ((ahc->features & AHC_TWIN) != 0) {
4618 u_int sblkctl;
4619
4620 sblkctl = ahc_inb(ahc, SBLKCTL);
4621 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4622 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4623 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4624 }
4625 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4626
4627 error = 0;
4628 if (reinit != 0)
4629 /*
4630 * If a recovery action has forced a chip reset,
4631 * re-initialize the chip to our liking.
4632 */
4633 error = ahc->bus_chip_init(ahc);
4634 #ifdef AHC_DUMP_SEQ
4635 else
4636 ahc_dumpseq(ahc);
4637 #endif
4638
4639 return (error);
4640 }
4641
4642 /*
4643 * Determine the number of SCBs available on the controller
4644 */
4645 int
4646 ahc_probe_scbs(struct ahc_softc *ahc) {
4647 int i;
4648
4649 for (i = 0; i < AHC_SCB_MAX; i++) {
4650
4651 ahc_outb(ahc, SCBPTR, i);
4652 ahc_outb(ahc, SCB_BASE, i);
4653 if (ahc_inb(ahc, SCB_BASE) != i)
4654 break;
4655 ahc_outb(ahc, SCBPTR, 0);
4656 if (ahc_inb(ahc, SCB_BASE) != 0)
4657 break;
4658 }
4659 return (i);
4660 }
4661
4662 static void
4663 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4664 {
4665 dma_addr_t *baddr;
4666
4667 baddr = (dma_addr_t *)arg;
4668 *baddr = segs->ds_addr;
4669 }
4670
4671 static void
4672 ahc_build_free_scb_list(struct ahc_softc *ahc)
4673 {
4674 int scbsize;
4675 int i;
4676
4677 scbsize = 32;
4678 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4679 scbsize = 64;
4680
4681 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4682 int j;
4683
4684 ahc_outb(ahc, SCBPTR, i);
4685
4686 /*
4687 * Touch all SCB bytes to avoid parity errors
4688 * should one of our debugging routines read
4689 * an otherwise uninitiatlized byte.
4690 */
4691 for (j = 0; j < scbsize; j++)
4692 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4693
4694 /* Clear the control byte. */
4695 ahc_outb(ahc, SCB_CONTROL, 0);
4696
4697 /* Set the next pointer */
4698 if ((ahc->flags & AHC_PAGESCBS) != 0)
4699 ahc_outb(ahc, SCB_NEXT, i+1);
4700 else
4701 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4702
4703 /* Make the tag number, SCSIID, and lun invalid */
4704 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4705 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4706 ahc_outb(ahc, SCB_LUN, 0xFF);
4707 }
4708
4709 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4710 /* SCB 0 heads the free list. */
4711 ahc_outb(ahc, FREE_SCBH, 0);
4712 } else {
4713 /* No free list. */
4714 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4715 }
4716
4717 /* Make sure that the last SCB terminates the free list */
4718 ahc_outb(ahc, SCBPTR, i-1);
4719 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4720 }
4721
4722 static int
4723 ahc_init_scbdata(struct ahc_softc *ahc)
4724 {
4725 struct scb_data *scb_data;
4726
4727 scb_data = ahc->scb_data;
4728 SLIST_INIT(&scb_data->free_scbs);
4729 SLIST_INIT(&scb_data->sg_maps);
4730
4731 /* Allocate SCB resources */
4732 scb_data->scbarray = (struct scb *)kmalloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, GFP_ATOMIC);
4733 if (scb_data->scbarray == NULL)
4734 return (ENOMEM);
4735 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4736
4737 /* Determine the number of hardware SCBs and initialize them */
4738
4739 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4740 if (ahc->scb_data->maxhscbs == 0) {
4741 printk("%s: No SCB space found\n", ahc_name(ahc));
4742 return (ENXIO);
4743 }
4744
4745 /*
4746 * Create our DMA tags. These tags define the kinds of device
4747 * accessible memory allocations and memory mappings we will
4748 * need to perform during normal operation.
4749 *
4750 * Unless we need to further restrict the allocation, we rely
4751 * on the restrictions of the parent dmat, hence the common
4752 * use of MAXADDR and MAXSIZE.
4753 */
4754
4755 /* DMA tag for our hardware scb structures */
4756 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4757 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4758 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4759 /*highaddr*/BUS_SPACE_MAXADDR,
4760 /*filter*/NULL, /*filterarg*/NULL,
4761 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4762 /*nsegments*/1,
4763 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4764 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4765 goto error_exit;
4766 }
4767
4768 scb_data->init_level++;
4769
4770 /* Allocation for our hscbs */
4771 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4772 (void **)&scb_data->hscbs,
4773 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4774 goto error_exit;
4775 }
4776
4777 scb_data->init_level++;
4778
4779 /* And permanently map them */
4780 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4781 scb_data->hscbs,
4782 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4783 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4784
4785 scb_data->init_level++;
4786
4787 /* DMA tag for our sense buffers */
4788 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4789 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4790 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4791 /*highaddr*/BUS_SPACE_MAXADDR,
4792 /*filter*/NULL, /*filterarg*/NULL,
4793 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4794 /*nsegments*/1,
4795 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4796 /*flags*/0, &scb_data->sense_dmat) != 0) {
4797 goto error_exit;
4798 }
4799
4800 scb_data->init_level++;
4801
4802 /* Allocate them */
4803 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4804 (void **)&scb_data->sense,
4805 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4806 goto error_exit;
4807 }
4808
4809 scb_data->init_level++;
4810
4811 /* And permanently map them */
4812 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4813 scb_data->sense,
4814 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4815 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4816
4817 scb_data->init_level++;
4818
4819 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4820 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4821 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4822 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4823 /*highaddr*/BUS_SPACE_MAXADDR,
4824 /*filter*/NULL, /*filterarg*/NULL,
4825 PAGE_SIZE, /*nsegments*/1,
4826 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4827 /*flags*/0, &scb_data->sg_dmat) != 0) {
4828 goto error_exit;
4829 }
4830
4831 scb_data->init_level++;
4832
4833 /* Perform initial CCB allocation */
4834 memset(scb_data->hscbs, 0,
4835 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4836 ahc_alloc_scbs(ahc);
4837
4838 if (scb_data->numscbs == 0) {
4839 printk("%s: ahc_init_scbdata - "
4840 "Unable to allocate initial scbs\n",
4841 ahc_name(ahc));
4842 goto error_exit;
4843 }
4844
4845 /*
4846 * Reserve the next queued SCB.
4847 */
4848 ahc->next_queued_scb = ahc_get_scb(ahc);
4849
4850 /*
4851 * Note that we were successfull
4852 */
4853 return (0);
4854
4855 error_exit:
4856
4857 return (ENOMEM);
4858 }
4859
4860 static void
4861 ahc_fini_scbdata(struct ahc_softc *ahc)
4862 {
4863 struct scb_data *scb_data;
4864
4865 scb_data = ahc->scb_data;
4866 if (scb_data == NULL)
4867 return;
4868
4869 switch (scb_data->init_level) {
4870 default:
4871 case 7:
4872 {
4873 struct sg_map_node *sg_map;
4874
4875 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4876 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4877 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4878 sg_map->sg_dmamap);
4879 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4880 sg_map->sg_vaddr,
4881 sg_map->sg_dmamap);
4882 kfree(sg_map);
4883 }
4884 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4885 }
4886 case 6:
4887 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4888 scb_data->sense_dmamap);
4889 case 5:
4890 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4891 scb_data->sense_dmamap);
4892 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4893 scb_data->sense_dmamap);
4894 case 4:
4895 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4896 case 3:
4897 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4898 scb_data->hscb_dmamap);
4899 case 2:
4900 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4901 scb_data->hscb_dmamap);
4902 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4903 scb_data->hscb_dmamap);
4904 case 1:
4905 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4906 break;
4907 case 0:
4908 break;
4909 }
4910 if (scb_data->scbarray != NULL)
4911 kfree(scb_data->scbarray);
4912 }
4913
4914 static void
4915 ahc_alloc_scbs(struct ahc_softc *ahc)
4916 {
4917 struct scb_data *scb_data;
4918 struct scb *next_scb;
4919 struct sg_map_node *sg_map;
4920 dma_addr_t physaddr;
4921 struct ahc_dma_seg *segs;
4922 int newcount;
4923 int i;
4924
4925 scb_data = ahc->scb_data;
4926 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4927 /* Can't allocate any more */
4928 return;
4929
4930 next_scb = &scb_data->scbarray[scb_data->numscbs];
4931
4932 sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC);
4933
4934 if (sg_map == NULL)
4935 return;
4936
4937 /* Allocate S/G space for the next batch of SCBS */
4938 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4939 (void **)&sg_map->sg_vaddr,
4940 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4941 kfree(sg_map);
4942 return;
4943 }
4944
4945 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4946
4947 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4948 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4949 &sg_map->sg_physaddr, /*flags*/0);
4950
4951 segs = sg_map->sg_vaddr;
4952 physaddr = sg_map->sg_physaddr;
4953
4954 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4955 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4956 for (i = 0; i < newcount; i++) {
4957 struct scb_platform_data *pdata;
4958 #ifndef __linux__
4959 int error;
4960 #endif
4961 pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC);
4962 if (pdata == NULL)
4963 break;
4964 next_scb->platform_data = pdata;
4965 next_scb->sg_map = sg_map;
4966 next_scb->sg_list = segs;
4967 /*
4968 * The sequencer always starts with the second entry.
4969 * The first entry is embedded in the scb.
4970 */
4971 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4972 next_scb->ahc_softc = ahc;
4973 next_scb->flags = SCB_FREE;
4974 #ifndef __linux__
4975 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4976 &next_scb->dmamap);
4977 if (error != 0)
4978 break;
4979 #endif
4980 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4981 next_scb->hscb->tag = ahc->scb_data->numscbs;
4982 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4983 next_scb, links.sle);
4984 segs += AHC_NSEG;
4985 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4986 next_scb++;
4987 ahc->scb_data->numscbs++;
4988 }
4989 }
4990
4991 void
4992 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4993 {
4994 int len;
4995
4996 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4997 buf += len;
4998 if ((ahc->features & AHC_TWIN) != 0)
4999 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
5000 "B SCSI Id=%d, primary %c, ",
5001 ahc->our_id, ahc->our_id_b,
5002 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
5003 else {
5004 const char *speed;
5005 const char *type;
5006
5007 speed = "";
5008 if ((ahc->features & AHC_ULTRA) != 0) {
5009 speed = "Ultra ";
5010 } else if ((ahc->features & AHC_DT) != 0) {
5011 speed = "Ultra160 ";
5012 } else if ((ahc->features & AHC_ULTRA2) != 0) {
5013 speed = "Ultra2 ";
5014 }
5015 if ((ahc->features & AHC_WIDE) != 0) {
5016 type = "Wide";
5017 } else {
5018 type = "Single";
5019 }
5020 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
5021 speed, type, ahc->channel, ahc->our_id);
5022 }
5023 buf += len;
5024
5025 if ((ahc->flags & AHC_PAGESCBS) != 0)
5026 sprintf(buf, "%d/%d SCBs",
5027 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
5028 else
5029 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
5030 }
5031
5032 int
5033 ahc_chip_init(struct ahc_softc *ahc)
5034 {
5035 int term;
5036 int error;
5037 u_int i;
5038 u_int scsi_conf;
5039 u_int scsiseq_template;
5040 uint32_t physaddr;
5041
5042 ahc_outb(ahc, SEQ_FLAGS, 0);
5043 ahc_outb(ahc, SEQ_FLAGS2, 0);
5044
5045 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
5046 if (ahc->features & AHC_TWIN) {
5047
5048 /*
5049 * Setup Channel B first.
5050 */
5051 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
5052 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
5053 ahc_outb(ahc, SCSIID, ahc->our_id_b);
5054 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5055 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5056 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
5057 if ((ahc->features & AHC_ULTRA2) != 0)
5058 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5059 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5060 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5061
5062 /* Select Channel A */
5063 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
5064 }
5065 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
5066 if ((ahc->features & AHC_ULTRA2) != 0)
5067 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
5068 else
5069 ahc_outb(ahc, SCSIID, ahc->our_id);
5070 scsi_conf = ahc_inb(ahc, SCSICONF);
5071 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5072 |term|ahc->seltime
5073 |ENSTIMER|ACTNEGEN);
5074 if ((ahc->features & AHC_ULTRA2) != 0)
5075 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5076 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5077 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5078
5079 /* There are no untagged SCBs active yet. */
5080 for (i = 0; i < 16; i++) {
5081 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
5082 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5083 int lun;
5084
5085 /*
5086 * The SCB based BTT allows an entry per
5087 * target and lun pair.
5088 */
5089 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
5090 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
5091 }
5092 }
5093
5094 /* All of our queues are empty */
5095 for (i = 0; i < 256; i++)
5096 ahc->qoutfifo[i] = SCB_LIST_NULL;
5097 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
5098
5099 for (i = 0; i < 256; i++)
5100 ahc->qinfifo[i] = SCB_LIST_NULL;
5101
5102 if ((ahc->features & AHC_MULTI_TID) != 0) {
5103 ahc_outb(ahc, TARGID, 0);
5104 ahc_outb(ahc, TARGID + 1, 0);
5105 }
5106
5107 /*
5108 * Tell the sequencer where it can find our arrays in memory.
5109 */
5110 physaddr = ahc->scb_data->hscb_busaddr;
5111 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
5112 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
5113 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
5114 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
5115
5116 physaddr = ahc->shared_data_busaddr;
5117 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
5118 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
5119 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
5120 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
5121
5122 /*
5123 * Initialize the group code to command length table.
5124 * This overrides the values in TARG_SCSIRATE, so only
5125 * setup the table after we have processed that information.
5126 */
5127 ahc_outb(ahc, CMDSIZE_TABLE, 5);
5128 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
5129 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
5130 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
5131 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
5132 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
5133 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
5134 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
5135
5136 if ((ahc->features & AHC_HS_MAILBOX) != 0)
5137 ahc_outb(ahc, HS_MAILBOX, 0);
5138
5139 /* Tell the sequencer of our initial queue positions */
5140 if ((ahc->features & AHC_TARGETMODE) != 0) {
5141 ahc->tqinfifonext = 1;
5142 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
5143 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
5144 }
5145 ahc->qinfifonext = 0;
5146 ahc->qoutfifonext = 0;
5147 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5148 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
5149 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5150 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
5151 ahc_outb(ahc, SDSCB_QOFF, 0);
5152 } else {
5153 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5154 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
5155 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
5156 }
5157
5158 /* We don't have any waiting selections */
5159 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
5160
5161 /* Our disconnection list is empty too */
5162 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
5163
5164 /* Message out buffer starts empty */
5165 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
5166
5167 /*
5168 * Setup the allowed SCSI Sequences based on operational mode.
5169 * If we are a target, we'll enable select in operations once
5170 * we've had a lun enabled.
5171 */
5172 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
5173 if ((ahc->flags & AHC_INITIATORROLE) != 0)
5174 scsiseq_template |= ENRSELI;
5175 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
5176
5177 /* Initialize our list of free SCBs. */
5178 ahc_build_free_scb_list(ahc);
5179
5180 /*
5181 * Tell the sequencer which SCB will be the next one it receives.
5182 */
5183 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5184
5185 /*
5186 * Load the Sequencer program and Enable the adapter
5187 * in "fast" mode.
5188 */
5189 if (bootverbose)
5190 printk("%s: Downloading Sequencer Program...",
5191 ahc_name(ahc));
5192
5193 error = ahc_loadseq(ahc);
5194 if (error != 0)
5195 return (error);
5196
5197 if ((ahc->features & AHC_ULTRA2) != 0) {
5198 int wait;
5199
5200 /*
5201 * Wait for up to 500ms for our transceivers
5202 * to settle. If the adapter does not have
5203 * a cable attached, the transceivers may
5204 * never settle, so don't complain if we
5205 * fail here.
5206 */
5207 for (wait = 5000;
5208 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
5209 wait--)
5210 ahc_delay(100);
5211 }
5212 ahc_restart(ahc);
5213 return (0);
5214 }
5215
5216 /*
5217 * Start the board, ready for normal operation
5218 */
5219 int
5220 ahc_init(struct ahc_softc *ahc)
5221 {
5222 int max_targ;
5223 u_int i;
5224 u_int scsi_conf;
5225 u_int ultraenb;
5226 u_int discenable;
5227 u_int tagenable;
5228 size_t driver_data_size;
5229
5230 #ifdef AHC_DEBUG
5231 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
5232 ahc->flags |= AHC_SEQUENCER_DEBUG;
5233 #endif
5234
5235 #ifdef AHC_PRINT_SRAM
5236 printk("Scratch Ram:");
5237 for (i = 0x20; i < 0x5f; i++) {
5238 if (((i % 8) == 0) && (i != 0)) {
5239 printk ("\n ");
5240 }
5241 printk (" 0x%x", ahc_inb(ahc, i));
5242 }
5243 if ((ahc->features & AHC_MORE_SRAM) != 0) {
5244 for (i = 0x70; i < 0x7f; i++) {
5245 if (((i % 8) == 0) && (i != 0)) {
5246 printk ("\n ");
5247 }
5248 printk (" 0x%x", ahc_inb(ahc, i));
5249 }
5250 }
5251 printk ("\n");
5252 /*
5253 * Reading uninitialized scratch ram may
5254 * generate parity errors.
5255 */
5256 ahc_outb(ahc, CLRINT, CLRPARERR);
5257 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
5258 #endif
5259 max_targ = 15;
5260
5261 /*
5262 * Assume we have a board at this stage and it has been reset.
5263 */
5264 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
5265 ahc->our_id = ahc->our_id_b = 7;
5266
5267 /*
5268 * Default to allowing initiator operations.
5269 */
5270 ahc->flags |= AHC_INITIATORROLE;
5271
5272 /*
5273 * Only allow target mode features if this unit has them enabled.
5274 */
5275 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
5276 ahc->features &= ~AHC_TARGETMODE;
5277
5278 #ifndef __linux__
5279 /* DMA tag for mapping buffers into device visible space. */
5280 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5281 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5282 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
5283 ? (dma_addr_t)0x7FFFFFFFFFULL
5284 : BUS_SPACE_MAXADDR_32BIT,
5285 /*highaddr*/BUS_SPACE_MAXADDR,
5286 /*filter*/NULL, /*filterarg*/NULL,
5287 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
5288 /*nsegments*/AHC_NSEG,
5289 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
5290 /*flags*/BUS_DMA_ALLOCNOW,
5291 &ahc->buffer_dmat) != 0) {
5292 return (ENOMEM);
5293 }
5294 #endif
5295
5296 ahc->init_level++;
5297
5298 /*
5299 * DMA tag for our command fifos and other data in system memory
5300 * the card's sequencer must be able to access. For initiator
5301 * roles, we need to allocate space for the qinfifo and qoutfifo.
5302 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
5303 * When providing for the target mode role, we must additionally
5304 * provide space for the incoming target command fifo and an extra
5305 * byte to deal with a dma bug in some chip versions.
5306 */
5307 driver_data_size = 2 * 256 * sizeof(uint8_t);
5308 if ((ahc->features & AHC_TARGETMODE) != 0)
5309 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
5310 + /*DMA WideOdd Bug Buffer*/1;
5311 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5312 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5313 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5314 /*highaddr*/BUS_SPACE_MAXADDR,
5315 /*filter*/NULL, /*filterarg*/NULL,
5316 driver_data_size,
5317 /*nsegments*/1,
5318 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5319 /*flags*/0, &ahc->shared_data_dmat) != 0) {
5320 return (ENOMEM);
5321 }
5322
5323 ahc->init_level++;
5324
5325 /* Allocation of driver data */
5326 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
5327 (void **)&ahc->qoutfifo,
5328 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
5329 return (ENOMEM);
5330 }
5331
5332 ahc->init_level++;
5333
5334 /* And permanently map it in */
5335 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
5336 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
5337 &ahc->shared_data_busaddr, /*flags*/0);
5338
5339 if ((ahc->features & AHC_TARGETMODE) != 0) {
5340 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
5341 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
5342 ahc->dma_bug_buf = ahc->shared_data_busaddr
5343 + driver_data_size - 1;
5344 /* All target command blocks start out invalid. */
5345 for (i = 0; i < AHC_TMODE_CMDS; i++)
5346 ahc->targetcmds[i].cmd_valid = 0;
5347 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
5348 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
5349 }
5350 ahc->qinfifo = &ahc->qoutfifo[256];
5351
5352 ahc->init_level++;
5353
5354 /* Allocate SCB data now that buffer_dmat is initialized */
5355 if (ahc->scb_data->maxhscbs == 0)
5356 if (ahc_init_scbdata(ahc) != 0)
5357 return (ENOMEM);
5358
5359 /*
5360 * Allocate a tstate to house information for our
5361 * initiator presence on the bus as well as the user
5362 * data for any target mode initiator.
5363 */
5364 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
5365 printk("%s: unable to allocate ahc_tmode_tstate. "
5366 "Failing attach\n", ahc_name(ahc));
5367 return (ENOMEM);
5368 }
5369
5370 if ((ahc->features & AHC_TWIN) != 0) {
5371 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
5372 printk("%s: unable to allocate ahc_tmode_tstate. "
5373 "Failing attach\n", ahc_name(ahc));
5374 return (ENOMEM);
5375 }
5376 }
5377
5378 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5379 ahc->flags |= AHC_PAGESCBS;
5380 } else {
5381 ahc->flags &= ~AHC_PAGESCBS;
5382 }
5383
5384 #ifdef AHC_DEBUG
5385 if (ahc_debug & AHC_SHOW_MISC) {
5386 printk("%s: hardware scb %u bytes; kernel scb %u bytes; "
5387 "ahc_dma %u bytes\n",
5388 ahc_name(ahc),
5389 (u_int)sizeof(struct hardware_scb),
5390 (u_int)sizeof(struct scb),
5391 (u_int)sizeof(struct ahc_dma_seg));
5392 }
5393 #endif /* AHC_DEBUG */
5394
5395 /*
5396 * Look at the information that board initialization or
5397 * the board bios has left us.
5398 */
5399 if (ahc->features & AHC_TWIN) {
5400 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5401 if ((scsi_conf & RESET_SCSI) != 0
5402 && (ahc->flags & AHC_INITIATORROLE) != 0)
5403 ahc->flags |= AHC_RESET_BUS_B;
5404 }
5405
5406 scsi_conf = ahc_inb(ahc, SCSICONF);
5407 if ((scsi_conf & RESET_SCSI) != 0
5408 && (ahc->flags & AHC_INITIATORROLE) != 0)
5409 ahc->flags |= AHC_RESET_BUS_A;
5410
5411 ultraenb = 0;
5412 tagenable = ALL_TARGETS_MASK;
5413
5414 /* Grab the disconnection disable table and invert it for our needs */
5415 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5416 printk("%s: Host Adapter Bios disabled. Using default SCSI "
5417 "device parameters\n", ahc_name(ahc));
5418 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5419 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5420 discenable = ALL_TARGETS_MASK;
5421 if ((ahc->features & AHC_ULTRA) != 0)
5422 ultraenb = ALL_TARGETS_MASK;
5423 } else {
5424 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5425 | ahc_inb(ahc, DISC_DSB));
5426 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5427 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5428 | ahc_inb(ahc, ULTRA_ENB);
5429 }
5430
5431 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5432 max_targ = 7;
5433
5434 for (i = 0; i <= max_targ; i++) {
5435 struct ahc_initiator_tinfo *tinfo;
5436 struct ahc_tmode_tstate *tstate;
5437 u_int our_id;
5438 u_int target_id;
5439 char channel;
5440
5441 channel = 'A';
5442 our_id = ahc->our_id;
5443 target_id = i;
5444 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5445 channel = 'B';
5446 our_id = ahc->our_id_b;
5447 target_id = i % 8;
5448 }
5449 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5450 target_id, &tstate);
5451 /* Default to async narrow across the board */
5452 memset(tinfo, 0, sizeof(*tinfo));
5453 if (ahc->flags & AHC_USEDEFAULTS) {
5454 if ((ahc->features & AHC_WIDE) != 0)
5455 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5456
5457 /*
5458 * These will be truncated when we determine the
5459 * connection type we have with the target.
5460 */
5461 tinfo->user.period = ahc_syncrates->period;
5462 tinfo->user.offset = MAX_OFFSET;
5463 } else {
5464 u_int scsirate;
5465 uint16_t mask;
5466
5467 /* Take the settings leftover in scratch RAM. */
5468 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5469 mask = (0x01 << i);
5470 if ((ahc->features & AHC_ULTRA2) != 0) {
5471 u_int offset;
5472 u_int maxsync;
5473
5474 if ((scsirate & SOFS) == 0x0F) {
5475 /*
5476 * Haven't negotiated yet,
5477 * so the format is different.
5478 */
5479 scsirate = (scsirate & SXFR) >> 4
5480 | (ultraenb & mask)
5481 ? 0x08 : 0x0
5482 | (scsirate & WIDEXFER);
5483 offset = MAX_OFFSET_ULTRA2;
5484 } else
5485 offset = ahc_inb(ahc, TARG_OFFSET + i);
5486 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5487 /* Set to the lowest sync rate, 5MHz */
5488 scsirate |= 0x1c;
5489 maxsync = AHC_SYNCRATE_ULTRA2;
5490 if ((ahc->features & AHC_DT) != 0)
5491 maxsync = AHC_SYNCRATE_DT;
5492 tinfo->user.period =
5493 ahc_find_period(ahc, scsirate, maxsync);
5494 if (offset == 0)
5495 tinfo->user.period = 0;
5496 else
5497 tinfo->user.offset = MAX_OFFSET;
5498 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5499 && (ahc->features & AHC_DT) != 0)
5500 tinfo->user.ppr_options =
5501 MSG_EXT_PPR_DT_REQ;
5502 } else if ((scsirate & SOFS) != 0) {
5503 if ((scsirate & SXFR) == 0x40
5504 && (ultraenb & mask) != 0) {
5505 /* Treat 10MHz as a non-ultra speed */
5506 scsirate &= ~SXFR;
5507 ultraenb &= ~mask;
5508 }
5509 tinfo->user.period =
5510 ahc_find_period(ahc, scsirate,
5511 (ultraenb & mask)
5512 ? AHC_SYNCRATE_ULTRA
5513 : AHC_SYNCRATE_FAST);
5514 if (tinfo->user.period != 0)
5515 tinfo->user.offset = MAX_OFFSET;
5516 }
5517 if (tinfo->user.period == 0)
5518 tinfo->user.offset = 0;
5519 if ((scsirate & WIDEXFER) != 0
5520 && (ahc->features & AHC_WIDE) != 0)
5521 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5522 tinfo->user.protocol_version = 4;
5523 if ((ahc->features & AHC_DT) != 0)
5524 tinfo->user.transport_version = 3;
5525 else
5526 tinfo->user.transport_version = 2;
5527 tinfo->goal.protocol_version = 2;
5528 tinfo->goal.transport_version = 2;
5529 tinfo->curr.protocol_version = 2;
5530 tinfo->curr.transport_version = 2;
5531 }
5532 tstate->ultraenb = 0;
5533 }
5534 ahc->user_discenable = discenable;
5535 ahc->user_tagenable = tagenable;
5536
5537 return (ahc->bus_chip_init(ahc));
5538 }
5539
5540 void
5541 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5542 {
5543 u_int hcntrl;
5544
5545 hcntrl = ahc_inb(ahc, HCNTRL);
5546 hcntrl &= ~INTEN;
5547 ahc->pause &= ~INTEN;
5548 ahc->unpause &= ~INTEN;
5549 if (enable) {
5550 hcntrl |= INTEN;
5551 ahc->pause |= INTEN;
5552 ahc->unpause |= INTEN;
5553 }
5554 ahc_outb(ahc, HCNTRL, hcntrl);
5555 }
5556
5557 /*
5558 * Ensure that the card is paused in a location
5559 * outside of all critical sections and that all
5560 * pending work is completed prior to returning.
5561 * This routine should only be called from outside
5562 * an interrupt context.
5563 */
5564 void
5565 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5566 {
5567 int intstat;
5568 int maxloops;
5569 int paused;
5570
5571 maxloops = 1000;
5572 ahc->flags |= AHC_ALL_INTERRUPTS;
5573 paused = FALSE;
5574 do {
5575 if (paused) {
5576 ahc_unpause(ahc);
5577 /*
5578 * Give the sequencer some time to service
5579 * any active selections.
5580 */
5581 ahc_delay(500);
5582 }
5583 ahc_intr(ahc);
5584 ahc_pause(ahc);
5585 paused = TRUE;
5586 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5587 intstat = ahc_inb(ahc, INTSTAT);
5588 if ((intstat & INT_PEND) == 0) {
5589 ahc_clear_critical_section(ahc);
5590 intstat = ahc_inb(ahc, INTSTAT);
5591 }
5592 } while (--maxloops
5593 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5594 && ((intstat & INT_PEND) != 0
5595 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5596 if (maxloops == 0) {
5597 printk("Infinite interrupt loop, INTSTAT = %x",
5598 ahc_inb(ahc, INTSTAT));
5599 }
5600 ahc_platform_flushwork(ahc);
5601 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5602 }
5603
5604 #ifdef CONFIG_PM
5605 int
5606 ahc_suspend(struct ahc_softc *ahc)
5607 {
5608
5609 ahc_pause_and_flushwork(ahc);
5610
5611 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5612 ahc_unpause(ahc);
5613 return (EBUSY);
5614 }
5615
5616 #ifdef AHC_TARGET_MODE
5617 if (ahc->pending_device != NULL) {
5618 ahc_unpause(ahc);
5619 return (EBUSY);
5620 }
5621 #endif
5622 ahc_shutdown(ahc);
5623 return (0);
5624 }
5625
5626 int
5627 ahc_resume(struct ahc_softc *ahc)
5628 {
5629
5630 ahc_reset(ahc, /*reinit*/TRUE);
5631 ahc_intr_enable(ahc, TRUE);
5632 ahc_restart(ahc);
5633 return (0);
5634 }
5635 #endif
5636 /************************** Busy Target Table *********************************/
5637 /*
5638 * Return the untagged transaction id for a given target/channel lun.
5639 * Optionally, clear the entry.
5640 */
5641 static u_int
5642 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5643 {
5644 u_int scbid;
5645 u_int target_offset;
5646
5647 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5648 u_int saved_scbptr;
5649
5650 saved_scbptr = ahc_inb(ahc, SCBPTR);
5651 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5652 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5653 ahc_outb(ahc, SCBPTR, saved_scbptr);
5654 } else {
5655 target_offset = TCL_TARGET_OFFSET(tcl);
5656 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5657 }
5658
5659 return (scbid);
5660 }
5661
5662 static void
5663 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5664 {
5665 u_int target_offset;
5666
5667 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5668 u_int saved_scbptr;
5669
5670 saved_scbptr = ahc_inb(ahc, SCBPTR);
5671 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5672 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5673 ahc_outb(ahc, SCBPTR, saved_scbptr);
5674 } else {
5675 target_offset = TCL_TARGET_OFFSET(tcl);
5676 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5677 }
5678 }
5679
5680 static void
5681 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5682 {
5683 u_int target_offset;
5684
5685 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5686 u_int saved_scbptr;
5687
5688 saved_scbptr = ahc_inb(ahc, SCBPTR);
5689 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5690 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5691 ahc_outb(ahc, SCBPTR, saved_scbptr);
5692 } else {
5693 target_offset = TCL_TARGET_OFFSET(tcl);
5694 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5695 }
5696 }
5697
5698 /************************** SCB and SCB queue management **********************/
5699 int
5700 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5701 char channel, int lun, u_int tag, role_t role)
5702 {
5703 int targ = SCB_GET_TARGET(ahc, scb);
5704 char chan = SCB_GET_CHANNEL(ahc, scb);
5705 int slun = SCB_GET_LUN(scb);
5706 int match;
5707
5708 match = ((chan == channel) || (channel == ALL_CHANNELS));
5709 if (match != 0)
5710 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5711 if (match != 0)
5712 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5713 if (match != 0) {
5714 #ifdef AHC_TARGET_MODE
5715 int group;
5716
5717 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5718 if (role == ROLE_INITIATOR) {
5719 match = (group != XPT_FC_GROUP_TMODE)
5720 && ((tag == scb->hscb->tag)
5721 || (tag == SCB_LIST_NULL));
5722 } else if (role == ROLE_TARGET) {
5723 match = (group == XPT_FC_GROUP_TMODE)
5724 && ((tag == scb->io_ctx->csio.tag_id)
5725 || (tag == SCB_LIST_NULL));
5726 }
5727 #else /* !AHC_TARGET_MODE */
5728 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5729 #endif /* AHC_TARGET_MODE */
5730 }
5731
5732 return match;
5733 }
5734
5735 static void
5736 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5737 {
5738 int target;
5739 char channel;
5740 int lun;
5741
5742 target = SCB_GET_TARGET(ahc, scb);
5743 lun = SCB_GET_LUN(scb);
5744 channel = SCB_GET_CHANNEL(ahc, scb);
5745
5746 ahc_search_qinfifo(ahc, target, channel, lun,
5747 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5748 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5749
5750 ahc_platform_freeze_devq(ahc, scb);
5751 }
5752
5753 void
5754 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5755 {
5756 struct scb *prev_scb;
5757
5758 prev_scb = NULL;
5759 if (ahc_qinfifo_count(ahc) != 0) {
5760 u_int prev_tag;
5761 uint8_t prev_pos;
5762
5763 prev_pos = ahc->qinfifonext - 1;
5764 prev_tag = ahc->qinfifo[prev_pos];
5765 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5766 }
5767 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5768 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5769 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5770 } else {
5771 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5772 }
5773 }
5774
5775 static void
5776 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5777 struct scb *scb)
5778 {
5779 if (prev_scb == NULL) {
5780 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5781 } else {
5782 prev_scb->hscb->next = scb->hscb->tag;
5783 ahc_sync_scb(ahc, prev_scb,
5784 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5785 }
5786 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5787 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5788 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5789 }
5790
5791 static int
5792 ahc_qinfifo_count(struct ahc_softc *ahc)
5793 {
5794 uint8_t qinpos;
5795 uint8_t diff;
5796
5797 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5798 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5799 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5800 } else
5801 qinpos = ahc_inb(ahc, QINPOS);
5802 diff = ahc->qinfifonext - qinpos;
5803 return (diff);
5804 }
5805
5806 int
5807 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5808 int lun, u_int tag, role_t role, uint32_t status,
5809 ahc_search_action action)
5810 {
5811 struct scb *scb;
5812 struct scb *prev_scb;
5813 uint8_t qinstart;
5814 uint8_t qinpos;
5815 uint8_t qintail;
5816 uint8_t next;
5817 uint8_t prev;
5818 uint8_t curscbptr;
5819 int found;
5820 int have_qregs;
5821
5822 qintail = ahc->qinfifonext;
5823 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5824 if (have_qregs) {
5825 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5826 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5827 } else
5828 qinstart = ahc_inb(ahc, QINPOS);
5829 qinpos = qinstart;
5830 found = 0;
5831 prev_scb = NULL;
5832
5833 if (action == SEARCH_COMPLETE) {
5834 /*
5835 * Don't attempt to run any queued untagged transactions
5836 * until we are done with the abort process.
5837 */
5838 ahc_freeze_untagged_queues(ahc);
5839 }
5840
5841 /*
5842 * Start with an empty queue. Entries that are not chosen
5843 * for removal will be re-added to the queue as we go.
5844 */
5845 ahc->qinfifonext = qinpos;
5846 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5847
5848 while (qinpos != qintail) {
5849 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5850 if (scb == NULL) {
5851 printk("qinpos = %d, SCB index = %d\n",
5852 qinpos, ahc->qinfifo[qinpos]);
5853 panic("Loop 1\n");
5854 }
5855
5856 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5857 /*
5858 * We found an scb that needs to be acted on.
5859 */
5860 found++;
5861 switch (action) {
5862 case SEARCH_COMPLETE:
5863 {
5864 cam_status ostat;
5865 cam_status cstat;
5866
5867 ostat = ahc_get_transaction_status(scb);
5868 if (ostat == CAM_REQ_INPROG)
5869 ahc_set_transaction_status(scb, status);
5870 cstat = ahc_get_transaction_status(scb);
5871 if (cstat != CAM_REQ_CMP)
5872 ahc_freeze_scb(scb);
5873 if ((scb->flags & SCB_ACTIVE) == 0)
5874 printk("Inactive SCB in qinfifo\n");
5875 ahc_done(ahc, scb);
5876
5877 /* FALLTHROUGH */
5878 }
5879 case SEARCH_REMOVE:
5880 break;
5881 case SEARCH_COUNT:
5882 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5883 prev_scb = scb;
5884 break;
5885 }
5886 } else {
5887 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5888 prev_scb = scb;
5889 }
5890 qinpos++;
5891 }
5892
5893 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5894 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5895 } else {
5896 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5897 }
5898
5899 if (action != SEARCH_COUNT
5900 && (found != 0)
5901 && (qinstart != ahc->qinfifonext)) {
5902 /*
5903 * The sequencer may be in the process of dmaing
5904 * down the SCB at the beginning of the queue.
5905 * This could be problematic if either the first,
5906 * or the second SCB is removed from the queue
5907 * (the first SCB includes a pointer to the "next"
5908 * SCB to dma). If we have removed any entries, swap
5909 * the first element in the queue with the next HSCB
5910 * so the sequencer will notice that NEXT_QUEUED_SCB
5911 * has changed during its dma attempt and will retry
5912 * the DMA.
5913 */
5914 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5915
5916 if (scb == NULL) {
5917 printk("found = %d, qinstart = %d, qinfifionext = %d\n",
5918 found, qinstart, ahc->qinfifonext);
5919 panic("First/Second Qinfifo fixup\n");
5920 }
5921 /*
5922 * ahc_swap_with_next_hscb forces our next pointer to
5923 * point to the reserved SCB for future commands. Save
5924 * and restore our original next pointer to maintain
5925 * queue integrity.
5926 */
5927 next = scb->hscb->next;
5928 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5929 ahc_swap_with_next_hscb(ahc, scb);
5930 scb->hscb->next = next;
5931 ahc->qinfifo[qinstart] = scb->hscb->tag;
5932
5933 /* Tell the card about the new head of the qinfifo. */
5934 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5935
5936 /* Fixup the tail "next" pointer. */
5937 qintail = ahc->qinfifonext - 1;
5938 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5939 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5940 }
5941
5942 /*
5943 * Search waiting for selection list.
5944 */
5945 curscbptr = ahc_inb(ahc, SCBPTR);
5946 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5947 prev = SCB_LIST_NULL;
5948
5949 while (next != SCB_LIST_NULL) {
5950 uint8_t scb_index;
5951
5952 ahc_outb(ahc, SCBPTR, next);
5953 scb_index = ahc_inb(ahc, SCB_TAG);
5954 if (scb_index >= ahc->scb_data->numscbs) {
5955 printk("Waiting List inconsistency. "
5956 "SCB index == %d, yet numscbs == %d.",
5957 scb_index, ahc->scb_data->numscbs);
5958 ahc_dump_card_state(ahc);
5959 panic("for safety");
5960 }
5961 scb = ahc_lookup_scb(ahc, scb_index);
5962 if (scb == NULL) {
5963 printk("scb_index = %d, next = %d\n",
5964 scb_index, next);
5965 panic("Waiting List traversal\n");
5966 }
5967 if (ahc_match_scb(ahc, scb, target, channel,
5968 lun, SCB_LIST_NULL, role)) {
5969 /*
5970 * We found an scb that needs to be acted on.
5971 */
5972 found++;
5973 switch (action) {
5974 case SEARCH_COMPLETE:
5975 {
5976 cam_status ostat;
5977 cam_status cstat;
5978
5979 ostat = ahc_get_transaction_status(scb);
5980 if (ostat == CAM_REQ_INPROG)
5981 ahc_set_transaction_status(scb,
5982 status);
5983 cstat = ahc_get_transaction_status(scb);
5984 if (cstat != CAM_REQ_CMP)
5985 ahc_freeze_scb(scb);
5986 if ((scb->flags & SCB_ACTIVE) == 0)
5987 printk("Inactive SCB in Waiting List\n");
5988 ahc_done(ahc, scb);
5989 /* FALLTHROUGH */
5990 }
5991 case SEARCH_REMOVE:
5992 next = ahc_rem_wscb(ahc, next, prev);
5993 break;
5994 case SEARCH_COUNT:
5995 prev = next;
5996 next = ahc_inb(ahc, SCB_NEXT);
5997 break;
5998 }
5999 } else {
6000
6001 prev = next;
6002 next = ahc_inb(ahc, SCB_NEXT);
6003 }
6004 }
6005 ahc_outb(ahc, SCBPTR, curscbptr);
6006
6007 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
6008 channel, lun, status, action);
6009
6010 if (action == SEARCH_COMPLETE)
6011 ahc_release_untagged_queues(ahc);
6012 return (found);
6013 }
6014
6015 int
6016 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
6017 int target, char channel, int lun, uint32_t status,
6018 ahc_search_action action)
6019 {
6020 struct scb *scb;
6021 int maxtarget;
6022 int found;
6023 int i;
6024
6025 if (action == SEARCH_COMPLETE) {
6026 /*
6027 * Don't attempt to run any queued untagged transactions
6028 * until we are done with the abort process.
6029 */
6030 ahc_freeze_untagged_queues(ahc);
6031 }
6032
6033 found = 0;
6034 i = 0;
6035 if ((ahc->flags & AHC_SCB_BTT) == 0) {
6036
6037 maxtarget = 16;
6038 if (target != CAM_TARGET_WILDCARD) {
6039
6040 i = target;
6041 if (channel == 'B')
6042 i += 8;
6043 maxtarget = i + 1;
6044 }
6045 } else {
6046 maxtarget = 0;
6047 }
6048
6049 for (; i < maxtarget; i++) {
6050 struct scb_tailq *untagged_q;
6051 struct scb *next_scb;
6052
6053 untagged_q = &(ahc->untagged_queues[i]);
6054 next_scb = TAILQ_FIRST(untagged_q);
6055 while (next_scb != NULL) {
6056
6057 scb = next_scb;
6058 next_scb = TAILQ_NEXT(scb, links.tqe);
6059
6060 /*
6061 * The head of the list may be the currently
6062 * active untagged command for a device.
6063 * We're only searching for commands that
6064 * have not been started. A transaction
6065 * marked active but still in the qinfifo
6066 * is removed by the qinfifo scanning code
6067 * above.
6068 */
6069 if ((scb->flags & SCB_ACTIVE) != 0)
6070 continue;
6071
6072 if (ahc_match_scb(ahc, scb, target, channel, lun,
6073 SCB_LIST_NULL, ROLE_INITIATOR) == 0
6074 || (ctx != NULL && ctx != scb->io_ctx))
6075 continue;
6076
6077 /*
6078 * We found an scb that needs to be acted on.
6079 */
6080 found++;
6081 switch (action) {
6082 case SEARCH_COMPLETE:
6083 {
6084 cam_status ostat;
6085 cam_status cstat;
6086
6087 ostat = ahc_get_transaction_status(scb);
6088 if (ostat == CAM_REQ_INPROG)
6089 ahc_set_transaction_status(scb, status);
6090 cstat = ahc_get_transaction_status(scb);
6091 if (cstat != CAM_REQ_CMP)
6092 ahc_freeze_scb(scb);
6093 if ((scb->flags & SCB_ACTIVE) == 0)
6094 printk("Inactive SCB in untaggedQ\n");
6095 ahc_done(ahc, scb);
6096 break;
6097 }
6098 case SEARCH_REMOVE:
6099 scb->flags &= ~SCB_UNTAGGEDQ;
6100 TAILQ_REMOVE(untagged_q, scb, links.tqe);
6101 break;
6102 case SEARCH_COUNT:
6103 break;
6104 }
6105 }
6106 }
6107
6108 if (action == SEARCH_COMPLETE)
6109 ahc_release_untagged_queues(ahc);
6110 return (found);
6111 }
6112
6113 int
6114 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
6115 int lun, u_int tag, int stop_on_first, int remove,
6116 int save_state)
6117 {
6118 struct scb *scbp;
6119 u_int next;
6120 u_int prev;
6121 u_int count;
6122 u_int active_scb;
6123
6124 count = 0;
6125 next = ahc_inb(ahc, DISCONNECTED_SCBH);
6126 prev = SCB_LIST_NULL;
6127
6128 if (save_state) {
6129 /* restore this when we're done */
6130 active_scb = ahc_inb(ahc, SCBPTR);
6131 } else
6132 /* Silence compiler */
6133 active_scb = SCB_LIST_NULL;
6134
6135 while (next != SCB_LIST_NULL) {
6136 u_int scb_index;
6137
6138 ahc_outb(ahc, SCBPTR, next);
6139 scb_index = ahc_inb(ahc, SCB_TAG);
6140 if (scb_index >= ahc->scb_data->numscbs) {
6141 printk("Disconnected List inconsistency. "
6142 "SCB index == %d, yet numscbs == %d.",
6143 scb_index, ahc->scb_data->numscbs);
6144 ahc_dump_card_state(ahc);
6145 panic("for safety");
6146 }
6147
6148 if (next == prev) {
6149 panic("Disconnected List Loop. "
6150 "cur SCBPTR == %x, prev SCBPTR == %x.",
6151 next, prev);
6152 }
6153 scbp = ahc_lookup_scb(ahc, scb_index);
6154 if (ahc_match_scb(ahc, scbp, target, channel, lun,
6155 tag, ROLE_INITIATOR)) {
6156 count++;
6157 if (remove) {
6158 next =
6159 ahc_rem_scb_from_disc_list(ahc, prev, next);
6160 } else {
6161 prev = next;
6162 next = ahc_inb(ahc, SCB_NEXT);
6163 }
6164 if (stop_on_first)
6165 break;
6166 } else {
6167 prev = next;
6168 next = ahc_inb(ahc, SCB_NEXT);
6169 }
6170 }
6171 if (save_state)
6172 ahc_outb(ahc, SCBPTR, active_scb);
6173 return (count);
6174 }
6175
6176 /*
6177 * Remove an SCB from the on chip list of disconnected transactions.
6178 * This is empty/unused if we are not performing SCB paging.
6179 */
6180 static u_int
6181 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
6182 {
6183 u_int next;
6184
6185 ahc_outb(ahc, SCBPTR, scbptr);
6186 next = ahc_inb(ahc, SCB_NEXT);
6187
6188 ahc_outb(ahc, SCB_CONTROL, 0);
6189
6190 ahc_add_curscb_to_free_list(ahc);
6191
6192 if (prev != SCB_LIST_NULL) {
6193 ahc_outb(ahc, SCBPTR, prev);
6194 ahc_outb(ahc, SCB_NEXT, next);
6195 } else
6196 ahc_outb(ahc, DISCONNECTED_SCBH, next);
6197
6198 return (next);
6199 }
6200
6201 /*
6202 * Add the SCB as selected by SCBPTR onto the on chip list of
6203 * free hardware SCBs. This list is empty/unused if we are not
6204 * performing SCB paging.
6205 */
6206 static void
6207 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
6208 {
6209 /*
6210 * Invalidate the tag so that our abort
6211 * routines don't think it's active.
6212 */
6213 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
6214
6215 if ((ahc->flags & AHC_PAGESCBS) != 0) {
6216 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
6217 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
6218 }
6219 }
6220
6221 /*
6222 * Manipulate the waiting for selection list and return the
6223 * scb that follows the one that we remove.
6224 */
6225 static u_int
6226 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
6227 {
6228 u_int curscb, next;
6229
6230 /*
6231 * Select the SCB we want to abort and
6232 * pull the next pointer out of it.
6233 */
6234 curscb = ahc_inb(ahc, SCBPTR);
6235 ahc_outb(ahc, SCBPTR, scbpos);
6236 next = ahc_inb(ahc, SCB_NEXT);
6237
6238 /* Clear the necessary fields */
6239 ahc_outb(ahc, SCB_CONTROL, 0);
6240
6241 ahc_add_curscb_to_free_list(ahc);
6242
6243 /* update the waiting list */
6244 if (prev == SCB_LIST_NULL) {
6245 /* First in the list */
6246 ahc_outb(ahc, WAITING_SCBH, next);
6247
6248 /*
6249 * Ensure we aren't attempting to perform
6250 * selection for this entry.
6251 */
6252 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
6253 } else {
6254 /*
6255 * Select the scb that pointed to us
6256 * and update its next pointer.
6257 */
6258 ahc_outb(ahc, SCBPTR, prev);
6259 ahc_outb(ahc, SCB_NEXT, next);
6260 }
6261
6262 /*
6263 * Point us back at the original scb position.
6264 */
6265 ahc_outb(ahc, SCBPTR, curscb);
6266 return next;
6267 }
6268
6269 /******************************** Error Handling ******************************/
6270 /*
6271 * Abort all SCBs that match the given description (target/channel/lun/tag),
6272 * setting their status to the passed in status if the status has not already
6273 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
6274 * is paused before it is called.
6275 */
6276 static int
6277 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
6278 int lun, u_int tag, role_t role, uint32_t status)
6279 {
6280 struct scb *scbp;
6281 struct scb *scbp_next;
6282 u_int active_scb;
6283 int i, j;
6284 int maxtarget;
6285 int minlun;
6286 int maxlun;
6287
6288 int found;
6289
6290 /*
6291 * Don't attempt to run any queued untagged transactions
6292 * until we are done with the abort process.
6293 */
6294 ahc_freeze_untagged_queues(ahc);
6295
6296 /* restore this when we're done */
6297 active_scb = ahc_inb(ahc, SCBPTR);
6298
6299 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
6300 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6301
6302 /*
6303 * Clean out the busy target table for any untagged commands.
6304 */
6305 i = 0;
6306 maxtarget = 16;
6307 if (target != CAM_TARGET_WILDCARD) {
6308 i = target;
6309 if (channel == 'B')
6310 i += 8;
6311 maxtarget = i + 1;
6312 }
6313
6314 if (lun == CAM_LUN_WILDCARD) {
6315
6316 /*
6317 * Unless we are using an SCB based
6318 * busy targets table, there is only
6319 * one table entry for all luns of
6320 * a target.
6321 */
6322 minlun = 0;
6323 maxlun = 1;
6324 if ((ahc->flags & AHC_SCB_BTT) != 0)
6325 maxlun = AHC_NUM_LUNS;
6326 } else {
6327 minlun = lun;
6328 maxlun = lun + 1;
6329 }
6330
6331 if (role != ROLE_TARGET) {
6332 for (;i < maxtarget; i++) {
6333 for (j = minlun;j < maxlun; j++) {
6334 u_int scbid;
6335 u_int tcl;
6336
6337 tcl = BUILD_TCL(i << 4, j);
6338 scbid = ahc_index_busy_tcl(ahc, tcl);
6339 scbp = ahc_lookup_scb(ahc, scbid);
6340 if (scbp == NULL
6341 || ahc_match_scb(ahc, scbp, target, channel,
6342 lun, tag, role) == 0)
6343 continue;
6344 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
6345 }
6346 }
6347
6348 /*
6349 * Go through the disconnected list and remove any entries we
6350 * have queued for completion, 0'ing their control byte too.
6351 * We save the active SCB and restore it ourselves, so there
6352 * is no reason for this search to restore it too.
6353 */
6354 ahc_search_disc_list(ahc, target, channel, lun, tag,
6355 /*stop_on_first*/FALSE, /*remove*/TRUE,
6356 /*save_state*/FALSE);
6357 }
6358
6359 /*
6360 * Go through the hardware SCB array looking for commands that
6361 * were active but not on any list. In some cases, these remnants
6362 * might not still have mappings in the scbindex array (e.g. unexpected
6363 * bus free with the same scb queued for an abort). Don't hold this
6364 * against them.
6365 */
6366 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6367 u_int scbid;
6368
6369 ahc_outb(ahc, SCBPTR, i);
6370 scbid = ahc_inb(ahc, SCB_TAG);
6371 scbp = ahc_lookup_scb(ahc, scbid);
6372 if ((scbp == NULL && scbid != SCB_LIST_NULL)
6373 || (scbp != NULL
6374 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
6375 ahc_add_curscb_to_free_list(ahc);
6376 }
6377
6378 /*
6379 * Go through the pending CCB list and look for
6380 * commands for this target that are still active.
6381 * These are other tagged commands that were
6382 * disconnected when the reset occurred.
6383 */
6384 scbp_next = LIST_FIRST(&ahc->pending_scbs);
6385 while (scbp_next != NULL) {
6386 scbp = scbp_next;
6387 scbp_next = LIST_NEXT(scbp, pending_links);
6388 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6389 cam_status ostat;
6390
6391 ostat = ahc_get_transaction_status(scbp);
6392 if (ostat == CAM_REQ_INPROG)
6393 ahc_set_transaction_status(scbp, status);
6394 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
6395 ahc_freeze_scb(scbp);
6396 if ((scbp->flags & SCB_ACTIVE) == 0)
6397 printk("Inactive SCB on pending list\n");
6398 ahc_done(ahc, scbp);
6399 found++;
6400 }
6401 }
6402 ahc_outb(ahc, SCBPTR, active_scb);
6403 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6404 ahc_release_untagged_queues(ahc);
6405 return found;
6406 }
6407
6408 static void
6409 ahc_reset_current_bus(struct ahc_softc *ahc)
6410 {
6411 uint8_t scsiseq;
6412
6413 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6414 scsiseq = ahc_inb(ahc, SCSISEQ);
6415 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6416 ahc_flush_device_writes(ahc);
6417 ahc_delay(AHC_BUSRESET_DELAY);
6418 /* Turn off the bus reset */
6419 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6420
6421 ahc_clear_intstat(ahc);
6422
6423 /* Re-enable reset interrupts */
6424 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6425 }
6426
6427 int
6428 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6429 {
6430 struct ahc_devinfo devinfo;
6431 u_int initiator, target, max_scsiid;
6432 u_int sblkctl;
6433 u_int scsiseq;
6434 u_int simode1;
6435 int found;
6436 int restart_needed;
6437 char cur_channel;
6438
6439 ahc->pending_device = NULL;
6440
6441 ahc_compile_devinfo(&devinfo,
6442 CAM_TARGET_WILDCARD,
6443 CAM_TARGET_WILDCARD,
6444 CAM_LUN_WILDCARD,
6445 channel, ROLE_UNKNOWN);
6446 ahc_pause(ahc);
6447
6448 /* Make sure the sequencer is in a safe location. */
6449 ahc_clear_critical_section(ahc);
6450
6451 /*
6452 * Run our command complete fifos to ensure that we perform
6453 * completion processing on any commands that 'completed'
6454 * before the reset occurred.
6455 */
6456 ahc_run_qoutfifo(ahc);
6457 #ifdef AHC_TARGET_MODE
6458 if ((ahc->flags & AHC_TARGETROLE) != 0) {
6459 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6460 }
6461 #endif
6462
6463 /*
6464 * Reset the bus if we are initiating this reset
6465 */
6466 sblkctl = ahc_inb(ahc, SBLKCTL);
6467 cur_channel = 'A';
6468 if ((ahc->features & AHC_TWIN) != 0
6469 && ((sblkctl & SELBUSB) != 0))
6470 cur_channel = 'B';
6471 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6472 if (cur_channel != channel) {
6473 /* Case 1: Command for another bus is active
6474 * Stealthily reset the other bus without
6475 * upsetting the current bus.
6476 */
6477 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6478 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6479 #ifdef AHC_TARGET_MODE
6480 /*
6481 * Bus resets clear ENSELI, so we cannot
6482 * defer re-enabling bus reset interrupts
6483 * if we are in target mode.
6484 */
6485 if ((ahc->flags & AHC_TARGETROLE) != 0)
6486 simode1 |= ENSCSIRST;
6487 #endif
6488 ahc_outb(ahc, SIMODE1, simode1);
6489 if (initiate_reset)
6490 ahc_reset_current_bus(ahc);
6491 ahc_clear_intstat(ahc);
6492 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6493 ahc_outb(ahc, SBLKCTL, sblkctl);
6494 restart_needed = FALSE;
6495 } else {
6496 /* Case 2: A command from this bus is active or we're idle */
6497 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6498 #ifdef AHC_TARGET_MODE
6499 /*
6500 * Bus resets clear ENSELI, so we cannot
6501 * defer re-enabling bus reset interrupts
6502 * if we are in target mode.
6503 */
6504 if ((ahc->flags & AHC_TARGETROLE) != 0)
6505 simode1 |= ENSCSIRST;
6506 #endif
6507 ahc_outb(ahc, SIMODE1, simode1);
6508 if (initiate_reset)
6509 ahc_reset_current_bus(ahc);
6510 ahc_clear_intstat(ahc);
6511 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6512 restart_needed = TRUE;
6513 }
6514
6515 /*
6516 * Clean up all the state information for the
6517 * pending transactions on this bus.
6518 */
6519 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6520 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6521 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6522
6523 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6524
6525 #ifdef AHC_TARGET_MODE
6526 /*
6527 * Send an immediate notify ccb to all target more peripheral
6528 * drivers affected by this action.
6529 */
6530 for (target = 0; target <= max_scsiid; target++) {
6531 struct ahc_tmode_tstate* tstate;
6532 u_int lun;
6533
6534 tstate = ahc->enabled_targets[target];
6535 if (tstate == NULL)
6536 continue;
6537 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6538 struct ahc_tmode_lstate* lstate;
6539
6540 lstate = tstate->enabled_luns[lun];
6541 if (lstate == NULL)
6542 continue;
6543
6544 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6545 EVENT_TYPE_BUS_RESET, /*arg*/0);
6546 ahc_send_lstate_events(ahc, lstate);
6547 }
6548 }
6549 #endif
6550 /* Notify the XPT that a bus reset occurred */
6551 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6552 CAM_LUN_WILDCARD, AC_BUS_RESET);
6553
6554 /*
6555 * Revert to async/narrow transfers until we renegotiate.
6556 */
6557 for (target = 0; target <= max_scsiid; target++) {
6558
6559 if (ahc->enabled_targets[target] == NULL)
6560 continue;
6561 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6562 struct ahc_devinfo devinfo;
6563
6564 ahc_compile_devinfo(&devinfo, target, initiator,
6565 CAM_LUN_WILDCARD,
6566 channel, ROLE_UNKNOWN);
6567 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6568 AHC_TRANS_CUR, /*paused*/TRUE);
6569 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6570 /*period*/0, /*offset*/0,
6571 /*ppr_options*/0, AHC_TRANS_CUR,
6572 /*paused*/TRUE);
6573 }
6574 }
6575
6576 if (restart_needed)
6577 ahc_restart(ahc);
6578 else
6579 ahc_unpause(ahc);
6580 return found;
6581 }
6582
6583
6584 /***************************** Residual Processing ****************************/
6585 /*
6586 * Calculate the residual for a just completed SCB.
6587 */
6588 static void
6589 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6590 {
6591 struct hardware_scb *hscb;
6592 struct status_pkt *spkt;
6593 uint32_t sgptr;
6594 uint32_t resid_sgptr;
6595 uint32_t resid;
6596
6597 /*
6598 * 5 cases.
6599 * 1) No residual.
6600 * SG_RESID_VALID clear in sgptr.
6601 * 2) Transferless command
6602 * 3) Never performed any transfers.
6603 * sgptr has SG_FULL_RESID set.
6604 * 4) No residual but target did not
6605 * save data pointers after the
6606 * last transfer, so sgptr was
6607 * never updated.
6608 * 5) We have a partial residual.
6609 * Use residual_sgptr to determine
6610 * where we are.
6611 */
6612
6613 hscb = scb->hscb;
6614 sgptr = ahc_le32toh(hscb->sgptr);
6615 if ((sgptr & SG_RESID_VALID) == 0)
6616 /* Case 1 */
6617 return;
6618 sgptr &= ~SG_RESID_VALID;
6619
6620 if ((sgptr & SG_LIST_NULL) != 0)
6621 /* Case 2 */
6622 return;
6623
6624 spkt = &hscb->shared_data.status;
6625 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6626 if ((sgptr & SG_FULL_RESID) != 0) {
6627 /* Case 3 */
6628 resid = ahc_get_transfer_length(scb);
6629 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6630 /* Case 4 */
6631 return;
6632 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6633 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6634 } else {
6635 struct ahc_dma_seg *sg;
6636
6637 /*
6638 * Remainder of the SG where the transfer
6639 * stopped.
6640 */
6641 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6642 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6643
6644 /* The residual sg_ptr always points to the next sg */
6645 sg--;
6646
6647 /*
6648 * Add up the contents of all residual
6649 * SG segments that are after the SG where
6650 * the transfer stopped.
6651 */
6652 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6653 sg++;
6654 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6655 }
6656 }
6657 if ((scb->flags & SCB_SENSE) == 0)
6658 ahc_set_residual(scb, resid);
6659 else
6660 ahc_set_sense_residual(scb, resid);
6661
6662 #ifdef AHC_DEBUG
6663 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6664 ahc_print_path(ahc, scb);
6665 printk("Handled %sResidual of %d bytes\n",
6666 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6667 }
6668 #endif
6669 }
6670
6671 /******************************* Target Mode **********************************/
6672 #ifdef AHC_TARGET_MODE
6673 /*
6674 * Add a target mode event to this lun's queue
6675 */
6676 static void
6677 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6678 u_int initiator_id, u_int event_type, u_int event_arg)
6679 {
6680 struct ahc_tmode_event *event;
6681 int pending;
6682
6683 xpt_freeze_devq(lstate->path, /*count*/1);
6684 if (lstate->event_w_idx >= lstate->event_r_idx)
6685 pending = lstate->event_w_idx - lstate->event_r_idx;
6686 else
6687 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6688 - (lstate->event_r_idx - lstate->event_w_idx);
6689
6690 if (event_type == EVENT_TYPE_BUS_RESET
6691 || event_type == MSG_BUS_DEV_RESET) {
6692 /*
6693 * Any earlier events are irrelevant, so reset our buffer.
6694 * This has the effect of allowing us to deal with reset
6695 * floods (an external device holding down the reset line)
6696 * without losing the event that is really interesting.
6697 */
6698 lstate->event_r_idx = 0;
6699 lstate->event_w_idx = 0;
6700 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6701 }
6702
6703 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6704 xpt_print_path(lstate->path);
6705 printk("immediate event %x:%x lost\n",
6706 lstate->event_buffer[lstate->event_r_idx].event_type,
6707 lstate->event_buffer[lstate->event_r_idx].event_arg);
6708 lstate->event_r_idx++;
6709 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6710 lstate->event_r_idx = 0;
6711 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6712 }
6713
6714 event = &lstate->event_buffer[lstate->event_w_idx];
6715 event->initiator_id = initiator_id;
6716 event->event_type = event_type;
6717 event->event_arg = event_arg;
6718 lstate->event_w_idx++;
6719 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6720 lstate->event_w_idx = 0;
6721 }
6722
6723 /*
6724 * Send any target mode events queued up waiting
6725 * for immediate notify resources.
6726 */
6727 void
6728 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6729 {
6730 struct ccb_hdr *ccbh;
6731 struct ccb_immed_notify *inot;
6732
6733 while (lstate->event_r_idx != lstate->event_w_idx
6734 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6735 struct ahc_tmode_event *event;
6736
6737 event = &lstate->event_buffer[lstate->event_r_idx];
6738 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6739 inot = (struct ccb_immed_notify *)ccbh;
6740 switch (event->event_type) {
6741 case EVENT_TYPE_BUS_RESET:
6742 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6743 break;
6744 default:
6745 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6746 inot->message_args[0] = event->event_type;
6747 inot->message_args[1] = event->event_arg;
6748 break;
6749 }
6750 inot->initiator_id = event->initiator_id;
6751 inot->sense_len = 0;
6752 xpt_done((union ccb *)inot);
6753 lstate->event_r_idx++;
6754 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6755 lstate->event_r_idx = 0;
6756 }
6757 }
6758 #endif
6759
6760 /******************** Sequencer Program Patching/Download *********************/
6761
6762 #ifdef AHC_DUMP_SEQ
6763 void
6764 ahc_dumpseq(struct ahc_softc* ahc)
6765 {
6766 int i;
6767
6768 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6769 ahc_outb(ahc, SEQADDR0, 0);
6770 ahc_outb(ahc, SEQADDR1, 0);
6771 for (i = 0; i < ahc->instruction_ram_size; i++) {
6772 uint8_t ins_bytes[4];
6773
6774 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6775 printk("0x%08x\n", ins_bytes[0] << 24
6776 | ins_bytes[1] << 16
6777 | ins_bytes[2] << 8
6778 | ins_bytes[3]);
6779 }
6780 }
6781 #endif
6782
6783 static int
6784 ahc_loadseq(struct ahc_softc *ahc)
6785 {
6786 struct cs cs_table[num_critical_sections];
6787 u_int begin_set[num_critical_sections];
6788 u_int end_set[num_critical_sections];
6789 const struct patch *cur_patch;
6790 u_int cs_count;
6791 u_int cur_cs;
6792 u_int i;
6793 u_int skip_addr;
6794 u_int sg_prefetch_cnt;
6795 int downloaded;
6796 uint8_t download_consts[7];
6797
6798 /*
6799 * Start out with 0 critical sections
6800 * that apply to this firmware load.
6801 */
6802 cs_count = 0;
6803 cur_cs = 0;
6804 memset(begin_set, 0, sizeof(begin_set));
6805 memset(end_set, 0, sizeof(end_set));
6806
6807 /* Setup downloadable constant table */
6808 download_consts[QOUTFIFO_OFFSET] = 0;
6809 if (ahc->targetcmds != NULL)
6810 download_consts[QOUTFIFO_OFFSET] += 32;
6811 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6812 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6813 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6814 sg_prefetch_cnt = ahc->pci_cachesize;
6815 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6816 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6817 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6818 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6819 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6820
6821 cur_patch = patches;
6822 downloaded = 0;
6823 skip_addr = 0;
6824 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6825 ahc_outb(ahc, SEQADDR0, 0);
6826 ahc_outb(ahc, SEQADDR1, 0);
6827
6828 for (i = 0; i < sizeof(seqprog)/4; i++) {
6829 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6830 /*
6831 * Don't download this instruction as it
6832 * is in a patch that was removed.
6833 */
6834 continue;
6835 }
6836
6837 if (downloaded == ahc->instruction_ram_size) {
6838 /*
6839 * We're about to exceed the instruction
6840 * storage capacity for this chip. Fail
6841 * the load.
6842 */
6843 printk("\n%s: Program too large for instruction memory "
6844 "size of %d!\n", ahc_name(ahc),
6845 ahc->instruction_ram_size);
6846 return (ENOMEM);
6847 }
6848
6849 /*
6850 * Move through the CS table until we find a CS
6851 * that might apply to this instruction.
6852 */
6853 for (; cur_cs < num_critical_sections; cur_cs++) {
6854 if (critical_sections[cur_cs].end <= i) {
6855 if (begin_set[cs_count] == TRUE
6856 && end_set[cs_count] == FALSE) {
6857 cs_table[cs_count].end = downloaded;
6858 end_set[cs_count] = TRUE;
6859 cs_count++;
6860 }
6861 continue;
6862 }
6863 if (critical_sections[cur_cs].begin <= i
6864 && begin_set[cs_count] == FALSE) {
6865 cs_table[cs_count].begin = downloaded;
6866 begin_set[cs_count] = TRUE;
6867 }
6868 break;
6869 }
6870 ahc_download_instr(ahc, i, download_consts);
6871 downloaded++;
6872 }
6873
6874 ahc->num_critical_sections = cs_count;
6875 if (cs_count != 0) {
6876
6877 cs_count *= sizeof(struct cs);
6878 ahc->critical_sections = kmalloc(cs_count, GFP_ATOMIC);
6879 if (ahc->critical_sections == NULL)
6880 panic("ahc_loadseq: Could not malloc");
6881 memcpy(ahc->critical_sections, cs_table, cs_count);
6882 }
6883 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6884
6885 if (bootverbose) {
6886 printk(" %d instructions downloaded\n", downloaded);
6887 printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6888 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6889 }
6890 return (0);
6891 }
6892
6893 static int
6894 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
6895 u_int start_instr, u_int *skip_addr)
6896 {
6897 const struct patch *cur_patch;
6898 const struct patch *last_patch;
6899 u_int num_patches;
6900
6901 num_patches = ARRAY_SIZE(patches);
6902 last_patch = &patches[num_patches];
6903 cur_patch = *start_patch;
6904
6905 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6906
6907 if (cur_patch->patch_func(ahc) == 0) {
6908
6909 /* Start rejecting code */
6910 *skip_addr = start_instr + cur_patch->skip_instr;
6911 cur_patch += cur_patch->skip_patch;
6912 } else {
6913 /* Accepted this patch. Advance to the next
6914 * one and wait for our intruction pointer to
6915 * hit this point.
6916 */
6917 cur_patch++;
6918 }
6919 }
6920
6921 *start_patch = cur_patch;
6922 if (start_instr < *skip_addr)
6923 /* Still skipping */
6924 return (0);
6925
6926 return (1);
6927 }
6928
6929 static void
6930 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6931 {
6932 union ins_formats instr;
6933 struct ins_format1 *fmt1_ins;
6934 struct ins_format3 *fmt3_ins;
6935 u_int opcode;
6936
6937 /*
6938 * The firmware is always compiled into a little endian format.
6939 */
6940 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6941
6942 fmt1_ins = &instr.format1;
6943 fmt3_ins = NULL;
6944
6945 /* Pull the opcode */
6946 opcode = instr.format1.opcode;
6947 switch (opcode) {
6948 case AIC_OP_JMP:
6949 case AIC_OP_JC:
6950 case AIC_OP_JNC:
6951 case AIC_OP_CALL:
6952 case AIC_OP_JNE:
6953 case AIC_OP_JNZ:
6954 case AIC_OP_JE:
6955 case AIC_OP_JZ:
6956 {
6957 const struct patch *cur_patch;
6958 int address_offset;
6959 u_int address;
6960 u_int skip_addr;
6961 u_int i;
6962
6963 fmt3_ins = &instr.format3;
6964 address_offset = 0;
6965 address = fmt3_ins->address;
6966 cur_patch = patches;
6967 skip_addr = 0;
6968
6969 for (i = 0; i < address;) {
6970
6971 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6972
6973 if (skip_addr > i) {
6974 int end_addr;
6975
6976 end_addr = min(address, skip_addr);
6977 address_offset += end_addr - i;
6978 i = skip_addr;
6979 } else {
6980 i++;
6981 }
6982 }
6983 address -= address_offset;
6984 fmt3_ins->address = address;
6985 /* FALLTHROUGH */
6986 }
6987 case AIC_OP_OR:
6988 case AIC_OP_AND:
6989 case AIC_OP_XOR:
6990 case AIC_OP_ADD:
6991 case AIC_OP_ADC:
6992 case AIC_OP_BMOV:
6993 if (fmt1_ins->parity != 0) {
6994 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6995 }
6996 fmt1_ins->parity = 0;
6997 if ((ahc->features & AHC_CMD_CHAN) == 0
6998 && opcode == AIC_OP_BMOV) {
6999 /*
7000 * Block move was added at the same time
7001 * as the command channel. Verify that
7002 * this is only a move of a single element
7003 * and convert the BMOV to a MOV
7004 * (AND with an immediate of FF).
7005 */
7006 if (fmt1_ins->immediate != 1)
7007 panic("%s: BMOV not supported\n",
7008 ahc_name(ahc));
7009 fmt1_ins->opcode = AIC_OP_AND;
7010 fmt1_ins->immediate = 0xff;
7011 }
7012 /* FALLTHROUGH */
7013 case AIC_OP_ROL:
7014 if ((ahc->features & AHC_ULTRA2) != 0) {
7015 int i, count;
7016
7017 /* Calculate odd parity for the instruction */
7018 for (i = 0, count = 0; i < 31; i++) {
7019 uint32_t mask;
7020
7021 mask = 0x01 << i;
7022 if ((instr.integer & mask) != 0)
7023 count++;
7024 }
7025 if ((count & 0x01) == 0)
7026 instr.format1.parity = 1;
7027 } else {
7028 /* Compress the instruction for older sequencers */
7029 if (fmt3_ins != NULL) {
7030 instr.integer =
7031 fmt3_ins->immediate
7032 | (fmt3_ins->source << 8)
7033 | (fmt3_ins->address << 16)
7034 | (fmt3_ins->opcode << 25);
7035 } else {
7036 instr.integer =
7037 fmt1_ins->immediate
7038 | (fmt1_ins->source << 8)
7039 | (fmt1_ins->destination << 16)
7040 | (fmt1_ins->ret << 24)
7041 | (fmt1_ins->opcode << 25);
7042 }
7043 }
7044 /* The sequencer is a little endian cpu */
7045 instr.integer = ahc_htole32(instr.integer);
7046 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
7047 break;
7048 default:
7049 panic("Unknown opcode encountered in seq program");
7050 break;
7051 }
7052 }
7053
7054 int
7055 ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
7056 const char *name, u_int address, u_int value,
7057 u_int *cur_column, u_int wrap_point)
7058 {
7059 int printed;
7060 u_int printed_mask;
7061
7062 if (cur_column != NULL && *cur_column >= wrap_point) {
7063 printk("\n");
7064 *cur_column = 0;
7065 }
7066 printed = printk("%s[0x%x]", name, value);
7067 if (table == NULL) {
7068 printed += printk(" ");
7069 *cur_column += printed;
7070 return (printed);
7071 }
7072 printed_mask = 0;
7073 while (printed_mask != 0xFF) {
7074 int entry;
7075
7076 for (entry = 0; entry < num_entries; entry++) {
7077 if (((value & table[entry].mask)
7078 != table[entry].value)
7079 || ((printed_mask & table[entry].mask)
7080 == table[entry].mask))
7081 continue;
7082
7083 printed += printk("%s%s",
7084 printed_mask == 0 ? ":(" : "|",
7085 table[entry].name);
7086 printed_mask |= table[entry].mask;
7087
7088 break;
7089 }
7090 if (entry >= num_entries)
7091 break;
7092 }
7093 if (printed_mask != 0)
7094 printed += printk(") ");
7095 else
7096 printed += printk(" ");
7097 if (cur_column != NULL)
7098 *cur_column += printed;
7099 return (printed);
7100 }
7101
7102 void
7103 ahc_dump_card_state(struct ahc_softc *ahc)
7104 {
7105 struct scb *scb;
7106 struct scb_tailq *untagged_q;
7107 u_int cur_col;
7108 int paused;
7109 int target;
7110 int maxtarget;
7111 int i;
7112 uint8_t last_phase;
7113 uint8_t qinpos;
7114 uint8_t qintail;
7115 uint8_t qoutpos;
7116 uint8_t scb_index;
7117 uint8_t saved_scbptr;
7118
7119 if (ahc_is_paused(ahc)) {
7120 paused = 1;
7121 } else {
7122 paused = 0;
7123 ahc_pause(ahc);
7124 }
7125
7126 saved_scbptr = ahc_inb(ahc, SCBPTR);
7127 last_phase = ahc_inb(ahc, LASTPHASE);
7128 printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
7129 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
7130 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
7131 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
7132 if (paused)
7133 printk("Card was paused\n");
7134 printk("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
7135 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
7136 ahc_inb(ahc, ARG_2));
7137 printk("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
7138 ahc_inb(ahc, SCBPTR));
7139 cur_col = 0;
7140 if ((ahc->features & AHC_DT) != 0)
7141 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
7142 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
7143 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
7144 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
7145 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
7146 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
7147 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
7148 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
7149 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
7150 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
7151 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
7152 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
7153 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
7154 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
7155 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
7156 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
7157 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
7158 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
7159 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
7160 if (cur_col != 0)
7161 printk("\n");
7162 printk("STACK:");
7163 for (i = 0; i < STACK_SIZE; i++)
7164 printk(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
7165 printk("\nSCB count = %d\n", ahc->scb_data->numscbs);
7166 printk("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
7167 printk("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
7168 /* QINFIFO */
7169 printk("QINFIFO entries: ");
7170 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
7171 qinpos = ahc_inb(ahc, SNSCB_QOFF);
7172 ahc_outb(ahc, SNSCB_QOFF, qinpos);
7173 } else
7174 qinpos = ahc_inb(ahc, QINPOS);
7175 qintail = ahc->qinfifonext;
7176 while (qinpos != qintail) {
7177 printk("%d ", ahc->qinfifo[qinpos]);
7178 qinpos++;
7179 }
7180 printk("\n");
7181
7182 printk("Waiting Queue entries: ");
7183 scb_index = ahc_inb(ahc, WAITING_SCBH);
7184 i = 0;
7185 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7186 ahc_outb(ahc, SCBPTR, scb_index);
7187 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7188 scb_index = ahc_inb(ahc, SCB_NEXT);
7189 }
7190 printk("\n");
7191
7192 printk("Disconnected Queue entries: ");
7193 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
7194 i = 0;
7195 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7196 ahc_outb(ahc, SCBPTR, scb_index);
7197 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7198 scb_index = ahc_inb(ahc, SCB_NEXT);
7199 }
7200 printk("\n");
7201
7202 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
7203 printk("QOUTFIFO entries: ");
7204 qoutpos = ahc->qoutfifonext;
7205 i = 0;
7206 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
7207 printk("%d ", ahc->qoutfifo[qoutpos]);
7208 qoutpos++;
7209 }
7210 printk("\n");
7211
7212 printk("Sequencer Free SCB List: ");
7213 scb_index = ahc_inb(ahc, FREE_SCBH);
7214 i = 0;
7215 while (scb_index != SCB_LIST_NULL && i++ < 256) {
7216 ahc_outb(ahc, SCBPTR, scb_index);
7217 printk("%d ", scb_index);
7218 scb_index = ahc_inb(ahc, SCB_NEXT);
7219 }
7220 printk("\n");
7221
7222 printk("Sequencer SCB Info: ");
7223 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
7224 ahc_outb(ahc, SCBPTR, i);
7225 cur_col = printk("\n%3d ", i);
7226
7227 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
7228 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
7229 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
7230 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7231 }
7232 printk("\n");
7233
7234 printk("Pending list: ");
7235 i = 0;
7236 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7237 if (i++ > 256)
7238 break;
7239 cur_col = printk("\n%3d ", scb->hscb->tag);
7240 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
7241 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
7242 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
7243 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7244 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7245 printk("(");
7246 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
7247 &cur_col, 60);
7248 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7249 printk(")");
7250 }
7251 }
7252 printk("\n");
7253
7254 printk("Kernel Free SCB list: ");
7255 i = 0;
7256 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
7257 if (i++ > 256)
7258 break;
7259 printk("%d ", scb->hscb->tag);
7260 }
7261 printk("\n");
7262
7263 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
7264 for (target = 0; target <= maxtarget; target++) {
7265 untagged_q = &ahc->untagged_queues[target];
7266 if (TAILQ_FIRST(untagged_q) == NULL)
7267 continue;
7268 printk("Untagged Q(%d): ", target);
7269 i = 0;
7270 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
7271 if (i++ > 256)
7272 break;
7273 printk("%d ", scb->hscb->tag);
7274 }
7275 printk("\n");
7276 }
7277
7278 ahc_platform_dump_card_state(ahc);
7279 printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
7280 ahc_outb(ahc, SCBPTR, saved_scbptr);
7281 if (paused == 0)
7282 ahc_unpause(ahc);
7283 }
7284
7285 /************************* Target Mode ****************************************/
7286 #ifdef AHC_TARGET_MODE
7287 cam_status
7288 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7289 struct ahc_tmode_tstate **tstate,
7290 struct ahc_tmode_lstate **lstate,
7291 int notfound_failure)
7292 {
7293
7294 if ((ahc->features & AHC_TARGETMODE) == 0)
7295 return (CAM_REQ_INVALID);
7296
7297 /*
7298 * Handle the 'black hole' device that sucks up
7299 * requests to unattached luns on enabled targets.
7300 */
7301 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7302 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7303 *tstate = NULL;
7304 *lstate = ahc->black_hole;
7305 } else {
7306 u_int max_id;
7307
7308 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
7309 if (ccb->ccb_h.target_id >= max_id)
7310 return (CAM_TID_INVALID);
7311
7312 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7313 return (CAM_LUN_INVALID);
7314
7315 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7316 *lstate = NULL;
7317 if (*tstate != NULL)
7318 *lstate =
7319 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7320 }
7321
7322 if (notfound_failure != 0 && *lstate == NULL)
7323 return (CAM_PATH_INVALID);
7324
7325 return (CAM_REQ_CMP);
7326 }
7327
7328 void
7329 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7330 {
7331 struct ahc_tmode_tstate *tstate;
7332 struct ahc_tmode_lstate *lstate;
7333 struct ccb_en_lun *cel;
7334 cam_status status;
7335 u_long s;
7336 u_int target;
7337 u_int lun;
7338 u_int target_mask;
7339 u_int our_id;
7340 int error;
7341 char channel;
7342
7343 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7344 /*notfound_failure*/FALSE);
7345
7346 if (status != CAM_REQ_CMP) {
7347 ccb->ccb_h.status = status;
7348 return;
7349 }
7350
7351 if (cam_sim_bus(sim) == 0)
7352 our_id = ahc->our_id;
7353 else
7354 our_id = ahc->our_id_b;
7355
7356 if (ccb->ccb_h.target_id != our_id) {
7357 /*
7358 * our_id represents our initiator ID, or
7359 * the ID of the first target to have an
7360 * enabled lun in target mode. There are
7361 * two cases that may preclude enabling a
7362 * target id other than our_id.
7363 *
7364 * o our_id is for an active initiator role.
7365 * Since the hardware does not support
7366 * reselections to the initiator role at
7367 * anything other than our_id, and our_id
7368 * is used by the hardware to indicate the
7369 * ID to use for both select-out and
7370 * reselect-out operations, the only target
7371 * ID we can support in this mode is our_id.
7372 *
7373 * o The MULTARGID feature is not available and
7374 * a previous target mode ID has been enabled.
7375 */
7376 if ((ahc->features & AHC_MULTIROLE) != 0) {
7377
7378 if ((ahc->features & AHC_MULTI_TID) != 0
7379 && (ahc->flags & AHC_INITIATORROLE) != 0) {
7380 /*
7381 * Only allow additional targets if
7382 * the initiator role is disabled.
7383 * The hardware cannot handle a re-select-in
7384 * on the initiator id during a re-select-out
7385 * on a different target id.
7386 */
7387 status = CAM_TID_INVALID;
7388 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7389 || ahc->enabled_luns > 0) {
7390 /*
7391 * Only allow our target id to change
7392 * if the initiator role is not configured
7393 * and there are no enabled luns which
7394 * are attached to the currently registered
7395 * scsi id.
7396 */
7397 status = CAM_TID_INVALID;
7398 }
7399 } else if ((ahc->features & AHC_MULTI_TID) == 0
7400 && ahc->enabled_luns > 0) {
7401
7402 status = CAM_TID_INVALID;
7403 }
7404 }
7405
7406 if (status != CAM_REQ_CMP) {
7407 ccb->ccb_h.status = status;
7408 return;
7409 }
7410
7411 /*
7412 * We now have an id that is valid.
7413 * If we aren't in target mode, switch modes.
7414 */
7415 if ((ahc->flags & AHC_TARGETROLE) == 0
7416 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7417 u_long s;
7418 ahc_flag saved_flags;
7419
7420 printk("Configuring Target Mode\n");
7421 ahc_lock(ahc, &s);
7422 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7423 ccb->ccb_h.status = CAM_BUSY;
7424 ahc_unlock(ahc, &s);
7425 return;
7426 }
7427 saved_flags = ahc->flags;
7428 ahc->flags |= AHC_TARGETROLE;
7429 if ((ahc->features & AHC_MULTIROLE) == 0)
7430 ahc->flags &= ~AHC_INITIATORROLE;
7431 ahc_pause(ahc);
7432 error = ahc_loadseq(ahc);
7433 if (error != 0) {
7434 /*
7435 * Restore original configuration and notify
7436 * the caller that we cannot support target mode.
7437 * Since the adapter started out in this
7438 * configuration, the firmware load will succeed,
7439 * so there is no point in checking ahc_loadseq's
7440 * return value.
7441 */
7442 ahc->flags = saved_flags;
7443 (void)ahc_loadseq(ahc);
7444 ahc_restart(ahc);
7445 ahc_unlock(ahc, &s);
7446 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7447 return;
7448 }
7449 ahc_restart(ahc);
7450 ahc_unlock(ahc, &s);
7451 }
7452 cel = &ccb->cel;
7453 target = ccb->ccb_h.target_id;
7454 lun = ccb->ccb_h.target_lun;
7455 channel = SIM_CHANNEL(ahc, sim);
7456 target_mask = 0x01 << target;
7457 if (channel == 'B')
7458 target_mask <<= 8;
7459
7460 if (cel->enable != 0) {
7461 u_int scsiseq;
7462
7463 /* Are we already enabled?? */
7464 if (lstate != NULL) {
7465 xpt_print_path(ccb->ccb_h.path);
7466 printk("Lun already enabled\n");
7467 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7468 return;
7469 }
7470
7471 if (cel->grp6_len != 0
7472 || cel->grp7_len != 0) {
7473 /*
7474 * Don't (yet?) support vendor
7475 * specific commands.
7476 */
7477 ccb->ccb_h.status = CAM_REQ_INVALID;
7478 printk("Non-zero Group Codes\n");
7479 return;
7480 }
7481
7482 /*
7483 * Seems to be okay.
7484 * Setup our data structures.
7485 */
7486 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7487 tstate = ahc_alloc_tstate(ahc, target, channel);
7488 if (tstate == NULL) {
7489 xpt_print_path(ccb->ccb_h.path);
7490 printk("Couldn't allocate tstate\n");
7491 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7492 return;
7493 }
7494 }
7495 lstate = kmalloc(sizeof(*lstate), GFP_ATOMIC);
7496 if (lstate == NULL) {
7497 xpt_print_path(ccb->ccb_h.path);
7498 printk("Couldn't allocate lstate\n");
7499 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7500 return;
7501 }
7502 memset(lstate, 0, sizeof(*lstate));
7503 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7504 xpt_path_path_id(ccb->ccb_h.path),
7505 xpt_path_target_id(ccb->ccb_h.path),
7506 xpt_path_lun_id(ccb->ccb_h.path));
7507 if (status != CAM_REQ_CMP) {
7508 kfree(lstate);
7509 xpt_print_path(ccb->ccb_h.path);
7510 printk("Couldn't allocate path\n");
7511 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7512 return;
7513 }
7514 SLIST_INIT(&lstate->accept_tios);
7515 SLIST_INIT(&lstate->immed_notifies);
7516 ahc_lock(ahc, &s);
7517 ahc_pause(ahc);
7518 if (target != CAM_TARGET_WILDCARD) {
7519 tstate->enabled_luns[lun] = lstate;
7520 ahc->enabled_luns++;
7521
7522 if ((ahc->features & AHC_MULTI_TID) != 0) {
7523 u_int targid_mask;
7524
7525 targid_mask = ahc_inb(ahc, TARGID)
7526 | (ahc_inb(ahc, TARGID + 1) << 8);
7527
7528 targid_mask |= target_mask;
7529 ahc_outb(ahc, TARGID, targid_mask);
7530 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7531
7532 ahc_update_scsiid(ahc, targid_mask);
7533 } else {
7534 u_int our_id;
7535 char channel;
7536
7537 channel = SIM_CHANNEL(ahc, sim);
7538 our_id = SIM_SCSI_ID(ahc, sim);
7539
7540 /*
7541 * This can only happen if selections
7542 * are not enabled
7543 */
7544 if (target != our_id) {
7545 u_int sblkctl;
7546 char cur_channel;
7547 int swap;
7548
7549 sblkctl = ahc_inb(ahc, SBLKCTL);
7550 cur_channel = (sblkctl & SELBUSB)
7551 ? 'B' : 'A';
7552 if ((ahc->features & AHC_TWIN) == 0)
7553 cur_channel = 'A';
7554 swap = cur_channel != channel;
7555 if (channel == 'A')
7556 ahc->our_id = target;
7557 else
7558 ahc->our_id_b = target;
7559
7560 if (swap)
7561 ahc_outb(ahc, SBLKCTL,
7562 sblkctl ^ SELBUSB);
7563
7564 ahc_outb(ahc, SCSIID, target);
7565
7566 if (swap)
7567 ahc_outb(ahc, SBLKCTL, sblkctl);
7568 }
7569 }
7570 } else
7571 ahc->black_hole = lstate;
7572 /* Allow select-in operations */
7573 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7574 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7575 scsiseq |= ENSELI;
7576 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7577 scsiseq = ahc_inb(ahc, SCSISEQ);
7578 scsiseq |= ENSELI;
7579 ahc_outb(ahc, SCSISEQ, scsiseq);
7580 }
7581 ahc_unpause(ahc);
7582 ahc_unlock(ahc, &s);
7583 ccb->ccb_h.status = CAM_REQ_CMP;
7584 xpt_print_path(ccb->ccb_h.path);
7585 printk("Lun now enabled for target mode\n");
7586 } else {
7587 struct scb *scb;
7588 int i, empty;
7589
7590 if (lstate == NULL) {
7591 ccb->ccb_h.status = CAM_LUN_INVALID;
7592 return;
7593 }
7594
7595 ahc_lock(ahc, &s);
7596
7597 ccb->ccb_h.status = CAM_REQ_CMP;
7598 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7599 struct ccb_hdr *ccbh;
7600
7601 ccbh = &scb->io_ctx->ccb_h;
7602 if (ccbh->func_code == XPT_CONT_TARGET_IO
7603 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7604 printk("CTIO pending\n");
7605 ccb->ccb_h.status = CAM_REQ_INVALID;
7606 ahc_unlock(ahc, &s);
7607 return;
7608 }
7609 }
7610
7611 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7612 printk("ATIOs pending\n");
7613 ccb->ccb_h.status = CAM_REQ_INVALID;
7614 }
7615
7616 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7617 printk("INOTs pending\n");
7618 ccb->ccb_h.status = CAM_REQ_INVALID;
7619 }
7620
7621 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7622 ahc_unlock(ahc, &s);
7623 return;
7624 }
7625
7626 xpt_print_path(ccb->ccb_h.path);
7627 printk("Target mode disabled\n");
7628 xpt_free_path(lstate->path);
7629 kfree(lstate);
7630
7631 ahc_pause(ahc);
7632 /* Can we clean up the target too? */
7633 if (target != CAM_TARGET_WILDCARD) {
7634 tstate->enabled_luns[lun] = NULL;
7635 ahc->enabled_luns--;
7636 for (empty = 1, i = 0; i < 8; i++)
7637 if (tstate->enabled_luns[i] != NULL) {
7638 empty = 0;
7639 break;
7640 }
7641
7642 if (empty) {
7643 ahc_free_tstate(ahc, target, channel,
7644 /*force*/FALSE);
7645 if (ahc->features & AHC_MULTI_TID) {
7646 u_int targid_mask;
7647
7648 targid_mask = ahc_inb(ahc, TARGID)
7649 | (ahc_inb(ahc, TARGID + 1)
7650 << 8);
7651
7652 targid_mask &= ~target_mask;
7653 ahc_outb(ahc, TARGID, targid_mask);
7654 ahc_outb(ahc, TARGID+1,
7655 (targid_mask >> 8));
7656 ahc_update_scsiid(ahc, targid_mask);
7657 }
7658 }
7659 } else {
7660
7661 ahc->black_hole = NULL;
7662
7663 /*
7664 * We can't allow selections without
7665 * our black hole device.
7666 */
7667 empty = TRUE;
7668 }
7669 if (ahc->enabled_luns == 0) {
7670 /* Disallow select-in */
7671 u_int scsiseq;
7672
7673 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7674 scsiseq &= ~ENSELI;
7675 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7676 scsiseq = ahc_inb(ahc, SCSISEQ);
7677 scsiseq &= ~ENSELI;
7678 ahc_outb(ahc, SCSISEQ, scsiseq);
7679
7680 if ((ahc->features & AHC_MULTIROLE) == 0) {
7681 printk("Configuring Initiator Mode\n");
7682 ahc->flags &= ~AHC_TARGETROLE;
7683 ahc->flags |= AHC_INITIATORROLE;
7684 /*
7685 * Returning to a configuration that
7686 * fit previously will always succeed.
7687 */
7688 (void)ahc_loadseq(ahc);
7689 ahc_restart(ahc);
7690 /*
7691 * Unpaused. The extra unpause
7692 * that follows is harmless.
7693 */
7694 }
7695 }
7696 ahc_unpause(ahc);
7697 ahc_unlock(ahc, &s);
7698 }
7699 }
7700
7701 static void
7702 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7703 {
7704 u_int scsiid_mask;
7705 u_int scsiid;
7706
7707 if ((ahc->features & AHC_MULTI_TID) == 0)
7708 panic("ahc_update_scsiid called on non-multitid unit\n");
7709
7710 /*
7711 * Since we will rely on the TARGID mask
7712 * for selection enables, ensure that OID
7713 * in SCSIID is not set to some other ID
7714 * that we don't want to allow selections on.
7715 */
7716 if ((ahc->features & AHC_ULTRA2) != 0)
7717 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7718 else
7719 scsiid = ahc_inb(ahc, SCSIID);
7720 scsiid_mask = 0x1 << (scsiid & OID);
7721 if ((targid_mask & scsiid_mask) == 0) {
7722 u_int our_id;
7723
7724 /* ffs counts from 1 */
7725 our_id = ffs(targid_mask);
7726 if (our_id == 0)
7727 our_id = ahc->our_id;
7728 else
7729 our_id--;
7730 scsiid &= TID;
7731 scsiid |= our_id;
7732 }
7733 if ((ahc->features & AHC_ULTRA2) != 0)
7734 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7735 else
7736 ahc_outb(ahc, SCSIID, scsiid);
7737 }
7738
7739 static void
7740 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7741 {
7742 struct target_cmd *cmd;
7743
7744 /*
7745 * If the card supports auto-access pause,
7746 * we can access the card directly regardless
7747 * of whether it is paused or not.
7748 */
7749 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7750 paused = TRUE;
7751
7752 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7753 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7754
7755 /*
7756 * Only advance through the queue if we
7757 * have the resources to process the command.
7758 */
7759 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7760 break;
7761
7762 cmd->cmd_valid = 0;
7763 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7764 ahc->shared_data_dmamap,
7765 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7766 sizeof(struct target_cmd),
7767 BUS_DMASYNC_PREREAD);
7768 ahc->tqinfifonext++;
7769
7770 /*
7771 * Lazily update our position in the target mode incoming
7772 * command queue as seen by the sequencer.
7773 */
7774 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7775 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7776 u_int hs_mailbox;
7777
7778 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7779 hs_mailbox &= ~HOST_TQINPOS;
7780 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7781 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7782 } else {
7783 if (!paused)
7784 ahc_pause(ahc);
7785 ahc_outb(ahc, KERNEL_TQINPOS,
7786 ahc->tqinfifonext & HOST_TQINPOS);
7787 if (!paused)
7788 ahc_unpause(ahc);
7789 }
7790 }
7791 }
7792 }
7793
7794 static int
7795 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7796 {
7797 struct ahc_tmode_tstate *tstate;
7798 struct ahc_tmode_lstate *lstate;
7799 struct ccb_accept_tio *atio;
7800 uint8_t *byte;
7801 int initiator;
7802 int target;
7803 int lun;
7804
7805 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7806 target = SCSIID_OUR_ID(cmd->scsiid);
7807 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7808
7809 byte = cmd->bytes;
7810 tstate = ahc->enabled_targets[target];
7811 lstate = NULL;
7812 if (tstate != NULL)
7813 lstate = tstate->enabled_luns[lun];
7814
7815 /*
7816 * Commands for disabled luns go to the black hole driver.
7817 */
7818 if (lstate == NULL)
7819 lstate = ahc->black_hole;
7820
7821 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7822 if (atio == NULL) {
7823 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7824 /*
7825 * Wait for more ATIOs from the peripheral driver for this lun.
7826 */
7827 if (bootverbose)
7828 printk("%s: ATIOs exhausted\n", ahc_name(ahc));
7829 return (1);
7830 } else
7831 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7832 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7833
7834 if (lstate == ahc->black_hole) {
7835 /* Fill in the wildcards */
7836 atio->ccb_h.target_id = target;
7837 atio->ccb_h.target_lun = lun;
7838 }
7839
7840 /*
7841 * Package it up and send it off to
7842 * whomever has this lun enabled.
7843 */
7844 atio->sense_len = 0;
7845 atio->init_id = initiator;
7846 if (byte[0] != 0xFF) {
7847 /* Tag was included */
7848 atio->tag_action = *byte++;
7849 atio->tag_id = *byte++;
7850 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7851 } else {
7852 atio->ccb_h.flags = 0;
7853 }
7854 byte++;
7855
7856 /* Okay. Now determine the cdb size based on the command code */
7857 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7858 case 0:
7859 atio->cdb_len = 6;
7860 break;
7861 case 1:
7862 case 2:
7863 atio->cdb_len = 10;
7864 break;
7865 case 4:
7866 atio->cdb_len = 16;
7867 break;
7868 case 5:
7869 atio->cdb_len = 12;
7870 break;
7871 case 3:
7872 default:
7873 /* Only copy the opcode. */
7874 atio->cdb_len = 1;
7875 printk("Reserved or VU command code type encountered\n");
7876 break;
7877 }
7878
7879 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7880
7881 atio->ccb_h.status |= CAM_CDB_RECVD;
7882
7883 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7884 /*
7885 * We weren't allowed to disconnect.
7886 * We're hanging on the bus until a
7887 * continue target I/O comes in response
7888 * to this accept tio.
7889 */
7890 ahc->pending_device = lstate;
7891 ahc_freeze_ccb((union ccb *)atio);
7892 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7893 }
7894 xpt_done((union ccb*)atio);
7895 return (0);
7896 }
7897
7898 #endif
Tomato firmware and modifications.