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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / pcmcia / m8xx_pcmcia.c
blobcaf5ab17d0ef696f78b92eb18edfc0d241d6a6ae
1 /*
2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
3 *
4 * (C) 1999-2000 Magnus Damm <damm@opensource.se>
5 * (C) 2001-2002 Montavista Software, Inc.
6 * <mlocke@mvista.com>
7 *
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
12 *
13 * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
15 *
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
20 *
21 * This controller does _not_ meet the ExCA standard.
22 *
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
28 *
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
35 */
36
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
42
43 #include <linux/kernel.h>
44 #include <linux/errno.h>
45 #include <linux/timer.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <linux/fsl_devices.h>
50 #include <linux/bitops.h>
51 #include <linux/of_device.h>
52 #include <linux/of_platform.h>
53
54 #include <asm/io.h>
55 #include <asm/system.h>
56 #include <asm/time.h>
57 #include <asm/mpc8xx.h>
58 #include <asm/8xx_immap.h>
59 #include <asm/irq.h>
60 #include <asm/fs_pd.h>
61
62 #include <pcmcia/cs.h>
63 #include <pcmcia/ss.h>
64
65 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
66 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
67
68 static const char *version = "Version 0.06, Aug 2005";
69 MODULE_LICENSE("Dual MPL/GPL");
70
71 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
72
73 /* The RPX series use SLOT_B */
74 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
75 #define CONFIG_PCMCIA_SLOT_B
76 #define CONFIG_BD_IS_MHZ
77 #endif
78
79 /* The ADS board use SLOT_A */
80 #ifdef CONFIG_ADS
81 #define CONFIG_PCMCIA_SLOT_A
82 #define CONFIG_BD_IS_MHZ
83 #endif
84
85 /* The FADS series are a mess */
86 #ifdef CONFIG_FADS
87 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
88 #define CONFIG_PCMCIA_SLOT_A
89 #else
90 #define CONFIG_PCMCIA_SLOT_B
91 #endif
92 #endif
93
94 #if defined(CONFIG_MPC885ADS)
95 #define CONFIG_PCMCIA_SLOT_A
96 #define PCMCIA_GLITCHY_CD
97 #endif
98
99 /* Cyclades ACS uses both slots */
100 #ifdef CONFIG_PRxK
101 #define CONFIG_PCMCIA_SLOT_A
102 #define CONFIG_PCMCIA_SLOT_B
103 #endif
104
105 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
106
107 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
108
109 #define PCMCIA_SOCKETS_NO 2
110 /* We have only 8 windows, dualsocket support will be limited. */
111 #define PCMCIA_MEM_WIN_NO 2
112 #define PCMCIA_IO_WIN_NO 2
113 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
114
115 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
116
117 #define PCMCIA_SOCKETS_NO 1
118 /* full support for one slot */
119 #define PCMCIA_MEM_WIN_NO 5
120 #define PCMCIA_IO_WIN_NO 2
121
122 /* define _slot_ to be able to optimize macros */
123
124 #ifdef CONFIG_PCMCIA_SLOT_A
125 #define _slot_ 0
126 #define PCMCIA_SLOT_MSG "SLOT_A"
127 #else
128 #define _slot_ 1
129 #define PCMCIA_SLOT_MSG "SLOT_B"
130 #endif
131
132 #else
133 #error m8xx_pcmcia: Bad configuration!
134 #endif
135
136 /* ------------------------------------------------------------------------- */
137
138 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
139 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
140 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
141 /* ------------------------------------------------------------------------- */
142
143 static int pcmcia_schlvl;
144
145 static DEFINE_SPINLOCK(events_lock);
146
147 #define PCMCIA_SOCKET_KEY_5V 1
148 #define PCMCIA_SOCKET_KEY_LV 2
149
150 /* look up table for pgcrx registers */
151 static u32 *m8xx_pgcrx[2];
152
153 /*
154 * This structure is used to address each window in the PCMCIA controller.
155 *
156 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
157 * after pcmcia_win[n]...
158 */
159
160 struct pcmcia_win {
161 u32 br;
162 u32 or;
163 };
164
165 /*
166 * For some reason the hardware guys decided to make both slots share
167 * some registers.
168 *
169 * Could someone invent object oriented hardware ?
170 *
171 * The macros are used to get the right bit from the registers.
172 * SLOT_A : slot = 0
173 * SLOT_B : slot = 1
174 */
175
176 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
177 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
178 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
179 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
180
181 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
182 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
183 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
184 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
185 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
186 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
187 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
188 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
189 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
190 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
191 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
192
193 #define M8XX_PCMCIA_POR_VALID 0x00000001
194 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
195 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
196 #define M8XX_PCMCIA_POR_IO 0x00000018
197 #define M8XX_PCMCIA_POR_16BIT 0x00000040
198
199 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
200
201 #define M8XX_PGCRX_CXOE 0x00000080
202 #define M8XX_PGCRX_CXRESET 0x00000040
203
204 /* we keep one lookup table per socket to check flags */
205
206 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
207
208 struct event_table {
209 u32 regbit;
210 u32 eventbit;
211 };
212
213 static const char driver_name[] = "m8xx-pcmcia";
214
215 struct socket_info {
216 void (*handler) (void *info, u32 events);
217 void *info;
218
219 u32 slot;
220 pcmconf8xx_t *pcmcia;
221 u32 bus_freq;
222 int hwirq;
223
224 socket_state_t state;
225 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
226 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
227 struct event_table events[PCMCIA_EVENTS_MAX];
228 struct pcmcia_socket socket;
229 };
230
231 static struct socket_info socket[PCMCIA_SOCKETS_NO];
232
233 /*
234 * Search this table to see if the windowsize is
235 * supported...
236 */
237
238 #define M8XX_SIZES_NO 32
239
240 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = {
241 0x00000001, 0x00000002, 0x00000008, 0x00000004,
242 0x00000080, 0x00000040, 0x00000010, 0x00000020,
243 0x00008000, 0x00004000, 0x00001000, 0x00002000,
244 0x00000100, 0x00000200, 0x00000800, 0x00000400,
245
246 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
247 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
248 0x00010000, 0x00020000, 0x00080000, 0x00040000,
249 0x00800000, 0x00400000, 0x00100000, 0x00200000
250 };
251
252 /* ------------------------------------------------------------------------- */
253
254 static irqreturn_t m8xx_interrupt(int irq, void *dev);
255
256 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
257
258 /* ------------------------------------------------------------------------- */
259 /* board specific stuff: */
260 /* voltage_set(), hardware_enable() and hardware_disable() */
261 /* ------------------------------------------------------------------------- */
262 /* RPX Boards from Embedded Planet */
263
264 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
265
266 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
267 * SYPCR is write once only, therefore must the slowest memory be faster
268 * than the bus monitor or we will get a machine check due to the bus timeout.
269 */
270
271 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
272
273 #undef PCMCIA_BMT_LIMIT
274 #define PCMCIA_BMT_LIMIT (6*8)
275
276 static int voltage_set(int slot, int vcc, int vpp)
277 {
278 u32 reg = 0;
279
280 switch (vcc) {
281 case 0:
282 break;
283 case 33:
284 reg |= BCSR1_PCVCTL4;
285 break;
286 case 50:
287 reg |= BCSR1_PCVCTL5;
288 break;
289 default:
290 return 1;
291 }
292
293 switch (vpp) {
294 case 0:
295 break;
296 case 33:
297 case 50:
298 if (vcc == vpp)
299 reg |= BCSR1_PCVCTL6;
300 else
301 return 1;
302 break;
303 case 120:
304 reg |= BCSR1_PCVCTL7;
305 default:
306 return 1;
307 }
308
309 if (!((vcc == 50) || (vcc == 0)))
310 return 1;
311
312 /* first, turn off all power */
313
314 out_be32(((u32 *) RPX_CSR_ADDR),
315 in_be32(((u32 *) RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 |
316 BCSR1_PCVCTL5 |
317 BCSR1_PCVCTL6 |
318 BCSR1_PCVCTL7));
319
320 /* enable new powersettings */
321
322 out_be32(((u32 *) RPX_CSR_ADDR), in_be32(((u32 *) RPX_CSR_ADDR)) | reg);
323
324 return 0;
325 }
326
327 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
328 #define hardware_enable(_slot_) /* No hardware to enable */
329 #define hardware_disable(_slot_) /* No hardware to disable */
330
331 #endif /* CONFIG_RPXCLASSIC */
332
333 /* FADS Boards from Motorola */
334
335 #if defined(CONFIG_FADS)
336
337 #define PCMCIA_BOARD_MSG "FADS"
338
339 static int voltage_set(int slot, int vcc, int vpp)
340 {
341 u32 reg = 0;
342
343 switch (vcc) {
344 case 0:
345 break;
346 case 33:
347 reg |= BCSR1_PCCVCC0;
348 break;
349 case 50:
350 reg |= BCSR1_PCCVCC1;
351 break;
352 default:
353 return 1;
354 }
355
356 switch (vpp) {
357 case 0:
358 break;
359 case 33:
360 case 50:
361 if (vcc == vpp)
362 reg |= BCSR1_PCCVPP1;
363 else
364 return 1;
365 break;
366 case 120:
367 if ((vcc == 33) || (vcc == 50))
368 reg |= BCSR1_PCCVPP0;
369 else
370 return 1;
371 default:
372 return 1;
373 }
374
375 /* first, turn off all power */
376 out_be32((u32 *) BCSR1,
377 in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK |
378 BCSR1_PCCVPP_MASK));
379
380 /* enable new powersettings */
381 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg);
382
383 return 0;
384 }
385
386 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
387
388 static void hardware_enable(int slot)
389 {
390 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN);
391 }
392
393 static void hardware_disable(int slot)
394 {
395 out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN);
396 }
397
398 #endif
399
400 /* MPC885ADS Boards */
401
402 #if defined(CONFIG_MPC885ADS)
403
404 #define PCMCIA_BOARD_MSG "MPC885ADS"
405 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
406
407 static inline void hardware_enable(int slot)
408 {
409 m8xx_pcmcia_ops.hw_ctrl(slot, 1);
410 }
411
412 static inline void hardware_disable(int slot)
413 {
414 m8xx_pcmcia_ops.hw_ctrl(slot, 0);
415 }
416
417 static inline int voltage_set(int slot, int vcc, int vpp)
418 {
419 return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
420 }
421
422 #endif
423
424 /* ------------------------------------------------------------------------- */
425 /* Motorola MBX860 */
426
427 #if defined(CONFIG_MBX)
428
429 #define PCMCIA_BOARD_MSG "MBX"
430
431 static int voltage_set(int slot, int vcc, int vpp)
432 {
433 u8 reg = 0;
434
435 switch (vcc) {
436 case 0:
437 break;
438 case 33:
439 reg |= CSR2_VCC_33;
440 break;
441 case 50:
442 reg |= CSR2_VCC_50;
443 break;
444 default:
445 return 1;
446 }
447
448 switch (vpp) {
449 case 0:
450 break;
451 case 33:
452 case 50:
453 if (vcc == vpp)
454 reg |= CSR2_VPP_VCC;
455 else
456 return 1;
457 break;
458 case 120:
459 if ((vcc == 33) || (vcc == 50))
460 reg |= CSR2_VPP_12;
461 else
462 return 1;
463 default:
464 return 1;
465 }
466
467 /* first, turn off all power */
468 out_8((u8 *) MBX_CSR2_ADDR,
469 in_8((u8 *) MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
470
471 /* enable new powersettings */
472 out_8((u8 *) MBX_CSR2_ADDR, in_8((u8 *) MBX_CSR2_ADDR) | reg);
473
474 return 0;
475 }
476
477 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
478 #define hardware_enable(_slot_) /* No hardware to enable */
479 #define hardware_disable(_slot_) /* No hardware to disable */
480
481 #endif /* CONFIG_MBX */
482
483 #if defined(CONFIG_PRxK)
484 #include <asm/cpld.h>
485 extern volatile fpga_pc_regs *fpga_pc;
486
487 #define PCMCIA_BOARD_MSG "MPC855T"
488
489 static int voltage_set(int slot, int vcc, int vpp)
490 {
491 u8 reg = 0;
492 u8 regread;
493 cpld_regs *ccpld = get_cpld();
494
495 switch (vcc) {
496 case 0:
497 break;
498 case 33:
499 reg |= PCMCIA_VCC_33;
500 break;
501 case 50:
502 reg |= PCMCIA_VCC_50;
503 break;
504 default:
505 return 1;
506 }
507
508 switch (vpp) {
509 case 0:
510 break;
511 case 33:
512 case 50:
513 if (vcc == vpp)
514 reg |= PCMCIA_VPP_VCC;
515 else
516 return 1;
517 break;
518 case 120:
519 if ((vcc == 33) || (vcc == 50))
520 reg |= PCMCIA_VPP_12;
521 else
522 return 1;
523 default:
524 return 1;
525 }
526
527 reg = reg >> (slot << 2);
528 regread = in_8(&ccpld->fpga_pc_ctl);
529 if (reg !=
530 (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
531 /* enable new powersettings */
532 regread =
533 regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >>
534 (slot << 2));
535 out_8(&ccpld->fpga_pc_ctl, reg | regread);
536 msleep(100);
537 }
538
539 return 0;
540 }
541
542 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
543 #define hardware_enable(_slot_) /* No hardware to enable */
544 #define hardware_disable(_slot_) /* No hardware to disable */
545
546 #endif /* CONFIG_PRxK */
547
548 static u32 pending_events[PCMCIA_SOCKETS_NO];
549 static DEFINE_SPINLOCK(pending_event_lock);
550
551 static irqreturn_t m8xx_interrupt(int irq, void *dev)
552 {
553 struct socket_info *s;
554 struct event_table *e;
555 unsigned int i, events, pscr, pipr, per;
556 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
557
558 pr_debug("m8xx_pcmcia: Interrupt!\n");
559 /* get interrupt sources */
560
561 pscr = in_be32(&pcmcia->pcmc_pscr);
562 pipr = in_be32(&pcmcia->pcmc_pipr);
563 per = in_be32(&pcmcia->pcmc_per);
564
565 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
566 s = &socket[i];
567 e = &s->events[0];
568 events = 0;
569
570 while (e->regbit) {
571 if (pscr & e->regbit)
572 events |= e->eventbit;
573
574 e++;
575 }
576
577 /*
578 * report only if both card detect signals are the same
579 * not too nice done,
580 * we depend on that CD2 is the bit to the left of CD1...
581 */
582 if (events & SS_DETECT)
583 if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
584 (pipr & M8XX_PCMCIA_CD1(i))) {
585 events &= ~SS_DETECT;
586 }
587 #ifdef PCMCIA_GLITCHY_CD
588 /*
589 * I've experienced CD problems with my ADS board.
590 * We make an extra check to see if there was a
591 * real change of Card detection.
592 */
593
594 if ((events & SS_DETECT) &&
595 ((pipr &
596 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
597 (s->state.Vcc | s->state.Vpp)) {
598 events &= ~SS_DETECT;
599 }
600 #endif
601
602 /* call the handler */
603
604 pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, "
605 "pipr = 0x%08x\n", i, events, pscr, pipr);
606
607 if (events) {
608 spin_lock(&pending_event_lock);
609 pending_events[i] |= events;
610 spin_unlock(&pending_event_lock);
611 /*
612 * Turn off RDY_L bits in the PER mask on
613 * CD interrupt receival.
614 *
615 * They can generate bad interrupts on the
616 * ACS4,8,16,32. - marcelo
617 */
618 per &= ~M8XX_PCMCIA_RDY_L(0);
619 per &= ~M8XX_PCMCIA_RDY_L(1);
620
621 out_be32(&pcmcia->pcmc_per, per);
622
623 if (events)
624 pcmcia_parse_events(&socket[i].socket, events);
625 }
626 }
627
628 /* clear the interrupt sources */
629 out_be32(&pcmcia->pcmc_pscr, pscr);
630
631 pr_debug("m8xx_pcmcia: Interrupt done.\n");
632
633 return IRQ_HANDLED;
634 }
635
636 static u32 m8xx_get_graycode(u32 size)
637 {
638 u32 k;
639
640 for (k = 0; k < M8XX_SIZES_NO; k++)
641 if (m8xx_size_to_gray[k] == size)
642 break;
643
644 if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
645 k = -1;
646
647 return k;
648 }
649
650 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
651 {
652 u32 reg, clocks, psst, psl, psht;
653
654 if (!ns) {
655
656 /*
657 * We get called with IO maps setup to 0ns
658 * if not specified by the user.
659 * They should be 255ns.
660 */
661
662 if (is_io)
663 ns = 255;
664 else
665 ns = 100; /* fast memory if 0 */
666 }
667
668 /*
669 * In PSST, PSL, PSHT fields we tell the controller
670 * timing parameters in CLKOUT clock cycles.
671 * CLKOUT is the same as GCLK2_50.
672 */
673
674 /* how we want to adjust the timing - in percent */
675
676 #define ADJ 180 /* 80 % longer accesstime - to be sure */
677
678 clocks = ((bus_freq / 1000) * ns) / 1000;
679 clocks = (clocks * ADJ) / (100 * 1000);
680 if (clocks >= PCMCIA_BMT_LIMIT) {
681 printk("Max access time limit reached\n");
682 clocks = PCMCIA_BMT_LIMIT - 1;
683 }
684
685 psst = clocks / 7; /* setup time */
686 psht = clocks / 7; /* hold time */
687 psl = (clocks * 5) / 7; /* strobe length */
688
689 psst += clocks - (psst + psht + psl);
690
691 reg = psst << 12;
692 reg |= psl << 7;
693 reg |= psht << 16;
694
695 return reg;
696 }
697
698 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
699 {
700 int lsock = container_of(sock, struct socket_info, socket)->slot;
701 struct socket_info *s = &socket[lsock];
702 unsigned int pipr, reg;
703 pcmconf8xx_t *pcmcia = s->pcmcia;
704
705 pipr = in_be32(&pcmcia->pcmc_pipr);
706
707 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
708 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
709 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
710
711 if (s->state.flags & SS_IOCARD)
712 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
713 else {
714 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
715 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
716 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
717 }
718
719 if (s->state.Vcc | s->state.Vpp)
720 *value |= SS_POWERON;
721
722 /*
723 * Voltage detection:
724 * This driver only supports 16-Bit pc-cards.
725 * Cardbus is not handled here.
726 *
727 * To determine what voltage to use we must read the VS1 and VS2 pin.
728 * Depending on what socket type is present,
729 * different combinations mean different things.
730 *
731 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
732 *
733 * 5V 5V, LV* NC NC 5V only 5V (if available)
734 *
735 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
736 *
737 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
738 *
739 * LV* 5V - - shall not fit into socket
740 *
741 * LV* LV* GND NC 3.3V only 3.3V
742 *
743 * LV* LV* NC GND x.xV x.xV (if avail.)
744 *
745 * LV* LV* GND GND 3.3 or x.xV as low as possible
746 *
747 * *LV means Low Voltage
748 *
749 *
750 * That gives us the following table:
751 *
752 * Socket VS1 VS2 Voltage
753 *
754 * 5V NC NC 5V
755 * 5V NC GND none (should not be possible)
756 * 5V GND NC >= 3.3V
757 * 5V GND GND >= x.xV
758 *
759 * LV NC NC 5V (if available)
760 * LV NC GND x.xV (if available)
761 * LV GND NC 3.3V
762 * LV GND GND >= x.xV
763 *
764 * So, how do I determine if I have a 5V or a LV
765 * socket on my board? Look at the socket!
766 *
767 *
768 * Socket with 5V key:
769 * ++--------------------------------------------+
770 * || |
771 * || ||
772 * || ||
773 * | |
774 * +---------------------------------------------+
775 *
776 * Socket with LV key:
777 * ++--------------------------------------------+
778 * || |
779 * | ||
780 * | ||
781 * | |
782 * +---------------------------------------------+
783 *
784 *
785 * With other words - LV only cards does not fit
786 * into the 5V socket!
787 */
788
789 /* read out VS1 and VS2 */
790
791 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
792 >> M8XX_PCMCIA_VS_SHIFT(lsock);
793
794 if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
795 switch (reg) {
796 case 1:
797 *value |= SS_3VCARD;
798 break; /* GND, NC - 3.3V only */
799 case 2:
800 *value |= SS_XVCARD;
801 break; /* NC. GND - x.xV only */
802 };
803 }
804
805 pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value);
806 return 0;
807 }
808
809 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state)
810 {
811 int lsock = container_of(sock, struct socket_info, socket)->slot;
812 struct socket_info *s = &socket[lsock];
813 struct event_table *e;
814 unsigned int reg;
815 unsigned long flags;
816 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
817
818 pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
819 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
820 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
821
822 /* First, set voltage - bail out if invalid */
823 if (voltage_set(lsock, state->Vcc, state->Vpp))
824 return -EINVAL;
825
826 /* Take care of reset... */
827 if (state->flags & SS_RESET)
828 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
829 else
830 out_be32(M8XX_PGCRX(lsock),
831 in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
832
833 /* ... and output enable. */
834
835 /* The CxOE signal is connected to a 74541 on the ADS.
836 I guess most other boards used the ADS as a reference.
837 I tried to control the CxOE signal with SS_OUTPUT_ENA,
838 but the reset signal seems connected via the 541.
839 If the CxOE is left high are some signals tristated and
840 no pullups are present -> the cards act weird.
841 So right now the buffers are enabled if the power is on. */
842
843 if (state->Vcc || state->Vpp)
844 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
845 else
846 out_be32(M8XX_PGCRX(lsock),
847 in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
848
849 /*
850 * We'd better turn off interrupts before
851 * we mess with the events-table..
852 */
853
854 spin_lock_irqsave(&events_lock, flags);
855
856 /*
857 * Play around with the interrupt mask to be able to
858 * give the events the generic pcmcia driver wants us to.
859 */
860
861 e = &s->events[0];
862 reg = 0;
863
864 if (state->csc_mask & SS_DETECT) {
865 e->eventbit = SS_DETECT;
866 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
867 | M8XX_PCMCIA_CD1(lsock));
868 e++;
869 }
870 if (state->flags & SS_IOCARD) {
871 /*
872 * I/O card
873 */
874 if (state->csc_mask & SS_STSCHG) {
875 e->eventbit = SS_STSCHG;
876 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
877 e++;
878 }
879 /*
880 * If io_irq is non-zero we should enable irq.
881 */
882 if (state->io_irq) {
883 out_be32(M8XX_PGCRX(lsock),
884 in_be32(M8XX_PGCRX(lsock)) |
885 mk_int_int_mask(s->hwirq) << 24);
886 /*
887 * Strange thing here:
888 * The manual does not tell us which interrupt
889 * the sources generate.
890 * Anyhow, I found out that RDY_L generates IREQLVL.
891 *
892 * We use level triggerd interrupts, and they don't
893 * have to be cleared in PSCR in the interrupt handler.
894 */
895 reg |= M8XX_PCMCIA_RDY_L(lsock);
896 } else
897 out_be32(M8XX_PGCRX(lsock),
898 in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
899 } else {
900 /*
901 * Memory card
902 */
903 if (state->csc_mask & SS_BATDEAD) {
904 e->eventbit = SS_BATDEAD;
905 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
906 e++;
907 }
908 if (state->csc_mask & SS_BATWARN) {
909 e->eventbit = SS_BATWARN;
910 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
911 e++;
912 }
913 /* What should I trigger on - low/high,raise,fall? */
914 if (state->csc_mask & SS_READY) {
915 e->eventbit = SS_READY;
916 reg |= e->regbit = 0; //??
917 e++;
918 }
919 }
920
921 e->regbit = 0; /* terminate list */
922
923 /*
924 * Clear the status changed .
925 * Port A and Port B share the same port.
926 * Writing ones will clear the bits.
927 */
928
929 out_be32(&pcmcia->pcmc_pscr, reg);
930
931 /*
932 * Write the mask.
933 * Port A and Port B share the same port.
934 * Need for read-modify-write.
935 * Ones will enable the interrupt.
936 */
937
938 reg |=
939 in_be32(&pcmcia->
940 pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
941 out_be32(&pcmcia->pcmc_per, reg);
942
943 spin_unlock_irqrestore(&events_lock, flags);
944
945 /* copy the struct and modify the copy */
946
947 s->state = *state;
948
949 return 0;
950 }
951
952 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
953 {
954 int lsock = container_of(sock, struct socket_info, socket)->slot;
955
956 struct socket_info *s = &socket[lsock];
957 struct pcmcia_win *w;
958 unsigned int reg, winnr;
959 pcmconf8xx_t *pcmcia = s->pcmcia;
960
961 #define M8XX_SIZE (io->stop - io->start + 1)
962 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
963
964 pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, "
965 "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags,
966 io->speed, (unsigned long long)io->start,
967 (unsigned long long)io->stop);
968
969 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
970 || (io->stop > 0xffff) || (io->stop < io->start))
971 return -EINVAL;
972
973 if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
974 return -EINVAL;
975
976 if (io->flags & MAP_ACTIVE) {
977
978 pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n");
979
980 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
981 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
982
983 /* setup registers */
984
985 w = (void *)&pcmcia->pcmc_pbr0;
986 w += winnr;
987
988 out_be32(&w->or, 0); /* turn off window first */
989 out_be32(&w->br, M8XX_BASE);
990
991 reg <<= 27;
992 reg |= M8XX_PCMCIA_POR_IO | (lsock << 2);
993
994 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
995
996 if (io->flags & MAP_WRPROT)
997 reg |= M8XX_PCMCIA_POR_WRPROT;
998
999 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */
1000 if (io->flags & MAP_16BIT)
1001 reg |= M8XX_PCMCIA_POR_16BIT;
1002
1003 if (io->flags & MAP_ACTIVE)
1004 reg |= M8XX_PCMCIA_POR_VALID;
1005
1006 out_be32(&w->or, reg);
1007
1008 pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at "
1009 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1010 } else {
1011 /* shutdown IO window */
1012 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1013 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1014
1015 /* setup registers */
1016
1017 w = (void *)&pcmcia->pcmc_pbr0;
1018 w += winnr;
1019
1020 out_be32(&w->or, 0); /* turn off window */
1021 out_be32(&w->br, 0); /* turn off base address */
1022
1023 pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at "
1024 "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1025 }
1026
1027 /* copy the struct and modify the copy */
1028 s->io_win[io->map] = *io;
1029 s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1030 pr_debug("m8xx_pcmcia: SetIOMap exit\n");
1031
1032 return 0;
1033 }
1034
1035 static int m8xx_set_mem_map(struct pcmcia_socket *sock,
1036 struct pccard_mem_map *mem)
1037 {
1038 int lsock = container_of(sock, struct socket_info, socket)->slot;
1039 struct socket_info *s = &socket[lsock];
1040 struct pcmcia_win *w;
1041 struct pccard_mem_map *old;
1042 unsigned int reg, winnr;
1043 pcmconf8xx_t *pcmcia = s->pcmcia;
1044
1045 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1046 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1047 mem->speed, (unsigned long long)mem->static_start,
1048 mem->card_start);
1049
1050 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1051 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1052 || (mem->card_start >= 0x04000000)
1053 || (mem->static_start & 0xfff) /* 4KByte resolution */
1054 ||(mem->card_start & 0xfff))
1055 return -EINVAL;
1056
1057 if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1058 printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1059 return -EINVAL;
1060 }
1061 reg <<= 27;
1062
1063 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1064
1065 /* Setup the window in the pcmcia controller */
1066
1067 w = (void *)&pcmcia->pcmc_pbr0;
1068 w += winnr;
1069
1070 reg |= lsock << 2;
1071
1072 reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1073
1074 if (mem->flags & MAP_ATTRIB)
1075 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1076
1077 if (mem->flags & MAP_WRPROT)
1078 reg |= M8XX_PCMCIA_POR_WRPROT;
1079
1080 if (mem->flags & MAP_16BIT)
1081 reg |= M8XX_PCMCIA_POR_16BIT;
1082
1083 if (mem->flags & MAP_ACTIVE)
1084 reg |= M8XX_PCMCIA_POR_VALID;
1085
1086 out_be32(&w->or, reg);
1087
1088 pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, "
1089 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1090
1091 if (mem->flags & MAP_ACTIVE) {
1092 /* get the new base address */
1093 mem->static_start = PCMCIA_MEM_WIN_BASE +
1094 (PCMCIA_MEM_WIN_SIZE * winnr)
1095 + mem->card_start;
1096 }
1097
1098 pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, "
1099 "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags,
1100 mem->speed, (unsigned long long)mem->static_start,
1101 mem->card_start);
1102
1103 /* copy the struct and modify the copy */
1104
1105 old = &s->mem_win[mem->map];
1106
1107 *old = *mem;
1108 old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE);
1109
1110 return 0;
1111 }
1112
1113 static int m8xx_sock_init(struct pcmcia_socket *sock)
1114 {
1115 int i;
1116 pccard_io_map io = { 0, 0, 0, 0, 1 };
1117 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1118
1119 pr_debug("m8xx_pcmcia: sock_init(%d)\n", s);
1120
1121 m8xx_set_socket(sock, &dead_socket);
1122 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1123 io.map = i;
1124 m8xx_set_io_map(sock, &io);
1125 }
1126 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1127 mem.map = i;
1128 m8xx_set_mem_map(sock, &mem);
1129 }
1130
1131 return 0;
1132
1133 }
1134
1135 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1136 {
1137 return m8xx_set_socket(sock, &dead_socket);
1138 }
1139
1140 static struct pccard_operations m8xx_services = {
1141 .init = m8xx_sock_init,
1142 .suspend = m8xx_sock_suspend,
1143 .get_status = m8xx_get_status,
1144 .set_socket = m8xx_set_socket,
1145 .set_io_map = m8xx_set_io_map,
1146 .set_mem_map = m8xx_set_mem_map,
1147 };
1148
1149 static int __init m8xx_probe(struct platform_device *ofdev,
1150 const struct of_device_id *match)
1151 {
1152 struct pcmcia_win *w;
1153 unsigned int i, m, hwirq;
1154 pcmconf8xx_t *pcmcia;
1155 int status;
1156 struct device_node *np = ofdev->dev.of_node;
1157
1158 pcmcia_info("%s\n", version);
1159
1160 pcmcia = of_iomap(np, 0);
1161 if (pcmcia == NULL)
1162 return -EINVAL;
1163
1164 pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1165 hwirq = irq_map[pcmcia_schlvl].hwirq;
1166 if (pcmcia_schlvl < 0) {
1167 iounmap(pcmcia);
1168 return -EINVAL;
1169 }
1170
1171 m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1172 m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1173
1174 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1175 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1176
1177 /* Configure Status change interrupt */
1178
1179 if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1180 driver_name, socket)) {
1181 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1182 pcmcia_schlvl);
1183 iounmap(pcmcia);
1184 return -1;
1185 }
1186
1187 w = (void *)&pcmcia->pcmc_pbr0;
1188
1189 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1190 clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1191
1192 /* connect interrupt and disable CxOE */
1193
1194 out_be32(M8XX_PGCRX(0),
1195 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1196 out_be32(M8XX_PGCRX(1),
1197 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1198
1199 /* intialize the fixed memory windows */
1200
1201 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1202 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1203 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1204 (PCMCIA_MEM_WIN_SIZE
1205 * (m + i * PCMCIA_MEM_WIN_NO)));
1206
1207 out_be32(&w->or, 0); /* set to not valid */
1208
1209 w++;
1210 }
1211 }
1212
1213 /* turn off voltage */
1214 voltage_set(0, 0, 0);
1215 voltage_set(1, 0, 0);
1216
1217 /* Enable external hardware */
1218 hardware_enable(0);
1219 hardware_enable(1);
1220
1221 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1222 socket[i].slot = i;
1223 socket[i].socket.owner = THIS_MODULE;
1224 socket[i].socket.features =
1225 SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1226 socket[i].socket.irq_mask = 0x000;
1227 socket[i].socket.map_size = 0x1000;
1228 socket[i].socket.io_offset = 0;
1229 socket[i].socket.pci_irq = pcmcia_schlvl;
1230 socket[i].socket.ops = &m8xx_services;
1231 socket[i].socket.resource_ops = &pccard_iodyn_ops;
1232 socket[i].socket.cb_dev = NULL;
1233 socket[i].socket.dev.parent = &ofdev->dev;
1234 socket[i].pcmcia = pcmcia;
1235 socket[i].bus_freq = ppc_proc_freq;
1236 socket[i].hwirq = hwirq;
1237
1238 }
1239
1240 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1241 status = pcmcia_register_socket(&socket[i].socket);
1242 if (status < 0)
1243 pcmcia_error("Socket register failed\n");
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int m8xx_remove(struct platform_device *ofdev)
1250 {
1251 u32 m, i;
1252 struct pcmcia_win *w;
1253 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1254
1255 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1256 w = (void *)&pcmcia->pcmc_pbr0;
1257
1258 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1259 out_be32(&pcmcia->pcmc_per,
1260 in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1261
1262 /* turn off interrupt and disable CxOE */
1263 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1264
1265 /* turn off memory windows */
1266 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1267 out_be32(&w->or, 0); /* set to not valid */
1268 w++;
1269 }
1270
1271 /* turn off voltage */
1272 voltage_set(i, 0, 0);
1273
1274 /* disable external hardware */
1275 hardware_disable(i);
1276 }
1277 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1278 pcmcia_unregister_socket(&socket[i].socket);
1279 iounmap(pcmcia);
1280
1281 free_irq(pcmcia_schlvl, NULL);
1282
1283 return 0;
1284 }
1285
1286 static const struct of_device_id m8xx_pcmcia_match[] = {
1287 {
1288 .type = "pcmcia",
1289 .compatible = "fsl,pq-pcmcia",
1290 },
1291 {},
1292 };
1293
1294 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1295
1296 static struct of_platform_driver m8xx_pcmcia_driver = {
1297 .driver = {
1298 .name = driver_name,
1299 .owner = THIS_MODULE,
1300 .of_match_table = m8xx_pcmcia_match,
1301 },
1302 .probe = m8xx_probe,
1303 .remove = m8xx_remove,
1304 };
1305
1306 static int __init m8xx_init(void)
1307 {
1308 return of_register_platform_driver(&m8xx_pcmcia_driver);
1309 }
1310
1311 static void __exit m8xx_exit(void)
1312 {
1313 of_unregister_platform_driver(&m8xx_pcmcia_driver);
1314 }
1315
1316 module_init(m8xx_init);
1317 module_exit(m8xx_exit);
Tomato firmware and modifications.