release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/wireless/rt2x00/rt73usb.h

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: Data structures and registers for the rt73usb module.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #ifndef RT73USB_H
  28 #define RT73USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5226                          0x0001
  34 #define RF2528                          0x0002
  35 #define RF5225                          0x0003
  36 #define RF2527                          0x0004
  37
  38 /*
  39  * Signal information.
  40  * Default offset is required for RSSI <-> dBm conversion.
  41  */
  42 #define DEFAULT_RSSI_OFFSET             120
  43
  44 /*
  45  * Register layout information.
  46  */
  47 #define CSR_REG_BASE                    0x3000
  48 #define CSR_REG_SIZE                    0x04b0
  49 #define EEPROM_BASE                     0x0000
  50 #define EEPROM_SIZE                     0x0100
  51 #define BBP_BASE                        0x0000
  52 #define BBP_SIZE                        0x0080
  53 #define RF_BASE                         0x0004
  54 #define RF_SIZE                         0x0010
  55
  56 /*
  57  * Number of TX queues.
  58  */
  59 #define NUM_TX_QUEUES                   4
  60
  61 /*
  62  * USB registers.
  63  */
  64
  65 /*
  66  * MCU_LEDCS: LED control for MCU Mailbox.
  67  */
  68 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
  69 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
  70 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
  71 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
  72 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
  73 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
  74 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
  75 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
  76 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
  77 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
  78 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
  79 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
  80
  81 /*
  82  * 8051 firmware image.
  83  */
  84 #define FIRMWARE_RT2571                 "rt73.bin"
  85 #define FIRMWARE_IMAGE_BASE             0x0800
  86
  87 /*
  88  * Security key table memory.
  89  * 16 entries 32-byte for shared key table
  90  * 64 entries 32-byte for pairwise key table
  91  * 64 entries 8-byte for pairwise ta key table
  92  */
  93 #define SHARED_KEY_TABLE_BASE           0x1000
  94 #define PAIRWISE_KEY_TABLE_BASE         0x1200
  95 #define PAIRWISE_TA_TABLE_BASE          0x1a00
  96
  97 #define SHARED_KEY_ENTRY(__idx) \
  98         ( SHARED_KEY_TABLE_BASE + \
  99                 ((__idx) * sizeof(struct hw_key_entry)) )
 100 #define PAIRWISE_KEY_ENTRY(__idx) \
 101         ( PAIRWISE_KEY_TABLE_BASE + \
 102                 ((__idx) * sizeof(struct hw_key_entry)) )
 103 #define PAIRWISE_TA_ENTRY(__idx) \
 104         ( PAIRWISE_TA_TABLE_BASE + \
 105                 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
 106
 107 struct hw_key_entry {
 108         u8 key[16];
 109         u8 tx_mic[8];
 110         u8 rx_mic[8];
 111 } __packed;
 112
 113 struct hw_pairwise_ta_entry {
 114         u8 address[6];
 115         u8 cipher;
 116         u8 reserved;
 117 } __packed;
 118
 119 /*
 120  * Since NULL frame won't be that long (256 byte),
 121  * We steal 16 tail bytes to save debugging settings.
 122  */
 123 #define HW_DEBUG_SETTING_BASE           0x2bf0
 124
 125 /*
 126  * On-chip BEACON frame space.
 127  */
 128 #define HW_BEACON_BASE0                 0x2400
 129 #define HW_BEACON_BASE1                 0x2500
 130 #define HW_BEACON_BASE2                 0x2600
 131 #define HW_BEACON_BASE3                 0x2700
 132
 133 #define HW_BEACON_OFFSET(__index) \
 134         ( HW_BEACON_BASE0 + (__index * 0x0100) )
 135
 136 /*
 137  * MAC Control/Status Registers(CSR).
 138  * Some values are set in TU, whereas 1 TU == 1024 us.
 139  */
 140
 141 /*
 142  * MAC_CSR0: ASIC revision number.
 143  */
 144 #define MAC_CSR0                        0x3000
 145 #define MAC_CSR0_REVISION               FIELD32(0x0000000f)
 146 #define MAC_CSR0_CHIPSET                FIELD32(0x000ffff0)
 147
 148 /*
 149  * MAC_CSR1: System control register.
 150  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 151  * BBP_RESET: Hardware reset BBP.
 152  * HOST_READY: Host is ready after initialization, 1: ready.
 153  */
 154 #define MAC_CSR1                        0x3004
 155 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 156 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 157 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 158
 159 /*
 160  * MAC_CSR2: STA MAC register 0.
 161  */
 162 #define MAC_CSR2                        0x3008
 163 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 164 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 165 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 166 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 167
 168 /*
 169  * MAC_CSR3: STA MAC register 1.
 170  * UNICAST_TO_ME_MASK:
 171  *      Used to mask off bits from byte 5 of the MAC address
 172  *      to determine the UNICAST_TO_ME bit for RX frames.
 173  *      The full mask is complemented by BSS_ID_MASK:
 174  *              MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
 175  */
 176 #define MAC_CSR3                        0x300c
 177 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 178 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 179 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 180
 181 /*
 182  * MAC_CSR4: BSSID register 0.
 183  */
 184 #define MAC_CSR4                        0x3010
 185 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 186 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 187 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 188 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 189
 190 /*
 191  * MAC_CSR5: BSSID register 1.
 192  * BSS_ID_MASK:
 193  *      This mask is used to mask off bits 0 and 1 of byte 5 of the
 194  *      BSSID. This will make sure that those bits will be ignored
 195  *      when determining the MY_BSS of RX frames.
 196  *              0: 1-BSSID mode (BSS index = 0)
 197  *              1: 2-BSSID mode (BSS index: Byte5, bit 0)
 198  *              2: 2-BSSID mode (BSS index: byte5, bit 1)
 199  *              3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
 200  */
 201 #define MAC_CSR5                        0x3014
 202 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 203 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 204 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 205
 206 /*
 207  * MAC_CSR6: Maximum frame length register.
 208  */
 209 #define MAC_CSR6                        0x3018
 210 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x00000fff)
 211
 212 /*
 213  * MAC_CSR7: Reserved
 214  */
 215 #define MAC_CSR7                        0x301c
 216
 217 /*
 218  * MAC_CSR8: SIFS/EIFS register.
 219  * All units are in US.
 220  */
 221 #define MAC_CSR8                        0x3020
 222 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 223 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 224 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 225
 226 /*
 227  * MAC_CSR9: Back-Off control register.
 228  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 229  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 230  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 231  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 232  */
 233 #define MAC_CSR9                        0x3024
 234 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 235 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 236 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 237 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 238
 239 /*
 240  * MAC_CSR10: Power state configuration.
 241  */
 242 #define MAC_CSR10                       0x3028
 243
 244 /*
 245  * MAC_CSR11: Power saving transition time register.
 246  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 247  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 248  * WAKEUP_LATENCY: In unit of TU.
 249  */
 250 #define MAC_CSR11                       0x302c
 251 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 252 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 253 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 254 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 255
 256 /*
 257  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 258  * CURRENT_STATE: 0:sleep, 1:awake.
 259  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 260  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 261  */
 262 #define MAC_CSR12                       0x3030
 263 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 264 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 265 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 266 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 267
 268 /*
 269  * MAC_CSR13: GPIO.
 270  */
 271 #define MAC_CSR13                       0x3034
 272 #define MAC_CSR13_BIT0                  FIELD32(0x00000001)
 273 #define MAC_CSR13_BIT1                  FIELD32(0x00000002)
 274 #define MAC_CSR13_BIT2                  FIELD32(0x00000004)
 275 #define MAC_CSR13_BIT3                  FIELD32(0x00000008)
 276 #define MAC_CSR13_BIT4                  FIELD32(0x00000010)
 277 #define MAC_CSR13_BIT5                  FIELD32(0x00000020)
 278 #define MAC_CSR13_BIT6                  FIELD32(0x00000040)
 279 #define MAC_CSR13_BIT7                  FIELD32(0x00000080)
 280 #define MAC_CSR13_BIT8                  FIELD32(0x00000100)
 281 #define MAC_CSR13_BIT9                  FIELD32(0x00000200)
 282 #define MAC_CSR13_BIT10                 FIELD32(0x00000400)
 283 #define MAC_CSR13_BIT11                 FIELD32(0x00000800)
 284 #define MAC_CSR13_BIT12                 FIELD32(0x00001000)
 285
 286 /*
 287  * MAC_CSR14: LED control register.
 288  * ON_PERIOD: On period, default 70ms.
 289  * OFF_PERIOD: Off period, default 30ms.
 290  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 291  * SW_LED: s/w LED, 1: ON, 0: OFF.
 292  * HW_LED_POLARITY: 0: active low, 1: active high.
 293  */
 294 #define MAC_CSR14                       0x3038
 295 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 296 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 297 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 298 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 299 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 300 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 301
 302 /*
 303  * MAC_CSR15: NAV control.
 304  */
 305 #define MAC_CSR15                       0x303c
 306
 307 /*
 308  * TXRX control registers.
 309  * Some values are set in TU, whereas 1 TU == 1024 us.
 310  */
 311
 312 /*
 313  * TXRX_CSR0: TX/RX configuration register.
 314  * TSF_OFFSET: Default is 24.
 315  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 316  * DISABLE_RX: Disable Rx engine.
 317  * DROP_CRC: Drop CRC error.
 318  * DROP_PHYSICAL: Drop physical error.
 319  * DROP_CONTROL: Drop control frame.
 320  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 321  * DROP_TO_DS: Drop fram ToDs bit is true.
 322  * DROP_VERSION_ERROR: Drop version error frame.
 323  * DROP_MULTICAST: Drop multicast frames.
 324  * DROP_BORADCAST: Drop broadcast frames.
 325  * ROP_ACK_CTS: Drop received ACK and CTS.
 326  */
 327 #define TXRX_CSR0                       0x3040
 328 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 329 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 330 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 331 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 332 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 333 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 334 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 335 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 336 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 337 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 338 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 339 #define TXRX_CSR0_DROP_BROADCAST        FIELD32(0x01000000)
 340 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 341 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 342
 343 /*
 344  * TXRX_CSR1
 345  */
 346 #define TXRX_CSR1                       0x3044
 347 #define TXRX_CSR1_BBP_ID0               FIELD32(0x0000007f)
 348 #define TXRX_CSR1_BBP_ID0_VALID         FIELD32(0x00000080)
 349 #define TXRX_CSR1_BBP_ID1               FIELD32(0x00007f00)
 350 #define TXRX_CSR1_BBP_ID1_VALID         FIELD32(0x00008000)
 351 #define TXRX_CSR1_BBP_ID2               FIELD32(0x007f0000)
 352 #define TXRX_CSR1_BBP_ID2_VALID         FIELD32(0x00800000)
 353 #define TXRX_CSR1_BBP_ID3               FIELD32(0x7f000000)
 354 #define TXRX_CSR1_BBP_ID3_VALID         FIELD32(0x80000000)
 355
 356 /*
 357  * TXRX_CSR2
 358  */
 359 #define TXRX_CSR2                       0x3048
 360 #define TXRX_CSR2_BBP_ID0               FIELD32(0x0000007f)
 361 #define TXRX_CSR2_BBP_ID0_VALID         FIELD32(0x00000080)
 362 #define TXRX_CSR2_BBP_ID1               FIELD32(0x00007f00)
 363 #define TXRX_CSR2_BBP_ID1_VALID         FIELD32(0x00008000)
 364 #define TXRX_CSR2_BBP_ID2               FIELD32(0x007f0000)
 365 #define TXRX_CSR2_BBP_ID2_VALID         FIELD32(0x00800000)
 366 #define TXRX_CSR2_BBP_ID3               FIELD32(0x7f000000)
 367 #define TXRX_CSR2_BBP_ID3_VALID         FIELD32(0x80000000)
 368
 369 /*
 370  * TXRX_CSR3
 371  */
 372 #define TXRX_CSR3                       0x304c
 373 #define TXRX_CSR3_BBP_ID0               FIELD32(0x0000007f)
 374 #define TXRX_CSR3_BBP_ID0_VALID         FIELD32(0x00000080)
 375 #define TXRX_CSR3_BBP_ID1               FIELD32(0x00007f00)
 376 #define TXRX_CSR3_BBP_ID1_VALID         FIELD32(0x00008000)
 377 #define TXRX_CSR3_BBP_ID2               FIELD32(0x007f0000)
 378 #define TXRX_CSR3_BBP_ID2_VALID         FIELD32(0x00800000)
 379 #define TXRX_CSR3_BBP_ID3               FIELD32(0x7f000000)
 380 #define TXRX_CSR3_BBP_ID3_VALID         FIELD32(0x80000000)
 381
 382 /*
 383  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 384  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 385  * OFDM_TX_RATE_DOWN: 1:enable.
 386  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 387  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 388  */
 389 #define TXRX_CSR4                       0x3050
 390 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 391 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 392 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 393 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 394 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 395 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 396 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 397 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 398 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 399 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 400
 401 /*
 402  * TXRX_CSR5
 403  */
 404 #define TXRX_CSR5                       0x3054
 405
 406 /*
 407  * TXRX_CSR6: ACK/CTS payload consumed time
 408  */
 409 #define TXRX_CSR6                       0x3058
 410
 411 /*
 412  * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
 413  */
 414 #define TXRX_CSR7                       0x305c
 415 #define TXRX_CSR7_ACK_CTS_6MBS          FIELD32(0x000000ff)
 416 #define TXRX_CSR7_ACK_CTS_9MBS          FIELD32(0x0000ff00)
 417 #define TXRX_CSR7_ACK_CTS_12MBS         FIELD32(0x00ff0000)
 418 #define TXRX_CSR7_ACK_CTS_18MBS         FIELD32(0xff000000)
 419
 420 /*
 421  * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
 422  */
 423 #define TXRX_CSR8                       0x3060
 424 #define TXRX_CSR8_ACK_CTS_24MBS         FIELD32(0x000000ff)
 425 #define TXRX_CSR8_ACK_CTS_36MBS         FIELD32(0x0000ff00)
 426 #define TXRX_CSR8_ACK_CTS_48MBS         FIELD32(0x00ff0000)
 427 #define TXRX_CSR8_ACK_CTS_54MBS         FIELD32(0xff000000)
 428
 429 /*
 430  * TXRX_CSR9: Synchronization control register.
 431  * BEACON_INTERVAL: In unit of 1/16 TU.
 432  * TSF_TICKING: Enable TSF auto counting.
 433  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 434  * BEACON_GEN: Enable beacon generator.
 435  */
 436 #define TXRX_CSR9                       0x3064
 437 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 438 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 439 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 440 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 441 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 442 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 443
 444 /*
 445  * TXRX_CSR10: BEACON alignment.
 446  */
 447 #define TXRX_CSR10                      0x3068
 448
 449 /*
 450  * TXRX_CSR11: AES mask.
 451  */
 452 #define TXRX_CSR11                      0x306c
 453
 454 /*
 455  * TXRX_CSR12: TSF low 32.
 456  */
 457 #define TXRX_CSR12                      0x3070
 458 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 459
 460 /*
 461  * TXRX_CSR13: TSF high 32.
 462  */
 463 #define TXRX_CSR13                      0x3074
 464 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 465
 466 /*
 467  * TXRX_CSR14: TBTT timer.
 468  */
 469 #define TXRX_CSR14                      0x3078
 470
 471 /*
 472  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 473  */
 474 #define TXRX_CSR15                      0x307c
 475
 476 /*
 477  * PHY control registers.
 478  * Some values are set in TU, whereas 1 TU == 1024 us.
 479  */
 480
 481 /*
 482  * PHY_CSR0: RF/PS control.
 483  */
 484 #define PHY_CSR0                        0x3080
 485 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 486 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 487
 488 /*
 489  * PHY_CSR1
 490  */
 491 #define PHY_CSR1                        0x3084
 492 #define PHY_CSR1_RF_RPI                 FIELD32(0x00010000)
 493
 494 /*
 495  * PHY_CSR2: Pre-TX BBP control.
 496  */
 497 #define PHY_CSR2                        0x3088
 498
 499 /*
 500  * PHY_CSR3: BBP serial control register.
 501  * VALUE: Register value to program into BBP.
 502  * REG_NUM: Selected BBP register.
 503  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 504  * BUSY: 1: ASIC is busy execute BBP programming.
 505  */
 506 #define PHY_CSR3                        0x308c
 507 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 508 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 509 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 510 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 511
 512 /*
 513  * PHY_CSR4: RF serial control register
 514  * VALUE: Register value (include register id) serial out to RF/IF chip.
 515  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 516  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 517  * PLL_LD: RF PLL_LD status.
 518  * BUSY: 1: ASIC is busy execute RF programming.
 519  */
 520 #define PHY_CSR4                        0x3090
 521 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 522 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 523 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 524 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 525 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 526
 527 /*
 528  * PHY_CSR5: RX to TX signal switch timing control.
 529  */
 530 #define PHY_CSR5                        0x3094
 531 #define PHY_CSR5_IQ_FLIP                FIELD32(0x00000004)
 532
 533 /*
 534  * PHY_CSR6: TX to RX signal timing control.
 535  */
 536 #define PHY_CSR6                        0x3098
 537 #define PHY_CSR6_IQ_FLIP                FIELD32(0x00000004)
 538
 539 /*
 540  * PHY_CSR7: TX DAC switching timing control.
 541  */
 542 #define PHY_CSR7                        0x309c
 543
 544 /*
 545  * Security control register.
 546  */
 547
 548 /*
 549  * SEC_CSR0: Shared key table control.
 550  */
 551 #define SEC_CSR0                        0x30a0
 552 #define SEC_CSR0_BSS0_KEY0_VALID        FIELD32(0x00000001)
 553 #define SEC_CSR0_BSS0_KEY1_VALID        FIELD32(0x00000002)
 554 #define SEC_CSR0_BSS0_KEY2_VALID        FIELD32(0x00000004)
 555 #define SEC_CSR0_BSS0_KEY3_VALID        FIELD32(0x00000008)
 556 #define SEC_CSR0_BSS1_KEY0_VALID        FIELD32(0x00000010)
 557 #define SEC_CSR0_BSS1_KEY1_VALID        FIELD32(0x00000020)
 558 #define SEC_CSR0_BSS1_KEY2_VALID        FIELD32(0x00000040)
 559 #define SEC_CSR0_BSS1_KEY3_VALID        FIELD32(0x00000080)
 560 #define SEC_CSR0_BSS2_KEY0_VALID        FIELD32(0x00000100)
 561 #define SEC_CSR0_BSS2_KEY1_VALID        FIELD32(0x00000200)
 562 #define SEC_CSR0_BSS2_KEY2_VALID        FIELD32(0x00000400)
 563 #define SEC_CSR0_BSS2_KEY3_VALID        FIELD32(0x00000800)
 564 #define SEC_CSR0_BSS3_KEY0_VALID        FIELD32(0x00001000)
 565 #define SEC_CSR0_BSS3_KEY1_VALID        FIELD32(0x00002000)
 566 #define SEC_CSR0_BSS3_KEY2_VALID        FIELD32(0x00004000)
 567 #define SEC_CSR0_BSS3_KEY3_VALID        FIELD32(0x00008000)
 568
 569 /*
 570  * SEC_CSR1: Shared key table security mode register.
 571  */
 572 #define SEC_CSR1                        0x30a4
 573 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 574 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 575 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 576 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 577 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 578 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 579 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 580 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 581
 582 /*
 583  * Pairwise key table valid bitmap registers.
 584  * SEC_CSR2: pairwise key table valid bitmap 0.
 585  * SEC_CSR3: pairwise key table valid bitmap 1.
 586  */
 587 #define SEC_CSR2                        0x30a8
 588 #define SEC_CSR3                        0x30ac
 589
 590 /*
 591  * SEC_CSR4: Pairwise key table lookup control.
 592  */
 593 #define SEC_CSR4                        0x30b0
 594 #define SEC_CSR4_ENABLE_BSS0            FIELD32(0x00000001)
 595 #define SEC_CSR4_ENABLE_BSS1            FIELD32(0x00000002)
 596 #define SEC_CSR4_ENABLE_BSS2            FIELD32(0x00000004)
 597 #define SEC_CSR4_ENABLE_BSS3            FIELD32(0x00000008)
 598
 599 /*
 600  * SEC_CSR5: shared key table security mode register.
 601  */
 602 #define SEC_CSR5                        0x30b4
 603 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 604 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 605 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 606 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 607 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 608 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 609 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 610 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 611
 612 /*
 613  * STA control registers.
 614  */
 615
 616 /*
 617  * STA_CSR0: RX PLCP error count & RX FCS error count.
 618  */
 619 #define STA_CSR0                        0x30c0
 620 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 621 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 622
 623 /*
 624  * STA_CSR1: RX False CCA count & RX LONG frame count.
 625  */
 626 #define STA_CSR1                        0x30c4
 627 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 628 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 629
 630 /*
 631  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 632  */
 633 #define STA_CSR2                        0x30c8
 634 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 635 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 636
 637 /*
 638  * STA_CSR3: TX Beacon count.
 639  */
 640 #define STA_CSR3                        0x30cc
 641 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 642
 643 /*
 644  * STA_CSR4: TX Retry count.
 645  */
 646 #define STA_CSR4                        0x30d0
 647 #define STA_CSR4_TX_NO_RETRY_COUNT      FIELD32(0x0000ffff)
 648 #define STA_CSR4_TX_ONE_RETRY_COUNT     FIELD32(0xffff0000)
 649
 650 /*
 651  * STA_CSR5: TX Retry count.
 652  */
 653 #define STA_CSR5                        0x30d4
 654 #define STA_CSR4_TX_MULTI_RETRY_COUNT   FIELD32(0x0000ffff)
 655 #define STA_CSR4_TX_RETRY_FAIL_COUNT    FIELD32(0xffff0000)
 656
 657 /*
 658  * QOS control registers.
 659  */
 660
 661 /*
 662  * QOS_CSR1: TXOP holder MAC address register.
 663  */
 664 #define QOS_CSR1                        0x30e4
 665 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 666 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 667
 668 /*
 669  * QOS_CSR2: TXOP holder timeout register.
 670  */
 671 #define QOS_CSR2                        0x30e8
 672
 673 /*
 674  * RX QOS-CFPOLL MAC address register.
 675  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 676  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 677  */
 678 #define QOS_CSR3                        0x30ec
 679 #define QOS_CSR4                        0x30f0
 680
 681 /*
 682  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 683  */
 684 #define QOS_CSR5                        0x30f4
 685
 686 /*
 687  * WMM Scheduler Register
 688  */
 689
 690 /*
 691  * AIFSN_CSR: AIFSN for each EDCA AC.
 692  * AIFSN0: For AC_BK.
 693  * AIFSN1: For AC_BE.
 694  * AIFSN2: For AC_VI.
 695  * AIFSN3: For AC_VO.
 696  */
 697 #define AIFSN_CSR                       0x0400
 698 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 699 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 700 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 701 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 702
 703 /*
 704  * CWMIN_CSR: CWmin for each EDCA AC.
 705  * CWMIN0: For AC_BK.
 706  * CWMIN1: For AC_BE.
 707  * CWMIN2: For AC_VI.
 708  * CWMIN3: For AC_VO.
 709  */
 710 #define CWMIN_CSR                       0x0404
 711 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 712 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 713 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 714 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 715
 716 /*
 717  * CWMAX_CSR: CWmax for each EDCA AC.
 718  * CWMAX0: For AC_BK.
 719  * CWMAX1: For AC_BE.
 720  * CWMAX2: For AC_VI.
 721  * CWMAX3: For AC_VO.
 722  */
 723 #define CWMAX_CSR                       0x0408
 724 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 725 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 726 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 727 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 728
 729 /*
 730  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
 731  * AC0_TX_OP: For AC_BK, in unit of 32us.
 732  * AC1_TX_OP: For AC_BE, in unit of 32us.
 733  */
 734 #define AC_TXOP_CSR0                    0x040c
 735 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 736 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 737
 738 /*
 739  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
 740  * AC2_TX_OP: For AC_VI, in unit of 32us.
 741  * AC3_TX_OP: For AC_VO, in unit of 32us.
 742  */
 743 #define AC_TXOP_CSR1                    0x0410
 744 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
 745 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
 746
 747 /*
 748  * BBP registers.
 749  * The wordsize of the BBP is 8 bits.
 750  */
 751
 752 /*
 753  * R2
 754  */
 755 #define BBP_R2_BG_MODE                  FIELD8(0x20)
 756
 757 /*
 758  * R3
 759  */
 760 #define BBP_R3_SMART_MODE               FIELD8(0x01)
 761
 762 /*
 763  * R4: RX antenna control
 764  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
 765  */
 766
 767 /*
 768  * ANTENNA_CONTROL semantics (guessed):
 769  * 0x1: Software controlled antenna switching (fixed or SW diversity)
 770  * 0x2: Hardware diversity.
 771  */
 772 #define BBP_R4_RX_ANTENNA_CONTROL       FIELD8(0x03)
 773 #define BBP_R4_RX_FRAME_END             FIELD8(0x20)
 774
 775 /*
 776  * R77
 777  */
 778 #define BBP_R77_RX_ANTENNA              FIELD8(0x03)
 779
 780 /*
 781  * RF registers
 782  */
 783
 784 /*
 785  * RF 3
 786  */
 787 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 788
 789 /*
 790  * RF 4
 791  */
 792 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
 793
 794 /*
 795  * EEPROM content.
 796  * The wordsize of the EEPROM is 16 bits.
 797  */
 798
 799 /*
 800  * HW MAC address.
 801  */
 802 #define EEPROM_MAC_ADDR_0               0x0002
 803 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 804 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 805 #define EEPROM_MAC_ADDR1                0x0003
 806 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 807 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 808 #define EEPROM_MAC_ADDR_2               0x0004
 809 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 810 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 811
 812 /*
 813  * EEPROM antenna.
 814  * ANTENNA_NUM: Number of antennas.
 815  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 816  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 817  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
 818  * DYN_TXAGC: Dynamic TX AGC control.
 819  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 820  * RF_TYPE: Rf_type of this adapter.
 821  */
 822 #define EEPROM_ANTENNA                  0x0010
 823 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 824 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 825 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 826 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
 827 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 828 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 829 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 830
 831 /*
 832  * EEPROM NIC config.
 833  * EXTERNAL_LNA: External LNA.
 834  */
 835 #define EEPROM_NIC                      0x0011
 836 #define EEPROM_NIC_EXTERNAL_LNA         FIELD16(0x0010)
 837
 838 /*
 839  * EEPROM geography.
 840  * GEO_A: Default geographical setting for 5GHz band
 841  * GEO: Default geographical setting.
 842  */
 843 #define EEPROM_GEOGRAPHY                0x0012
 844 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
 845 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
 846
 847 /*
 848  * EEPROM BBP.
 849  */
 850 #define EEPROM_BBP_START                0x0013
 851 #define EEPROM_BBP_SIZE                 16
 852 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 853 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 854
 855 /*
 856  * EEPROM TXPOWER 802.11G
 857  */
 858 #define EEPROM_TXPOWER_G_START          0x0023
 859 #define EEPROM_TXPOWER_G_SIZE           7
 860 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
 861 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
 862
 863 /*
 864  * EEPROM Frequency
 865  */
 866 #define EEPROM_FREQ                     0x002f
 867 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
 868 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
 869 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
 870
 871 /*
 872  * EEPROM LED.
 873  * POLARITY_RDY_G: Polarity RDY_G setting.
 874  * POLARITY_RDY_A: Polarity RDY_A setting.
 875  * POLARITY_ACT: Polarity ACT setting.
 876  * POLARITY_GPIO_0: Polarity GPIO0 setting.
 877  * POLARITY_GPIO_1: Polarity GPIO1 setting.
 878  * POLARITY_GPIO_2: Polarity GPIO2 setting.
 879  * POLARITY_GPIO_3: Polarity GPIO3 setting.
 880  * POLARITY_GPIO_4: Polarity GPIO4 setting.
 881  * LED_MODE: Led mode.
 882  */
 883 #define EEPROM_LED                      0x0030
 884 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
 885 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
 886 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
 887 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
 888 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
 889 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
 890 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
 891 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
 892 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
 893
 894 /*
 895  * EEPROM TXPOWER 802.11A
 896  */
 897 #define EEPROM_TXPOWER_A_START          0x0031
 898 #define EEPROM_TXPOWER_A_SIZE           12
 899 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
 900 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
 901
 902 /*
 903  * EEPROM RSSI offset 802.11BG
 904  */
 905 #define EEPROM_RSSI_OFFSET_BG           0x004d
 906 #define EEPROM_RSSI_OFFSET_BG_1         FIELD16(0x00ff)
 907 #define EEPROM_RSSI_OFFSET_BG_2         FIELD16(0xff00)
 908
 909 /*
 910  * EEPROM RSSI offset 802.11A
 911  */
 912 #define EEPROM_RSSI_OFFSET_A            0x004e
 913 #define EEPROM_RSSI_OFFSET_A_1          FIELD16(0x00ff)
 914 #define EEPROM_RSSI_OFFSET_A_2          FIELD16(0xff00)
 915
 916 /*
 917  * DMA descriptor defines.
 918  */
 919 #define TXD_DESC_SIZE                   ( 6 * sizeof(__le32) )
 920 #define TXINFO_SIZE                     ( 6 * sizeof(__le32) )
 921 #define RXD_DESC_SIZE                   ( 6 * sizeof(__le32) )
 922
 923 /*
 924  * TX descriptor format for TX, PRIO and Beacon Ring.
 925  */
 926
 927 /*
 928  * Word0
 929  * BURST: Next frame belongs to same "burst" event.
 930  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
 931  * KEY_TABLE: Use per-client pairwise KEY table.
 932  * KEY_INDEX:
 933  * Key index (0~31) to the pairwise KEY table.
 934  * 0~3 to shared KEY table 0 (BSS0).
 935  * 4~7 to shared KEY table 1 (BSS1).
 936  * 8~11 to shared KEY table 2 (BSS2).
 937  * 12~15 to shared KEY table 3 (BSS3).
 938  * BURST2: For backward compatibility, set to same value as BURST.
 939  */
 940 #define TXD_W0_BURST                    FIELD32(0x00000001)
 941 #define TXD_W0_VALID                    FIELD32(0x00000002)
 942 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
 943 #define TXD_W0_ACK                      FIELD32(0x00000008)
 944 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
 945 #define TXD_W0_OFDM                     FIELD32(0x00000020)
 946 #define TXD_W0_IFS                      FIELD32(0x00000040)
 947 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
 948 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
 949 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
 950 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
 951 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 952 #define TXD_W0_BURST2                   FIELD32(0x10000000)
 953 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
 954
 955 /*
 956  * Word1
 957  * HOST_Q_ID: EDCA/HCCA queue ID.
 958  * HW_SEQUENCE: MAC overwrites the frame sequence number.
 959  * BUFFER_COUNT: Number of buffers in this TXD.
 960  */
 961 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
 962 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
 963 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 964 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 965 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
 966 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
 967 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
 968
 969 /*
 970  * Word2: PLCP information
 971  */
 972 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 973 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 974 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 975 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 976
 977 /*
 978  * Word3
 979  */
 980 #define TXD_W3_IV                       FIELD32(0xffffffff)
 981
 982 /*
 983  * Word4
 984  */
 985 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 986
 987 /*
 988  * Word5
 989  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
 990  * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
 991  * WAITING_DMA_DONE_INT: TXD been filled with data
 992  * and waiting for TxDoneISR housekeeping.
 993  */
 994 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
 995 #define TXD_W5_PACKET_ID                FIELD32(0x0000ff00)
 996 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
 997 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
 998
 999 /*
1000  * RX descriptor format for RX Ring.
1001  */
1002
1003 /*
1004  * Word0
1005  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1006  * KEY_INDEX: Decryption key actually used.
1007  */
1008 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1009 #define RXD_W0_DROP                     FIELD32(0x00000002)
1010 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
1011 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
1012 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
1013 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
1014 #define RXD_W0_CRC_ERROR                FIELD32(0x00000040)
1015 #define RXD_W0_OFDM                     FIELD32(0x00000080)
1016 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
1017 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1018 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1019 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1020
1021 /*
1022  * WORD1
1023  * SIGNAL: RX raw data rate reported by BBP.
1024  * RSSI: RSSI reported by BBP.
1025  */
1026 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
1027 #define RXD_W1_RSSI_AGC                 FIELD32(0x00001f00)
1028 #define RXD_W1_RSSI_LNA                 FIELD32(0x00006000)
1029 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
1030
1031 /*
1032  * Word2
1033  * IV: Received IV of originally encrypted.
1034  */
1035 #define RXD_W2_IV                       FIELD32(0xffffffff)
1036
1037 /*
1038  * Word3
1039  * EIV: Received EIV of originally encrypted.
1040  */
1041 #define RXD_W3_EIV                      FIELD32(0xffffffff)
1042
1043 /*
1044  * Word4
1045  * ICV: Received ICV of originally encrypted.
1046  * NOTE: This is a guess, the official definition is "reserved"
1047  */
1048 #define RXD_W4_ICV                      FIELD32(0xffffffff)
1049
1050 /*
1051  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1052  * and passed to the HOST driver.
1053  * The following fields are for DMA block and HOST usage only.
1054  * Can't be touched by ASIC MAC block.
1055  */
1056
1057 /*
1058  * Word5
1059  */
1060 #define RXD_W5_RESERVED                 FIELD32(0xffffffff)
1061
1062 /*
1063  * Macros for converting txpower from EEPROM to mac80211 value
1064  * and from mac80211 value to register value.
1065  */
1066 #define MIN_TXPOWER     0
1067 #define MAX_TXPOWER     31
1068 #define DEFAULT_TXPOWER 24
1069
1070 #define TXPOWER_FROM_DEV(__txpower) \
1071         (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1072
1073 #define TXPOWER_TO_DEV(__txpower) \
1074         clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1075
1076 #endif /* RT73USB_H */