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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / wireless / ath / ath5k / reset.c
blob652d8dbd36682e2069b86d1b686df82923eb5b4a
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 /*****************************\
23 Reset functions and helpers
24 \*****************************/
25
26 #include <asm/unaligned.h>
27
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include "ath5k.h"
31 #include "reg.h"
32 #include "base.h"
33 #include "debug.h"
34
35 /*
36 * Check if a register write has been completed
37 */
38 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
39 bool is_set)
40 {
41 int i;
42 u32 data;
43
44 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
45 data = ath5k_hw_reg_read(ah, reg);
46 if (is_set && (data & flag))
47 break;
48 else if ((data & flag) == val)
49 break;
50 udelay(15);
51 }
52
53 return (i <= 0) ? -EAGAIN : 0;
54 }
55
56 /**
57 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
58 *
59 * @ah: the &struct ath5k_hw
60 * @channel: the currently set channel upon reset
61 *
62 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
63 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
64 *
65 * Since delta slope is floating point we split it on its exponent and
66 * mantissa and provide these values on hw.
67 *
68 * For more infos i think this patent is related
69 * http://www.freepatentsonline.com/7184495.html
70 */
71 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
72 struct ieee80211_channel *channel)
73 {
74 /* Get exponent and mantissa and set it */
75 u32 coef_scaled, coef_exp, coef_man,
76 ds_coef_exp, ds_coef_man, clock;
77
78 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
79 !(channel->hw_value & CHANNEL_OFDM));
80
81 /* Get coefficient
82 * ALGO: coef = (5 * clock / carrier_freq) / 2
83 * we scale coef by shifting clock value by 24 for
84 * better precision since we use integers */
85 /* TODO: Half/quarter rate */
86 clock = (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
87 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
88
89 /* Get exponent
90 * ALGO: coef_exp = 14 - highest set bit position */
91 coef_exp = ilog2(coef_scaled);
92
93 /* Doesn't make sense if it's zero*/
94 if (!coef_scaled || !coef_exp)
95 return -EINVAL;
96
97 /* Note: we've shifted coef_scaled by 24 */
98 coef_exp = 14 - (coef_exp - 24);
99
100
101 /* Get mantissa (significant digits)
102 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
103 coef_man = coef_scaled +
104 (1 << (24 - coef_exp - 1));
105
106 /* Calculate delta slope coefficient exponent
107 * and mantissa (remove scaling) and set them on hw */
108 ds_coef_man = coef_man >> (24 - coef_exp);
109 ds_coef_exp = coef_exp - 16;
110
111 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
112 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
113 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
114 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
115
116 return 0;
117 }
118
119
120 /*
121 * index into rates for control rates, we can set it up like this because
122 * this is only used for AR5212 and we know it supports G mode
123 */
124 static const unsigned int control_rates[] =
125 { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
126
127 /**
128 * ath5k_hw_write_rate_duration - fill rate code to duration table
129 *
130 * @ah: the &struct ath5k_hw
131 * @mode: one of enum ath5k_driver_mode
132 *
133 * Write the rate code to duration table upon hw reset. This is a helper for
134 * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
135 * the hardware, based on current mode, for each rate. The rates which are
136 * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
137 * different rate code so we write their value twice (one for long preample
138 * and one for short).
139 *
140 * Note: Band doesn't matter here, if we set the values for OFDM it works
141 * on both a and g modes. So all we have to do is set values for all g rates
142 * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
143 * quarter rate mode, we need to use another set of bitrates (that's why we
144 * need the mode parameter) but we don't handle these proprietary modes yet.
145 */
146 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
147 unsigned int mode)
148 {
149 struct ath5k_softc *sc = ah->ah_sc;
150 struct ieee80211_rate *rate;
151 unsigned int i;
152
153 /* Write rate duration table */
154 for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
155 u32 reg;
156 u16 tx_time;
157
158 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
159
160 /* Set ACK timeout */
161 reg = AR5K_RATE_DUR(rate->hw_value);
162
163 /* An ACK frame consists of 10 bytes. If you add the FCS,
164 * which ieee80211_generic_frame_duration() adds,
165 * its 14 bytes. Note we use the control rate and not the
166 * actual rate for this rate. See mac80211 tx.c
167 * ieee80211_duration() for a brief description of
168 * what rate we should choose to TX ACKs. */
169 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
170 sc->vif, 10, rate));
171
172 ath5k_hw_reg_write(ah, tx_time, reg);
173
174 if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
175 continue;
176
177 /*
178 * We're not distinguishing short preamble here,
179 * This is true, all we'll get is a longer value here
180 * which is not necessarilly bad. We could use
181 * export ieee80211_frame_duration() but that needs to be
182 * fixed first to be properly used by mac802111 drivers:
183 *
184 * - remove erp stuff and let the routine figure ofdm
185 * erp rates
186 * - remove passing argument ieee80211_local as
187 * drivers don't have access to it
188 * - move drivers using ieee80211_generic_frame_duration()
189 * to this
190 */
191 ath5k_hw_reg_write(ah, tx_time,
192 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
193 }
194 }
195
196 /*
197 * Reset chipset
198 */
199 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
200 {
201 int ret;
202 u32 mask = val ? val : ~0U;
203
204 /* Read-and-clear RX Descriptor Pointer*/
205 ath5k_hw_reg_read(ah, AR5K_RXDP);
206
207 /*
208 * Reset the device and wait until success
209 */
210 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
211
212 /* Wait at least 128 PCI clocks */
213 udelay(15);
214
215 if (ah->ah_version == AR5K_AR5210) {
216 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
217 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
218 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
219 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
220 } else {
221 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
222 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
223 }
224
225 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
226
227 /*
228 * Reset configuration register (for hw byte-swap). Note that this
229 * is only set for big endian. We do the necessary magic in
230 * AR5K_INIT_CFG.
231 */
232 if ((val & AR5K_RESET_CTL_PCU) == 0)
233 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
234
235 return ret;
236 }
237
238 /*
239 * Sleep control
240 */
241 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
242 bool set_chip, u16 sleep_duration)
243 {
244 unsigned int i;
245 u32 staid, data;
246
247 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
248
249 switch (mode) {
250 case AR5K_PM_AUTO:
251 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
252 /* fallthrough */
253 case AR5K_PM_NETWORK_SLEEP:
254 if (set_chip)
255 ath5k_hw_reg_write(ah,
256 AR5K_SLEEP_CTL_SLE_ALLOW |
257 sleep_duration,
258 AR5K_SLEEP_CTL);
259
260 staid |= AR5K_STA_ID1_PWR_SV;
261 break;
262
263 case AR5K_PM_FULL_SLEEP:
264 if (set_chip)
265 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
266 AR5K_SLEEP_CTL);
267
268 staid |= AR5K_STA_ID1_PWR_SV;
269 break;
270
271 case AR5K_PM_AWAKE:
272
273 staid &= ~AR5K_STA_ID1_PWR_SV;
274
275 if (!set_chip)
276 goto commit;
277
278 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
279
280 /* If card is down we 'll get 0xffff... so we
281 * need to clean this up before we write the register
282 */
283 if (data & 0xffc00000)
284 data = 0;
285 else
286 /* Preserve sleep duration etc */
287 data = data & ~AR5K_SLEEP_CTL_SLE;
288
289 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
290 AR5K_SLEEP_CTL);
291 udelay(15);
292
293 for (i = 200; i > 0; i--) {
294 /* Check if the chip did wake up */
295 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
296 AR5K_PCICFG_SPWR_DN) == 0)
297 break;
298
299 /* Wait a bit and retry */
300 udelay(50);
301 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
302 AR5K_SLEEP_CTL);
303 }
304
305 /* Fail if the chip didn't wake up */
306 if (i == 0)
307 return -EIO;
308
309 break;
310
311 default:
312 return -EINVAL;
313 }
314
315 commit:
316 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
317
318 return 0;
319 }
320
321 /*
322 * Put device on hold
323 *
324 * Put MAC and Baseband on warm reset and
325 * keep that state (don't clean sleep control
326 * register). After this MAC and Baseband are
327 * disabled and a full reset is needed to come
328 * back. This way we save as much power as possible
329 * without puting the card on full sleep.
330 */
331 int ath5k_hw_on_hold(struct ath5k_hw *ah)
332 {
333 struct pci_dev *pdev = ah->ah_sc->pdev;
334 u32 bus_flags;
335 int ret;
336
337 /* Make sure device is awake */
338 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
339 if (ret) {
340 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
341 return ret;
342 }
343
344 /*
345 * Put chipset on warm reset...
346 *
347 * Note: puting PCI core on warm reset on PCI-E cards
348 * results card to hang and always return 0xffff... so
349 * we ingore that flag for PCI-E cards. On PCI cards
350 * this flag gets cleared after 64 PCI clocks.
351 */
352 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
353
354 if (ah->ah_version == AR5K_AR5210) {
355 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
356 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
357 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
358 mdelay(2);
359 } else {
360 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
361 AR5K_RESET_CTL_BASEBAND | bus_flags);
362 }
363
364 if (ret) {
365 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
366 return -EIO;
367 }
368
369 /* ...wakeup again!*/
370 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
371 if (ret) {
372 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
373 return ret;
374 }
375
376 return ret;
377 }
378
379 /*
380 * Bring up MAC + PHY Chips and program PLL
381 * TODO: Half/Quarter rate support
382 */
383 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
384 {
385 struct pci_dev *pdev = ah->ah_sc->pdev;
386 u32 turbo, mode, clock, bus_flags;
387 int ret;
388
389 turbo = 0;
390 mode = 0;
391 clock = 0;
392
393 /* Wakeup the device */
394 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
395 if (ret) {
396 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
397 return ret;
398 }
399
400 /*
401 * Put chipset on warm reset...
402 *
403 * Note: puting PCI core on warm reset on PCI-E cards
404 * results card to hang and always return 0xffff... so
405 * we ingore that flag for PCI-E cards. On PCI cards
406 * this flag gets cleared after 64 PCI clocks.
407 */
408 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
409
410 if (ah->ah_version == AR5K_AR5210) {
411 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
412 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
413 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
414 mdelay(2);
415 } else {
416 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
417 AR5K_RESET_CTL_BASEBAND | bus_flags);
418 }
419
420 if (ret) {
421 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
422 return -EIO;
423 }
424
425 /* ...wakeup again!...*/
426 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
427 if (ret) {
428 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
429 return ret;
430 }
431
432 /* ...clear reset control register and pull device out of
433 * warm reset */
434 if (ath5k_hw_nic_reset(ah, 0)) {
435 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
436 return -EIO;
437 }
438
439 /* On initialization skip PLL programming since we don't have
440 * a channel / mode set yet */
441 if (initial)
442 return 0;
443
444 if (ah->ah_version != AR5K_AR5210) {
445 /*
446 * Get channel mode flags
447 */
448
449 if (ah->ah_radio >= AR5K_RF5112) {
450 mode = AR5K_PHY_MODE_RAD_RF5112;
451 clock = AR5K_PHY_PLL_RF5112;
452 } else {
453 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
454 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
455 }
456
457 if (flags & CHANNEL_2GHZ) {
458 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
459 clock |= AR5K_PHY_PLL_44MHZ;
460
461 if (flags & CHANNEL_CCK) {
462 mode |= AR5K_PHY_MODE_MOD_CCK;
463 } else if (flags & CHANNEL_OFDM) {
464 if (ah->ah_version == AR5K_AR5211)
465 mode |= AR5K_PHY_MODE_MOD_OFDM;
466 else
467 mode |= AR5K_PHY_MODE_MOD_DYN;
468 } else {
469 ATH5K_ERR(ah->ah_sc,
470 "invalid radio modulation mode\n");
471 return -EINVAL;
472 }
473 } else if (flags & CHANNEL_5GHZ) {
474 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
475
476 if (ah->ah_radio == AR5K_RF5413)
477 clock = AR5K_PHY_PLL_40MHZ_5413;
478 else
479 clock |= AR5K_PHY_PLL_40MHZ;
480
481 if (flags & CHANNEL_OFDM)
482 mode |= AR5K_PHY_MODE_MOD_OFDM;
483 else {
484 ATH5K_ERR(ah->ah_sc,
485 "invalid radio modulation mode\n");
486 return -EINVAL;
487 }
488 } else {
489 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
490 return -EINVAL;
491 }
492
493 if (flags & CHANNEL_TURBO)
494 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
495 } else { /* Reset the device */
496
497 /* ...enable Atheros turbo mode if requested */
498 if (flags & CHANNEL_TURBO)
499 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
500 AR5K_PHY_TURBO);
501 }
502
503 if (ah->ah_version != AR5K_AR5210) {
504
505 /* ...update PLL if needed */
506 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
507 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
508 udelay(300);
509 }
510
511 /* ...set the PHY operating mode */
512 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
513 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
514 }
515
516 return 0;
517 }
518
519 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
520 {
521 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
522 u32 scal, spending, usec32;
523
524 /* Only set 32KHz settings if we have an external
525 * 32KHz crystal present */
526 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
527 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
528 enable) {
529
530 /* 1 usec/cycle */
531 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
532 /* Set up tsf increment on each cycle */
533 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
534
535 /* Set baseband sleep control registers
536 * and sleep control rate */
537 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
538
539 if ((ah->ah_radio == AR5K_RF5112) ||
540 (ah->ah_radio == AR5K_RF5413) ||
541 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
542 spending = 0x14;
543 else
544 spending = 0x18;
545 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
546
547 if ((ah->ah_radio == AR5K_RF5112) ||
548 (ah->ah_radio == AR5K_RF5413) ||
549 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
550 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
551 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
552 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
553 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
554 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
555 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
556 } else {
557 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
558 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
559 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
560 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
561 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
562 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
563 }
564
565 /* Enable sleep clock operation */
566 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
567 AR5K_PCICFG_SLEEP_CLOCK_EN);
568
569 } else {
570
571 /* Disable sleep clock operation and
572 * restore default parameters */
573 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
574 AR5K_PCICFG_SLEEP_CLOCK_EN);
575
576 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
577 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
578
579 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
580 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
581
582 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
583 scal = AR5K_PHY_SCAL_32MHZ_2417;
584 else if (ee->ee_is_hb63)
585 scal = AR5K_PHY_SCAL_32MHZ_HB63;
586 else
587 scal = AR5K_PHY_SCAL_32MHZ;
588 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
589
590 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
591 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
592
593 if ((ah->ah_radio == AR5K_RF5112) ||
594 (ah->ah_radio == AR5K_RF5413) ||
595 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
596 spending = 0x14;
597 else
598 spending = 0x18;
599 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
600
601 if ((ah->ah_radio == AR5K_RF5112) ||
602 (ah->ah_radio == AR5K_RF5413))
603 usec32 = 39;
604 else
605 usec32 = 31;
606 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
607
608 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
609 }
610 }
611
612 /* TODO: Half/Quarter rate */
613 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
614 struct ieee80211_channel *channel)
615 {
616 if (ah->ah_version == AR5K_AR5212 &&
617 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
618
619 /* Setup ADC control */
620 ath5k_hw_reg_write(ah,
621 (AR5K_REG_SM(2,
622 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
623 AR5K_REG_SM(2,
624 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
625 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
626 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
627 AR5K_PHY_ADC_CTL);
628
629
630
631 /* Disable barker RSSI threshold */
632 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
633 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
634
635 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
636 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
637
638 /* Set the mute mask */
639 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
640 }
641
642 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
643 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
644 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
645
646 /* Enable DCU double buffering */
647 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
648 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
649 AR5K_TXCFG_DCU_DBL_BUF_DIS);
650
651 /* Set DAC/ADC delays */
652 if (ah->ah_version == AR5K_AR5212) {
653 u32 scal;
654 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
655 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
656 scal = AR5K_PHY_SCAL_32MHZ_2417;
657 else if (ee->ee_is_hb63)
658 scal = AR5K_PHY_SCAL_32MHZ_HB63;
659 else
660 scal = AR5K_PHY_SCAL_32MHZ;
661 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
662 }
663
664 /* Set fast ADC */
665 if ((ah->ah_radio == AR5K_RF5413) ||
666 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
667 u32 fast_adc = true;
668
669 if (channel->center_freq == 2462 ||
670 channel->center_freq == 2467)
671 fast_adc = 0;
672
673 /* Only update if needed */
674 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
675 ath5k_hw_reg_write(ah, fast_adc,
676 AR5K_PHY_FAST_ADC);
677 }
678
679 /* Fix for first revision of the RF5112 RF chipset */
680 if (ah->ah_radio == AR5K_RF5112 &&
681 ah->ah_radio_5ghz_revision <
682 AR5K_SREV_RAD_5112A) {
683 u32 data;
684 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
685 AR5K_PHY_CCKTXCTL);
686 if (channel->hw_value & CHANNEL_5GHZ)
687 data = 0xffb81020;
688 else
689 data = 0xffb80d20;
690 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
691 }
692
693 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
694 u32 usec_reg;
695 /* 5311 has different tx/rx latency masks
696 * from 5211, since we deal 5311 the same
697 * as 5211 when setting initvals, shift
698 * values here to their proper locations */
699 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
700 ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
701 AR5K_USEC_32 |
702 AR5K_USEC_TX_LATENCY_5211 |
703 AR5K_REG_SM(29,
704 AR5K_USEC_RX_LATENCY_5210)),
705 AR5K_USEC_5211);
706 /* Clear QCU/DCU clock gating register */
707 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
708 /* Set DAC/ADC delays */
709 ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
710 /* Enable PCU FIFO corruption ECO */
711 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
712 AR5K_DIAG_SW_ECO_ENABLE);
713 }
714 }
715
716 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
717 struct ieee80211_channel *channel, u8 ee_mode)
718 {
719 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
720 s16 cck_ofdm_pwr_delta;
721
722 /* Adjust power delta for channel 14 */
723 if (channel->center_freq == 2484)
724 cck_ofdm_pwr_delta =
725 ((ee->ee_cck_ofdm_power_delta -
726 ee->ee_scaled_cck_delta) * 2) / 10;
727 else
728 cck_ofdm_pwr_delta =
729 (ee->ee_cck_ofdm_power_delta * 2) / 10;
730
731 /* Set CCK to OFDM power delta on tx power
732 * adjustment register */
733 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
734 if (channel->hw_value == CHANNEL_G)
735 ath5k_hw_reg_write(ah,
736 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
737 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
738 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
739 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
740 AR5K_PHY_TX_PWR_ADJ);
741 else
742 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
743 } else {
744 /* For older revs we scale power on sw during tx power
745 * setup */
746 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
747 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
748 ee->ee_cck_ofdm_gain_delta;
749 }
750
751 ath5k_hw_set_antenna_switch(ah, ee_mode);
752
753 /* Noise floor threshold */
754 ath5k_hw_reg_write(ah,
755 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
756 AR5K_PHY_NFTHRES);
757
758 if ((channel->hw_value & CHANNEL_TURBO) &&
759 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
760 /* Switch settling time (Turbo) */
761 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
762 AR5K_PHY_SETTLING_SWITCH,
763 ee->ee_switch_settling_turbo[ee_mode]);
764
765 /* Tx/Rx attenuation (Turbo) */
766 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
767 AR5K_PHY_GAIN_TXRX_ATTEN,
768 ee->ee_atn_tx_rx_turbo[ee_mode]);
769
770 /* ADC/PGA desired size (Turbo) */
771 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
772 AR5K_PHY_DESIRED_SIZE_ADC,
773 ee->ee_adc_desired_size_turbo[ee_mode]);
774
775 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
776 AR5K_PHY_DESIRED_SIZE_PGA,
777 ee->ee_pga_desired_size_turbo[ee_mode]);
778
779 /* Tx/Rx margin (Turbo) */
780 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
781 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
782 ee->ee_margin_tx_rx_turbo[ee_mode]);
783
784 } else {
785 /* Switch settling time */
786 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
787 AR5K_PHY_SETTLING_SWITCH,
788 ee->ee_switch_settling[ee_mode]);
789
790 /* Tx/Rx attenuation */
791 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
792 AR5K_PHY_GAIN_TXRX_ATTEN,
793 ee->ee_atn_tx_rx[ee_mode]);
794
795 /* ADC/PGA desired size */
796 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
797 AR5K_PHY_DESIRED_SIZE_ADC,
798 ee->ee_adc_desired_size[ee_mode]);
799
800 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
801 AR5K_PHY_DESIRED_SIZE_PGA,
802 ee->ee_pga_desired_size[ee_mode]);
803
804 /* Tx/Rx margin */
805 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
806 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
807 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
808 ee->ee_margin_tx_rx[ee_mode]);
809 }
810
811 /* XPA delays */
812 ath5k_hw_reg_write(ah,
813 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
814 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
815 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
816 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
817
818 /* XLNA delay */
819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
820 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
821 ee->ee_tx_end2xlna_enable[ee_mode]);
822
823 /* Thresh64 (ANI) */
824 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
825 AR5K_PHY_NF_THRESH62,
826 ee->ee_thr_62[ee_mode]);
827
828 /* False detect backoff for channels
829 * that have spur noise. Write the new
830 * cyclic power RSSI threshold. */
831 if (ath5k_hw_chan_has_spur_noise(ah, channel))
832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
833 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
834 AR5K_INIT_CYCRSSI_THR1 +
835 ee->ee_false_detect[ee_mode]);
836 else
837 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
838 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
839 AR5K_INIT_CYCRSSI_THR1);
840
841 /* I/Q correction (set enable bit last to match HAL sources) */
842 /* TODO: Per channel i/q infos ? */
843 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
844 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
845 ee->ee_i_cal[ee_mode]);
846 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
847 ee->ee_q_cal[ee_mode]);
848 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
849 }
850
851 /* Heavy clipping -disable for now */
852 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
853 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
854 }
855
856 /*
857 * Main reset function
858 */
859 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
860 struct ieee80211_channel *channel, bool change_channel)
861 {
862 struct ath_common *common = ath5k_hw_common(ah);
863 u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
864 u32 phy_tst1;
865 u8 mode, freq, ee_mode;
866 int i, ret;
867
868 ee_mode = 0;
869 staid1_flags = 0;
870 tsf_up = 0;
871 tsf_lo = 0;
872 freq = 0;
873 mode = 0;
874
875 /*
876 * Save some registers before a reset
877 */
878 /*DCU/Antenna selection not available on 5210*/
879 if (ah->ah_version != AR5K_AR5210) {
880
881 switch (channel->hw_value & CHANNEL_MODES) {
882 case CHANNEL_A:
883 mode = AR5K_MODE_11A;
884 freq = AR5K_INI_RFGAIN_5GHZ;
885 ee_mode = AR5K_EEPROM_MODE_11A;
886 break;
887 case CHANNEL_G:
888 mode = AR5K_MODE_11G;
889 freq = AR5K_INI_RFGAIN_2GHZ;
890 ee_mode = AR5K_EEPROM_MODE_11G;
891 break;
892 case CHANNEL_B:
893 mode = AR5K_MODE_11B;
894 freq = AR5K_INI_RFGAIN_2GHZ;
895 ee_mode = AR5K_EEPROM_MODE_11B;
896 break;
897 case CHANNEL_T:
898 mode = AR5K_MODE_11A_TURBO;
899 freq = AR5K_INI_RFGAIN_5GHZ;
900 ee_mode = AR5K_EEPROM_MODE_11A;
901 break;
902 case CHANNEL_TG:
903 if (ah->ah_version == AR5K_AR5211) {
904 ATH5K_ERR(ah->ah_sc,
905 "TurboG mode not available on 5211");
906 return -EINVAL;
907 }
908 mode = AR5K_MODE_11G_TURBO;
909 freq = AR5K_INI_RFGAIN_2GHZ;
910 ee_mode = AR5K_EEPROM_MODE_11G;
911 break;
912 case CHANNEL_XR:
913 if (ah->ah_version == AR5K_AR5211) {
914 ATH5K_ERR(ah->ah_sc,
915 "XR mode not available on 5211");
916 return -EINVAL;
917 }
918 mode = AR5K_MODE_XR;
919 freq = AR5K_INI_RFGAIN_5GHZ;
920 ee_mode = AR5K_EEPROM_MODE_11A;
921 break;
922 default:
923 ATH5K_ERR(ah->ah_sc,
924 "invalid channel: %d\n", channel->center_freq);
925 return -EINVAL;
926 }
927
928 if (change_channel) {
929 /*
930 * Save frame sequence count
931 * For revs. after Oahu, only save
932 * seq num for DCU 0 (Global seq num)
933 */
934 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
935
936 for (i = 0; i < 10; i++)
937 s_seq[i] = ath5k_hw_reg_read(ah,
938 AR5K_QUEUE_DCU_SEQNUM(i));
939
940 } else {
941 s_seq[0] = ath5k_hw_reg_read(ah,
942 AR5K_QUEUE_DCU_SEQNUM(0));
943 }
944
945 if (ah->ah_version == AR5K_AR5211) {
946 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
947 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
948 }
949 }
950
951 if (ah->ah_version == AR5K_AR5212) {
952 /* Restore normal 32/40MHz clock operation
953 * to avoid register access delay on certain
954 * PHY registers */
955 ath5k_hw_set_sleep_clock(ah, false);
956
957 /* Since we are going to write rf buffer
958 * check if we have any pending gain_F
959 * optimization settings */
960 if (change_channel && ah->ah_rf_banks != NULL)
961 ath5k_hw_gainf_calibrate(ah);
962 }
963 }
964
965 /*GPIOs*/
966 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
967 AR5K_PCICFG_LEDSTATE;
968 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
969 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
970
971 /* AR5K_STA_ID1 flags, only preserve antenna
972 * settings and ack/cts rate mode */
973 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
974 (AR5K_STA_ID1_DEFAULT_ANTENNA |
975 AR5K_STA_ID1_DESC_ANTENNA |
976 AR5K_STA_ID1_RTS_DEF_ANTENNA |
977 AR5K_STA_ID1_ACKCTS_6MB |
978 AR5K_STA_ID1_BASE_RATE_11B |
979 AR5K_STA_ID1_SELFGEN_DEF_ANT);
980
981 /* Wakeup the device */
982 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
983 if (ret)
984 return ret;
985
986 /* PHY access enable */
987 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
988 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
989 else
990 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
991 AR5K_PHY(0));
992
993 /* Write initial settings */
994 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
995 if (ret)
996 return ret;
997
998 /*
999 * 5211/5212 Specific
1000 */
1001 if (ah->ah_version != AR5K_AR5210) {
1002
1003 /*
1004 * Write initial RF gain settings
1005 * This should work for both 5111/5112
1006 */
1007 ret = ath5k_hw_rfgain_init(ah, freq);
1008 if (ret)
1009 return ret;
1010
1011 mdelay(1);
1012
1013 /*
1014 * Tweak initval settings for revised
1015 * chipsets and add some more config
1016 * bits
1017 */
1018 ath5k_hw_tweak_initval_settings(ah, channel);
1019
1020 /*
1021 * Set TX power
1022 */
1023 ret = ath5k_hw_txpower(ah, channel, ee_mode,
1024 ah->ah_txpower.txp_max_pwr / 2);
1025 if (ret)
1026 return ret;
1027
1028 if (ah->ah_version == AR5K_AR5212 &&
1029 ah->ah_sc->vif != NULL)
1030 ath5k_hw_write_rate_duration(ah, mode);
1031
1032 /*
1033 * Write RF buffer
1034 */
1035 ret = ath5k_hw_rfregs_init(ah, channel, mode);
1036 if (ret)
1037 return ret;
1038
1039
1040 /* Write OFDM timings on 5212*/
1041 if (ah->ah_version == AR5K_AR5212 &&
1042 channel->hw_value & CHANNEL_OFDM) {
1043
1044 ret = ath5k_hw_write_ofdm_timings(ah, channel);
1045 if (ret)
1046 return ret;
1047
1048 /* Spur info is available only from EEPROM versions
1049 * bigger than 5.3 but but the EEPOM routines will use
1050 * static values for older versions */
1051 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
1052 ath5k_hw_set_spur_mitigation_filter(ah,
1053 channel);
1054 }
1055
1056 /*Enable/disable 802.11b mode on 5111
1057 (enable 2111 frequency converter + CCK)*/
1058 if (ah->ah_radio == AR5K_RF5111) {
1059 if (mode == AR5K_MODE_11B)
1060 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
1061 AR5K_TXCFG_B_MODE);
1062 else
1063 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
1064 AR5K_TXCFG_B_MODE);
1065 }
1066
1067 /* Commit values from EEPROM */
1068 ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
1069
1070 } else {
1071 /*
1072 * For 5210 we do all initialization using
1073 * initvals, so we don't have to modify
1074 * any settings (5210 also only supports
1075 * a/aturbo modes)
1076 */
1077 mdelay(1);
1078 /* Disable phy and wait */
1079 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1080 mdelay(1);
1081 }
1082
1083 /*
1084 * Restore saved values
1085 */
1086
1087 /*DCU/Antenna selection not available on 5210*/
1088 if (ah->ah_version != AR5K_AR5210) {
1089
1090 if (change_channel) {
1091 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1092 for (i = 0; i < 10; i++)
1093 ath5k_hw_reg_write(ah, s_seq[i],
1094 AR5K_QUEUE_DCU_SEQNUM(i));
1095 } else {
1096 ath5k_hw_reg_write(ah, s_seq[0],
1097 AR5K_QUEUE_DCU_SEQNUM(0));
1098 }
1099
1100
1101 if (ah->ah_version == AR5K_AR5211) {
1102 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1103 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1104 }
1105 }
1106 }
1107
1108 /* Ledstate */
1109 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1110
1111 /* Gpio settings */
1112 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1113 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1114
1115 /* Restore sta_id flags and preserve our mac address*/
1116 ath5k_hw_reg_write(ah,
1117 get_unaligned_le32(common->macaddr),
1118 AR5K_STA_ID0);
1119 ath5k_hw_reg_write(ah,
1120 staid1_flags | get_unaligned_le16(common->macaddr + 4),
1121 AR5K_STA_ID1);
1122
1123
1124 /*
1125 * Configure PCU
1126 */
1127
1128 /* Restore bssid and bssid mask */
1129 ath5k_hw_set_associd(ah);
1130
1131 /* Set PCU config */
1132 ath5k_hw_set_opmode(ah, op_mode);
1133
1134 /* Clear any pending interrupts
1135 * PISR/SISR Not available on 5210 */
1136 if (ah->ah_version != AR5K_AR5210)
1137 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1138
1139 /* Set RSSI/BRSSI thresholds
1140 *
1141 * Note: If we decide to set this value
1142 * dynamicaly, have in mind that when AR5K_RSSI_THR
1143 * register is read it might return 0x40 if we haven't
1144 * wrote anything to it plus BMISS RSSI threshold is zeroed.
1145 * So doing a save/restore procedure here isn't the right
1146 * choice. Instead store it on ath5k_hw */
1147 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
1148 AR5K_TUNE_BMISS_THRES <<
1149 AR5K_RSSI_THR_BMISS_S),
1150 AR5K_RSSI_THR);
1151
1152 /* MIC QoS support */
1153 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
1154 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
1155 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
1156 }
1157
1158 /* QoS NOACK Policy */
1159 if (ah->ah_version == AR5K_AR5212) {
1160 ath5k_hw_reg_write(ah,
1161 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
1162 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) |
1163 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
1164 AR5K_QOS_NOACK);
1165 }
1166
1167
1168 /*
1169 * Configure PHY
1170 */
1171
1172 /* Set channel on PHY */
1173 ret = ath5k_hw_channel(ah, channel);
1174 if (ret)
1175 return ret;
1176
1177 /*
1178 * Enable the PHY and wait until completion
1179 * This includes BaseBand and Synthesizer
1180 * activation.
1181 */
1182 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1183
1184 /*
1185 * On 5211+ read activation -> rx delay
1186 * and use it.
1187 *
1188 * TODO: Half/quarter rate support
1189 */
1190 if (ah->ah_version != AR5K_AR5210) {
1191 u32 delay;
1192 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1193 AR5K_PHY_RX_DELAY_M;
1194 delay = (channel->hw_value & CHANNEL_CCK) ?
1195 ((delay << 2) / 22) : (delay / 10);
1196
1197 udelay(100 + (2 * delay));
1198 } else {
1199 mdelay(1);
1200 }
1201
1202 /*
1203 * Perform ADC test to see if baseband is ready
1204 * Set tx hold and check adc test register
1205 */
1206 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
1207 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
1208 for (i = 0; i <= 20; i++) {
1209 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
1210 break;
1211 udelay(200);
1212 }
1213 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
1214
1215 /*
1216 * Start automatic gain control calibration
1217 *
1218 * During AGC calibration RX path is re-routed to
1219 * a power detector so we don't receive anything.
1220 *
1221 * This method is used to calibrate some static offsets
1222 * used together with on-the fly I/Q calibration (the
1223 * one performed via ath5k_hw_phy_calibrate), that doesn't
1224 * interrupt rx path.
1225 *
1226 * While rx path is re-routed to the power detector we also
1227 * start a noise floor calibration, to measure the
1228 * card's noise floor (the noise we measure when we are not
1229 * transmiting or receiving anything).
1230 *
1231 * If we are in a noisy environment AGC calibration may time
1232 * out and/or noise floor calibration might timeout.
1233 */
1234 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1235 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
1236
1237 /* At the same time start I/Q calibration for QAM constellation
1238 * -no need for CCK- */
1239 ah->ah_calibration = false;
1240 if (!(mode == AR5K_MODE_11B)) {
1241 ah->ah_calibration = true;
1242 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1243 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1244 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1245 AR5K_PHY_IQ_RUN);
1246 }
1247
1248 /* Wait for gain calibration to finish (we check for I/Q calibration
1249 * during ath5k_phy_calibrate) */
1250 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1251 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1252 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
1253 channel->center_freq);
1254 }
1255
1256 /* Restore antenna mode */
1257 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
1258
1259 /* Restore slot time and ACK timeouts */
1260 if (ah->ah_coverage_class > 0)
1261 ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
1262
1263 /*
1264 * Configure QCUs/DCUs
1265 */
1266
1267 /* TODO: HW Compression support for data queues */
1268 /* TODO: Burst prefetch for data queues */
1269
1270 /*
1271 * Reset queues and start beacon timers at the end of the reset routine
1272 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
1273 * Note: If we want we can assign multiple qcus on one dcu.
1274 */
1275 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1276 ret = ath5k_hw_reset_tx_queue(ah, i);
1277 if (ret) {
1278 ATH5K_ERR(ah->ah_sc,
1279 "failed to reset TX queue #%d\n", i);
1280 return ret;
1281 }
1282 }
1283
1284
1285 /*
1286 * Configure DMA/Interrupts
1287 */
1288
1289 if (ah->ah_version != AR5K_AR5210) {
1290 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1291 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
1292 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1293 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
1294 }
1295
1296 /* Pre-enable interrupts on 5211/5212*/
1297 if (ah->ah_version != AR5K_AR5210)
1298 ath5k_hw_set_imr(ah, ah->ah_imr);
1299
1300 /* Enable 32KHz clock function for AR5212+ chips
1301 * Set clocks to 32KHz operation and use an
1302 * external 32KHz crystal when sleeping if one
1303 * exists */
1304 if (ah->ah_version == AR5K_AR5212 &&
1305 op_mode != NL80211_IFTYPE_AP)
1306 ath5k_hw_set_sleep_clock(ah, true);
1307
1308 /*
1309 * Disable beacons and reset the TSF
1310 */
1311 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1312 ath5k_hw_reset_tsf(ah);
1313 return 0;
1314 }
Tomato firmware and modifications.