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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / smc91x.h
blobfdddc4fc769235295254438e6b76f3fa65ee268b
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@fluxnic.net>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) || defined(CONFIG_MACH_MAINSTONE) || \
44 defined(CONFIG_MACH_ZYLONITE) || defined(CONFIG_MACH_LITTLETON) || \
45 defined(CONFIG_MACH_ZYLONITE2) || defined(CONFIG_ARCH_VIPER) || \
46 defined(CONFIG_MACH_STARGATE2)
47
48 #include <asm/mach-types.h>
49
50 /* Now the bus width is specified in the platform data
51 * pretend here to support all I/O access types
52 */
53 #define SMC_CAN_USE_8BIT 1
54 #define SMC_CAN_USE_16BIT 1
55 #define SMC_CAN_USE_32BIT 1
56 #define SMC_NOWAIT 1
57
58 #define SMC_IO_SHIFT (lp->io_shift)
59
60 #define SMC_inb(a, r) readb((a) + (r))
61 #define SMC_inw(a, r) readw((a) + (r))
62 #define SMC_inl(a, r) readl((a) + (r))
63 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
64 #define SMC_outl(v, a, r) writel(v, (a) + (r))
65 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
66 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
67 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
68 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
69 #define SMC_IRQ_FLAGS (-1) /* from resource */
70
71 /* We actually can't write halfwords properly if not word aligned */
72 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
73 {
74 if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) {
75 unsigned int v = val << 16;
76 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
77 writel(v, ioaddr + (reg & ~2));
78 } else {
79 writew(val, ioaddr + reg);
80 }
81 }
82
83 #elif defined(CONFIG_SA1100_PLEB)
84 /* We can only do 16-bit reads and writes in the static memory space. */
85 #define SMC_CAN_USE_8BIT 1
86 #define SMC_CAN_USE_16BIT 1
87 #define SMC_CAN_USE_32BIT 0
88 #define SMC_IO_SHIFT 0
89 #define SMC_NOWAIT 1
90
91 #define SMC_inb(a, r) readb((a) + (r))
92 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
93 #define SMC_inw(a, r) readw((a) + (r))
94 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
95 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
96 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
97 #define SMC_outw(v, a, r) writew(v, (a) + (r))
98 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
99
100 #define SMC_IRQ_FLAGS (-1)
101
102 #elif defined(CONFIG_SA1100_ASSABET)
103
104 #include <mach/neponset.h>
105
106 /* We can only do 8-bit reads and writes in the static memory space. */
107 #define SMC_CAN_USE_8BIT 1
108 #define SMC_CAN_USE_16BIT 0
109 #define SMC_CAN_USE_32BIT 0
110 #define SMC_NOWAIT 1
111
112 /* The first two address lines aren't connected... */
113 #define SMC_IO_SHIFT 2
114
115 #define SMC_inb(a, r) readb((a) + (r))
116 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
117 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
118 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
119 #define SMC_IRQ_FLAGS (-1) /* from resource */
120
121 #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \
122 defined(CONFIG_MACH_NOMADIK_8815NHK)
123
124 #define SMC_CAN_USE_8BIT 0
125 #define SMC_CAN_USE_16BIT 1
126 #define SMC_CAN_USE_32BIT 0
127 #define SMC_IO_SHIFT 0
128 #define SMC_NOWAIT 1
129
130 #define SMC_inw(a, r) readw((a) + (r))
131 #define SMC_outw(v, a, r) writew(v, (a) + (r))
132 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
133 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
134
135 #elif defined(CONFIG_ARCH_INNOKOM) || \
136 defined(CONFIG_ARCH_PXA_IDP) || \
137 defined(CONFIG_ARCH_RAMSES) || \
138 defined(CONFIG_ARCH_PCM027)
139
140 #define SMC_CAN_USE_8BIT 1
141 #define SMC_CAN_USE_16BIT 1
142 #define SMC_CAN_USE_32BIT 1
143 #define SMC_IO_SHIFT 0
144 #define SMC_NOWAIT 1
145 #define SMC_USE_PXA_DMA 1
146
147 #define SMC_inb(a, r) readb((a) + (r))
148 #define SMC_inw(a, r) readw((a) + (r))
149 #define SMC_inl(a, r) readl((a) + (r))
150 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
151 #define SMC_outl(v, a, r) writel(v, (a) + (r))
152 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
153 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
154 #define SMC_IRQ_FLAGS (-1) /* from resource */
155
156 /* We actually can't write halfwords properly if not word aligned */
157 static inline void
158 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
159 {
160 if (reg & 2) {
161 unsigned int v = val << 16;
162 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
163 writel(v, ioaddr + (reg & ~2));
164 } else {
165 writew(val, ioaddr + reg);
166 }
167 }
168
169 #elif defined(CONFIG_SH_SH4202_MICRODEV)
170
171 #define SMC_CAN_USE_8BIT 0
172 #define SMC_CAN_USE_16BIT 1
173 #define SMC_CAN_USE_32BIT 0
174
175 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
176 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
177 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
178 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
179 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
180 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
181 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
182 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
183 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
184 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
185
186 #define SMC_IRQ_FLAGS (0)
187
188 #elif defined(CONFIG_M32R)
189
190 #define SMC_CAN_USE_8BIT 0
191 #define SMC_CAN_USE_16BIT 1
192 #define SMC_CAN_USE_32BIT 0
193
194 #define SMC_inb(a, r) inb(((u32)a) + (r))
195 #define SMC_inw(a, r) inw(((u32)a) + (r))
196 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
197 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
198 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
199 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
200
201 #define SMC_IRQ_FLAGS (0)
202
203 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
204 #define RPC_LSB_DEFAULT RPC_LED_100_10
205
206 #elif defined(CONFIG_MACH_LPD79520) || \
207 defined(CONFIG_MACH_LPD7A400) || \
208 defined(CONFIG_MACH_LPD7A404)
209
210 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
211 * way that the CPU handles chip selects and the way that the SMC chip
212 * expects the chip select to operate. Refer to
213 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
214 * IOBARRIER is a byte, in order that we read the least-common
215 * denominator. It would be wasteful to read 32 bits from an 8-bit
216 * accessible region.
217 *
218 * There is no explicit protection against interrupts intervening
219 * between the writew and the IOBARRIER. In SMC ISR there is a
220 * preamble that performs an IOBARRIER in the extremely unlikely event
221 * that the driver interrupts itself between a writew to the chip an
222 * the IOBARRIER that follows *and* the cache is large enough that the
223 * first off-chip access while handing the interrupt is to the SMC
224 * chip. Other devices in the same address space as the SMC chip must
225 * be aware of the potential for trouble and perform a similar
226 * IOBARRIER on entry to their ISR.
227 */
228
229 #include <mach/constants.h> /* IOBARRIER_VIRT */
230
231 #define SMC_CAN_USE_8BIT 0
232 #define SMC_CAN_USE_16BIT 1
233 #define SMC_CAN_USE_32BIT 0
234 #define SMC_NOWAIT 0
235 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
236
237 #define SMC_inw(a,r)\
238 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
239 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
240
241 #define SMC_insw LPD7_SMC_insw
242 static inline void LPD7_SMC_insw (unsigned char* a, int r,
243 unsigned char* p, int l)
244 {
245 unsigned short* ps = (unsigned short*) p;
246 while (l-- > 0) {
247 *ps++ = readw (a + r);
248 LPD7X_IOBARRIER;
249 }
250 }
251
252 #define SMC_outsw LPD7_SMC_outsw
253 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
254 unsigned char* p, int l)
255 {
256 unsigned short* ps = (unsigned short*) p;
257 while (l-- > 0) {
258 writew (*ps++, a + r);
259 LPD7X_IOBARRIER;
260 }
261 }
262
263 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
264
265 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
266 #define RPC_LSB_DEFAULT RPC_LED_100_10
267
268 #elif defined(CONFIG_ARCH_VERSATILE)
269
270 #define SMC_CAN_USE_8BIT 1
271 #define SMC_CAN_USE_16BIT 1
272 #define SMC_CAN_USE_32BIT 1
273 #define SMC_NOWAIT 1
274
275 #define SMC_inb(a, r) readb((a) + (r))
276 #define SMC_inw(a, r) readw((a) + (r))
277 #define SMC_inl(a, r) readl((a) + (r))
278 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
279 #define SMC_outw(v, a, r) writew(v, (a) + (r))
280 #define SMC_outl(v, a, r) writel(v, (a) + (r))
281 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
282 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
283 #define SMC_IRQ_FLAGS (-1) /* from resource */
284
285 #elif defined(CONFIG_MN10300)
286
287 /*
288 * MN10300/AM33 configuration
289 */
290
291 #include <unit/smc91111.h>
292
293 #elif defined(CONFIG_ARCH_MSM)
294
295 #define SMC_CAN_USE_8BIT 0
296 #define SMC_CAN_USE_16BIT 1
297 #define SMC_CAN_USE_32BIT 0
298 #define SMC_NOWAIT 1
299
300 #define SMC_inw(a, r) readw((a) + (r))
301 #define SMC_outw(v, a, r) writew(v, (a) + (r))
302 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
303 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
304
305 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
306
307 #elif defined(CONFIG_COLDFIRE)
308
309 #define SMC_CAN_USE_8BIT 0
310 #define SMC_CAN_USE_16BIT 1
311 #define SMC_CAN_USE_32BIT 0
312 #define SMC_NOWAIT 1
313
314 static inline void mcf_insw(void *a, unsigned char *p, int l)
315 {
316 u16 *wp = (u16 *) p;
317 while (l-- > 0)
318 *wp++ = readw(a);
319 }
320
321 static inline void mcf_outsw(void *a, unsigned char *p, int l)
322 {
323 u16 *wp = (u16 *) p;
324 while (l-- > 0)
325 writew(*wp++, a);
326 }
327
328 #define SMC_inw(a, r) _swapw(readw((a) + (r)))
329 #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r))
330 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
331 #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
332
333 #define SMC_IRQ_FLAGS (IRQF_DISABLED)
334
335 #else
336
337 /*
338 * Default configuration
339 */
340
341 #define SMC_CAN_USE_8BIT 1
342 #define SMC_CAN_USE_16BIT 1
343 #define SMC_CAN_USE_32BIT 1
344 #define SMC_NOWAIT 1
345
346 #define SMC_IO_SHIFT (lp->io_shift)
347
348 #define SMC_inb(a, r) readb((a) + (r))
349 #define SMC_inw(a, r) readw((a) + (r))
350 #define SMC_inl(a, r) readl((a) + (r))
351 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
352 #define SMC_outw(v, a, r) writew(v, (a) + (r))
353 #define SMC_outl(v, a, r) writel(v, (a) + (r))
354 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
355 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
356 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
357 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
358
359 #define RPC_LSA_DEFAULT RPC_LED_100_10
360 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
361
362 #endif
363
364
365 /* store this information for the driver.. */
366 struct smc_local {
367 /*
368 * If I have to wait until memory is available to send a
369 * packet, I will store the skbuff here, until I get the
370 * desired memory. Then, I'll send it out and free it.
371 */
372 struct sk_buff *pending_tx_skb;
373 struct tasklet_struct tx_task;
374
375 /* version/revision of the SMC91x chip */
376 int version;
377
378 /* Contains the current active transmission mode */
379 int tcr_cur_mode;
380
381 /* Contains the current active receive mode */
382 int rcr_cur_mode;
383
384 /* Contains the current active receive/phy mode */
385 int rpc_cur_mode;
386 int ctl_rfduplx;
387 int ctl_rspeed;
388
389 u32 msg_enable;
390 u32 phy_type;
391 struct mii_if_info mii;
392
393 /* work queue */
394 struct work_struct phy_configure;
395 struct net_device *dev;
396 int work_pending;
397
398 spinlock_t lock;
399
400 #ifdef CONFIG_ARCH_PXA
401 /* DMA needs the physical address of the chip */
402 u_long physaddr;
403 struct device *device;
404 #endif
405 void __iomem *base;
406 void __iomem *datacs;
407
408 /* the low address lines on some platforms aren't connected... */
409 int io_shift;
410
411 struct smc91x_platdata cfg;
412 };
413
414 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
415 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
416 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
417
418 #ifdef CONFIG_ARCH_PXA
419 /*
420 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
421 * always happening in irq context so no need to worry about races. TX is
422 * different and probably not worth it for that reason, and not as critical
423 * as RX which can overrun memory and lose packets.
424 */
425 #include <linux/dma-mapping.h>
426 #include <mach/dma.h>
427
428 #ifdef SMC_insl
429 #undef SMC_insl
430 #define SMC_insl(a, r, p, l) \
431 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
432 static inline void
433 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
434 u_char *buf, int len)
435 {
436 u_long physaddr = lp->physaddr;
437 dma_addr_t dmabuf;
438
439 /* fallback if no DMA available */
440 if (dma == (unsigned char)-1) {
441 readsl(ioaddr + reg, buf, len);
442 return;
443 }
444
445 /* 64 bit alignment is required for memory to memory DMA */
446 if ((long)buf & 4) {
447 *((u32 *)buf) = SMC_inl(ioaddr, reg);
448 buf += 4;
449 len--;
450 }
451
452 len *= 4;
453 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
454 DCSR(dma) = DCSR_NODESC;
455 DTADR(dma) = dmabuf;
456 DSADR(dma) = physaddr + reg;
457 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
458 DCMD_WIDTH4 | (DCMD_LENGTH & len));
459 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
460 while (!(DCSR(dma) & DCSR_STOPSTATE))
461 cpu_relax();
462 DCSR(dma) = 0;
463 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
464 }
465 #endif
466
467 #ifdef SMC_insw
468 #undef SMC_insw
469 #define SMC_insw(a, r, p, l) \
470 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
471 static inline void
472 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
473 u_char *buf, int len)
474 {
475 u_long physaddr = lp->physaddr;
476 dma_addr_t dmabuf;
477
478 /* fallback if no DMA available */
479 if (dma == (unsigned char)-1) {
480 readsw(ioaddr + reg, buf, len);
481 return;
482 }
483
484 /* 64 bit alignment is required for memory to memory DMA */
485 while ((long)buf & 6) {
486 *((u16 *)buf) = SMC_inw(ioaddr, reg);
487 buf += 2;
488 len--;
489 }
490
491 len *= 2;
492 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
493 DCSR(dma) = DCSR_NODESC;
494 DTADR(dma) = dmabuf;
495 DSADR(dma) = physaddr + reg;
496 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
497 DCMD_WIDTH2 | (DCMD_LENGTH & len));
498 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
499 while (!(DCSR(dma) & DCSR_STOPSTATE))
500 cpu_relax();
501 DCSR(dma) = 0;
502 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
503 }
504 #endif
505
506 static void
507 smc_pxa_dma_irq(int dma, void *dummy)
508 {
509 DCSR(dma) = 0;
510 }
511 #endif /* CONFIG_ARCH_PXA */
512
513
514 /*
515 * Everything a particular hardware setup needs should have been defined
516 * at this point. Add stubs for the undefined cases, mainly to avoid
517 * compilation warnings since they'll be optimized away, or to prevent buggy
518 * use of them.
519 */
520
521 #if ! SMC_CAN_USE_32BIT
522 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
523 #define SMC_outl(x, ioaddr, reg) BUG()
524 #define SMC_insl(a, r, p, l) BUG()
525 #define SMC_outsl(a, r, p, l) BUG()
526 #endif
527
528 #if !defined(SMC_insl) || !defined(SMC_outsl)
529 #define SMC_insl(a, r, p, l) BUG()
530 #define SMC_outsl(a, r, p, l) BUG()
531 #endif
532
533 #if ! SMC_CAN_USE_16BIT
534
535 /*
536 * Any 16-bit access is performed with two 8-bit accesses if the hardware
537 * can't do it directly. Most registers are 16-bit so those are mandatory.
538 */
539 #define SMC_outw(x, ioaddr, reg) \
540 do { \
541 unsigned int __val16 = (x); \
542 SMC_outb( __val16, ioaddr, reg ); \
543 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
544 } while (0)
545 #define SMC_inw(ioaddr, reg) \
546 ({ \
547 unsigned int __val16; \
548 __val16 = SMC_inb( ioaddr, reg ); \
549 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
550 __val16; \
551 })
552
553 #define SMC_insw(a, r, p, l) BUG()
554 #define SMC_outsw(a, r, p, l) BUG()
555
556 #endif
557
558 #if !defined(SMC_insw) || !defined(SMC_outsw)
559 #define SMC_insw(a, r, p, l) BUG()
560 #define SMC_outsw(a, r, p, l) BUG()
561 #endif
562
563 #if ! SMC_CAN_USE_8BIT
564 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
565 #define SMC_outb(x, ioaddr, reg) BUG()
566 #define SMC_insb(a, r, p, l) BUG()
567 #define SMC_outsb(a, r, p, l) BUG()
568 #endif
569
570 #if !defined(SMC_insb) || !defined(SMC_outsb)
571 #define SMC_insb(a, r, p, l) BUG()
572 #define SMC_outsb(a, r, p, l) BUG()
573 #endif
574
575 #ifndef SMC_CAN_USE_DATACS
576 #define SMC_CAN_USE_DATACS 0
577 #endif
578
579 #ifndef SMC_IO_SHIFT
580 #define SMC_IO_SHIFT 0
581 #endif
582
583 #ifndef SMC_IRQ_FLAGS
584 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
585 #endif
586
587 #ifndef SMC_INTERRUPT_PREAMBLE
588 #define SMC_INTERRUPT_PREAMBLE
589 #endif
590
591
592 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
593 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
594 #define SMC_DATA_EXTENT (4)
595
596 /*
597 . Bank Select Register:
598 .
599 . yyyy yyyy 0000 00xx
600 . xx = bank number
601 . yyyy yyyy = 0x33, for identification purposes.
602 */
603 #define BANK_SELECT (14 << SMC_IO_SHIFT)
604
605
606 // Transmit Control Register
607 /* BANK 0 */
608 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
609 #define TCR_ENABLE 0x0001 // When 1 we can transmit
610 #define TCR_LOOP 0x0002 // Controls output pin LBK
611 #define TCR_FORCOL 0x0004 // When 1 will force a collision
612 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
613 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
614 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
615 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
616 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
617 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
618 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
619
620 #define TCR_CLEAR 0 /* do NOTHING */
621 /* the default settings for the TCR register : */
622 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
623
624
625 // EPH Status Register
626 /* BANK 0 */
627 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
628 #define ES_TX_SUC 0x0001 // Last TX was successful
629 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
630 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
631 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
632 #define ES_16COL 0x0010 // 16 Collisions Reached
633 #define ES_SQET 0x0020 // Signal Quality Error Test
634 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
635 #define ES_TXDEFR 0x0080 // Transmit Deferred
636 #define ES_LATCOL 0x0200 // Late collision detected on last tx
637 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
638 #define ES_EXC_DEF 0x0800 // Excessive Deferral
639 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
640 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
641 #define ES_TXUNRN 0x8000 // Tx Underrun
642
643
644 // Receive Control Register
645 /* BANK 0 */
646 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
647 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
648 #define RCR_PRMS 0x0002 // Enable promiscuous mode
649 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
650 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
651 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
652 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
653 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
654 #define RCR_SOFTRST 0x8000 // resets the chip
655
656 /* the normal settings for the RCR register : */
657 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
658 #define RCR_CLEAR 0x0 // set it to a base state
659
660
661 // Counter Register
662 /* BANK 0 */
663 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
664
665
666 // Memory Information Register
667 /* BANK 0 */
668 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
669
670
671 // Receive/Phy Control Register
672 /* BANK 0 */
673 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
674 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
675 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
676 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
677 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
678 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
679
680 #ifndef RPC_LSA_DEFAULT
681 #define RPC_LSA_DEFAULT RPC_LED_100
682 #endif
683 #ifndef RPC_LSB_DEFAULT
684 #define RPC_LSB_DEFAULT RPC_LED_FD
685 #endif
686
687 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
688
689
690 /* Bank 0 0x0C is reserved */
691
692 // Bank Select Register
693 /* All Banks */
694 #define BSR_REG 0x000E
695
696
697 // Configuration Reg
698 /* BANK 1 */
699 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
700 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
701 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
702 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
703 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
704
705 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
706 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
707
708
709 // Base Address Register
710 /* BANK 1 */
711 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
712
713
714 // Individual Address Registers
715 /* BANK 1 */
716 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
717 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
718 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
719
720
721 // General Purpose Register
722 /* BANK 1 */
723 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
724
725
726 // Control Register
727 /* BANK 1 */
728 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
729 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
730 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
731 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
732 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
733 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
734 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
735 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
736 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
737
738
739 // MMU Command Register
740 /* BANK 2 */
741 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
742 #define MC_BUSY 1 // When 1 the last release has not completed
743 #define MC_NOP (0<<5) // No Op
744 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
745 #define MC_RESET (2<<5) // Reset MMU to initial state
746 #define MC_REMOVE (3<<5) // Remove the current rx packet
747 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
748 #define MC_FREEPKT (5<<5) // Release packet in PNR register
749 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
750 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
751
752
753 // Packet Number Register
754 /* BANK 2 */
755 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
756
757
758 // Allocation Result Register
759 /* BANK 2 */
760 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
761 #define AR_FAILED 0x80 // Alocation Failed
762
763
764 // TX FIFO Ports Register
765 /* BANK 2 */
766 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
767 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
768
769 // RX FIFO Ports Register
770 /* BANK 2 */
771 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
772 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
773
774 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
775
776 // Pointer Register
777 /* BANK 2 */
778 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
779 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
780 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
781 #define PTR_READ 0x2000 // When 1 the operation is a read
782
783
784 // Data Register
785 /* BANK 2 */
786 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
787
788
789 // Interrupt Status/Acknowledge Register
790 /* BANK 2 */
791 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
792
793
794 // Interrupt Mask Register
795 /* BANK 2 */
796 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
797 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
798 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
799 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
800 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
801 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
802 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
803 #define IM_TX_INT 0x02 // Transmit Interrupt
804 #define IM_RCV_INT 0x01 // Receive Interrupt
805
806
807 // Multicast Table Registers
808 /* BANK 3 */
809 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
810 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
811 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
812 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
813
814
815 // Management Interface Register (MII)
816 /* BANK 3 */
817 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
818 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
819 #define MII_MDOE 0x0008 // MII Output Enable
820 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
821 #define MII_MDI 0x0002 // MII Input, pin MDI
822 #define MII_MDO 0x0001 // MII Output, pin MDO
823
824
825 // Revision Register
826 /* BANK 3 */
827 /* ( hi: chip id low: rev # ) */
828 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
829
830
831 // Early RCV Register
832 /* BANK 3 */
833 /* this is NOT on SMC9192 */
834 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
835 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
836 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
837
838
839 // External Register
840 /* BANK 7 */
841 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
842
843
844 #define CHIP_9192 3
845 #define CHIP_9194 4
846 #define CHIP_9195 5
847 #define CHIP_9196 6
848 #define CHIP_91100 7
849 #define CHIP_91100FD 8
850 #define CHIP_91111FD 9
851
852 static const char * chip_ids[ 16 ] = {
853 NULL, NULL, NULL,
854 /* 3 */ "SMC91C90/91C92",
855 /* 4 */ "SMC91C94",
856 /* 5 */ "SMC91C95",
857 /* 6 */ "SMC91C96",
858 /* 7 */ "SMC91C100",
859 /* 8 */ "SMC91C100FD",
860 /* 9 */ "SMC91C11xFD",
861 NULL, NULL, NULL,
862 NULL, NULL, NULL};
863
864
865 /*
866 . Receive status bits
867 */
868 #define RS_ALGNERR 0x8000
869 #define RS_BRODCAST 0x4000
870 #define RS_BADCRC 0x2000
871 #define RS_ODDFRAME 0x1000
872 #define RS_TOOLONG 0x0800
873 #define RS_TOOSHORT 0x0400
874 #define RS_MULTICAST 0x0001
875 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
876
877
878 /*
879 * PHY IDs
880 * LAN83C183 == LAN91C111 Internal PHY
881 */
882 #define PHY_LAN83C183 0x0016f840
883 #define PHY_LAN83C180 0x02821c50
884
885 /*
886 * PHY Register Addresses (LAN91C111 Internal PHY)
887 *
888 * Generic PHY registers can be found in <linux/mii.h>
889 *
890 * These phy registers are specific to our on-board phy.
891 */
892
893 // PHY Configuration Register 1
894 #define PHY_CFG1_REG 0x10
895 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
896 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
897 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
898 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
899 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
900 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
901 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
902 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
903 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
904 #define PHY_CFG1_TLVL_MASK 0x003C
905 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
906
907
908 // PHY Configuration Register 2
909 #define PHY_CFG2_REG 0x11
910 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
911 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
912 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
913 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
914
915 // PHY Status Output (and Interrupt status) Register
916 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
917 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
918 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
919 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
920 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
921 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
922 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
923 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
924 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
925 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
926 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
927
928 // PHY Interrupt/Status Mask Register
929 #define PHY_MASK_REG 0x13 // Interrupt Mask
930 // Uses the same bit definitions as PHY_INT_REG
931
932
933 /*
934 * SMC91C96 ethernet config and status registers.
935 * These are in the "attribute" space.
936 */
937 #define ECOR 0x8000
938 #define ECOR_RESET 0x80
939 #define ECOR_LEVEL_IRQ 0x40
940 #define ECOR_WR_ATTRIB 0x04
941 #define ECOR_ENABLE 0x01
942
943 #define ECSR 0x8002
944 #define ECSR_IOIS8 0x20
945 #define ECSR_PWRDWN 0x04
946 #define ECSR_INT 0x02
947
948 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
949
950
951 /*
952 * Macros to abstract register access according to the data bus
953 * capabilities. Please use those and not the in/out primitives.
954 * Note: the following macros do *not* select the bank -- this must
955 * be done separately as needed in the main code. The SMC_REG() macro
956 * only uses the bank argument for debugging purposes (when enabled).
957 *
958 * Note: despite inline functions being safer, everything leading to this
959 * should preferably be macros to let BUG() display the line number in
960 * the core source code since we're interested in the top call site
961 * not in any inline function location.
962 */
963
964 #if SMC_DEBUG > 0
965 #define SMC_REG(lp, reg, bank) \
966 ({ \
967 int __b = SMC_CURRENT_BANK(lp); \
968 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
969 printk( "%s: bank reg screwed (0x%04x)\n", \
970 CARDNAME, __b ); \
971 BUG(); \
972 } \
973 reg<<SMC_IO_SHIFT; \
974 })
975 #else
976 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
977 #endif
978
979 /*
980 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
981 * aligned to a 32 bit boundary. I tell you that does exist!
982 * Fortunately the affected register accesses can be easily worked around
983 * since we can write zeroes to the preceeding 16 bits without adverse
984 * effects and use a 32-bit access.
985 *
986 * Enforce it on any 32-bit capable setup for now.
987 */
988 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
989
990 #define SMC_GET_PN(lp) \
991 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
992 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
993
994 #define SMC_SET_PN(lp, x) \
995 do { \
996 if (SMC_MUST_ALIGN_WRITE(lp)) \
997 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
998 else if (SMC_8BIT(lp)) \
999 SMC_outb(x, ioaddr, PN_REG(lp)); \
1000 else \
1001 SMC_outw(x, ioaddr, PN_REG(lp)); \
1002 } while (0)
1003
1004 #define SMC_GET_AR(lp) \
1005 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1006 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1007
1008 #define SMC_GET_TXFIFO(lp) \
1009 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1010 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1011
1012 #define SMC_GET_RXFIFO(lp) \
1013 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1014 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1015
1016 #define SMC_GET_INT(lp) \
1017 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1018 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1019
1020 #define SMC_ACK_INT(lp, x) \
1021 do { \
1022 if (SMC_8BIT(lp)) \
1023 SMC_outb(x, ioaddr, INT_REG(lp)); \
1024 else { \
1025 unsigned long __flags; \
1026 int __mask; \
1027 local_irq_save(__flags); \
1028 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1029 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1030 local_irq_restore(__flags); \
1031 } \
1032 } while (0)
1033
1034 #define SMC_GET_INT_MASK(lp) \
1035 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1036 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1037
1038 #define SMC_SET_INT_MASK(lp, x) \
1039 do { \
1040 if (SMC_8BIT(lp)) \
1041 SMC_outb(x, ioaddr, IM_REG(lp)); \
1042 else \
1043 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1044 } while (0)
1045
1046 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1047
1048 #define SMC_SELECT_BANK(lp, x) \
1049 do { \
1050 if (SMC_MUST_ALIGN_WRITE(lp)) \
1051 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1052 else \
1053 SMC_outw(x, ioaddr, BANK_SELECT); \
1054 } while (0)
1055
1056 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1057
1058 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1059
1060 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1061
1062 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1063
1064 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1065
1066 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1067
1068 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1069
1070 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1071
1072 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1073
1074 #define SMC_SET_GP(lp, x) \
1075 do { \
1076 if (SMC_MUST_ALIGN_WRITE(lp)) \
1077 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1078 else \
1079 SMC_outw(x, ioaddr, GP_REG(lp)); \
1080 } while (0)
1081
1082 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1083
1084 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1085
1086 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1087
1088 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1089
1090 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1091
1092 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1093
1094 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1095
1096 #define SMC_SET_PTR(lp, x) \
1097 do { \
1098 if (SMC_MUST_ALIGN_WRITE(lp)) \
1099 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1100 else \
1101 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1102 } while (0)
1103
1104 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1105
1106 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1107
1108 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1109
1110 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1111
1112 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1113
1114 #define SMC_SET_RPC(lp, x) \
1115 do { \
1116 if (SMC_MUST_ALIGN_WRITE(lp)) \
1117 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1118 else \
1119 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1120 } while (0)
1121
1122 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1123
1124 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1125
1126 #ifndef SMC_GET_MAC_ADDR
1127 #define SMC_GET_MAC_ADDR(lp, addr) \
1128 do { \
1129 unsigned int __v; \
1130 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1131 addr[0] = __v; addr[1] = __v >> 8; \
1132 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1133 addr[2] = __v; addr[3] = __v >> 8; \
1134 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1135 addr[4] = __v; addr[5] = __v >> 8; \
1136 } while (0)
1137 #endif
1138
1139 #define SMC_SET_MAC_ADDR(lp, addr) \
1140 do { \
1141 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1142 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1143 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1144 } while (0)
1145
1146 #define SMC_SET_MCAST(lp, x) \
1147 do { \
1148 const unsigned char *mt = (x); \
1149 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1150 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1151 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1152 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1153 } while (0)
1154
1155 #define SMC_PUT_PKT_HDR(lp, status, length) \
1156 do { \
1157 if (SMC_32BIT(lp)) \
1158 SMC_outl((status) | (length)<<16, ioaddr, \
1159 DATA_REG(lp)); \
1160 else { \
1161 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1162 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1163 } \
1164 } while (0)
1165
1166 #define SMC_GET_PKT_HDR(lp, status, length) \
1167 do { \
1168 if (SMC_32BIT(lp)) { \
1169 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1170 (status) = __val & 0xffff; \
1171 (length) = __val >> 16; \
1172 } else { \
1173 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1174 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1175 } \
1176 } while (0)
1177
1178 #define SMC_PUSH_DATA(lp, p, l) \
1179 do { \
1180 if (SMC_32BIT(lp)) { \
1181 void *__ptr = (p); \
1182 int __len = (l); \
1183 void __iomem *__ioaddr = ioaddr; \
1184 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1185 __len -= 2; \
1186 SMC_outw(*(u16 *)__ptr, ioaddr, \
1187 DATA_REG(lp)); \
1188 __ptr += 2; \
1189 } \
1190 if (SMC_CAN_USE_DATACS && lp->datacs) \
1191 __ioaddr = lp->datacs; \
1192 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1193 if (__len & 2) { \
1194 __ptr += (__len & ~3); \
1195 SMC_outw(*((u16 *)__ptr), ioaddr, \
1196 DATA_REG(lp)); \
1197 } \
1198 } else if (SMC_16BIT(lp)) \
1199 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1200 else if (SMC_8BIT(lp)) \
1201 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1202 } while (0)
1203
1204 #define SMC_PULL_DATA(lp, p, l) \
1205 do { \
1206 if (SMC_32BIT(lp)) { \
1207 void *__ptr = (p); \
1208 int __len = (l); \
1209 void __iomem *__ioaddr = ioaddr; \
1210 if ((unsigned long)__ptr & 2) { \
1211 /* \
1212 * We want 32bit alignment here. \
1213 * Since some buses perform a full \
1214 * 32bit fetch even for 16bit data \
1215 * we can't use SMC_inw() here. \
1216 * Back both source (on-chip) and \
1217 * destination pointers of 2 bytes. \
1218 * This is possible since the call to \
1219 * SMC_GET_PKT_HDR() already advanced \
1220 * the source pointer of 4 bytes, and \
1221 * the skb_reserve(skb, 2) advanced \
1222 * the destination pointer of 2 bytes. \
1223 */ \
1224 __ptr -= 2; \
1225 __len += 2; \
1226 SMC_SET_PTR(lp, \
1227 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1228 } \
1229 if (SMC_CAN_USE_DATACS && lp->datacs) \
1230 __ioaddr = lp->datacs; \
1231 __len += 2; \
1232 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1233 } else if (SMC_16BIT(lp)) \
1234 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1235 else if (SMC_8BIT(lp)) \
1236 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1237 } while (0)
1238
1239 #endif /* _SMC91X_H_ */
Tomato firmware and modifications.