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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / sc92031.c
blobf96d824e9226599d1c1727814385ceb5f8d8e3d0
1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
2 *
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
14 *
15 * Rewritten for 2.6 by Cesar Eduardo Barros
16 *
17 * A datasheet for this chip can be found at
18 * http://www.silan.com.cn/english/products/pdf/SC92031AY.pdf
19 */
20
21 /* Note about set_mac_address: I don't know how to change the hardware
22 * matching, so you need to enable IFF_PROMISC when using it.
23 */
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34
35 #include <asm/irq.h>
36
37 #define SC92031_NAME "sc92031"
38
39 /* BAR 0 is MMIO, BAR 1 is PIO */
40 #ifndef SC92031_USE_BAR
41 #define SC92031_USE_BAR 0
42 #endif
43
44 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
45 static int multicast_filter_limit = 64;
46 module_param(multicast_filter_limit, int, 0);
47 MODULE_PARM_DESC(multicast_filter_limit,
48 "Maximum number of filtered multicast addresses");
49
50 static int media;
51 module_param(media, int, 0);
52 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
53 " 0x01 = 10M half, 0x02 = 10M full,"
54 " 0x04 = 100M half, 0x08 = 100M full)");
55
56 /* Size of the in-memory receive ring. */
57 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
58 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
59
60 /* Number of Tx descriptor registers. */
61 #define NUM_TX_DESC 4
62
63 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
64 #define MAX_ETH_FRAME_SIZE 1536
65
66 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
67 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
68 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
69
70 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
71 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
72
73 /* Time in jiffies before concluding the transmitter is hung. */
74 #define TX_TIMEOUT (4*HZ)
75
76 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
77
78 /* media options */
79 #define AUTOSELECT 0x00
80 #define M10_HALF 0x01
81 #define M10_FULL 0x02
82 #define M100_HALF 0x04
83 #define M100_FULL 0x08
84
85 /* Symbolic offsets to registers. */
86 enum silan_registers {
87 Config0 = 0x00, // Config0
88 Config1 = 0x04, // Config1
89 RxBufWPtr = 0x08, // Rx buffer writer poiter
90 IntrStatus = 0x0C, // Interrupt status
91 IntrMask = 0x10, // Interrupt mask
92 RxbufAddr = 0x14, // Rx buffer start address
93 RxBufRPtr = 0x18, // Rx buffer read pointer
94 Txstatusall = 0x1C, // Transmit status of all descriptors
95 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
96 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
97 RxConfig = 0x40, // Rx configuration
98 MAC0 = 0x44, // Ethernet hardware address.
99 MAR0 = 0x4C, // Multicast filter.
100 RxStatus0 = 0x54, // Rx status
101 TxConfig = 0x5C, // Tx configuration
102 PhyCtrl = 0x60, // physical control
103 FlowCtrlConfig = 0x64, // flow control
104 Miicmd0 = 0x68, // Mii command0 register
105 Miicmd1 = 0x6C, // Mii command1 register
106 Miistatus = 0x70, // Mii status register
107 Timercnt = 0x74, // Timer counter register
108 TimerIntr = 0x78, // Timer interrupt register
109 PMConfig = 0x7C, // Power Manager configuration
110 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
111 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
112 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
113 TestD0 = 0xD0,
114 TestD4 = 0xD4,
115 TestD8 = 0xD8,
116 };
117
118 #define MII_BMCR 0 // Basic mode control register
119 #define MII_BMSR 1 // Basic mode status register
120 #define MII_JAB 16
121 #define MII_OutputStatus 24
122
123 #define BMCR_FULLDPLX 0x0100 // Full duplex
124 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
125 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
126 #define BMCR_SPEED100 0x2000 // Select 100Mbps
127 #define BMSR_LSTATUS 0x0004 // Link status
128 #define PHY_16_JAB_ENB 0x1000
129 #define PHY_16_PORT_ENB 0x1
130
131 enum IntrStatusBits {
132 LinkFail = 0x80000000,
133 LinkOK = 0x40000000,
134 TimeOut = 0x20000000,
135 RxOverflow = 0x0040,
136 RxOK = 0x0020,
137 TxOK = 0x0001,
138 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
139 };
140
141 enum TxStatusBits {
142 TxCarrierLost = 0x20000000,
143 TxAborted = 0x10000000,
144 TxOutOfWindow = 0x08000000,
145 TxNccShift = 22,
146 EarlyTxThresShift = 16,
147 TxStatOK = 0x8000,
148 TxUnderrun = 0x4000,
149 TxOwn = 0x2000,
150 };
151
152 enum RxStatusBits {
153 RxStatesOK = 0x80000,
154 RxBadAlign = 0x40000,
155 RxHugeFrame = 0x20000,
156 RxSmallFrame = 0x10000,
157 RxCRCOK = 0x8000,
158 RxCrlFrame = 0x4000,
159 Rx_Broadcast = 0x2000,
160 Rx_Multicast = 0x1000,
161 RxAddrMatch = 0x0800,
162 MiiErr = 0x0400,
163 };
164
165 enum RxConfigBits {
166 RxFullDx = 0x80000000,
167 RxEnb = 0x40000000,
168 RxSmall = 0x20000000,
169 RxHuge = 0x10000000,
170 RxErr = 0x08000000,
171 RxAllphys = 0x04000000,
172 RxMulticast = 0x02000000,
173 RxBroadcast = 0x01000000,
174 RxLoopBack = (1 << 23) | (1 << 22),
175 LowThresholdShift = 12,
176 HighThresholdShift = 2,
177 };
178
179 enum TxConfigBits {
180 TxFullDx = 0x80000000,
181 TxEnb = 0x40000000,
182 TxEnbPad = 0x20000000,
183 TxEnbHuge = 0x10000000,
184 TxEnbFCS = 0x08000000,
185 TxNoBackOff = 0x04000000,
186 TxEnbPrem = 0x02000000,
187 TxCareLostCrs = 0x1000000,
188 TxExdCollNum = 0xf00000,
189 TxDataRate = 0x80000,
190 };
191
192 enum PhyCtrlconfigbits {
193 PhyCtrlAne = 0x80000000,
194 PhyCtrlSpd100 = 0x40000000,
195 PhyCtrlSpd10 = 0x20000000,
196 PhyCtrlPhyBaseAddr = 0x1f000000,
197 PhyCtrlDux = 0x800000,
198 PhyCtrlReset = 0x400000,
199 };
200
201 enum FlowCtrlConfigBits {
202 FlowCtrlFullDX = 0x80000000,
203 FlowCtrlEnb = 0x40000000,
204 };
205
206 enum Config0Bits {
207 Cfg0_Reset = 0x80000000,
208 Cfg0_Anaoff = 0x40000000,
209 Cfg0_LDPS = 0x20000000,
210 };
211
212 enum Config1Bits {
213 Cfg1_EarlyRx = 1 << 31,
214 Cfg1_EarlyTx = 1 << 30,
215
216 //rx buffer size
217 Cfg1_Rcv8K = 0x0,
218 Cfg1_Rcv16K = 0x1,
219 Cfg1_Rcv32K = 0x3,
220 Cfg1_Rcv64K = 0x7,
221 Cfg1_Rcv128K = 0xf,
222 };
223
224 enum MiiCmd0Bits {
225 Mii_Divider = 0x20000000,
226 Mii_WRITE = 0x400000,
227 Mii_READ = 0x200000,
228 Mii_SCAN = 0x100000,
229 Mii_Tamod = 0x80000,
230 Mii_Drvmod = 0x40000,
231 Mii_mdc = 0x20000,
232 Mii_mdoen = 0x10000,
233 Mii_mdo = 0x8000,
234 Mii_mdi = 0x4000,
235 };
236
237 enum MiiStatusBits {
238 Mii_StatusBusy = 0x80000000,
239 };
240
241 enum PMConfigBits {
242 PM_Enable = 1 << 31,
243 PM_LongWF = 1 << 30,
244 PM_Magic = 1 << 29,
245 PM_LANWake = 1 << 28,
246 PM_LWPTN = (1 << 27 | 1<< 26),
247 PM_LinkUp = 1 << 25,
248 PM_WakeUp = 1 << 24,
249 };
250
251 /* Locking rules:
252 * priv->lock protects most of the fields of priv and most of the
253 * hardware registers. It does not have to protect against softirqs
254 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
255 * it also does not need to be used in ->open and ->stop while the
256 * device interrupts are off.
257 * Not having to protect against softirqs is very useful due to heavy
258 * use of mdelay() at _sc92031_reset.
259 * Functions prefixed with _sc92031_ must be called with the lock held;
260 * functions prefixed with sc92031_ must be called without the lock held.
261 * Use mmiowb() before unlocking if the hardware was written to.
262 */
263
264 /* Locking rules for the interrupt:
265 * - the interrupt and the tasklet never run at the same time
266 * - neither run between sc92031_disable_interrupts and
267 * sc92031_enable_interrupt
268 */
269
270 struct sc92031_priv {
271 spinlock_t lock;
272 /* iomap.h cookie */
273 void __iomem *port_base;
274 /* pci device structure */
275 struct pci_dev *pdev;
276 /* tasklet */
277 struct tasklet_struct tasklet;
278
279 /* CPU address of rx ring */
280 void *rx_ring;
281 /* PCI address of rx ring */
282 dma_addr_t rx_ring_dma_addr;
283 /* PCI address of rx ring read pointer */
284 dma_addr_t rx_ring_tail;
285
286 /* tx ring write index */
287 unsigned tx_head;
288 /* tx ring read index */
289 unsigned tx_tail;
290 /* CPU address of tx bounce buffer */
291 void *tx_bufs;
292 /* PCI address of tx bounce buffer */
293 dma_addr_t tx_bufs_dma_addr;
294
295 /* copies of some hardware registers */
296 u32 intr_status;
297 atomic_t intr_mask;
298 u32 rx_config;
299 u32 tx_config;
300 u32 pm_config;
301
302 /* copy of some flags from dev->flags */
303 unsigned int mc_flags;
304
305 /* for ETHTOOL_GSTATS */
306 u64 tx_timeouts;
307 u64 rx_loss;
308
309 /* for dev->get_stats */
310 long rx_value;
311 };
312
313 /* I don't know which registers can be safely read; however, I can guess
314 * MAC0 is one of them. */
315 static inline void _sc92031_dummy_read(void __iomem *port_base)
316 {
317 ioread32(port_base + MAC0);
318 }
319
320 static u32 _sc92031_mii_wait(void __iomem *port_base)
321 {
322 u32 mii_status;
323
324 do {
325 udelay(10);
326 mii_status = ioread32(port_base + Miistatus);
327 } while (mii_status & Mii_StatusBusy);
328
329 return mii_status;
330 }
331
332 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
333 {
334 iowrite32(Mii_Divider, port_base + Miicmd0);
335
336 _sc92031_mii_wait(port_base);
337
338 iowrite32(cmd1, port_base + Miicmd1);
339 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
340
341 return _sc92031_mii_wait(port_base);
342 }
343
344 static void _sc92031_mii_scan(void __iomem *port_base)
345 {
346 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
347 }
348
349 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
350 {
351 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
352 }
353
354 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
355 {
356 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
357 }
358
359 static void sc92031_disable_interrupts(struct net_device *dev)
360 {
361 struct sc92031_priv *priv = netdev_priv(dev);
362 void __iomem *port_base = priv->port_base;
363
364 /* tell the tasklet/interrupt not to enable interrupts */
365 atomic_set(&priv->intr_mask, 0);
366 wmb();
367
368 /* stop interrupts */
369 iowrite32(0, port_base + IntrMask);
370 _sc92031_dummy_read(port_base);
371 mmiowb();
372
373 /* wait for any concurrent interrupt/tasklet to finish */
374 synchronize_irq(dev->irq);
375 tasklet_disable(&priv->tasklet);
376 }
377
378 static void sc92031_enable_interrupts(struct net_device *dev)
379 {
380 struct sc92031_priv *priv = netdev_priv(dev);
381 void __iomem *port_base = priv->port_base;
382
383 tasklet_enable(&priv->tasklet);
384
385 atomic_set(&priv->intr_mask, IntrBits);
386 wmb();
387
388 iowrite32(IntrBits, port_base + IntrMask);
389 mmiowb();
390 }
391
392 static void _sc92031_disable_tx_rx(struct net_device *dev)
393 {
394 struct sc92031_priv *priv = netdev_priv(dev);
395 void __iomem *port_base = priv->port_base;
396
397 priv->rx_config &= ~RxEnb;
398 priv->tx_config &= ~TxEnb;
399 iowrite32(priv->rx_config, port_base + RxConfig);
400 iowrite32(priv->tx_config, port_base + TxConfig);
401 }
402
403 static void _sc92031_enable_tx_rx(struct net_device *dev)
404 {
405 struct sc92031_priv *priv = netdev_priv(dev);
406 void __iomem *port_base = priv->port_base;
407
408 priv->rx_config |= RxEnb;
409 priv->tx_config |= TxEnb;
410 iowrite32(priv->rx_config, port_base + RxConfig);
411 iowrite32(priv->tx_config, port_base + TxConfig);
412 }
413
414 static void _sc92031_tx_clear(struct net_device *dev)
415 {
416 struct sc92031_priv *priv = netdev_priv(dev);
417
418 while (priv->tx_head - priv->tx_tail > 0) {
419 priv->tx_tail++;
420 dev->stats.tx_dropped++;
421 }
422 priv->tx_head = priv->tx_tail = 0;
423 }
424
425 static void _sc92031_set_mar(struct net_device *dev)
426 {
427 struct sc92031_priv *priv = netdev_priv(dev);
428 void __iomem *port_base = priv->port_base;
429 u32 mar0 = 0, mar1 = 0;
430
431 if ((dev->flags & IFF_PROMISC) ||
432 netdev_mc_count(dev) > multicast_filter_limit ||
433 (dev->flags & IFF_ALLMULTI))
434 mar0 = mar1 = 0xffffffff;
435 else if (dev->flags & IFF_MULTICAST) {
436 struct netdev_hw_addr *ha;
437
438 netdev_for_each_mc_addr(ha, dev) {
439 u32 crc;
440 unsigned bit = 0;
441
442 crc = ~ether_crc(ETH_ALEN, ha->addr);
443 crc >>= 24;
444
445 if (crc & 0x01) bit |= 0x02;
446 if (crc & 0x02) bit |= 0x01;
447 if (crc & 0x10) bit |= 0x20;
448 if (crc & 0x20) bit |= 0x10;
449 if (crc & 0x40) bit |= 0x08;
450 if (crc & 0x80) bit |= 0x04;
451
452 if (bit > 31)
453 mar0 |= 0x1 << (bit - 32);
454 else
455 mar1 |= 0x1 << bit;
456 }
457 }
458
459 iowrite32(mar0, port_base + MAR0);
460 iowrite32(mar1, port_base + MAR0 + 4);
461 }
462
463 static void _sc92031_set_rx_config(struct net_device *dev)
464 {
465 struct sc92031_priv *priv = netdev_priv(dev);
466 void __iomem *port_base = priv->port_base;
467 unsigned int old_mc_flags;
468 u32 rx_config_bits = 0;
469
470 old_mc_flags = priv->mc_flags;
471
472 if (dev->flags & IFF_PROMISC)
473 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
474 | RxMulticast | RxAllphys;
475
476 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
477 rx_config_bits |= RxMulticast;
478
479 if (dev->flags & IFF_BROADCAST)
480 rx_config_bits |= RxBroadcast;
481
482 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
483 | RxMulticast | RxAllphys);
484 priv->rx_config |= rx_config_bits;
485
486 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
487 | IFF_MULTICAST | IFF_BROADCAST);
488
489 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
490 iowrite32(priv->rx_config, port_base + RxConfig);
491 }
492
493 static bool _sc92031_check_media(struct net_device *dev)
494 {
495 struct sc92031_priv *priv = netdev_priv(dev);
496 void __iomem *port_base = priv->port_base;
497 u16 bmsr;
498
499 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
500 rmb();
501 if (bmsr & BMSR_LSTATUS) {
502 bool speed_100, duplex_full;
503 u32 flow_ctrl_config = 0;
504 u16 output_status = _sc92031_mii_read(port_base,
505 MII_OutputStatus);
506 _sc92031_mii_scan(port_base);
507
508 speed_100 = output_status & 0x2;
509 duplex_full = output_status & 0x4;
510
511 /* Initial Tx/Rx configuration */
512 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
513 priv->tx_config = 0x48800000;
514
515 /* NOTE: vendor driver had dead code here to enable tx padding */
516
517 if (!speed_100)
518 priv->tx_config |= 0x80000;
519
520 // configure rx mode
521 _sc92031_set_rx_config(dev);
522
523 if (duplex_full) {
524 priv->rx_config |= RxFullDx;
525 priv->tx_config |= TxFullDx;
526 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
527 } else {
528 priv->rx_config &= ~RxFullDx;
529 priv->tx_config &= ~TxFullDx;
530 }
531
532 _sc92031_set_mar(dev);
533 _sc92031_set_rx_config(dev);
534 _sc92031_enable_tx_rx(dev);
535 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
536
537 netif_carrier_on(dev);
538
539 if (printk_ratelimit())
540 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
541 dev->name,
542 speed_100 ? "100" : "10",
543 duplex_full ? "full" : "half");
544 return true;
545 } else {
546 _sc92031_mii_scan(port_base);
547
548 netif_carrier_off(dev);
549
550 _sc92031_disable_tx_rx(dev);
551
552 if (printk_ratelimit())
553 printk(KERN_INFO "%s: link down\n", dev->name);
554 return false;
555 }
556 }
557
558 static void _sc92031_phy_reset(struct net_device *dev)
559 {
560 struct sc92031_priv *priv = netdev_priv(dev);
561 void __iomem *port_base = priv->port_base;
562 u32 phy_ctrl;
563
564 phy_ctrl = ioread32(port_base + PhyCtrl);
565 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
566 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
567
568 switch (media) {
569 default:
570 case AUTOSELECT:
571 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
572 break;
573 case M10_HALF:
574 phy_ctrl |= PhyCtrlSpd10;
575 break;
576 case M10_FULL:
577 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
578 break;
579 case M100_HALF:
580 phy_ctrl |= PhyCtrlSpd100;
581 break;
582 case M100_FULL:
583 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
584 break;
585 }
586
587 iowrite32(phy_ctrl, port_base + PhyCtrl);
588 mdelay(10);
589
590 phy_ctrl &= ~PhyCtrlReset;
591 iowrite32(phy_ctrl, port_base + PhyCtrl);
592 mdelay(1);
593
594 _sc92031_mii_write(port_base, MII_JAB,
595 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
596 _sc92031_mii_scan(port_base);
597
598 netif_carrier_off(dev);
599 netif_stop_queue(dev);
600 }
601
602 static void _sc92031_reset(struct net_device *dev)
603 {
604 struct sc92031_priv *priv = netdev_priv(dev);
605 void __iomem *port_base = priv->port_base;
606
607 /* disable PM */
608 iowrite32(0, port_base + PMConfig);
609
610 /* soft reset the chip */
611 iowrite32(Cfg0_Reset, port_base + Config0);
612 mdelay(200);
613
614 iowrite32(0, port_base + Config0);
615 mdelay(10);
616
617 /* disable interrupts */
618 iowrite32(0, port_base + IntrMask);
619
620 /* clear multicast address */
621 iowrite32(0, port_base + MAR0);
622 iowrite32(0, port_base + MAR0 + 4);
623
624 /* init rx ring */
625 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
626 priv->rx_ring_tail = priv->rx_ring_dma_addr;
627
628 /* init tx ring */
629 _sc92031_tx_clear(dev);
630
631 /* clear old register values */
632 priv->intr_status = 0;
633 atomic_set(&priv->intr_mask, 0);
634 priv->rx_config = 0;
635 priv->tx_config = 0;
636 priv->mc_flags = 0;
637
638 /* configure rx buffer size */
639 /* NOTE: vendor driver had dead code here to enable early tx/rx */
640 iowrite32(Cfg1_Rcv64K, port_base + Config1);
641
642 _sc92031_phy_reset(dev);
643 _sc92031_check_media(dev);
644
645 /* calculate rx fifo overflow */
646 priv->rx_value = 0;
647
648 /* enable PM */
649 iowrite32(priv->pm_config, port_base + PMConfig);
650
651 /* clear intr register */
652 ioread32(port_base + IntrStatus);
653 }
654
655 static void _sc92031_tx_tasklet(struct net_device *dev)
656 {
657 struct sc92031_priv *priv = netdev_priv(dev);
658 void __iomem *port_base = priv->port_base;
659
660 unsigned old_tx_tail;
661 unsigned entry;
662 u32 tx_status;
663
664 old_tx_tail = priv->tx_tail;
665 while (priv->tx_head - priv->tx_tail > 0) {
666 entry = priv->tx_tail % NUM_TX_DESC;
667 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
668
669 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
670 break;
671
672 priv->tx_tail++;
673
674 if (tx_status & TxStatOK) {
675 dev->stats.tx_bytes += tx_status & 0x1fff;
676 dev->stats.tx_packets++;
677 /* Note: TxCarrierLost is always asserted at 100mbps. */
678 dev->stats.collisions += (tx_status >> 22) & 0xf;
679 }
680
681 if (tx_status & (TxOutOfWindow | TxAborted)) {
682 dev->stats.tx_errors++;
683
684 if (tx_status & TxAborted)
685 dev->stats.tx_aborted_errors++;
686
687 if (tx_status & TxCarrierLost)
688 dev->stats.tx_carrier_errors++;
689
690 if (tx_status & TxOutOfWindow)
691 dev->stats.tx_window_errors++;
692 }
693
694 if (tx_status & TxUnderrun)
695 dev->stats.tx_fifo_errors++;
696 }
697
698 if (priv->tx_tail != old_tx_tail)
699 if (netif_queue_stopped(dev))
700 netif_wake_queue(dev);
701 }
702
703 static void _sc92031_rx_tasklet_error(struct net_device *dev,
704 u32 rx_status, unsigned rx_size)
705 {
706 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
707 dev->stats.rx_errors++;
708 dev->stats.rx_length_errors++;
709 }
710
711 if (!(rx_status & RxStatesOK)) {
712 dev->stats.rx_errors++;
713
714 if (rx_status & (RxHugeFrame | RxSmallFrame))
715 dev->stats.rx_length_errors++;
716
717 if (rx_status & RxBadAlign)
718 dev->stats.rx_frame_errors++;
719
720 if (!(rx_status & RxCRCOK))
721 dev->stats.rx_crc_errors++;
722 } else {
723 struct sc92031_priv *priv = netdev_priv(dev);
724 priv->rx_loss++;
725 }
726 }
727
728 static void _sc92031_rx_tasklet(struct net_device *dev)
729 {
730 struct sc92031_priv *priv = netdev_priv(dev);
731 void __iomem *port_base = priv->port_base;
732
733 dma_addr_t rx_ring_head;
734 unsigned rx_len;
735 unsigned rx_ring_offset;
736 void *rx_ring = priv->rx_ring;
737
738 rx_ring_head = ioread32(port_base + RxBufWPtr);
739 rmb();
740
741 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
742 * we need to change it to 32 bits physical address
743 */
744 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
745 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
746 if (rx_ring_head < priv->rx_ring_dma_addr)
747 rx_ring_head += RX_BUF_LEN;
748
749 if (rx_ring_head >= priv->rx_ring_tail)
750 rx_len = rx_ring_head - priv->rx_ring_tail;
751 else
752 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
753
754 if (!rx_len)
755 return;
756
757 if (unlikely(rx_len > RX_BUF_LEN)) {
758 if (printk_ratelimit())
759 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
760 dev->name);
761 return;
762 }
763
764 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
765
766 while (rx_len) {
767 u32 rx_status;
768 unsigned rx_size, rx_size_align, pkt_size;
769 struct sk_buff *skb;
770
771 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
772 rmb();
773
774 rx_size = rx_status >> 20;
775 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
776 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
777
778 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
779
780 if (unlikely(rx_status == 0 ||
781 rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
782 rx_size < 16 ||
783 !(rx_status & RxStatesOK))) {
784 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
785 break;
786 }
787
788 if (unlikely(rx_size_align + 4 > rx_len)) {
789 if (printk_ratelimit())
790 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
791 break;
792 }
793
794 rx_len -= rx_size_align + 4;
795
796 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
797 if (unlikely(!skb)) {
798 if (printk_ratelimit())
799 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
800 dev->name, pkt_size);
801 goto next;
802 }
803
804 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
805 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
806 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
807 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
808 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
809 } else {
810 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
811 }
812
813 skb->protocol = eth_type_trans(skb, dev);
814 netif_rx(skb);
815
816 dev->stats.rx_bytes += pkt_size;
817 dev->stats.rx_packets++;
818
819 if (rx_status & Rx_Multicast)
820 dev->stats.multicast++;
821
822 next:
823 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
824 }
825 mb();
826
827 priv->rx_ring_tail = rx_ring_head;
828 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
829 }
830
831 static void _sc92031_link_tasklet(struct net_device *dev)
832 {
833 if (_sc92031_check_media(dev))
834 netif_wake_queue(dev);
835 else {
836 netif_stop_queue(dev);
837 dev->stats.tx_carrier_errors++;
838 }
839 }
840
841 static void sc92031_tasklet(unsigned long data)
842 {
843 struct net_device *dev = (struct net_device *)data;
844 struct sc92031_priv *priv = netdev_priv(dev);
845 void __iomem *port_base = priv->port_base;
846 u32 intr_status, intr_mask;
847
848 intr_status = priv->intr_status;
849
850 spin_lock(&priv->lock);
851
852 if (unlikely(!netif_running(dev)))
853 goto out;
854
855 if (intr_status & TxOK)
856 _sc92031_tx_tasklet(dev);
857
858 if (intr_status & RxOK)
859 _sc92031_rx_tasklet(dev);
860
861 if (intr_status & RxOverflow)
862 dev->stats.rx_errors++;
863
864 if (intr_status & TimeOut) {
865 dev->stats.rx_errors++;
866 dev->stats.rx_length_errors++;
867 }
868
869 if (intr_status & (LinkFail | LinkOK))
870 _sc92031_link_tasklet(dev);
871
872 out:
873 intr_mask = atomic_read(&priv->intr_mask);
874 rmb();
875
876 iowrite32(intr_mask, port_base + IntrMask);
877 mmiowb();
878
879 spin_unlock(&priv->lock);
880 }
881
882 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
883 {
884 struct net_device *dev = dev_id;
885 struct sc92031_priv *priv = netdev_priv(dev);
886 void __iomem *port_base = priv->port_base;
887 u32 intr_status, intr_mask;
888
889 /* mask interrupts before clearing IntrStatus */
890 iowrite32(0, port_base + IntrMask);
891 _sc92031_dummy_read(port_base);
892
893 intr_status = ioread32(port_base + IntrStatus);
894 if (unlikely(intr_status == 0xffffffff))
895 return IRQ_NONE; // hardware has gone missing
896
897 intr_status &= IntrBits;
898 if (!intr_status)
899 goto out_none;
900
901 priv->intr_status = intr_status;
902 tasklet_schedule(&priv->tasklet);
903
904 return IRQ_HANDLED;
905
906 out_none:
907 intr_mask = atomic_read(&priv->intr_mask);
908 rmb();
909
910 iowrite32(intr_mask, port_base + IntrMask);
911 mmiowb();
912
913 return IRQ_NONE;
914 }
915
916 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
917 {
918 struct sc92031_priv *priv = netdev_priv(dev);
919 void __iomem *port_base = priv->port_base;
920
921 if (netif_running(dev)) {
922 int temp;
923
924 spin_lock_bh(&priv->lock);
925
926 /* Update the error count. */
927 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
928
929 if (temp == 0xffff) {
930 priv->rx_value += temp;
931 dev->stats.rx_fifo_errors = priv->rx_value;
932 } else
933 dev->stats.rx_fifo_errors = temp + priv->rx_value;
934
935 spin_unlock_bh(&priv->lock);
936 }
937
938 return &dev->stats;
939 }
940
941 static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
942 struct net_device *dev)
943 {
944 struct sc92031_priv *priv = netdev_priv(dev);
945 void __iomem *port_base = priv->port_base;
946 unsigned len;
947 unsigned entry;
948 u32 tx_status;
949
950 if (unlikely(skb->len > TX_BUF_SIZE)) {
951 dev->stats.tx_dropped++;
952 goto out;
953 }
954
955 spin_lock(&priv->lock);
956
957 if (unlikely(!netif_carrier_ok(dev))) {
958 dev->stats.tx_dropped++;
959 goto out_unlock;
960 }
961
962 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
963
964 entry = priv->tx_head++ % NUM_TX_DESC;
965
966 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
967
968 len = skb->len;
969 if (len < ETH_ZLEN) {
970 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
971 0, ETH_ZLEN - len);
972 len = ETH_ZLEN;
973 }
974
975 wmb();
976
977 if (len < 100)
978 tx_status = len;
979 else if (len < 300)
980 tx_status = 0x30000 | len;
981 else
982 tx_status = 0x50000 | len;
983
984 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
985 port_base + TxAddr0 + entry * 4);
986 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
987 mmiowb();
988
989 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
990 netif_stop_queue(dev);
991
992 out_unlock:
993 spin_unlock(&priv->lock);
994
995 out:
996 dev_kfree_skb(skb);
997
998 return NETDEV_TX_OK;
999 }
1000
1001 static int sc92031_open(struct net_device *dev)
1002 {
1003 int err;
1004 struct sc92031_priv *priv = netdev_priv(dev);
1005 struct pci_dev *pdev = priv->pdev;
1006
1007 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1008 &priv->rx_ring_dma_addr);
1009 if (unlikely(!priv->rx_ring)) {
1010 err = -ENOMEM;
1011 goto out_alloc_rx_ring;
1012 }
1013
1014 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1015 &priv->tx_bufs_dma_addr);
1016 if (unlikely(!priv->tx_bufs)) {
1017 err = -ENOMEM;
1018 goto out_alloc_tx_bufs;
1019 }
1020 priv->tx_head = priv->tx_tail = 0;
1021
1022 err = request_irq(pdev->irq, sc92031_interrupt,
1023 IRQF_SHARED, dev->name, dev);
1024 if (unlikely(err < 0))
1025 goto out_request_irq;
1026
1027 priv->pm_config = 0;
1028
1029 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1030 spin_lock_bh(&priv->lock);
1031
1032 _sc92031_reset(dev);
1033 mmiowb();
1034
1035 spin_unlock_bh(&priv->lock);
1036 sc92031_enable_interrupts(dev);
1037
1038 if (netif_carrier_ok(dev))
1039 netif_start_queue(dev);
1040 else
1041 netif_tx_disable(dev);
1042
1043 return 0;
1044
1045 out_request_irq:
1046 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1047 priv->tx_bufs_dma_addr);
1048 out_alloc_tx_bufs:
1049 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1050 priv->rx_ring_dma_addr);
1051 out_alloc_rx_ring:
1052 return err;
1053 }
1054
1055 static int sc92031_stop(struct net_device *dev)
1056 {
1057 struct sc92031_priv *priv = netdev_priv(dev);
1058 struct pci_dev *pdev = priv->pdev;
1059
1060 netif_tx_disable(dev);
1061
1062 /* Disable interrupts, stop Tx and Rx. */
1063 sc92031_disable_interrupts(dev);
1064
1065 spin_lock_bh(&priv->lock);
1066
1067 _sc92031_disable_tx_rx(dev);
1068 _sc92031_tx_clear(dev);
1069 mmiowb();
1070
1071 spin_unlock_bh(&priv->lock);
1072
1073 free_irq(pdev->irq, dev);
1074 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1075 priv->tx_bufs_dma_addr);
1076 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1077 priv->rx_ring_dma_addr);
1078
1079 return 0;
1080 }
1081
1082 static void sc92031_set_multicast_list(struct net_device *dev)
1083 {
1084 struct sc92031_priv *priv = netdev_priv(dev);
1085
1086 spin_lock_bh(&priv->lock);
1087
1088 _sc92031_set_mar(dev);
1089 _sc92031_set_rx_config(dev);
1090 mmiowb();
1091
1092 spin_unlock_bh(&priv->lock);
1093 }
1094
1095 static void sc92031_tx_timeout(struct net_device *dev)
1096 {
1097 struct sc92031_priv *priv = netdev_priv(dev);
1098
1099 /* Disable interrupts by clearing the interrupt mask.*/
1100 sc92031_disable_interrupts(dev);
1101
1102 spin_lock(&priv->lock);
1103
1104 priv->tx_timeouts++;
1105
1106 _sc92031_reset(dev);
1107 mmiowb();
1108
1109 spin_unlock(&priv->lock);
1110
1111 /* enable interrupts */
1112 sc92031_enable_interrupts(dev);
1113
1114 if (netif_carrier_ok(dev))
1115 netif_wake_queue(dev);
1116 }
1117
1118 #ifdef CONFIG_NET_POLL_CONTROLLER
1119 static void sc92031_poll_controller(struct net_device *dev)
1120 {
1121 disable_irq(dev->irq);
1122 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1123 sc92031_tasklet((unsigned long)dev);
1124 enable_irq(dev->irq);
1125 }
1126 #endif
1127
1128 static int sc92031_ethtool_get_settings(struct net_device *dev,
1129 struct ethtool_cmd *cmd)
1130 {
1131 struct sc92031_priv *priv = netdev_priv(dev);
1132 void __iomem *port_base = priv->port_base;
1133 u8 phy_address;
1134 u32 phy_ctrl;
1135 u16 output_status;
1136
1137 spin_lock_bh(&priv->lock);
1138
1139 phy_address = ioread32(port_base + Miicmd1) >> 27;
1140 phy_ctrl = ioread32(port_base + PhyCtrl);
1141
1142 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1143 _sc92031_mii_scan(port_base);
1144 mmiowb();
1145
1146 spin_unlock_bh(&priv->lock);
1147
1148 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1149 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1150 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1151
1152 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1153
1154 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1155 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1156 cmd->advertising |= ADVERTISED_Autoneg;
1157
1158 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1159 cmd->advertising |= ADVERTISED_10baseT_Half;
1160
1161 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1162 == (PhyCtrlSpd10 | PhyCtrlDux))
1163 cmd->advertising |= ADVERTISED_10baseT_Full;
1164
1165 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1166 cmd->advertising |= ADVERTISED_100baseT_Half;
1167
1168 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1169 == (PhyCtrlSpd100 | PhyCtrlDux))
1170 cmd->advertising |= ADVERTISED_100baseT_Full;
1171
1172 if (phy_ctrl & PhyCtrlAne)
1173 cmd->advertising |= ADVERTISED_Autoneg;
1174
1175 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1176 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1177 cmd->port = PORT_MII;
1178 cmd->phy_address = phy_address;
1179 cmd->transceiver = XCVR_INTERNAL;
1180 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1181
1182 return 0;
1183 }
1184
1185 static int sc92031_ethtool_set_settings(struct net_device *dev,
1186 struct ethtool_cmd *cmd)
1187 {
1188 struct sc92031_priv *priv = netdev_priv(dev);
1189 void __iomem *port_base = priv->port_base;
1190 u32 phy_ctrl;
1191 u32 old_phy_ctrl;
1192
1193 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1194 return -EINVAL;
1195 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1196 return -EINVAL;
1197 if (!(cmd->port == PORT_MII))
1198 return -EINVAL;
1199 if (!(cmd->phy_address == 0x1f))
1200 return -EINVAL;
1201 if (!(cmd->transceiver == XCVR_INTERNAL))
1202 return -EINVAL;
1203 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1204 return -EINVAL;
1205
1206 if (cmd->autoneg == AUTONEG_ENABLE) {
1207 if (!(cmd->advertising & (ADVERTISED_Autoneg
1208 | ADVERTISED_100baseT_Full
1209 | ADVERTISED_100baseT_Half
1210 | ADVERTISED_10baseT_Full
1211 | ADVERTISED_10baseT_Half)))
1212 return -EINVAL;
1213
1214 phy_ctrl = PhyCtrlAne;
1215
1216 if (cmd->advertising & ADVERTISED_Autoneg)
1217 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1218 if (cmd->advertising & ADVERTISED_100baseT_Full)
1219 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1220 if (cmd->advertising & ADVERTISED_100baseT_Half)
1221 phy_ctrl |= PhyCtrlSpd100;
1222 if (cmd->advertising & ADVERTISED_10baseT_Full)
1223 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1224 if (cmd->advertising & ADVERTISED_10baseT_Half)
1225 phy_ctrl |= PhyCtrlSpd10;
1226 } else {
1227 phy_ctrl = 0;
1228
1229 if (cmd->speed == SPEED_10)
1230 phy_ctrl |= PhyCtrlSpd10;
1231 else /* cmd->speed == SPEED_100 */
1232 phy_ctrl |= PhyCtrlSpd100;
1233
1234 if (cmd->duplex == DUPLEX_FULL)
1235 phy_ctrl |= PhyCtrlDux;
1236 }
1237
1238 spin_lock_bh(&priv->lock);
1239
1240 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1241 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1242 | PhyCtrlSpd100 | PhyCtrlSpd10);
1243 if (phy_ctrl != old_phy_ctrl)
1244 iowrite32(phy_ctrl, port_base + PhyCtrl);
1245
1246 spin_unlock_bh(&priv->lock);
1247
1248 return 0;
1249 }
1250
1251 static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1252 struct ethtool_drvinfo *drvinfo)
1253 {
1254 struct sc92031_priv *priv = netdev_priv(dev);
1255 struct pci_dev *pdev = priv->pdev;
1256
1257 strcpy(drvinfo->driver, SC92031_NAME);
1258 strcpy(drvinfo->bus_info, pci_name(pdev));
1259 }
1260
1261 static void sc92031_ethtool_get_wol(struct net_device *dev,
1262 struct ethtool_wolinfo *wolinfo)
1263 {
1264 struct sc92031_priv *priv = netdev_priv(dev);
1265 void __iomem *port_base = priv->port_base;
1266 u32 pm_config;
1267
1268 spin_lock_bh(&priv->lock);
1269 pm_config = ioread32(port_base + PMConfig);
1270 spin_unlock_bh(&priv->lock);
1271
1272 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1273 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1274 wolinfo->wolopts = 0;
1275
1276 if (pm_config & PM_LinkUp)
1277 wolinfo->wolopts |= WAKE_PHY;
1278
1279 if (pm_config & PM_Magic)
1280 wolinfo->wolopts |= WAKE_MAGIC;
1281
1282 if (pm_config & PM_WakeUp)
1283 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1284 }
1285
1286 static int sc92031_ethtool_set_wol(struct net_device *dev,
1287 struct ethtool_wolinfo *wolinfo)
1288 {
1289 struct sc92031_priv *priv = netdev_priv(dev);
1290 void __iomem *port_base = priv->port_base;
1291 u32 pm_config;
1292
1293 spin_lock_bh(&priv->lock);
1294
1295 pm_config = ioread32(port_base + PMConfig)
1296 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1297
1298 if (wolinfo->wolopts & WAKE_PHY)
1299 pm_config |= PM_LinkUp;
1300
1301 if (wolinfo->wolopts & WAKE_MAGIC)
1302 pm_config |= PM_Magic;
1303
1304 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1305 pm_config |= PM_WakeUp;
1306
1307 priv->pm_config = pm_config;
1308 iowrite32(pm_config, port_base + PMConfig);
1309 mmiowb();
1310
1311 spin_unlock_bh(&priv->lock);
1312
1313 return 0;
1314 }
1315
1316 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1317 {
1318 int err = 0;
1319 struct sc92031_priv *priv = netdev_priv(dev);
1320 void __iomem *port_base = priv->port_base;
1321 u16 bmcr;
1322
1323 spin_lock_bh(&priv->lock);
1324
1325 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1326 if (!(bmcr & BMCR_ANENABLE)) {
1327 err = -EINVAL;
1328 goto out;
1329 }
1330
1331 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1332
1333 out:
1334 _sc92031_mii_scan(port_base);
1335 mmiowb();
1336
1337 spin_unlock_bh(&priv->lock);
1338
1339 return err;
1340 }
1341
1342 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1343 "tx_timeout",
1344 "rx_loss",
1345 };
1346
1347 static void sc92031_ethtool_get_strings(struct net_device *dev,
1348 u32 stringset, u8 *data)
1349 {
1350 if (stringset == ETH_SS_STATS)
1351 memcpy(data, sc92031_ethtool_stats_strings,
1352 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1353 }
1354
1355 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1356 {
1357 switch (sset) {
1358 case ETH_SS_STATS:
1359 return SILAN_STATS_NUM;
1360 default:
1361 return -EOPNOTSUPP;
1362 }
1363 }
1364
1365 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1366 struct ethtool_stats *stats, u64 *data)
1367 {
1368 struct sc92031_priv *priv = netdev_priv(dev);
1369
1370 spin_lock_bh(&priv->lock);
1371 data[0] = priv->tx_timeouts;
1372 data[1] = priv->rx_loss;
1373 spin_unlock_bh(&priv->lock);
1374 }
1375
1376 static const struct ethtool_ops sc92031_ethtool_ops = {
1377 .get_settings = sc92031_ethtool_get_settings,
1378 .set_settings = sc92031_ethtool_set_settings,
1379 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1380 .get_wol = sc92031_ethtool_get_wol,
1381 .set_wol = sc92031_ethtool_set_wol,
1382 .nway_reset = sc92031_ethtool_nway_reset,
1383 .get_link = ethtool_op_get_link,
1384 .get_strings = sc92031_ethtool_get_strings,
1385 .get_sset_count = sc92031_ethtool_get_sset_count,
1386 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1387 };
1388
1389
1390 static const struct net_device_ops sc92031_netdev_ops = {
1391 .ndo_get_stats = sc92031_get_stats,
1392 .ndo_start_xmit = sc92031_start_xmit,
1393 .ndo_open = sc92031_open,
1394 .ndo_stop = sc92031_stop,
1395 .ndo_set_multicast_list = sc92031_set_multicast_list,
1396 .ndo_change_mtu = eth_change_mtu,
1397 .ndo_validate_addr = eth_validate_addr,
1398 .ndo_set_mac_address = eth_mac_addr,
1399 .ndo_tx_timeout = sc92031_tx_timeout,
1400 #ifdef CONFIG_NET_POLL_CONTROLLER
1401 .ndo_poll_controller = sc92031_poll_controller,
1402 #endif
1403 };
1404
1405 static int __devinit sc92031_probe(struct pci_dev *pdev,
1406 const struct pci_device_id *id)
1407 {
1408 int err;
1409 void __iomem* port_base;
1410 struct net_device *dev;
1411 struct sc92031_priv *priv;
1412 u32 mac0, mac1;
1413 unsigned long base_addr;
1414
1415 err = pci_enable_device(pdev);
1416 if (unlikely(err < 0))
1417 goto out_enable_device;
1418
1419 pci_set_master(pdev);
1420
1421 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1422 if (unlikely(err < 0))
1423 goto out_set_dma_mask;
1424
1425 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1426 if (unlikely(err < 0))
1427 goto out_set_dma_mask;
1428
1429 err = pci_request_regions(pdev, SC92031_NAME);
1430 if (unlikely(err < 0))
1431 goto out_request_regions;
1432
1433 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1434 if (unlikely(!port_base)) {
1435 err = -EIO;
1436 goto out_iomap;
1437 }
1438
1439 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1440 if (unlikely(!dev)) {
1441 err = -ENOMEM;
1442 goto out_alloc_etherdev;
1443 }
1444
1445 pci_set_drvdata(pdev, dev);
1446 SET_NETDEV_DEV(dev, &pdev->dev);
1447
1448 #if SC92031_USE_BAR == 0
1449 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1450 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1451 #elif SC92031_USE_BAR == 1
1452 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1453 #endif
1454 dev->irq = pdev->irq;
1455
1456 /* faked with skb_copy_and_csum_dev */
1457 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1458
1459 dev->netdev_ops = &sc92031_netdev_ops;
1460 dev->watchdog_timeo = TX_TIMEOUT;
1461 dev->ethtool_ops = &sc92031_ethtool_ops;
1462
1463 priv = netdev_priv(dev);
1464 spin_lock_init(&priv->lock);
1465 priv->port_base = port_base;
1466 priv->pdev = pdev;
1467 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1468 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1469 * sc92031_open will work correctly */
1470 tasklet_disable_nosync(&priv->tasklet);
1471
1472 /* PCI PM Wakeup */
1473 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1474
1475 mac0 = ioread32(port_base + MAC0);
1476 mac1 = ioread32(port_base + MAC0 + 4);
1477 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1478 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1479 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1480 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1481 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1482 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1483
1484 err = register_netdev(dev);
1485 if (err < 0)
1486 goto out_register_netdev;
1487
1488 #if SC92031_USE_BAR == 0
1489 base_addr = dev->mem_start;
1490 #elif SC92031_USE_BAR == 1
1491 base_addr = dev->base_addr;
1492 #endif
1493 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1494 base_addr, dev->dev_addr, dev->irq);
1495
1496 return 0;
1497
1498 out_register_netdev:
1499 free_netdev(dev);
1500 out_alloc_etherdev:
1501 pci_iounmap(pdev, port_base);
1502 out_iomap:
1503 pci_release_regions(pdev);
1504 out_request_regions:
1505 out_set_dma_mask:
1506 pci_disable_device(pdev);
1507 out_enable_device:
1508 return err;
1509 }
1510
1511 static void __devexit sc92031_remove(struct pci_dev *pdev)
1512 {
1513 struct net_device *dev = pci_get_drvdata(pdev);
1514 struct sc92031_priv *priv = netdev_priv(dev);
1515 void __iomem* port_base = priv->port_base;
1516
1517 unregister_netdev(dev);
1518 free_netdev(dev);
1519 pci_iounmap(pdev, port_base);
1520 pci_release_regions(pdev);
1521 pci_disable_device(pdev);
1522 }
1523
1524 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1525 {
1526 struct net_device *dev = pci_get_drvdata(pdev);
1527 struct sc92031_priv *priv = netdev_priv(dev);
1528
1529 pci_save_state(pdev);
1530
1531 if (!netif_running(dev))
1532 goto out;
1533
1534 netif_device_detach(dev);
1535
1536 /* Disable interrupts, stop Tx and Rx. */
1537 sc92031_disable_interrupts(dev);
1538
1539 spin_lock_bh(&priv->lock);
1540
1541 _sc92031_disable_tx_rx(dev);
1542 _sc92031_tx_clear(dev);
1543 mmiowb();
1544
1545 spin_unlock_bh(&priv->lock);
1546
1547 out:
1548 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1549
1550 return 0;
1551 }
1552
1553 static int sc92031_resume(struct pci_dev *pdev)
1554 {
1555 struct net_device *dev = pci_get_drvdata(pdev);
1556 struct sc92031_priv *priv = netdev_priv(dev);
1557
1558 pci_restore_state(pdev);
1559 pci_set_power_state(pdev, PCI_D0);
1560
1561 if (!netif_running(dev))
1562 goto out;
1563
1564 /* Interrupts already disabled by sc92031_suspend */
1565 spin_lock_bh(&priv->lock);
1566
1567 _sc92031_reset(dev);
1568 mmiowb();
1569
1570 spin_unlock_bh(&priv->lock);
1571 sc92031_enable_interrupts(dev);
1572
1573 netif_device_attach(dev);
1574
1575 if (netif_carrier_ok(dev))
1576 netif_wake_queue(dev);
1577 else
1578 netif_tx_disable(dev);
1579
1580 out:
1581 return 0;
1582 }
1583
1584 static DEFINE_PCI_DEVICE_TABLE(sc92031_pci_device_id_table) = {
1585 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1586 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1587 { PCI_DEVICE(0x1088, 0x2031) },
1588 { 0, }
1589 };
1590 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1591
1592 static struct pci_driver sc92031_pci_driver = {
1593 .name = SC92031_NAME,
1594 .id_table = sc92031_pci_device_id_table,
1595 .probe = sc92031_probe,
1596 .remove = __devexit_p(sc92031_remove),
1597 .suspend = sc92031_suspend,
1598 .resume = sc92031_resume,
1599 };
1600
1601 static int __init sc92031_init(void)
1602 {
1603 return pci_register_driver(&sc92031_pci_driver);
1604 }
1605
1606 static void __exit sc92031_exit(void)
1607 {
1608 pci_unregister_driver(&sc92031_pci_driver);
1609 }
1610
1611 module_init(sc92031_init);
1612 module_exit(sc92031_exit);
1613
1614 MODULE_LICENSE("GPL");
1615 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1616 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");
Tomato firmware and modifications.