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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / net / pci-skeleton.c
blob56815663ca773d833e4e52ef52ead0b45ff6a89b
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
89
90 #include <linux/module.h>
91 #include <linux/kernel.h>
92 #include <linux/pci.h>
93 #include <linux/init.h>
94 #include <linux/ioport.h>
95 #include <linux/netdevice.h>
96 #include <linux/etherdevice.h>
97 #include <linux/delay.h>
98 #include <linux/ethtool.h>
99 #include <linux/mii.h>
100 #include <linux/crc32.h>
101 #include <linux/io.h>
102
103 #define NETDRV_VERSION "1.0.1"
104 #define MODNAME "netdrv"
105 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
106
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 " Support available from http://foo.com/bar/baz.html\n";
110
111 /* define to 1 to enable PIO instead of MMIO */
112 #undef USE_IO_OPS
113
114 /* define to 1 to enable copious debugging info */
115 #undef NETDRV_DEBUG
116
117 /* define to 1 to disable lightweight runtime debugging checks */
118 #undef NETDRV_NDEBUG
119
120
121 #ifdef NETDRV_DEBUG
122 /* note: prints function name for you */
123 #define DPRINTK(fmt, args...) \
124 printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
125 #else
126 #define DPRINTK(fmt, args...) \
127 do { \
128 if (0) \
129 printk(KERN_DEBUG fmt, ##args); \
130 } while (0)
131 #endif
132
133 #ifdef NETDRV_NDEBUG
134 #define assert(expr) do {} while (0)
135 #else
136 #define assert(expr) \
137 if (!(expr)) { \
138 printk("Assertion failed! %s,%s,%s,line=%d\n", \
139 #expr, __FILE__, __func__, __LINE__); \
140 }
141 #endif
142
143
144 /* A few user-configurable values. */
145 /* media options */
146 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
147
148 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
149 static int max_interrupt_work = 20;
150
151 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
152 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
153 static int multicast_filter_limit = 32;
154
155 /* Size of the in-memory receive ring. */
156 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
157 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
158 #define RX_BUF_PAD 16
159 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
160 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
161
162 /* Number of Tx descriptor registers. */
163 #define NUM_TX_DESC 4
164
165 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
166 #define MAX_ETH_FRAME_SIZE 1536
167
168 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
169 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
170 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
171
172 /* PCI Tuning Parameters
173 Threshold is bytes transferred to chip before transmission starts. */
174 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
175
176 /* The following settings are log_2(bytes)-4:
177 0==16 bytes 1==32 2==64 3==128 4==256 5==512 6==1024 7==end of packet.
178 */
179 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
180 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
181 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
182
183
184 /* Operational parameters that usually are not changed. */
185 /* Time in jiffies before concluding the transmitter is hung. */
186 #define TX_TIMEOUT (6 * HZ)
187
188 enum {
189 HAS_CHIP_XCVR = 0x020000,
190 HAS_LNK_CHNG = 0x040000,
191 };
192
193 #define NETDRV_MIN_IO_SIZE 0x80
194 #define RTL8139B_IO_SIZE 256
195
196 #define NETDRV_CAPS (HAS_CHIP_XCVR | HAS_LNK_CHNG)
197
198 typedef enum {
199 RTL8139 = 0,
200 NETDRV_CB,
201 SMC1211TX,
202 /*MPX5030,*/
203 DELTA8139,
204 ADDTRON8139,
205 } board_t;
206
207
208 /* indexed by board_t, above */
209 static struct {
210 const char *name;
211 } board_info[] __devinitdata = {
212 { "RealTek RTL8139 Fast Ethernet" },
213 { "RealTek RTL8139B PCI/CardBus" },
214 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
215 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
216 { "Delta Electronics 8139 10/100BaseTX" },
217 { "Addtron Technolgy 8139 10/100BaseTX" },
218 };
219
220
221 static DEFINE_PCI_DEVICE_TABLE(netdrv_pci_tbl) = {
222 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
223 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
224 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
225 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
226 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
227 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
228 {0,}
229 };
230 MODULE_DEVICE_TABLE(pci, netdrv_pci_tbl);
231
232
233 /* The rest of these values should never change. */
234
235 /* Symbolic offsets to registers. */
236 enum NETDRV_registers {
237 MAC0 = 0, /* Ethernet hardware address. */
238 MAR0 = 8, /* Multicast filter. */
239 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
240 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
241 RxBuf = 0x30,
242 RxEarlyCnt = 0x34,
243 RxEarlyStatus = 0x36,
244 ChipCmd = 0x37,
245 RxBufPtr = 0x38,
246 RxBufAddr = 0x3A,
247 IntrMask = 0x3C,
248 IntrStatus = 0x3E,
249 TxConfig = 0x40,
250 ChipVersion = 0x43,
251 RxConfig = 0x44,
252 Timer = 0x48, /* A general-purpose counter. */
253 RxMissed = 0x4C, /* 24 bits valid, write clears. */
254 Cfg9346 = 0x50,
255 Config0 = 0x51,
256 Config1 = 0x52,
257 FlashReg = 0x54,
258 MediaStatus = 0x58,
259 Config3 = 0x59,
260 Config4 = 0x5A, /* absent on RTL-8139A */
261 HltClk = 0x5B,
262 MultiIntr = 0x5C,
263 TxSummary = 0x60,
264 BasicModeCtrl = 0x62,
265 BasicModeStatus = 0x64,
266 NWayAdvert = 0x66,
267 NWayLPAR = 0x68,
268 NWayExpansion = 0x6A,
269 /* Undocumented registers, but required for proper operation. */
270 FIFOTMS = 0x70, /* FIFO Control and test. */
271 CSCR = 0x74, /* Chip Status and Configuration Register. */
272 PARA78 = 0x78,
273 PARA7c = 0x7c, /* Magic transceiver parameter register. */
274 Config5 = 0xD8, /* absent on RTL-8139A */
275 };
276
277 enum ClearBitMasks {
278 MultiIntrClear = 0xF000,
279 ChipCmdClear = 0xE2,
280 Config1Clear = (1 << 7) | (1 << 6) | (1 << 3) | (1 << 2) | (1 << 1),
281 };
282
283 enum ChipCmdBits {
284 CmdReset = 0x10,
285 CmdRxEnb = 0x08,
286 CmdTxEnb = 0x04,
287 RxBufEmpty = 0x01,
288 };
289
290 /* Interrupt register bits, using my own meaningful names. */
291 enum IntrStatusBits {
292 PCIErr = 0x8000,
293 PCSTimeout = 0x4000,
294 RxFIFOOver = 0x40,
295 RxUnderrun = 0x20,
296 RxOverflow = 0x10,
297 TxErr = 0x08,
298 TxOK = 0x04,
299 RxErr = 0x02,
300 RxOK = 0x01,
301 };
302 enum TxStatusBits {
303 TxHostOwns = 0x2000,
304 TxUnderrun = 0x4000,
305 TxStatOK = 0x8000,
306 TxOutOfWindow = 0x20000000,
307 TxAborted = 0x40000000,
308 TxCarrierLost = 0x80000000,
309 };
310 enum RxStatusBits {
311 RxMulticast = 0x8000,
312 RxPhysical = 0x4000,
313 RxBroadcast = 0x2000,
314 RxBadSymbol = 0x0020,
315 RxRunt = 0x0010,
316 RxTooLong = 0x0008,
317 RxCRCErr = 0x0004,
318 RxBadAlign = 0x0002,
319 RxStatusOK = 0x0001,
320 };
321
322 /* Bits in RxConfig. */
323 enum rx_mode_bits {
324 AcceptErr = 0x20,
325 AcceptRunt = 0x10,
326 AcceptBroadcast = 0x08,
327 AcceptMulticast = 0x04,
328 AcceptMyPhys = 0x02,
329 AcceptAllPhys = 0x01,
330 };
331
332 /* Bits in TxConfig. */
333 enum tx_config_bits {
334 TxIFG1 = (1 << 25), /* Interframe Gap Time */
335 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
336 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
337 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
338 TxClearAbt = (1 << 0), /* Clear abort (WO) */
339 TxDMAShift = 8, /* DMA burst value(0-7) is shift this many bits */
340
341 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
342 };
343
344 /* Bits in Config1 */
345 enum Config1Bits {
346 Cfg1_PM_Enable = 0x01,
347 Cfg1_VPD_Enable = 0x02,
348 Cfg1_PIO = 0x04,
349 Cfg1_MMIO = 0x08,
350 Cfg1_LWAKE = 0x10,
351 Cfg1_Driver_Load = 0x20,
352 Cfg1_LED0 = 0x40,
353 Cfg1_LED1 = 0x80,
354 };
355
356 enum RxConfigBits {
357 /* Early Rx threshold, none or X/16 */
358 RxCfgEarlyRxNone = 0,
359 RxCfgEarlyRxShift = 24,
360
361 /* rx fifo threshold */
362 RxCfgFIFOShift = 13,
363 RxCfgFIFONone = (7 << RxCfgFIFOShift),
364
365 /* Max DMA burst */
366 RxCfgDMAShift = 8,
367 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
368
369 /* rx ring buffer length */
370 RxCfgRcv8K = 0,
371 RxCfgRcv16K = (1 << 11),
372 RxCfgRcv32K = (1 << 12),
373 RxCfgRcv64K = (1 << 11) | (1 << 12),
374
375 /* Disable packet wrap at end of Rx buffer */
376 RxNoWrap = (1 << 7),
377 };
378
379
380 /* Twister tuning parameters from RealTek.
381 Completely undocumented, but required to tune bad links. */
382 enum CSCRBits {
383 CSCR_LinkOKBit = 0x0400,
384 CSCR_LinkChangeBit = 0x0800,
385 CSCR_LinkStatusBits = 0x0f000,
386 CSCR_LinkDownOffCmd = 0x003c0,
387 CSCR_LinkDownCmd = 0x0f3c0,
388 };
389
390
391 enum Cfg9346Bits {
392 Cfg9346_Lock = 0x00,
393 Cfg9346_Unlock = 0xC0,
394 };
395
396
397 #define PARA78_default 0x78fa8388
398 #define PARA7c_default 0xcb38de43 /* param[0][3] */
399 #define PARA7c_xxx 0xcb38de43
400 static const unsigned long param[4][4] = {
401 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
402 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
403 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
404 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
405 };
406
407 struct ring_info {
408 struct sk_buff *skb;
409 dma_addr_t mapping;
410 };
411
412
413 typedef enum {
414 CH_8139 = 0,
415 CH_8139_K,
416 CH_8139A,
417 CH_8139B,
418 CH_8130,
419 CH_8139C,
420 } chip_t;
421
422
423 /* directly indexed by chip_t, above */
424 static const struct {
425 const char *name;
426 u8 version; /* from RTL8139C docs */
427 u32 RxConfigMask; /* should clear the bits supported by this chip */
428 } rtl_chip_info[] = {
429 { "RTL-8139",
430 0x40,
431 0xf0fe0040,
432 },
433
434 { "RTL-8139 rev K",
435 0x60,
436 0xf0fe0040,
437 },
438
439 { "RTL-8139A",
440 0x70,
441 0xf0fe0040,
442 },
443
444 { "RTL-8139B",
445 0x78,
446 0xf0fc0040
447 },
448
449 { "RTL-8130",
450 0x7C,
451 0xf0fe0040,
452 },
453
454 { "RTL-8139C",
455 0x74,
456 0xf0fc0040,
457 },
458
459 };
460
461
462 struct netdrv_private {
463 board_t board;
464 void *mmio_addr;
465 int drv_flags;
466 struct pci_dev *pci_dev;
467 struct timer_list timer; /* Media selection timer. */
468 unsigned char *rx_ring;
469 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
470 unsigned int tx_flag;
471 atomic_t cur_tx;
472 atomic_t dirty_tx;
473 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
474 struct ring_info tx_info[NUM_TX_DESC];
475 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
476 unsigned char *tx_bufs; /* Tx bounce buffer region. */
477 dma_addr_t rx_ring_dma;
478 dma_addr_t tx_bufs_dma;
479 char phys[4]; /* MII device addresses. */
480 char twistie, twist_row, twist_col; /* Twister tune state. */
481 unsigned int full_duplex:1; /* Full-duplex operation requested. */
482 unsigned int duplex_lock:1;
483 unsigned int default_port:4; /* Last dev->if_port value. */
484 unsigned int media2:4; /* Secondary monitored media port. */
485 unsigned int medialock:1; /* Don't sense media type. */
486 unsigned int mediasense:1; /* Media sensing in progress. */
487 spinlock_t lock;
488 chip_t chipset;
489 };
490
491 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
492 MODULE_DESCRIPTION("Skeleton for a PCI Fast Ethernet driver");
493 MODULE_LICENSE("GPL");
494 module_param(multicast_filter_limit, int, 0);
495 module_param(max_interrupt_work, int, 0);
496 module_param_array(media, int, NULL, 0);
497 MODULE_PARM_DESC(multicast_filter_limit,
498 MODNAME " maximum number of filtered multicast addresses");
499 MODULE_PARM_DESC(max_interrupt_work,
500 MODNAME " maximum events handled per interrupt");
501 MODULE_PARM_DESC(media,
502 MODNAME " Bits 0-3: media type, bit 17: full duplex");
503
504 static int read_eeprom(void *ioaddr, int location, int addr_len);
505 static int netdrv_open(struct net_device *dev);
506 static int mdio_read(struct net_device *dev, int phy_id, int location);
507 static void mdio_write(struct net_device *dev, int phy_id, int location,
508 int val);
509 static void netdrv_timer(unsigned long data);
510 static void netdrv_tx_timeout(struct net_device *dev);
511 static void netdrv_init_ring(struct net_device *dev);
512 static int netdrv_start_xmit(struct sk_buff *skb,
513 struct net_device *dev);
514 static irqreturn_t netdrv_interrupt(int irq, void *dev_instance);
515 static int netdrv_close(struct net_device *dev);
516 static int netdrv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
517 static void netdrv_set_rx_mode(struct net_device *dev);
518 static void netdrv_hw_start(struct net_device *dev);
519
520
521 #ifdef USE_IO_OPS
522
523 #define NETDRV_R8(reg) inb(((unsigned long)ioaddr) + (reg))
524 #define NETDRV_R16(reg) inw(((unsigned long)ioaddr) + (reg))
525 #define NETDRV_R32(reg) ((unsigned long)inl(((unsigned long)ioaddr) + (reg)))
526 #define NETDRV_W8(reg, val8) outb((val8), ((unsigned long)ioaddr) + (reg))
527 #define NETDRV_W16(reg, val16) outw((val16), ((unsigned long)ioaddr) + (reg))
528 #define NETDRV_W32(reg, val32) outl((val32), ((unsigned long)ioaddr) + (reg))
529 #define NETDRV_W8_F NETDRV_W8
530 #define NETDRV_W16_F NETDRV_W16
531 #define NETDRV_W32_F NETDRV_W32
532 #undef readb
533 #undef readw
534 #undef readl
535 #undef writeb
536 #undef writew
537 #undef writel
538 #define readb(addr) inb((unsigned long)(addr))
539 #define readw(addr) inw((unsigned long)(addr))
540 #define readl(addr) inl((unsigned long)(addr))
541 #define writeb(val, addr) outb((val), (unsigned long)(addr))
542 #define writew(val, addr) outw((val), (unsigned long)(addr))
543 #define writel(val, addr) outl((val), (unsigned long)(addr))
544
545 #else
546
547 /* write MMIO register, with flush */
548 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
549 #define NETDRV_W8_F(reg, val8) \
550 do { \
551 writeb((val8), ioaddr + (reg)); \
552 readb(ioaddr + (reg)); \
553 } while (0)
554 #define NETDRV_W16_F(reg, val16) \
555 do { \
556 writew((val16), ioaddr + (reg)); \
557 readw(ioaddr + (reg)); \
558 } while (0)
559 #define NETDRV_W32_F(reg, val32) \
560 do { \
561 writel((val32), ioaddr + (reg)); \
562 readl(ioaddr + (reg)); \
563 } while (0)
564
565
566 #ifdef MMIO_FLUSH_AUDIT_COMPLETE
567
568 /* write MMIO register */
569 #define NETDRV_W8(reg, val8) writeb((val8), ioaddr + (reg))
570 #define NETDRV_W16(reg, val16) writew((val16), ioaddr + (reg))
571 #define NETDRV_W32(reg, val32) writel((val32), ioaddr + (reg))
572
573 #else
574
575 /* write MMIO register, then flush */
576 #define NETDRV_W8 NETDRV_W8_F
577 #define NETDRV_W16 NETDRV_W16_F
578 #define NETDRV_W32 NETDRV_W32_F
579
580 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
581
582 /* read MMIO register */
583 #define NETDRV_R8(reg) readb(ioaddr + (reg))
584 #define NETDRV_R16(reg) readw(ioaddr + (reg))
585 #define NETDRV_R32(reg) ((unsigned long) readl(ioaddr + (reg)))
586
587 #endif /* USE_IO_OPS */
588
589
590 static const u16 netdrv_intr_mask =
591 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
592 TxErr | TxOK | RxErr | RxOK;
593
594 static const unsigned int netdrv_rx_config =
595 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
596 (RX_FIFO_THRESH << RxCfgFIFOShift) |
597 (RX_DMA_BURST << RxCfgDMAShift);
598
599
600 static int __devinit netdrv_init_board(struct pci_dev *pdev,
601 struct net_device **dev_out,
602 void **ioaddr_out)
603 {
604 void *ioaddr = NULL;
605 struct net_device *dev;
606 struct netdrv_private *tp;
607 int rc, i;
608 u32 pio_start, pio_end, pio_flags, pio_len;
609 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
610 u32 tmp;
611
612 DPRINTK("ENTER\n");
613
614 assert(pdev != NULL);
615 assert(ioaddr_out != NULL);
616
617 *ioaddr_out = NULL;
618 *dev_out = NULL;
619
620 /* dev zeroed in alloc_etherdev */
621 dev = alloc_etherdev(sizeof(*tp));
622 if (dev == NULL) {
623 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
624 DPRINTK("EXIT, returning -ENOMEM\n");
625 return -ENOMEM;
626 }
627 SET_NETDEV_DEV(dev, &pdev->dev);
628 tp = netdev_priv(dev);
629
630 /* enable device(incl. PCI PM wakeup), and bus-mastering */
631 rc = pci_enable_device(pdev);
632 if (rc)
633 goto err_out;
634
635 pio_start = pci_resource_start(pdev, 0);
636 pio_end = pci_resource_end(pdev, 0);
637 pio_flags = pci_resource_flags(pdev, 0);
638 pio_len = pci_resource_len(pdev, 0);
639
640 mmio_start = pci_resource_start(pdev, 1);
641 mmio_end = pci_resource_end(pdev, 1);
642 mmio_flags = pci_resource_flags(pdev, 1);
643 mmio_len = pci_resource_len(pdev, 1);
644
645 /* set this immediately, we need to know before
646 * we talk to the chip directly */
647 DPRINTK("PIO region size == %#02X\n", pio_len);
648 DPRINTK("MMIO region size == %#02lX\n", mmio_len);
649
650 /* make sure PCI base addr 0 is PIO */
651 if (!(pio_flags & IORESOURCE_IO)) {
652 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
653 rc = -ENODEV;
654 goto err_out;
655 }
656
657 /* make sure PCI base addr 1 is MMIO */
658 if (!(mmio_flags & IORESOURCE_MEM)) {
659 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
660 rc = -ENODEV;
661 goto err_out;
662 }
663
664 /* check for weird/broken PCI region reporting */
665 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
666 (mmio_len < NETDRV_MIN_IO_SIZE)) {
667 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
668 rc = -ENODEV;
669 goto err_out;
670 }
671
672 rc = pci_request_regions(pdev, MODNAME);
673 if (rc)
674 goto err_out;
675
676 pci_set_master(pdev);
677
678 #ifdef USE_IO_OPS
679 ioaddr = (void *)pio_start;
680 #else
681 /* ioremap MMIO region */
682 ioaddr = ioremap(mmio_start, mmio_len);
683 if (ioaddr == NULL) {
684 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
685 rc = -EIO;
686 goto err_out_free_res;
687 }
688 #endif /* USE_IO_OPS */
689
690 /* Soft reset the chip. */
691 NETDRV_W8(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear) | CmdReset);
692
693 /* Check that the chip has finished the reset. */
694 for (i = 1000; i > 0; i--)
695 if ((NETDRV_R8(ChipCmd) & CmdReset) == 0)
696 break;
697 else
698 udelay(10);
699
700 /* Bring the chip out of low-power mode. */
701 /* <insert device-specific code here> */
702
703 #ifndef USE_IO_OPS
704 /* sanity checks -- ensure PIO and MMIO registers agree */
705 assert(inb(pio_start+Config0) == readb(ioaddr+Config0));
706 assert(inb(pio_start+Config1) == readb(ioaddr+Config1));
707 assert(inb(pio_start+TxConfig) == readb(ioaddr+TxConfig));
708 assert(inb(pio_start+RxConfig) == readb(ioaddr+RxConfig));
709 #endif /* !USE_IO_OPS */
710
711 /* identify chip attached to board */
712 tmp = NETDRV_R8(ChipVersion);
713 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
714 if (tmp == rtl_chip_info[i].version) {
715 tp->chipset = i;
716 goto match;
717 }
718
719 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
720 dev_printk(KERN_DEBUG, &pdev->dev,
721 "unknown chip version, assuming RTL-8139\n");
722 dev_printk(KERN_DEBUG, &pdev->dev, "TxConfig = %#lx\n",
723 NETDRV_R32(TxConfig));
724 tp->chipset = 0;
725
726 match:
727 DPRINTK("chipset id(%d) == index %d, '%s'\n",
728 tmp, tp->chipset, rtl_chip_info[tp->chipset].name);
729
730 rc = register_netdev(dev);
731 if (rc)
732 goto err_out_unmap;
733
734 DPRINTK("EXIT, returning 0\n");
735 *ioaddr_out = ioaddr;
736 *dev_out = dev;
737 return 0;
738
739 err_out_unmap:
740 #ifndef USE_IO_OPS
741 iounmap(ioaddr);
742 err_out_free_res:
743 #endif
744 pci_release_regions(pdev);
745 err_out:
746 free_netdev(dev);
747 DPRINTK("EXIT, returning %d\n", rc);
748 return rc;
749 }
750
751 static const struct net_device_ops netdrv_netdev_ops = {
752 .ndo_open = netdrv_open,
753 .ndo_stop = netdrv_close,
754 .ndo_start_xmit = netdrv_start_xmit,
755 .ndo_set_multicast_list = netdrv_set_rx_mode,
756 .ndo_do_ioctl = netdrv_ioctl,
757 .ndo_tx_timeout = netdrv_tx_timeout,
758 .ndo_change_mtu = eth_change_mtu,
759 .ndo_validate_addr = eth_validate_addr,
760 .ndo_set_mac_address = eth_mac_addr,
761 };
762
763 static int __devinit netdrv_init_one(struct pci_dev *pdev,
764 const struct pci_device_id *ent)
765 {
766 struct net_device *dev = NULL;
767 struct netdrv_private *tp;
768 int i, addr_len, option;
769 void *ioaddr = NULL;
770 static int board_idx = -1;
771
772 /* when built into the kernel, we only print version if device is found */
773 #ifndef MODULE
774 static int printed_version;
775 if (!printed_version++)
776 printk(version);
777 #endif
778
779 DPRINTK("ENTER\n");
780
781 assert(pdev != NULL);
782 assert(ent != NULL);
783
784 board_idx++;
785
786 i = netdrv_init_board(pdev, &dev, &ioaddr);
787 if (i < 0) {
788 DPRINTK("EXIT, returning %d\n", i);
789 return i;
790 }
791
792 tp = netdev_priv(dev);
793
794 assert(ioaddr != NULL);
795 assert(dev != NULL);
796 assert(tp != NULL);
797
798 addr_len = read_eeprom(ioaddr, 0, 8) == 0x8129 ? 8 : 6;
799 for (i = 0; i < 3; i++)
800 ((u16 *)(dev->dev_addr))[i] =
801 le16_to_cpu(read_eeprom(ioaddr, i + 7, addr_len));
802
803 dev->netdev_ops = &netdrv_netdev_ops;
804 dev->watchdog_timeo = TX_TIMEOUT;
805
806 dev->irq = pdev->irq;
807 dev->base_addr = (unsigned long) ioaddr;
808
809 /* netdev_priv()/tp zeroed and aligned in alloc_etherdev */
810 tp = netdev_priv(dev);
811
812 /* note: tp->chipset set in netdrv_init_board */
813 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
814 PCI_COMMAND_MASTER | NETDRV_CAPS;
815 tp->pci_dev = pdev;
816 tp->board = ent->driver_data;
817 tp->mmio_addr = ioaddr;
818 spin_lock_init(&tp->lock);
819
820 pci_set_drvdata(pdev, dev);
821
822 tp->phys[0] = 32;
823
824 netdev_info(dev, "%s at %#lx, %pM IRQ %d\n",
825 board_info[ent->driver_data].name,
826 dev->base_addr, dev->dev_addr, dev->irq);
827
828 netdev_printk(KERN_DEBUG, dev, "Identified 8139 chip type '%s'\n",
829 rtl_chip_info[tp->chipset].name);
830
831 /* Put the chip into low-power mode. */
832 NETDRV_W8_F(Cfg9346, Cfg9346_Unlock);
833
834 /* The lower four bits are the media type. */
835 option = (board_idx > 7) ? 0 : media[board_idx];
836 if (option > 0) {
837 tp->full_duplex = (option & 0x200) ? 1 : 0;
838 tp->default_port = option & 15;
839 if (tp->default_port)
840 tp->medialock = 1;
841 }
842
843 if (tp->full_duplex) {
844 netdev_info(dev, "Media type forced to Full Duplex\n");
845 mdio_write(dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
846 tp->duplex_lock = 1;
847 }
848
849 DPRINTK("EXIT - returning 0\n");
850 return 0;
851 }
852
853
854 static void __devexit netdrv_remove_one(struct pci_dev *pdev)
855 {
856 struct net_device *dev = pci_get_drvdata(pdev);
857 struct netdrv_private *np;
858
859 DPRINTK("ENTER\n");
860
861 assert(dev != NULL);
862
863 np = netdev_priv(dev);
864 assert(np != NULL);
865
866 unregister_netdev(dev);
867
868 #ifndef USE_IO_OPS
869 iounmap(np->mmio_addr);
870 #endif /* !USE_IO_OPS */
871
872 pci_release_regions(pdev);
873
874 free_netdev(dev);
875
876 pci_set_drvdata(pdev, NULL);
877
878 pci_disable_device(pdev);
879
880 DPRINTK("EXIT\n");
881 }
882
883
884 /* Serial EEPROM section. */
885
886 /* EEPROM_Ctrl bits. */
887 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
888 #define EE_CS 0x08 /* EEPROM chip select. */
889 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
890 #define EE_WRITE_0 0x00
891 #define EE_WRITE_1 0x02
892 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
893 #define EE_ENB (0x80 | EE_CS)
894
895 /* Delay between EEPROM clock transitions.
896 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
897 */
898
899 #define eeprom_delay() readl(ee_addr)
900
901 /* The EEPROM commands include the alway-set leading bit. */
902 #define EE_WRITE_CMD (5)
903 #define EE_READ_CMD (6)
904 #define EE_ERASE_CMD (7)
905
906 static int __devinit read_eeprom(void *ioaddr, int location, int addr_len)
907 {
908 int i;
909 unsigned retval = 0;
910 void *ee_addr = ioaddr + Cfg9346;
911 int read_cmd = location | (EE_READ_CMD << addr_len);
912
913 DPRINTK("ENTER\n");
914
915 writeb(EE_ENB & ~EE_CS, ee_addr);
916 writeb(EE_ENB, ee_addr);
917 eeprom_delay();
918
919 /* Shift the read command bits out. */
920 for (i = 4 + addr_len; i >= 0; i--) {
921 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
922 writeb(EE_ENB | dataval, ee_addr);
923 eeprom_delay();
924 writeb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
925 eeprom_delay();
926 }
927 writeb(EE_ENB, ee_addr);
928 eeprom_delay();
929
930 for (i = 16; i > 0; i--) {
931 writeb(EE_ENB | EE_SHIFT_CLK, ee_addr);
932 eeprom_delay();
933 retval =
934 (retval << 1) | ((readb(ee_addr) & EE_DATA_READ) ? 1 :
935 0);
936 writeb(EE_ENB, ee_addr);
937 eeprom_delay();
938 }
939
940 /* Terminate the EEPROM access. */
941 writeb(~EE_CS, ee_addr);
942 eeprom_delay();
943
944 DPRINTK("EXIT - returning %d\n", retval);
945 return retval;
946 }
947
948 /* MII serial management: mostly bogus for now. */
949 /* Read and write the MII management registers using software-generated
950 serial MDIO protocol.
951 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
952 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
953 "overclocking" issues. */
954 #define MDIO_DIR 0x80
955 #define MDIO_DATA_OUT 0x04
956 #define MDIO_DATA_IN 0x02
957 #define MDIO_CLK 0x01
958 #define MDIO_WRITE0 (MDIO_DIR)
959 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
960
961 #define mdio_delay() readb(mdio_addr)
962
963
964 static char mii_2_8139_map[8] = {
965 BasicModeCtrl,
966 BasicModeStatus,
967 0,
968 0,
969 NWayAdvert,
970 NWayLPAR,
971 NWayExpansion,
972 0
973 };
974
975
976 /* Syncronize the MII management interface by shifting 32 one bits out. */
977 static void mdio_sync(void *mdio_addr)
978 {
979 int i;
980
981 DPRINTK("ENTER\n");
982
983 for (i = 32; i >= 0; i--) {
984 writeb(MDIO_WRITE1, mdio_addr);
985 mdio_delay();
986 writeb(MDIO_WRITE1 | MDIO_CLK, mdio_addr);
987 mdio_delay();
988 }
989
990 DPRINTK("EXIT\n");
991 }
992
993
994 static int mdio_read(struct net_device *dev, int phy_id, int location)
995 {
996 struct netdrv_private *tp = netdev_priv(dev);
997 void *mdio_addr = tp->mmio_addr + Config4;
998 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
999 int retval = 0;
1000 int i;
1001
1002 DPRINTK("ENTER\n");
1003
1004 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1005 DPRINTK("EXIT after directly using 8139 internal regs\n");
1006 return location < 8 && mii_2_8139_map[location] ?
1007 readw(tp->mmio_addr + mii_2_8139_map[location]) : 0;
1008 }
1009 mdio_sync(mdio_addr);
1010 /* Shift the read command bits out. */
1011 for (i = 15; i >= 0; i--) {
1012 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1013
1014 writeb(MDIO_DIR | dataval, mdio_addr);
1015 mdio_delay();
1016 writeb(MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1017 mdio_delay();
1018 }
1019
1020 /* Read the two transition, 16 data, and wire-idle bits. */
1021 for (i = 19; i > 0; i--) {
1022 writeb(0, mdio_addr);
1023 mdio_delay();
1024 retval = ((retval << 1) | ((readb(mdio_addr) & MDIO_DATA_IN))
1025 ? 1 : 0);
1026 writeb(MDIO_CLK, mdio_addr);
1027 mdio_delay();
1028 }
1029
1030 DPRINTK("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1031 return (retval >> 1) & 0xffff;
1032 }
1033
1034
1035 static void mdio_write(struct net_device *dev, int phy_id, int location,
1036 int value)
1037 {
1038 struct netdrv_private *tp = netdev_priv(dev);
1039 void *mdio_addr = tp->mmio_addr + Config4;
1040 int mii_cmd =
1041 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1042 int i;
1043
1044 DPRINTK("ENTER\n");
1045
1046 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1047 if (location < 8 && mii_2_8139_map[location]) {
1048 writew(value,
1049 tp->mmio_addr + mii_2_8139_map[location]);
1050 readw(tp->mmio_addr + mii_2_8139_map[location]);
1051 }
1052 DPRINTK("EXIT after directly using 8139 internal regs\n");
1053 return;
1054 }
1055 mdio_sync(mdio_addr);
1056
1057 /* Shift the command bits out. */
1058 for (i = 31; i >= 0; i--) {
1059 int dataval =
1060 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1061 writeb(dataval, mdio_addr);
1062 mdio_delay();
1063 writeb(dataval | MDIO_CLK, mdio_addr);
1064 mdio_delay();
1065 }
1066
1067 /* Clear out extra bits. */
1068 for (i = 2; i > 0; i--) {
1069 writeb(0, mdio_addr);
1070 mdio_delay();
1071 writeb(MDIO_CLK, mdio_addr);
1072 mdio_delay();
1073 }
1074
1075 DPRINTK("EXIT\n");
1076 }
1077
1078
1079 static int netdrv_open(struct net_device *dev)
1080 {
1081 struct netdrv_private *tp = netdev_priv(dev);
1082 int retval;
1083 void *ioaddr = tp->mmio_addr;
1084
1085 DPRINTK("ENTER\n");
1086
1087 retval = request_irq(dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1088 if (retval) {
1089 DPRINTK("EXIT, returning %d\n", retval);
1090 return retval;
1091 }
1092
1093 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1094 &tp->tx_bufs_dma);
1095 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1096 &tp->rx_ring_dma);
1097 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1098 free_irq(dev->irq, dev);
1099
1100 if (tp->tx_bufs)
1101 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1102 tp->tx_bufs, tp->tx_bufs_dma);
1103 if (tp->rx_ring)
1104 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1105 tp->rx_ring, tp->rx_ring_dma);
1106
1107 DPRINTK("EXIT, returning -ENOMEM\n");
1108 return -ENOMEM;
1109
1110 }
1111
1112 tp->full_duplex = tp->duplex_lock;
1113 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1114
1115 netdrv_init_ring(dev);
1116 netdrv_hw_start(dev);
1117
1118 netdev_dbg(dev, "ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1119 (unsigned long long)pci_resource_start(tp->pci_dev, 1),
1120 dev->irq, NETDRV_R8(MediaStatus),
1121 tp->full_duplex ? "full" : "half");
1122
1123 /* Set the timer to switch to check for link beat and perhaps switch
1124 to an alternate media type. */
1125 init_timer(&tp->timer);
1126 tp->timer.expires = jiffies + 3 * HZ;
1127 tp->timer.data = (unsigned long) dev;
1128 tp->timer.function = &netdrv_timer;
1129 add_timer(&tp->timer);
1130
1131 DPRINTK("EXIT, returning 0\n");
1132 return 0;
1133 }
1134
1135
1136 /* Start the hardware at open or resume. */
1137 static void netdrv_hw_start(struct net_device *dev)
1138 {
1139 struct netdrv_private *tp = netdev_priv(dev);
1140 void *ioaddr = tp->mmio_addr;
1141 u32 i;
1142
1143 DPRINTK("ENTER\n");
1144
1145 /* Soft reset the chip. */
1146 NETDRV_W8(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear) | CmdReset);
1147 udelay(100);
1148
1149 /* Check that the chip has finished the reset. */
1150 for (i = 1000; i > 0; i--)
1151 if ((NETDRV_R8(ChipCmd) & CmdReset) == 0)
1152 break;
1153
1154 /* Restore our idea of the MAC address. */
1155 NETDRV_W32_F(MAC0 + 0, cpu_to_le32(*(u32 *)(dev->dev_addr + 0)));
1156 NETDRV_W32_F(MAC0 + 4, cpu_to_le32(*(u32 *)(dev->dev_addr + 4)));
1157
1158 /* Must enable Tx/Rx before setting transfer thresholds! */
1159 NETDRV_W8_F(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear) |
1160 CmdRxEnb | CmdTxEnb);
1161
1162 i = netdrv_rx_config |
1163 (NETDRV_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1164 NETDRV_W32_F(RxConfig, i);
1165
1166 /* Check this value: the documentation for IFG contradicts ifself. */
1167 NETDRV_W32(TxConfig, (TX_DMA_BURST << TxDMAShift));
1168
1169 /* unlock Config[01234] and BMCR register writes */
1170 NETDRV_W8_F(Cfg9346, Cfg9346_Unlock);
1171 udelay(10);
1172
1173 tp->cur_rx = 0;
1174
1175 /* Lock Config[01234] and BMCR register writes */
1176 NETDRV_W8_F(Cfg9346, Cfg9346_Lock);
1177 udelay(10);
1178
1179 /* init Rx ring buffer DMA address */
1180 NETDRV_W32_F(RxBuf, tp->rx_ring_dma);
1181
1182 /* init Tx buffer DMA addresses */
1183 for (i = 0; i < NUM_TX_DESC; i++)
1184 NETDRV_W32_F(TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1185
1186 NETDRV_W32_F(RxMissed, 0);
1187
1188 netdrv_set_rx_mode(dev);
1189
1190 /* no early-rx interrupts */
1191 NETDRV_W16(MultiIntr, NETDRV_R16(MultiIntr) & MultiIntrClear);
1192
1193 /* make sure RxTx has started */
1194 NETDRV_W8_F(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear) |
1195 CmdRxEnb | CmdTxEnb);
1196
1197 /* Enable all known interrupts by setting the interrupt mask. */
1198 NETDRV_W16_F(IntrMask, netdrv_intr_mask);
1199
1200 netif_start_queue(dev);
1201
1202 DPRINTK("EXIT\n");
1203 }
1204
1205
1206 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1207 static void netdrv_init_ring(struct net_device *dev)
1208 {
1209 struct netdrv_private *tp = netdev_priv(dev);
1210 int i;
1211
1212 DPRINTK("ENTER\n");
1213
1214 tp->cur_rx = 0;
1215 atomic_set(&tp->cur_tx, 0);
1216 atomic_set(&tp->dirty_tx, 0);
1217
1218 for (i = 0; i < NUM_TX_DESC; i++) {
1219 tp->tx_info[i].skb = NULL;
1220 tp->tx_info[i].mapping = 0;
1221 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1222 }
1223
1224 DPRINTK("EXIT\n");
1225 }
1226
1227
1228 static void netdrv_timer(unsigned long data)
1229 {
1230 struct net_device *dev = (struct net_device *) data;
1231 struct netdrv_private *tp = netdev_priv(dev);
1232 void *ioaddr = tp->mmio_addr;
1233 int next_tick = 60 * HZ;
1234 int mii_lpa;
1235
1236 mii_lpa = mdio_read(dev, tp->phys[0], MII_LPA);
1237
1238 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1239 int duplex = ((mii_lpa & LPA_100FULL) ||
1240 (mii_lpa & 0x01C0) == 0x0040);
1241 if (tp->full_duplex != duplex) {
1242 tp->full_duplex = duplex;
1243 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1244 tp->full_duplex ? "full" : "half",
1245 tp->phys[0], mii_lpa);
1246 NETDRV_W8(Cfg9346, Cfg9346_Unlock);
1247 NETDRV_W8(Config1, tp->full_duplex ? 0x60 : 0x20);
1248 NETDRV_W8(Cfg9346, Cfg9346_Lock);
1249 }
1250 }
1251
1252 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1253 NETDRV_R16(NWayLPAR));
1254 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x RxStatus %04lx\n",
1255 NETDRV_R16(IntrMask),
1256 NETDRV_R16(IntrStatus),
1257 NETDRV_R32(RxEarlyStatus));
1258 netdev_dbg(dev, "Chip config %02x %02x\n",
1259 NETDRV_R8(Config0), NETDRV_R8(Config1));
1260
1261 tp->timer.expires = jiffies + next_tick;
1262 add_timer(&tp->timer);
1263 }
1264
1265
1266 static void netdrv_tx_clear(struct net_device *dev)
1267 {
1268 int i;
1269 struct netdrv_private *tp = netdev_priv(dev);
1270
1271 atomic_set(&tp->cur_tx, 0);
1272 atomic_set(&tp->dirty_tx, 0);
1273
1274 /* Dump the unsent Tx packets. */
1275 for (i = 0; i < NUM_TX_DESC; i++) {
1276 struct ring_info *rp = &tp->tx_info[i];
1277 if (rp->mapping != 0) {
1278 pci_unmap_single(tp->pci_dev, rp->mapping,
1279 rp->skb->len, PCI_DMA_TODEVICE);
1280 rp->mapping = 0;
1281 }
1282 if (rp->skb) {
1283 dev_kfree_skb(rp->skb);
1284 rp->skb = NULL;
1285 dev->stats.tx_dropped++;
1286 }
1287 }
1288 }
1289
1290
1291 static void netdrv_tx_timeout(struct net_device *dev)
1292 {
1293 struct netdrv_private *tp = netdev_priv(dev);
1294 void *ioaddr = tp->mmio_addr;
1295 int i;
1296 u8 tmp8;
1297 unsigned long flags;
1298
1299 netdev_dbg(dev, "Transmit timeout, status %02x %04x media %02x\n",
1300 NETDRV_R8(ChipCmd),
1301 NETDRV_R16(IntrStatus),
1302 NETDRV_R8(MediaStatus));
1303
1304 /* disable Tx ASAP, if not already */
1305 tmp8 = NETDRV_R8(ChipCmd);
1306 if (tmp8 & CmdTxEnb)
1307 NETDRV_W8(ChipCmd, tmp8 & ~CmdTxEnb);
1308
1309 /* Disable interrupts by clearing the interrupt mask. */
1310 NETDRV_W16(IntrMask, 0x0000);
1311
1312 /* Emit info to figure out what went wrong. */
1313 netdev_dbg(dev, "Tx queue start entry %d dirty entry %d\n",
1314 atomic_read(&tp->cur_tx),
1315 atomic_read(&tp->dirty_tx));
1316 for (i = 0; i < NUM_TX_DESC; i++)
1317 netdev_dbg(dev, "Tx descriptor %d is %08lx%s\n",
1318 i, NETDRV_R32(TxStatus0 + (i * 4)),
1319 i == atomic_read(&tp->dirty_tx) % NUM_TX_DESC ?
1320 "(queue head)" : "");
1321
1322 /* Stop a shared interrupt from scavenging while we are. */
1323 spin_lock_irqsave(&tp->lock, flags);
1324
1325 netdrv_tx_clear(dev);
1326
1327 spin_unlock_irqrestore(&tp->lock, flags);
1328
1329 /* ...and finally, reset everything */
1330 netdrv_hw_start(dev);
1331
1332 netif_wake_queue(dev);
1333 }
1334
1335
1336
1337 static int netdrv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1338 {
1339 struct netdrv_private *tp = netdev_priv(dev);
1340 void *ioaddr = tp->mmio_addr;
1341 int entry;
1342
1343 /* Calculate the next Tx descriptor entry. */
1344 entry = atomic_read(&tp->cur_tx) % NUM_TX_DESC;
1345
1346 assert(tp->tx_info[entry].skb == NULL);
1347 assert(tp->tx_info[entry].mapping == 0);
1348
1349 tp->tx_info[entry].skb = skb;
1350 /* tp->tx_info[entry].mapping = 0; */
1351 skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1352
1353 /* Note: the chip doesn't have auto-pad! */
1354 NETDRV_W32(TxStatus0 + (entry * sizeof(u32)),
1355 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1356
1357 atomic_inc(&tp->cur_tx);
1358 if ((atomic_read(&tp->cur_tx) - atomic_read(&tp->dirty_tx)) >= NUM_TX_DESC)
1359 netif_stop_queue(dev);
1360
1361 netdev_dbg(dev, "Queued Tx packet at %p size %u to slot %d\n",
1362 skb->data, skb->len, entry);
1363
1364 return NETDEV_TX_OK;
1365 }
1366
1367
1368 static void netdrv_tx_interrupt(struct net_device *dev,
1369 struct netdrv_private *tp,
1370 void *ioaddr)
1371 {
1372 int cur_tx, dirty_tx, tx_left;
1373
1374 assert(dev != NULL);
1375 assert(tp != NULL);
1376 assert(ioaddr != NULL);
1377
1378 dirty_tx = atomic_read(&tp->dirty_tx);
1379
1380 cur_tx = atomic_read(&tp->cur_tx);
1381 tx_left = cur_tx - dirty_tx;
1382 while (tx_left > 0) {
1383 int entry = dirty_tx % NUM_TX_DESC;
1384 int txstatus;
1385
1386 txstatus = NETDRV_R32(TxStatus0 + (entry * sizeof(u32)));
1387
1388 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1389 break; /* It still hasn't been Txed */
1390
1391 /* Note: TxCarrierLost is always asserted at 100mbps. */
1392 if (txstatus & (TxOutOfWindow | TxAborted)) {
1393 /* There was an major error, log it. */
1394 netdev_dbg(dev, "Transmit error, Tx status %#08x\n",
1395 txstatus);
1396 dev->stats.tx_errors++;
1397 if (txstatus & TxAborted) {
1398 dev->stats.tx_aborted_errors++;
1399 NETDRV_W32(TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1400 }
1401 if (txstatus & TxCarrierLost)
1402 dev->stats.tx_carrier_errors++;
1403 if (txstatus & TxOutOfWindow)
1404 dev->stats.tx_window_errors++;
1405 } else {
1406 if (txstatus & TxUnderrun) {
1407 /* Add 64 to the Tx FIFO threshold. */
1408 if (tp->tx_flag < 0x00300000)
1409 tp->tx_flag += 0x00020000;
1410 dev->stats.tx_fifo_errors++;
1411 }
1412 dev->stats.collisions += (txstatus >> 24) & 15;
1413 dev->stats.tx_bytes += txstatus & 0x7ff;
1414 dev->stats.tx_packets++;
1415 }
1416
1417 /* Free the original skb. */
1418 if (tp->tx_info[entry].mapping != 0) {
1419 pci_unmap_single(tp->pci_dev,
1420 tp->tx_info[entry].mapping,
1421 tp->tx_info[entry].skb->len,
1422 PCI_DMA_TODEVICE);
1423 tp->tx_info[entry].mapping = 0;
1424 }
1425 dev_kfree_skb_irq(tp->tx_info[entry].skb);
1426 tp->tx_info[entry].skb = NULL;
1427 dirty_tx++;
1428 if (dirty_tx < 0) { /* handle signed int overflow */
1429 atomic_sub(cur_tx, &tp->cur_tx);
1430 dirty_tx = cur_tx - tx_left + 1;
1431 }
1432 if (netif_queue_stopped(dev))
1433 netif_wake_queue(dev);
1434
1435 cur_tx = atomic_read(&tp->cur_tx);
1436 tx_left = cur_tx - dirty_tx;
1437
1438 }
1439
1440 #ifndef NETDRV_NDEBUG
1441 if (atomic_read(&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1442 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d\n",
1443 dirty_tx, atomic_read(&tp->cur_tx));
1444 dirty_tx += NUM_TX_DESC;
1445 }
1446 #endif /* NETDRV_NDEBUG */
1447
1448 atomic_set(&tp->dirty_tx, dirty_tx);
1449 }
1450
1451
1452 /* TODO: clean this up! Rx reset need not be this intensive */
1453 static void netdrv_rx_err(u32 rx_status, struct net_device *dev,
1454 struct netdrv_private *tp, void *ioaddr)
1455 {
1456 u8 tmp8;
1457 int tmp_work = 1000;
1458
1459 netdev_dbg(dev, "Ethernet frame had errors, status %08x\n", rx_status);
1460 if (rx_status & RxTooLong)
1461 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1462 rx_status);
1463 /* A.C.: The chip hangs here. */
1464 dev->stats.rx_errors++;
1465 if (rx_status & (RxBadSymbol | RxBadAlign))
1466 dev->stats.rx_frame_errors++;
1467 if (rx_status & (RxRunt | RxTooLong))
1468 dev->stats.rx_length_errors++;
1469 if (rx_status & RxCRCErr)
1470 dev->stats.rx_crc_errors++;
1471 /* Reset the receiver, based on RealTek recommendation.(Bug?) */
1472 tp->cur_rx = 0;
1473
1474 /* disable receive */
1475 tmp8 = NETDRV_R8(ChipCmd) & ChipCmdClear;
1476 NETDRV_W8_F(ChipCmd, tmp8 | CmdTxEnb);
1477
1478 /* A.C.: Reset the multicast list. */
1479 netdrv_set_rx_mode(dev);
1480
1481 while (--tmp_work > 0) {
1482 tmp8 = NETDRV_R8(ChipCmd);
1483 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1484 break;
1485 NETDRV_W8_F(ChipCmd,
1486 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1487 }
1488
1489 /* G.S.: Re-enable receiver */
1490 netdrv_set_rx_mode(dev);
1491
1492 if (tmp_work <= 0)
1493 netdev_warn(dev, "tx/rx enable wait too long\n");
1494 }
1495
1496
1497 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1498 field alignments and semantics. */
1499 static void netdrv_rx_interrupt(struct net_device *dev,
1500 struct netdrv_private *tp, void *ioaddr)
1501 {
1502 unsigned char *rx_ring;
1503 u16 cur_rx;
1504
1505 assert(dev != NULL);
1506 assert(tp != NULL);
1507 assert(ioaddr != NULL);
1508
1509 rx_ring = tp->rx_ring;
1510 cur_rx = tp->cur_rx;
1511
1512 netdev_dbg(dev, "In netdrv_rx(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1513 cur_rx, NETDRV_R16(RxBufAddr),
1514 NETDRV_R16(RxBufPtr), NETDRV_R8(ChipCmd));
1515
1516 while ((NETDRV_R8(ChipCmd) & RxBufEmpty) == 0) {
1517 int ring_offset = cur_rx % RX_BUF_LEN;
1518 u32 rx_status;
1519 unsigned int rx_size;
1520 unsigned int pkt_size;
1521 struct sk_buff *skb;
1522
1523 /* read size+status of next frame from DMA ring buffer */
1524 rx_status = le32_to_cpu(*(u32 *)(rx_ring + ring_offset));
1525 rx_size = rx_status >> 16;
1526 pkt_size = rx_size - 4;
1527
1528 netdev_dbg(dev, "netdrv_rx() status %04x, size %04x, cur %04x\n",
1529 rx_status, rx_size, cur_rx);
1530 #if defined(NETDRV_DEBUG) && (NETDRV_DEBUG > 2)
1531 print_hex_dump_bytes("Frame contents: ", HEX_DUMP_OFFSET,
1532 &rx_ring[ring_offset], 70);
1533 #endif
1534
1535 /* If Rx err or invalid rx_size/rx_status received
1536 *(which happens if we get lost in the ring),
1537 * Rx process gets reset, so we abort any further
1538 * Rx processing.
1539 */
1540 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1541 (!(rx_status & RxStatusOK))) {
1542 netdrv_rx_err(rx_status, dev, tp, ioaddr);
1543 return;
1544 }
1545
1546 /* Malloc up new buffer, compatible with net-2e. */
1547 /* Omit the four octet CRC from the length. */
1548
1549 /* TODO: consider allocating skb's outside of
1550 * interrupt context, both to speed interrupt processing,
1551 * and also to reduce the chances of having to
1552 * drop packets here under memory pressure.
1553 */
1554
1555 skb = dev_alloc_skb(pkt_size + 2);
1556 if (skb) {
1557 skb_reserve(skb, 2); /* 16 byte align the IP fields. */
1558
1559 skb_copy_to_linear_data(skb, &rx_ring[ring_offset + 4], pkt_size);
1560 skb_put(skb, pkt_size);
1561
1562 skb->protocol = eth_type_trans(skb, dev);
1563 netif_rx(skb);
1564 dev->stats.rx_bytes += pkt_size;
1565 dev->stats.rx_packets++;
1566 } else {
1567 netdev_warn(dev, "Memory squeeze, dropping packet\n");
1568 dev->stats.rx_dropped++;
1569 }
1570
1571 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1572 NETDRV_W16_F(RxBufPtr, cur_rx - 16);
1573 }
1574
1575 netdev_dbg(dev, "Done netdrv_rx(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1576 cur_rx, NETDRV_R16(RxBufAddr),
1577 NETDRV_R16(RxBufPtr), NETDRV_R8(ChipCmd));
1578
1579 tp->cur_rx = cur_rx;
1580 }
1581
1582
1583 static void netdrv_weird_interrupt(struct net_device *dev,
1584 struct netdrv_private *tp,
1585 void *ioaddr,
1586 int status, int link_changed)
1587 {
1588 netdev_printk(KERN_DEBUG, dev, "Abnormal interrupt, status %08x\n",
1589 status);
1590
1591 assert(dev != NULL);
1592 assert(tp != NULL);
1593 assert(ioaddr != NULL);
1594
1595 /* Update the error count. */
1596 dev->stats.rx_missed_errors += NETDRV_R32(RxMissed);
1597 NETDRV_W32(RxMissed, 0);
1598
1599 if ((status & RxUnderrun) && link_changed &&
1600 (tp->drv_flags & HAS_LNK_CHNG)) {
1601 /* Really link-change on new chips. */
1602 int lpar = NETDRV_R16(NWayLPAR);
1603 int duplex = ((lpar & 0x0100) || (lpar & 0x01C0) == 0x0040 ||
1604 tp->duplex_lock);
1605 if (tp->full_duplex != duplex) {
1606 tp->full_duplex = duplex;
1607 NETDRV_W8(Cfg9346, Cfg9346_Unlock);
1608 NETDRV_W8(Config1, tp->full_duplex ? 0x60 : 0x20);
1609 NETDRV_W8(Cfg9346, Cfg9346_Lock);
1610 }
1611 status &= ~RxUnderrun;
1612 }
1613
1614 if (status & (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1615 dev->stats.rx_errors++;
1616
1617 if (status & (PCSTimeout))
1618 dev->stats.rx_length_errors++;
1619 if (status & (RxUnderrun | RxFIFOOver))
1620 dev->stats.rx_fifo_errors++;
1621 if (status & RxOverflow) {
1622 dev->stats.rx_over_errors++;
1623 tp->cur_rx = NETDRV_R16(RxBufAddr) % RX_BUF_LEN;
1624 NETDRV_W16_F(RxBufPtr, tp->cur_rx - 16);
1625 }
1626 if (status & PCIErr) {
1627 u16 pci_cmd_status;
1628 pci_read_config_word(tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1629
1630 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
1631 }
1632 }
1633
1634
1635 /* The interrupt handler does all of the Rx thread work and cleans up
1636 after the Tx thread. */
1637 static irqreturn_t netdrv_interrupt(int irq, void *dev_instance)
1638 {
1639 struct net_device *dev = (struct net_device *) dev_instance;
1640 struct netdrv_private *tp = netdev_priv(dev);
1641 int boguscnt = max_interrupt_work;
1642 void *ioaddr = tp->mmio_addr;
1643 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1644 int handled = 0;
1645
1646 spin_lock(&tp->lock);
1647
1648 do {
1649 status = NETDRV_R16(IntrStatus);
1650
1651 /* h/w no longer present(hotplug?) or major error, bail */
1652 if (status == 0xFFFF)
1653 break;
1654
1655 handled = 1;
1656 /* Acknowledge all of the current interrupt sources ASAP */
1657 NETDRV_W16_F(IntrStatus, status);
1658
1659 netdev_dbg(dev, "interrupt status=%#04x new intstat=%#04x\n",
1660 status, NETDRV_R16(IntrStatus));
1661
1662 if ((status &
1663 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1664 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1665 break;
1666
1667 /* Check uncommon events with one test. */
1668 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1669 RxFIFOOver | TxErr | RxErr))
1670 netdrv_weird_interrupt(dev, tp, ioaddr,
1671 status, link_changed);
1672
1673 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1674 netdrv_rx_interrupt(dev, tp, ioaddr);
1675
1676 if (status & (TxOK | TxErr))
1677 netdrv_tx_interrupt(dev, tp, ioaddr);
1678
1679 boguscnt--;
1680 } while (boguscnt > 0);
1681
1682 if (boguscnt <= 0) {
1683 netdev_warn(dev, "Too much work at interrupt, IntrStatus=%#04x\n",
1684 status);
1685
1686 /* Clear all interrupt sources. */
1687 NETDRV_W16(IntrStatus, 0xffff);
1688 }
1689
1690 spin_unlock(&tp->lock);
1691
1692 netdev_dbg(dev, "exiting interrupt, intr_status=%#04x\n",
1693 NETDRV_R16(IntrStatus));
1694 return IRQ_RETVAL(handled);
1695 }
1696
1697
1698 static int netdrv_close(struct net_device *dev)
1699 {
1700 struct netdrv_private *tp = netdev_priv(dev);
1701 void *ioaddr = tp->mmio_addr;
1702 unsigned long flags;
1703
1704 DPRINTK("ENTER\n");
1705
1706 netif_stop_queue(dev);
1707
1708 netdev_dbg(dev, "Shutting down ethercard, status was %#04x\n",
1709 NETDRV_R16(IntrStatus));
1710
1711 del_timer_sync(&tp->timer);
1712
1713 spin_lock_irqsave(&tp->lock, flags);
1714
1715 /* Stop the chip's Tx and Rx DMA processes. */
1716 NETDRV_W8(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear));
1717
1718 /* Disable interrupts by clearing the interrupt mask. */
1719 NETDRV_W16(IntrMask, 0x0000);
1720
1721 /* Update the error counts. */
1722 dev->stats.rx_missed_errors += NETDRV_R32(RxMissed);
1723 NETDRV_W32(RxMissed, 0);
1724
1725 spin_unlock_irqrestore(&tp->lock, flags);
1726
1727 free_irq(dev->irq, dev);
1728
1729 netdrv_tx_clear(dev);
1730
1731 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1732 tp->rx_ring, tp->rx_ring_dma);
1733 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1734 tp->tx_bufs, tp->tx_bufs_dma);
1735 tp->rx_ring = NULL;
1736 tp->tx_bufs = NULL;
1737
1738 /* Green! Put the chip in low-power mode. */
1739 NETDRV_W8(Cfg9346, Cfg9346_Unlock);
1740 NETDRV_W8(Config1, 0x03);
1741 NETDRV_W8(Cfg9346, Cfg9346_Lock);
1742
1743 DPRINTK("EXIT\n");
1744 return 0;
1745 }
1746
1747
1748 static int netdrv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1749 {
1750 struct netdrv_private *tp = netdev_priv(dev);
1751 struct mii_ioctl_data *data = if_mii(rq);
1752 unsigned long flags;
1753 int rc = 0;
1754
1755 DPRINTK("ENTER\n");
1756
1757 switch (cmd) {
1758 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1759 data->phy_id = tp->phys[0] & 0x3f;
1760 /* Fall Through */
1761
1762 case SIOCGMIIREG: /* Read MII PHY register. */
1763 spin_lock_irqsave(&tp->lock, flags);
1764 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1765 spin_unlock_irqrestore(&tp->lock, flags);
1766 break;
1767
1768 case SIOCSMIIREG: /* Write MII PHY register. */
1769 spin_lock_irqsave(&tp->lock, flags);
1770 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1771 spin_unlock_irqrestore(&tp->lock, flags);
1772 break;
1773
1774 default:
1775 rc = -EOPNOTSUPP;
1776 break;
1777 }
1778
1779 DPRINTK("EXIT, returning %d\n", rc);
1780 return rc;
1781 }
1782
1783 /* Set or clear the multicast filter for this adaptor.
1784 This routine is not state sensitive and need not be SMP locked. */
1785
1786 static void netdrv_set_rx_mode(struct net_device *dev)
1787 {
1788 struct netdrv_private *tp = netdev_priv(dev);
1789 void *ioaddr = tp->mmio_addr;
1790 u32 mc_filter[2]; /* Multicast hash filter */
1791 int rx_mode;
1792 u32 tmp;
1793
1794 DPRINTK("ENTER\n");
1795
1796 netdev_dbg(dev, "%s(%04x) done -- Rx config %08lx\n",
1797 __func__, dev->flags, NETDRV_R32(RxConfig));
1798
1799 /* Note: do not reorder, GCC is clever about common statements. */
1800 if (dev->flags & IFF_PROMISC) {
1801 rx_mode =
1802 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1803 AcceptAllPhys;
1804 mc_filter[1] = mc_filter[0] = 0xffffffff;
1805 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1806 (dev->flags & IFF_ALLMULTI)) {
1807 /* Too many to filter perfectly -- accept all multicasts. */
1808 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1809 mc_filter[1] = mc_filter[0] = 0xffffffff;
1810 } else {
1811 struct netdev_hw_addr *ha;
1812
1813 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1814 mc_filter[1] = mc_filter[0] = 0;
1815 netdev_for_each_mc_addr(ha, dev) {
1816 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1817
1818 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1819 }
1820 }
1821
1822 /* if called from irq handler, lock already acquired */
1823 if (!in_irq())
1824 spin_lock_irq(&tp->lock);
1825
1826 /* We can safely update without stopping the chip. */
1827 tmp = netdrv_rx_config | rx_mode |
1828 (NETDRV_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1829 NETDRV_W32_F(RxConfig, tmp);
1830 NETDRV_W32_F(MAR0 + 0, mc_filter[0]);
1831 NETDRV_W32_F(MAR0 + 4, mc_filter[1]);
1832
1833 if (!in_irq())
1834 spin_unlock_irq(&tp->lock);
1835
1836 DPRINTK("EXIT\n");
1837 }
1838
1839
1840 #ifdef CONFIG_PM
1841
1842 static int netdrv_suspend(struct pci_dev *pdev, pm_message_t state)
1843 {
1844 struct net_device *dev = pci_get_drvdata(pdev);
1845 struct netdrv_private *tp = netdev_priv(dev);
1846 void *ioaddr = tp->mmio_addr;
1847 unsigned long flags;
1848
1849 if (!netif_running(dev))
1850 return 0;
1851 netif_device_detach(dev);
1852
1853 spin_lock_irqsave(&tp->lock, flags);
1854
1855 /* Disable interrupts, stop Tx and Rx. */
1856 NETDRV_W16(IntrMask, 0x0000);
1857 NETDRV_W8(ChipCmd, (NETDRV_R8(ChipCmd) & ChipCmdClear));
1858
1859 /* Update the error counts. */
1860 dev->stats.rx_missed_errors += NETDRV_R32(RxMissed);
1861 NETDRV_W32(RxMissed, 0);
1862
1863 spin_unlock_irqrestore(&tp->lock, flags);
1864
1865 pci_save_state(pdev);
1866 pci_set_power_state(pdev, PCI_D3hot);
1867
1868 return 0;
1869 }
1870
1871
1872 static int netdrv_resume(struct pci_dev *pdev)
1873 {
1874 struct net_device *dev = pci_get_drvdata(pdev);
1875 /*struct netdrv_private *tp = netdev_priv(dev);*/
1876
1877 if (!netif_running(dev))
1878 return 0;
1879 pci_set_power_state(pdev, PCI_D0);
1880 pci_restore_state(pdev);
1881 netif_device_attach(dev);
1882 netdrv_hw_start(dev);
1883
1884 return 0;
1885 }
1886
1887 #endif /* CONFIG_PM */
1888
1889
1890 static struct pci_driver netdrv_pci_driver = {
1891 .name = MODNAME,
1892 .id_table = netdrv_pci_tbl,
1893 .probe = netdrv_init_one,
1894 .remove = __devexit_p(netdrv_remove_one),
1895 #ifdef CONFIG_PM
1896 .suspend = netdrv_suspend,
1897 .resume = netdrv_resume,
1898 #endif /* CONFIG_PM */
1899 };
1900
1901
1902 static int __init netdrv_init_module(void)
1903 {
1904 /* when a module, this is printed whether or not devices are found in probe */
1905 #ifdef MODULE
1906 printk(version);
1907 #endif
1908 return pci_register_driver(&netdrv_pci_driver);
1909 }
1910
1911
1912 static void __exit netdrv_cleanup_module(void)
1913 {
1914 pci_unregister_driver(&netdrv_pci_driver);
1915 }
1916
1917
1918 module_init(netdrv_init_module);
1919 module_exit(netdrv_cleanup_module);
Tomato firmware and modifications.