1 /*******************************************************************************
3 Intel PRO/10GbE Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the adapter
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38 #include <linux/etherdevice.h>
40 /* Local function prototypes */
42 static u32
ixgb_hash_mc_addr(struct ixgb_hw
*hw
, u8
* mc_addr
);
44 static void ixgb_mta_set(struct ixgb_hw
*hw
, u32 hash_value
);
46 static void ixgb_get_bus_info(struct ixgb_hw
*hw
);
48 static bool ixgb_link_reset(struct ixgb_hw
*hw
);
50 static void ixgb_optics_reset(struct ixgb_hw
*hw
);
52 static void ixgb_optics_reset_bcm(struct ixgb_hw
*hw
);
54 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw
*hw
);
56 static void ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
);
58 static void ixgb_clear_vfta(struct ixgb_hw
*hw
);
60 static void ixgb_init_rx_addrs(struct ixgb_hw
*hw
);
62 static u16
ixgb_read_phy_reg(struct ixgb_hw
*hw
,
67 static bool ixgb_setup_fc(struct ixgb_hw
*hw
);
69 static bool mac_addr_valid(u8
*mac_addr
);
71 static u32
ixgb_mac_reset(struct ixgb_hw
*hw
)
75 ctrl_reg
= IXGB_CTRL0_RST
|
76 IXGB_CTRL0_SDP3_DIR
| /* All pins are Output=1 */
80 IXGB_CTRL0_SDP3
| /* Initial value 1101 */
85 IXGB_WRITE_REG_IO(hw
, CTRL0
, ctrl_reg
);
87 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
90 /* Delay a few ms just to allow the reset to complete */
91 msleep(IXGB_DELAY_AFTER_RESET
);
92 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
94 /* Make sure the self-clearing global reset bit did self clear */
95 ASSERT(!(ctrl_reg
& IXGB_CTRL0_RST
));
98 if (hw
->subsystem_vendor_id
== SUN_SUBVENDOR_ID
) {
99 ctrl_reg
= /* Enable interrupt from XFP and SerDes */
101 IXGB_CTRL1_SDP6_DIR
|
102 IXGB_CTRL1_SDP7_DIR
|
105 IXGB_WRITE_REG(hw
, CTRL1
, ctrl_reg
);
106 ixgb_optics_reset_bcm(hw
);
109 if (hw
->phy_type
== ixgb_phy_type_txn17401
)
110 ixgb_optics_reset(hw
);
115 /******************************************************************************
116 * Reset the transmit and receive units; mask and clear all interrupts.
118 * hw - Struct containing variables accessed by shared code
119 *****************************************************************************/
121 ixgb_adapter_stop(struct ixgb_hw
*hw
)
128 /* If we are stopped or resetting exit gracefully and wait to be
129 * started again before accessing the hardware.
131 if (hw
->adapter_stopped
) {
132 pr_debug("Exiting because the adapter is already stopped!!!\n");
136 /* Set the Adapter Stopped flag so other driver functions stop
137 * touching the Hardware.
139 hw
->adapter_stopped
= true;
141 /* Clear interrupt mask to stop board from generating interrupts */
142 pr_debug("Masking off all interrupts\n");
143 IXGB_WRITE_REG(hw
, IMC
, 0xFFFFFFFF);
145 /* Disable the Transmit and Receive units. Then delay to allow
146 * any pending transactions to complete before we hit the MAC with
149 IXGB_WRITE_REG(hw
, RCTL
, IXGB_READ_REG(hw
, RCTL
) & ~IXGB_RCTL_RXEN
);
150 IXGB_WRITE_REG(hw
, TCTL
, IXGB_READ_REG(hw
, TCTL
) & ~IXGB_TCTL_TXEN
);
151 msleep(IXGB_DELAY_BEFORE_RESET
);
153 /* Issue a global reset to the MAC. This will reset the chip's
154 * transmit, receive, DMA, and link units. It will not effect
155 * the current PCI configuration. The global reset bit is self-
156 * clearing, and should clear within a microsecond.
158 pr_debug("Issuing a global reset to MAC\n");
160 ctrl_reg
= ixgb_mac_reset(hw
);
162 /* Clear interrupt mask to stop board from generating interrupts */
163 pr_debug("Masking off all interrupts\n");
164 IXGB_WRITE_REG(hw
, IMC
, 0xffffffff);
166 /* Clear any pending interrupt events. */
167 icr_reg
= IXGB_READ_REG(hw
, ICR
);
169 return (ctrl_reg
& IXGB_CTRL0_RST
);
173 /******************************************************************************
174 * Identifies the vendor of the optics module on the adapter. The SR adapters
175 * support two different types of XPAK optics, so it is necessary to determine
176 * which optics are present before applying any optics-specific workarounds.
178 * hw - Struct containing variables accessed by shared code.
180 * Returns: the vendor of the XPAK optics module.
181 *****************************************************************************/
182 static ixgb_xpak_vendor
183 ixgb_identify_xpak_vendor(struct ixgb_hw
*hw
)
187 ixgb_xpak_vendor xpak_vendor
;
191 /* Read the first few bytes of the vendor string from the XPAK NVR
192 * registers. These are standard XENPAK/XPAK registers, so all XPAK
193 * devices should implement them. */
194 for (i
= 0; i
< 5; i
++) {
195 vendor_name
[i
] = ixgb_read_phy_reg(hw
,
196 MDIO_PMA_PMD_XPAK_VENDOR_NAME
197 + i
, IXGB_PHY_ADDRESS
,
201 /* Determine the actual vendor */
202 if (vendor_name
[0] == 'I' &&
203 vendor_name
[1] == 'N' &&
204 vendor_name
[2] == 'T' &&
205 vendor_name
[3] == 'E' && vendor_name
[4] == 'L') {
206 xpak_vendor
= ixgb_xpak_vendor_intel
;
208 xpak_vendor
= ixgb_xpak_vendor_infineon
;
211 return (xpak_vendor
);
214 /******************************************************************************
215 * Determine the physical layer module on the adapter.
217 * hw - Struct containing variables accessed by shared code. The device_id
218 * field must be (correctly) populated before calling this routine.
220 * Returns: the phy type of the adapter.
221 *****************************************************************************/
223 ixgb_identify_phy(struct ixgb_hw
*hw
)
225 ixgb_phy_type phy_type
;
226 ixgb_xpak_vendor xpak_vendor
;
230 /* Infer the transceiver/phy type from the device id */
231 switch (hw
->device_id
) {
232 case IXGB_DEVICE_ID_82597EX
:
233 pr_debug("Identified TXN17401 optics\n");
234 phy_type
= ixgb_phy_type_txn17401
;
237 case IXGB_DEVICE_ID_82597EX_SR
:
238 /* The SR adapters carry two different types of XPAK optics
239 * modules; read the vendor identifier to determine the exact
241 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
242 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
243 pr_debug("Identified TXN17201 optics\n");
244 phy_type
= ixgb_phy_type_txn17201
;
246 pr_debug("Identified G6005 optics\n");
247 phy_type
= ixgb_phy_type_g6005
;
250 case IXGB_DEVICE_ID_82597EX_LR
:
251 pr_debug("Identified G6104 optics\n");
252 phy_type
= ixgb_phy_type_g6104
;
254 case IXGB_DEVICE_ID_82597EX_CX4
:
255 pr_debug("Identified CX4\n");
256 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
257 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
258 pr_debug("Identified TXN17201 optics\n");
259 phy_type
= ixgb_phy_type_txn17201
;
261 pr_debug("Identified G6005 optics\n");
262 phy_type
= ixgb_phy_type_g6005
;
266 pr_debug("Unknown physical layer module\n");
267 phy_type
= ixgb_phy_type_unknown
;
271 /* update phy type for sun specific board */
272 if (hw
->subsystem_vendor_id
== SUN_SUBVENDOR_ID
)
273 phy_type
= ixgb_phy_type_bcm
;
278 /******************************************************************************
279 * Performs basic configuration of the adapter.
281 * hw - Struct containing variables accessed by shared code
283 * Resets the controller.
284 * Reads and validates the EEPROM.
285 * Initializes the receive address registers.
286 * Initializes the multicast table.
287 * Clears all on-chip counters.
288 * Calls routine to setup flow control settings.
289 * Leaves the transmit and receive units disabled and uninitialized.
292 * true if successful,
293 * false if unrecoverable problems were encountered.
294 *****************************************************************************/
296 ixgb_init_hw(struct ixgb_hw
*hw
)
304 /* Issue a global reset to the MAC. This will reset the chip's
305 * transmit, receive, DMA, and link units. It will not effect
306 * the current PCI configuration. The global reset bit is self-
307 * clearing, and should clear within a microsecond.
309 pr_debug("Issuing a global reset to MAC\n");
311 ctrl_reg
= ixgb_mac_reset(hw
);
313 pr_debug("Issuing an EE reset to MAC\n");
315 IXGB_WRITE_REG_IO(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
317 IXGB_WRITE_REG(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
320 /* Delay a few ms just to allow the reset to complete */
321 msleep(IXGB_DELAY_AFTER_EE_RESET
);
323 if (!ixgb_get_eeprom_data(hw
))
326 /* Use the device id to determine the type of phy/transceiver. */
327 hw
->device_id
= ixgb_get_ee_device_id(hw
);
328 hw
->phy_type
= ixgb_identify_phy(hw
);
330 /* Setup the receive addresses.
331 * Receive Address Registers (RARs 0 - 15).
333 ixgb_init_rx_addrs(hw
);
336 * Check that a valid MAC address has been set.
337 * If it is not valid, we fail hardware init.
339 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
340 pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
344 /* tell the routines in this file they can access hardware again */
345 hw
->adapter_stopped
= false;
347 /* Fill in the bus_info structure */
348 ixgb_get_bus_info(hw
);
350 /* Zero out the Multicast HASH table */
351 pr_debug("Zeroing the MTA\n");
352 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
353 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
355 /* Zero out the VLAN Filter Table Array */
358 /* Zero all of the hardware counters */
359 ixgb_clear_hw_cntrs(hw
);
361 /* Call a subroutine to setup flow control. */
362 status
= ixgb_setup_fc(hw
);
364 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
365 ixgb_check_for_link(hw
);
370 /******************************************************************************
371 * Initializes receive address filters.
373 * hw - Struct containing variables accessed by shared code
375 * Places the MAC address in receive address register 0 and clears the rest
376 * of the receive address registers. Clears the multicast table. Assumes
377 * the receiver is in reset when the routine is called.
378 *****************************************************************************/
380 ixgb_init_rx_addrs(struct ixgb_hw
*hw
)
387 * If the current mac address is valid, assume it is a software override
388 * to the permanent address.
389 * Otherwise, use the permanent address from the eeprom.
391 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
393 /* Get the MAC address from the eeprom for later reference */
394 ixgb_get_ee_mac_addr(hw
, hw
->curr_mac_addr
);
396 pr_debug("Keeping Permanent MAC Addr = %pM\n",
400 /* Setup the receive address. */
401 pr_debug("Overriding MAC Address in RAR[0]\n");
402 pr_debug("New MAC Addr = %pM\n", hw
->curr_mac_addr
);
404 ixgb_rar_set(hw
, hw
->curr_mac_addr
, 0);
407 /* Zero out the other 15 receive addresses. */
408 pr_debug("Clearing RAR[1-15]\n");
409 for (i
= 1; i
< IXGB_RAR_ENTRIES
; i
++) {
410 /* Write high reg first to disable the AV bit first */
411 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
412 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
416 /******************************************************************************
417 * Updates the MAC's list of multicast addresses.
419 * hw - Struct containing variables accessed by shared code
420 * mc_addr_list - the list of new multicast addresses
421 * mc_addr_count - number of addresses
422 * pad - number of bytes between addresses in the list
424 * The given list replaces any existing list. Clears the last 15 receive
425 * address registers and the multicast table. Uses receive address registers
426 * for the first 15 multicast addresses, and hashes the rest into the
428 *****************************************************************************/
430 ixgb_mc_addr_list_update(struct ixgb_hw
*hw
,
437 u32 rar_used_count
= 1; /* RAR[0] is used for our MAC address */
442 /* Set the new number of MC addresses that we are being requested to use. */
443 hw
->num_mc_addrs
= mc_addr_count
;
445 /* Clear RAR[1-15] */
446 pr_debug("Clearing RAR[1-15]\n");
447 for (i
= rar_used_count
; i
< IXGB_RAR_ENTRIES
; i
++) {
448 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
449 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
453 pr_debug("Clearing MTA\n");
454 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
455 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
457 /* Add the new addresses */
459 for (i
= 0; i
< mc_addr_count
; i
++) {
460 pr_debug("Adding the multicast addresses:\n");
461 pr_debug("MC Addr #%d = %pM\n", i
, mca
);
463 /* Place this multicast address in the RAR if there is room, *
464 * else put it in the MTA
466 if (rar_used_count
< IXGB_RAR_ENTRIES
) {
467 ixgb_rar_set(hw
, mca
, rar_used_count
);
468 pr_debug("Added a multicast address to RAR[%d]\n", i
);
471 hash_value
= ixgb_hash_mc_addr(hw
, mca
);
473 pr_debug("Hash value = 0x%03X\n", hash_value
);
475 ixgb_mta_set(hw
, hash_value
);
478 mca
+= IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
;
481 pr_debug("MC Update Complete\n");
484 /******************************************************************************
485 * Hashes an address to determine its location in the multicast table
487 * hw - Struct containing variables accessed by shared code
488 * mc_addr - the multicast address to hash
492 *****************************************************************************/
494 ixgb_hash_mc_addr(struct ixgb_hw
*hw
,
501 /* The portion of the address that is used for the hash table is
502 * determined by the mc_filter_type setting.
504 switch (hw
->mc_filter_type
) {
505 /* [0] [1] [2] [3] [4] [5]
507 * LSB MSB - According to H/W docs */
509 /* [47:36] i.e. 0x563 for above example address */
511 ((mc_addr
[4] >> 4) | (((u16
) mc_addr
[5]) << 4));
513 case 1: /* [46:35] i.e. 0xAC6 for above example address */
515 ((mc_addr
[4] >> 3) | (((u16
) mc_addr
[5]) << 5));
517 case 2: /* [45:34] i.e. 0x5D8 for above example address */
519 ((mc_addr
[4] >> 2) | (((u16
) mc_addr
[5]) << 6));
521 case 3: /* [43:32] i.e. 0x634 for above example address */
522 hash_value
= ((mc_addr
[4]) | (((u16
) mc_addr
[5]) << 8));
525 /* Invalid mc_filter_type, what should we do? */
526 pr_debug("MC filter type param set incorrectly\n");
535 /******************************************************************************
536 * Sets the bit in the multicast table corresponding to the hash value.
538 * hw - Struct containing variables accessed by shared code
539 * hash_value - Multicast address hash value
540 *****************************************************************************/
542 ixgb_mta_set(struct ixgb_hw
*hw
,
545 u32 hash_bit
, hash_reg
;
548 /* The MTA is a register array of 128 32-bit registers.
549 * It is treated like an array of 4096 bits. We want to set
550 * bit BitArray[hash_value]. So we figure out what register
551 * the bit is in, read it, OR in the new bit, then write
552 * back the new value. The register is determined by the
553 * upper 7 bits of the hash value and the bit within that
554 * register are determined by the lower 5 bits of the value.
556 hash_reg
= (hash_value
>> 5) & 0x7F;
557 hash_bit
= hash_value
& 0x1F;
559 mta_reg
= IXGB_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
561 mta_reg
|= (1 << hash_bit
);
563 IXGB_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta_reg
);
566 /******************************************************************************
567 * Puts an ethernet address into a receive address register.
569 * hw - Struct containing variables accessed by shared code
570 * addr - Address to put into receive address register
571 * index - Receive address register to write
572 *****************************************************************************/
574 ixgb_rar_set(struct ixgb_hw
*hw
,
578 u32 rar_low
, rar_high
;
582 /* HW expects these in little endian so we reverse the byte order
583 * from network order (big endian) to little endian
585 rar_low
= ((u32
) addr
[0] |
586 ((u32
)addr
[1] << 8) |
587 ((u32
)addr
[2] << 16) |
588 ((u32
)addr
[3] << 24));
590 rar_high
= ((u32
) addr
[4] |
591 ((u32
)addr
[5] << 8) |
594 IXGB_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
595 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
598 /******************************************************************************
599 * Writes a value to the specified offset in the VLAN filter table.
601 * hw - Struct containing variables accessed by shared code
602 * offset - Offset in VLAN filer table to write
603 * value - Value to write into VLAN filter table
604 *****************************************************************************/
606 ixgb_write_vfta(struct ixgb_hw
*hw
,
610 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
613 /******************************************************************************
614 * Clears the VLAN filer table
616 * hw - Struct containing variables accessed by shared code
617 *****************************************************************************/
619 ixgb_clear_vfta(struct ixgb_hw
*hw
)
623 for (offset
= 0; offset
< IXGB_VLAN_FILTER_TBL_SIZE
; offset
++)
624 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, 0);
627 /******************************************************************************
628 * Configures the flow control settings based on SW configuration.
630 * hw - Struct containing variables accessed by shared code
631 *****************************************************************************/
634 ixgb_setup_fc(struct ixgb_hw
*hw
)
637 u32 pap_reg
= 0; /* by default, assume no pause time */
642 /* Get the current control reg 0 settings */
643 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
645 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
646 ctrl_reg
&= ~(IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
648 /* The possible values of the "flow_control" parameter are:
649 * 0: Flow control is completely disabled
650 * 1: Rx flow control is enabled (we can receive pause frames
651 * but not send pause frames).
652 * 2: Tx flow control is enabled (we can send pause frames
653 * but we do not support receiving pause frames).
654 * 3: Both Rx and TX flow control (symmetric) are enabled.
657 switch (hw
->fc
.type
) {
658 case ixgb_fc_none
: /* 0 */
659 /* Set CMDC bit to disable Rx Flow control */
660 ctrl_reg
|= (IXGB_CTRL0_CMDC
);
662 case ixgb_fc_rx_pause
: /* 1 */
663 /* RX Flow control is enabled, and TX Flow control is
666 ctrl_reg
|= (IXGB_CTRL0_RPE
);
668 case ixgb_fc_tx_pause
: /* 2 */
669 /* TX Flow control is enabled, and RX Flow control is
670 * disabled, by a software over-ride.
672 ctrl_reg
|= (IXGB_CTRL0_TPE
);
673 pap_reg
= hw
->fc
.pause_time
;
675 case ixgb_fc_full
: /* 3 */
676 /* Flow control (both RX and TX) is enabled by a software
679 ctrl_reg
|= (IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
680 pap_reg
= hw
->fc
.pause_time
;
683 /* We should never get here. The value should be 0-3. */
684 pr_debug("Flow control param set incorrectly\n");
689 /* Write the new settings */
690 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
693 IXGB_WRITE_REG(hw
, PAP
, pap_reg
);
695 /* Set the flow control receive threshold registers. Normally,
696 * these registers will be set to a default threshold that may be
697 * adjusted later by the driver's runtime code. However, if the
698 * ability to transmit pause frames in not enabled, then these
699 * registers will be set to 0.
701 if (!(hw
->fc
.type
& ixgb_fc_tx_pause
)) {
702 IXGB_WRITE_REG(hw
, FCRTL
, 0);
703 IXGB_WRITE_REG(hw
, FCRTH
, 0);
705 /* We need to set up the Receive Threshold high and low water
706 * marks as well as (optionally) enabling the transmission of XON
708 if (hw
->fc
.send_xon
) {
709 IXGB_WRITE_REG(hw
, FCRTL
,
710 (hw
->fc
.low_water
| IXGB_FCRTL_XONE
));
712 IXGB_WRITE_REG(hw
, FCRTL
, hw
->fc
.low_water
);
714 IXGB_WRITE_REG(hw
, FCRTH
, hw
->fc
.high_water
);
719 /******************************************************************************
720 * Reads a word from a device over the Management Data Interface (MDI) bus.
721 * This interface is used to manage Physical layer devices.
723 * hw - Struct containing variables accessed by hw code
724 * reg_address - Offset of device register being read.
725 * phy_address - Address of device on MDI.
727 * Returns: Data word (16 bits) from MDI device.
729 * The 82597EX has support for several MDI access methods. This routine
730 * uses the new protocol MDI Single Command and Address Operation.
731 * This requires that first an address cycle command is sent, followed by a
733 *****************************************************************************/
735 ixgb_read_phy_reg(struct ixgb_hw
*hw
,
744 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
745 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
746 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
748 /* Setup and write the address cycle command */
749 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
750 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
751 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
752 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
754 IXGB_WRITE_REG(hw
, MSCA
, command
);
756 /**************************************************************
757 ** Check every 10 usec to see if the address cycle completed
758 ** The COMMAND bit will clear when the operation is complete.
759 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
760 ** from the CPU Write to the Ready bit assertion.
761 **************************************************************/
763 for (i
= 0; i
< 10; i
++)
767 command
= IXGB_READ_REG(hw
, MSCA
);
769 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
773 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
775 /* Address cycle complete, setup and write the read command */
776 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
777 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
778 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
779 (IXGB_MSCA_READ
| IXGB_MSCA_MDI_COMMAND
));
781 IXGB_WRITE_REG(hw
, MSCA
, command
);
783 /**************************************************************
784 ** Check every 10 usec to see if the read command completed
785 ** The COMMAND bit will clear when the operation is complete.
786 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
787 ** from the CPU Write to the Ready bit assertion.
788 **************************************************************/
790 for (i
= 0; i
< 10; i
++)
794 command
= IXGB_READ_REG(hw
, MSCA
);
796 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
800 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
802 /* Operation is complete, get the data from the MDIO Read/Write Data
803 * register and return.
805 data
= IXGB_READ_REG(hw
, MSRWD
);
806 data
>>= IXGB_MSRWD_READ_DATA_SHIFT
;
810 /******************************************************************************
811 * Writes a word to a device over the Management Data Interface (MDI) bus.
812 * This interface is used to manage Physical layer devices.
814 * hw - Struct containing variables accessed by hw code
815 * reg_address - Offset of device register being read.
816 * phy_address - Address of device on MDI.
817 * device_type - Also known as the Device ID or DID.
818 * data - 16-bit value to be written
822 * The 82597EX has support for several MDI access methods. This routine
823 * uses the new protocol MDI Single Command and Address Operation.
824 * This requires that first an address cycle command is sent, followed by a
826 *****************************************************************************/
828 ixgb_write_phy_reg(struct ixgb_hw
*hw
,
837 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
838 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
839 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
841 /* Put the data in the MDIO Read/Write Data register */
842 IXGB_WRITE_REG(hw
, MSRWD
, (u32
)data
);
844 /* Setup and write the address cycle command */
845 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
846 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
847 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
848 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
850 IXGB_WRITE_REG(hw
, MSCA
, command
);
852 /**************************************************************
853 ** Check every 10 usec to see if the address cycle completed
854 ** The COMMAND bit will clear when the operation is complete.
855 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
856 ** from the CPU Write to the Ready bit assertion.
857 **************************************************************/
859 for (i
= 0; i
< 10; i
++)
863 command
= IXGB_READ_REG(hw
, MSCA
);
865 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
869 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
871 /* Address cycle complete, setup and write the write command */
872 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
873 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
874 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
875 (IXGB_MSCA_WRITE
| IXGB_MSCA_MDI_COMMAND
));
877 IXGB_WRITE_REG(hw
, MSCA
, command
);
879 /**************************************************************
880 ** Check every 10 usec to see if the read command completed
881 ** The COMMAND bit will clear when the operation is complete.
882 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
883 ** from the CPU Write to the Ready bit assertion.
884 **************************************************************/
886 for (i
= 0; i
< 10; i
++)
890 command
= IXGB_READ_REG(hw
, MSCA
);
892 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
896 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
898 /* Operation is complete, return. */
901 /******************************************************************************
902 * Checks to see if the link status of the hardware has changed.
904 * hw - Struct containing variables accessed by hw code
906 * Called by any function that needs to check the link status of the adapter.
907 *****************************************************************************/
909 ixgb_check_for_link(struct ixgb_hw
*hw
)
916 xpcss_reg
= IXGB_READ_REG(hw
, XPCSS
);
917 status_reg
= IXGB_READ_REG(hw
, STATUS
);
919 if ((xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
920 (status_reg
& IXGB_STATUS_LU
)) {
922 } else if (!(xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
923 (status_reg
& IXGB_STATUS_LU
)) {
924 pr_debug("XPCSS Not Aligned while Status:LU is set\n");
925 hw
->link_up
= ixgb_link_reset(hw
);
928 * 82597EX errata. Since the lane deskew problem may prevent
929 * link, reset the link before reporting link down.
931 hw
->link_up
= ixgb_link_reset(hw
);
933 /* Anything else for 10 Gig?? */
936 /******************************************************************************
937 * Check for a bad link condition that may have occurred.
938 * The indication is that the RFC / LFC registers may be incrementing
939 * continually. A full adapter reset is required to recover.
941 * hw - Struct containing variables accessed by hw code
943 * Called by any function that needs to check the link status of the adapter.
944 *****************************************************************************/
945 bool ixgb_check_for_bad_link(struct ixgb_hw
*hw
)
948 bool bad_link_returncode
= false;
950 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
951 newLFC
= IXGB_READ_REG(hw
, LFC
);
952 newRFC
= IXGB_READ_REG(hw
, RFC
);
953 if ((hw
->lastLFC
+ 250 < newLFC
)
954 || (hw
->lastRFC
+ 250 < newRFC
)) {
955 pr_debug("BAD LINK! too many LFC/RFC since last check\n");
956 bad_link_returncode
= true;
958 hw
->lastLFC
= newLFC
;
959 hw
->lastRFC
= newRFC
;
962 return bad_link_returncode
;
965 /******************************************************************************
966 * Clears all hardware statistics counters.
968 * hw - Struct containing variables accessed by shared code
969 *****************************************************************************/
971 ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
)
973 volatile u32 temp_reg
;
977 /* if we are stopped or resetting exit gracefully */
978 if (hw
->adapter_stopped
) {
979 pr_debug("Exiting because the adapter is stopped!!!\n");
983 temp_reg
= IXGB_READ_REG(hw
, TPRL
);
984 temp_reg
= IXGB_READ_REG(hw
, TPRH
);
985 temp_reg
= IXGB_READ_REG(hw
, GPRCL
);
986 temp_reg
= IXGB_READ_REG(hw
, GPRCH
);
987 temp_reg
= IXGB_READ_REG(hw
, BPRCL
);
988 temp_reg
= IXGB_READ_REG(hw
, BPRCH
);
989 temp_reg
= IXGB_READ_REG(hw
, MPRCL
);
990 temp_reg
= IXGB_READ_REG(hw
, MPRCH
);
991 temp_reg
= IXGB_READ_REG(hw
, UPRCL
);
992 temp_reg
= IXGB_READ_REG(hw
, UPRCH
);
993 temp_reg
= IXGB_READ_REG(hw
, VPRCL
);
994 temp_reg
= IXGB_READ_REG(hw
, VPRCH
);
995 temp_reg
= IXGB_READ_REG(hw
, JPRCL
);
996 temp_reg
= IXGB_READ_REG(hw
, JPRCH
);
997 temp_reg
= IXGB_READ_REG(hw
, GORCL
);
998 temp_reg
= IXGB_READ_REG(hw
, GORCH
);
999 temp_reg
= IXGB_READ_REG(hw
, TORL
);
1000 temp_reg
= IXGB_READ_REG(hw
, TORH
);
1001 temp_reg
= IXGB_READ_REG(hw
, RNBC
);
1002 temp_reg
= IXGB_READ_REG(hw
, RUC
);
1003 temp_reg
= IXGB_READ_REG(hw
, ROC
);
1004 temp_reg
= IXGB_READ_REG(hw
, RLEC
);
1005 temp_reg
= IXGB_READ_REG(hw
, CRCERRS
);
1006 temp_reg
= IXGB_READ_REG(hw
, ICBC
);
1007 temp_reg
= IXGB_READ_REG(hw
, ECBC
);
1008 temp_reg
= IXGB_READ_REG(hw
, MPC
);
1009 temp_reg
= IXGB_READ_REG(hw
, TPTL
);
1010 temp_reg
= IXGB_READ_REG(hw
, TPTH
);
1011 temp_reg
= IXGB_READ_REG(hw
, GPTCL
);
1012 temp_reg
= IXGB_READ_REG(hw
, GPTCH
);
1013 temp_reg
= IXGB_READ_REG(hw
, BPTCL
);
1014 temp_reg
= IXGB_READ_REG(hw
, BPTCH
);
1015 temp_reg
= IXGB_READ_REG(hw
, MPTCL
);
1016 temp_reg
= IXGB_READ_REG(hw
, MPTCH
);
1017 temp_reg
= IXGB_READ_REG(hw
, UPTCL
);
1018 temp_reg
= IXGB_READ_REG(hw
, UPTCH
);
1019 temp_reg
= IXGB_READ_REG(hw
, VPTCL
);
1020 temp_reg
= IXGB_READ_REG(hw
, VPTCH
);
1021 temp_reg
= IXGB_READ_REG(hw
, JPTCL
);
1022 temp_reg
= IXGB_READ_REG(hw
, JPTCH
);
1023 temp_reg
= IXGB_READ_REG(hw
, GOTCL
);
1024 temp_reg
= IXGB_READ_REG(hw
, GOTCH
);
1025 temp_reg
= IXGB_READ_REG(hw
, TOTL
);
1026 temp_reg
= IXGB_READ_REG(hw
, TOTH
);
1027 temp_reg
= IXGB_READ_REG(hw
, DC
);
1028 temp_reg
= IXGB_READ_REG(hw
, PLT64C
);
1029 temp_reg
= IXGB_READ_REG(hw
, TSCTC
);
1030 temp_reg
= IXGB_READ_REG(hw
, TSCTFC
);
1031 temp_reg
= IXGB_READ_REG(hw
, IBIC
);
1032 temp_reg
= IXGB_READ_REG(hw
, RFC
);
1033 temp_reg
= IXGB_READ_REG(hw
, LFC
);
1034 temp_reg
= IXGB_READ_REG(hw
, PFRC
);
1035 temp_reg
= IXGB_READ_REG(hw
, PFTC
);
1036 temp_reg
= IXGB_READ_REG(hw
, MCFRC
);
1037 temp_reg
= IXGB_READ_REG(hw
, MCFTC
);
1038 temp_reg
= IXGB_READ_REG(hw
, XONRXC
);
1039 temp_reg
= IXGB_READ_REG(hw
, XONTXC
);
1040 temp_reg
= IXGB_READ_REG(hw
, XOFFRXC
);
1041 temp_reg
= IXGB_READ_REG(hw
, XOFFTXC
);
1042 temp_reg
= IXGB_READ_REG(hw
, RJC
);
1045 /******************************************************************************
1046 * Turns on the software controllable LED
1048 * hw - Struct containing variables accessed by shared code
1049 *****************************************************************************/
1051 ixgb_led_on(struct ixgb_hw
*hw
)
1053 u32 ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1055 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1056 ctrl0_reg
&= ~IXGB_CTRL0_SDP0
;
1057 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1060 /******************************************************************************
1061 * Turns off the software controllable LED
1063 * hw - Struct containing variables accessed by shared code
1064 *****************************************************************************/
1066 ixgb_led_off(struct ixgb_hw
*hw
)
1068 u32 ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1070 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1071 ctrl0_reg
|= IXGB_CTRL0_SDP0
;
1072 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1075 /******************************************************************************
1076 * Gets the current PCI bus type, speed, and width of the hardware
1078 * hw - Struct containing variables accessed by shared code
1079 *****************************************************************************/
1081 ixgb_get_bus_info(struct ixgb_hw
*hw
)
1085 status_reg
= IXGB_READ_REG(hw
, STATUS
);
1087 hw
->bus
.type
= (status_reg
& IXGB_STATUS_PCIX_MODE
) ?
1088 ixgb_bus_type_pcix
: ixgb_bus_type_pci
;
1090 if (hw
->bus
.type
== ixgb_bus_type_pci
) {
1091 hw
->bus
.speed
= (status_reg
& IXGB_STATUS_PCI_SPD
) ?
1092 ixgb_bus_speed_66
: ixgb_bus_speed_33
;
1094 switch (status_reg
& IXGB_STATUS_PCIX_SPD_MASK
) {
1095 case IXGB_STATUS_PCIX_SPD_66
:
1096 hw
->bus
.speed
= ixgb_bus_speed_66
;
1098 case IXGB_STATUS_PCIX_SPD_100
:
1099 hw
->bus
.speed
= ixgb_bus_speed_100
;
1101 case IXGB_STATUS_PCIX_SPD_133
:
1102 hw
->bus
.speed
= ixgb_bus_speed_133
;
1105 hw
->bus
.speed
= ixgb_bus_speed_reserved
;
1110 hw
->bus
.width
= (status_reg
& IXGB_STATUS_BUS64
) ?
1111 ixgb_bus_width_64
: ixgb_bus_width_32
;
1114 /******************************************************************************
1115 * Tests a MAC address to ensure it is a valid Individual Address
1117 * mac_addr - pointer to MAC address.
1119 *****************************************************************************/
1121 mac_addr_valid(u8
*mac_addr
)
1123 bool is_valid
= true;
1126 /* Make sure it is not a multicast address */
1127 if (is_multicast_ether_addr(mac_addr
)) {
1128 pr_debug("MAC address is multicast\n");
1131 /* Not a broadcast address */
1132 else if (is_broadcast_ether_addr(mac_addr
)) {
1133 pr_debug("MAC address is broadcast\n");
1136 /* Reject the zero address */
1137 else if (is_zero_ether_addr(mac_addr
)) {
1138 pr_debug("MAC address is all zeros\n");
1144 /******************************************************************************
1145 * Resets the 10GbE link. Waits the settle time and returns the state of
1148 * hw - Struct containing variables accessed by shared code
1149 *****************************************************************************/
1151 ixgb_link_reset(struct ixgb_hw
*hw
)
1153 bool link_status
= false;
1154 u8 wait_retries
= MAX_RESET_ITERATIONS
;
1155 u8 lrst_retries
= MAX_RESET_ITERATIONS
;
1158 /* Reset the link */
1159 IXGB_WRITE_REG(hw
, CTRL0
,
1160 IXGB_READ_REG(hw
, CTRL0
) | IXGB_CTRL0_LRST
);
1162 /* Wait for link-up and lane re-alignment */
1164 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET
);
1166 ((IXGB_READ_REG(hw
, STATUS
) & IXGB_STATUS_LU
)
1167 && (IXGB_READ_REG(hw
, XPCSS
) &
1168 IXGB_XPCSS_ALIGN_STATUS
)) ? true : false;
1169 } while (!link_status
&& --wait_retries
);
1171 } while (!link_status
&& --lrst_retries
);
1176 /******************************************************************************
1177 * Resets the 10GbE optics module.
1179 * hw - Struct containing variables accessed by shared code
1180 *****************************************************************************/
1182 ixgb_optics_reset(struct ixgb_hw
*hw
)
1184 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
1187 ixgb_write_phy_reg(hw
,
1193 mdio_reg
= ixgb_read_phy_reg(hw
,
1200 /******************************************************************************
1201 * Resets the 10GbE optics module for Sun variant NIC.
1203 * hw - Struct containing variables accessed by shared code
1204 *****************************************************************************/
1206 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1207 #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1208 #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1209 #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1210 #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1211 #define IXGB_SUN_PHY_ADDRESS 0x0000
1212 #define IXGB_SUN_PHY_RESET_DELAY 305
1215 ixgb_optics_reset_bcm(struct ixgb_hw
*hw
)
1217 u32 ctrl
= IXGB_READ_REG(hw
, CTRL0
);
1218 ctrl
&= ~IXGB_CTRL0_SDP2
;
1219 ctrl
|= IXGB_CTRL0_SDP3
;
1220 IXGB_WRITE_REG(hw
, CTRL0
, ctrl
);
1222 /* SerDes needs extra delay */
1223 msleep(IXGB_SUN_PHY_RESET_DELAY
);
1225 /* Broadcom 7408L configuration */
1226 /* Reference clock config */
1227 ixgb_write_phy_reg(hw
,
1228 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1229 IXGB_SUN_PHY_ADDRESS
,
1230 IXGB_BCM8704_USER_DEV3_ADDR
,
1231 IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL
);
1232 /* we must read the registers twice */
1233 ixgb_read_phy_reg(hw
,
1234 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1235 IXGB_SUN_PHY_ADDRESS
,
1236 IXGB_BCM8704_USER_DEV3_ADDR
);
1237 ixgb_read_phy_reg(hw
,
1238 IXGB_BCM8704_USER_PMD_TX_CTRL_REG
,
1239 IXGB_SUN_PHY_ADDRESS
,
1240 IXGB_BCM8704_USER_DEV3_ADDR
);
1242 ixgb_write_phy_reg(hw
,
1243 IXGB_BCM8704_USER_CTRL_REG
,
1244 IXGB_SUN_PHY_ADDRESS
,
1245 IXGB_BCM8704_USER_DEV3_ADDR
,
1246 IXGB_BCM8704_USER_CTRL_REG_VAL
);
1247 ixgb_read_phy_reg(hw
,
1248 IXGB_BCM8704_USER_CTRL_REG
,
1249 IXGB_SUN_PHY_ADDRESS
,
1250 IXGB_BCM8704_USER_DEV3_ADDR
);
1251 ixgb_read_phy_reg(hw
,
1252 IXGB_BCM8704_USER_CTRL_REG
,
1253 IXGB_SUN_PHY_ADDRESS
,
1254 IXGB_BCM8704_USER_DEV3_ADDR
);
1256 /* SerDes needs extra delay */
1257 msleep(IXGB_SUN_PHY_RESET_DELAY
);