?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / media / video / arv.c
blob372a1b09b1d256c0d0ce673ad16806623348842d
1 /*
2 * Colour AR M64278(VGA) driver for Video4Linux
3 *
4 * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Some code is taken from AR driver sample program for M3T-M32700UT.
12 *
13 * AR driver sample (M32R SDK):
14 * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
15 * AND RENESAS SOLUTIONS CORPORATION
16 * All Rights Reserved.
17 *
18 * 2003-09-01: Support w3cam by Takeo Takahashi
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/fs.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/mm.h>
29 #include <linux/sched.h>
30 #include <linux/version.h>
31 #include <linux/videodev2.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-ioctl.h>
35 #include <linux/mutex.h>
36
37 #include <asm/uaccess.h>
38 #include <asm/m32r.h>
39 #include <asm/io.h>
40 #include <asm/dma.h>
41 #include <asm/byteorder.h>
42
43 #define DEBUG(n, args...)
44 #define CHECK_LOST 0
45
46 /*
47 * USE_INT is always 0, interrupt mode is not available
48 * on linux due to lack of speed
49 */
50 #define USE_INT 0 /* Don't modify */
51
52 #define VERSION "0.04"
53
54 #define ar_inl(addr) inl((unsigned long)(addr))
55 #define ar_outl(val, addr) outl((unsigned long)(val), (unsigned long)(addr))
56
57 extern struct cpuinfo_m32r boot_cpu_data;
58
59 /*
60 * CCD pixel size
61 * Note that M32700UT does not support CIF mode, but QVGA is
62 * supported by M32700UT hardware using VGA mode of AR LSI.
63 *
64 * Supported: VGA (Normal mode, Interlace mode)
65 * QVGA (Always Interlace mode of VGA)
66 *
67 */
68 #define AR_WIDTH_VGA 640
69 #define AR_HEIGHT_VGA 480
70 #define AR_WIDTH_QVGA 320
71 #define AR_HEIGHT_QVGA 240
72 #define MIN_AR_WIDTH AR_WIDTH_QVGA
73 #define MIN_AR_HEIGHT AR_HEIGHT_QVGA
74 #define MAX_AR_WIDTH AR_WIDTH_VGA
75 #define MAX_AR_HEIGHT AR_HEIGHT_VGA
76
77 /* bits & bytes per pixel */
78 #define AR_BITS_PER_PIXEL 16
79 #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL / 8)
80
81 /* line buffer size */
82 #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
83 #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
84 #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
85
86 /* frame size & type */
87 #define AR_FRAME_BYTES_VGA \
88 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
89 #define AR_FRAME_BYTES_QVGA \
90 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
91 #define MAX_AR_FRAME_BYTES \
92 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
93
94 #define AR_MAX_FRAME 15
95
96 /* capture size */
97 #define AR_SIZE_VGA 0
98 #define AR_SIZE_QVGA 1
99
100 /* capture mode */
101 #define AR_MODE_INTERLACE 0
102 #define AR_MODE_NORMAL 1
103
104 struct ar {
105 struct v4l2_device v4l2_dev;
106 struct video_device vdev;
107 unsigned int start_capture; /* duaring capture in INT. mode. */
108 #if USE_INT
109 unsigned char *line_buff; /* DMA line buffer */
110 #endif
111 unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
112 short size; /* capture size */
113 short mode; /* capture mode */
114 int width, height;
115 int frame_bytes, line_bytes;
116 wait_queue_head_t wait;
117 struct mutex lock;
118 };
119
120 static struct ar ardev;
121
122 static int video_nr = -1; /* video device number (first free) */
123 static unsigned char yuv[MAX_AR_FRAME_BYTES];
124
125 /* module parameters */
126 /* default frequency */
127 #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
128 static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
129 static int vga; /* default mode(0:QVGA mode, other:VGA mode) */
130 static int vga_interlace; /* 0 is normal mode for, else interlace mode */
131 module_param(freq, int, 0);
132 module_param(vga, int, 0);
133 module_param(vga_interlace, int, 0);
134
135 static void wait_for_vsync(void)
136 {
137 while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
138 cpu_relax();
139 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
140 cpu_relax();
141 }
142
143 static void wait_acknowledge(void)
144 {
145 int i;
146
147 for (i = 0; i < 1000; i++)
148 cpu_relax();
149 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
150 cpu_relax();
151 }
152
153 /*******************************************************************
154 * I2C functions
155 *******************************************************************/
156 static void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
157 unsigned long data3)
158 {
159 int i;
160
161 /* Slave Address */
162 ar_outl(addr, PLDI2CDATA);
163 wait_for_vsync();
164
165 /* Start */
166 ar_outl(1, PLDI2CCND);
167 wait_acknowledge();
168
169 /* Transfer data 1 */
170 ar_outl(data1, PLDI2CDATA);
171 wait_for_vsync();
172 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
173 wait_acknowledge();
174
175 /* Transfer data 2 */
176 ar_outl(data2, PLDI2CDATA);
177 wait_for_vsync();
178 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
179 wait_acknowledge();
180
181 if (n == 3) {
182 /* Transfer data 3 */
183 ar_outl(data3, PLDI2CDATA);
184 wait_for_vsync();
185 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
186 wait_acknowledge();
187 }
188
189 /* Stop */
190 for (i = 0; i < 100; i++)
191 cpu_relax();
192 ar_outl(2, PLDI2CCND);
193 ar_outl(2, PLDI2CCND);
194
195 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
196 cpu_relax();
197 }
198
199
200 static void init_iic(void)
201 {
202 DEBUG(1, "init_iic:\n");
203
204 /*
205 * ICU Setting (iic)
206 */
207 /* I2C Setting */
208 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
209 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
210 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
211
212 /* I2C CLK */
213 /* 50MH-100k */
214 if (freq == 75)
215 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
216 else if (freq == 50)
217 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
218 else
219 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
220 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
221 }
222
223 /**************************************************************************
224 *
225 * Video4Linux Interface functions
226 *
227 **************************************************************************/
228
229 static inline void disable_dma(void)
230 {
231 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
232 }
233
234 static inline void enable_dma(void)
235 {
236 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
237 }
238
239 static inline void clear_dma_status(void)
240 {
241 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
242 }
243
244 static void wait_for_vertical_sync(struct ar *ar, int exp_line)
245 {
246 #if CHECK_LOST
247 int tmout = 10000;
248 int l;
249
250 /*
251 * check HCOUNT because we cannot check vertical sync.
252 */
253 for (; tmout >= 0; tmout--) {
254 l = ar_inl(ARVHCOUNT);
255 if (l == exp_line)
256 break;
257 }
258 if (tmout < 0)
259 v4l2_err(&ar->v4l2_dev, "lost %d -> %d\n", exp_line, l);
260 #else
261 while (ar_inl(ARVHCOUNT) != exp_line)
262 cpu_relax();
263 #endif
264 }
265
266 static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
267 {
268 struct ar *ar = video_drvdata(file);
269 long ret = ar->frame_bytes; /* return read bytes */
270 unsigned long arvcr1 = 0;
271 unsigned long flags;
272 unsigned char *p;
273 int h, w;
274 unsigned char *py, *pu, *pv;
275 #if !USE_INT
276 int l;
277 #endif
278
279 DEBUG(1, "ar_read()\n");
280
281 if (ar->size == AR_SIZE_QVGA)
282 arvcr1 |= ARVCR1_QVGA;
283 if (ar->mode == AR_MODE_NORMAL)
284 arvcr1 |= ARVCR1_NORMAL;
285
286 mutex_lock(&ar->lock);
287
288 #if USE_INT
289 local_irq_save(flags);
290 disable_dma();
291 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
292 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
293
294 /* set AR FIFO address as source(BSEL5) */
295 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
296 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
297 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
298 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
299 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
300 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
301
302 /*
303 * Okay, kick AR LSI to invoke an interrupt
304 */
305 ar->start_capture = 0;
306 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
307 local_irq_restore(flags);
308 /* .... AR interrupts .... */
309 interruptible_sleep_on(&ar->wait);
310 if (signal_pending(current)) {
311 printk(KERN_ERR "arv: interrupted while get frame data.\n");
312 ret = -EINTR;
313 goto out_up;
314 }
315 #else /* ! USE_INT */
316 /* polling */
317 ar_outl(arvcr1, ARVCR1);
318 disable_dma();
319 ar_outl(0x8000, M32R_DMAEDET_PORTL);
320 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
321 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
322 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
323 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
324 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
325 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
326
327 local_irq_save(flags);
328 while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
329 cpu_relax();
330 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
331 for (h = 0; h < ar->height; h++) {
332 wait_for_vertical_sync(ar, h);
333 if (h < (AR_HEIGHT_VGA/2))
334 l = h << 1;
335 else
336 l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
337 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
338 enable_dma();
339 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
340 cpu_relax();
341 disable_dma();
342 clear_dma_status();
343 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
344 }
345 } else {
346 for (h = 0; h < ar->height; h++) {
347 wait_for_vertical_sync(ar, h);
348 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
349 enable_dma();
350 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
351 cpu_relax();
352 disable_dma();
353 clear_dma_status();
354 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
355 }
356 }
357 local_irq_restore(flags);
358 #endif /* ! USE_INT */
359
360 /*
361 * convert YUV422 to YUV422P
362 * +--------------------+
363 * | Y0,Y1,... |
364 * | ..............Yn |
365 * +--------------------+
366 * | U0,U1,........Un |
367 * +--------------------+
368 * | V0,V1,........Vn |
369 * +--------------------+
370 */
371 py = yuv;
372 pu = py + (ar->frame_bytes / 2);
373 pv = pu + (ar->frame_bytes / 4);
374 for (h = 0; h < ar->height; h++) {
375 p = ar->frame[h];
376 for (w = 0; w < ar->line_bytes; w += 4) {
377 *py++ = *p++;
378 *pu++ = *p++;
379 *py++ = *p++;
380 *pv++ = *p++;
381 }
382 }
383 if (copy_to_user(buf, yuv, ar->frame_bytes)) {
384 v4l2_err(&ar->v4l2_dev, "failed while copy_to_user yuv.\n");
385 ret = -EFAULT;
386 goto out_up;
387 }
388 DEBUG(1, "ret = %d\n", ret);
389 out_up:
390 mutex_unlock(&ar->lock);
391 return ret;
392 }
393
394 static int ar_querycap(struct file *file, void *priv,
395 struct v4l2_capability *vcap)
396 {
397 struct ar *ar = video_drvdata(file);
398
399 strlcpy(vcap->driver, ar->vdev.name, sizeof(vcap->driver));
400 strlcpy(vcap->card, "Colour AR VGA", sizeof(vcap->card));
401 strlcpy(vcap->bus_info, "Platform", sizeof(vcap->bus_info));
402 vcap->version = KERNEL_VERSION(0, 0, 4);
403 vcap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE;
404 return 0;
405 }
406
407 static int ar_enum_input(struct file *file, void *fh, struct v4l2_input *vin)
408 {
409 if (vin->index > 0)
410 return -EINVAL;
411 strlcpy(vin->name, "Camera", sizeof(vin->name));
412 vin->type = V4L2_INPUT_TYPE_CAMERA;
413 vin->audioset = 0;
414 vin->tuner = 0;
415 vin->std = V4L2_STD_ALL;
416 vin->status = 0;
417 return 0;
418 }
419
420 static int ar_g_input(struct file *file, void *fh, unsigned int *inp)
421 {
422 *inp = 0;
423 return 0;
424 }
425
426 static int ar_s_input(struct file *file, void *fh, unsigned int inp)
427 {
428 return inp ? -EINVAL : 0;
429 }
430
431 static int ar_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
432 {
433 struct ar *ar = video_drvdata(file);
434 struct v4l2_pix_format *pix = &fmt->fmt.pix;
435
436 pix->width = ar->width;
437 pix->height = ar->height;
438 pix->pixelformat = V4L2_PIX_FMT_YUV422P;
439 pix->field = (ar->mode == AR_MODE_NORMAL) ? V4L2_FIELD_NONE : V4L2_FIELD_INTERLACED;
440 pix->bytesperline = ar->width;
441 pix->sizeimage = 2 * ar->width * ar->height;
442 /* Just a guess */
443 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
444 return 0;
445 }
446
447 static int ar_try_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
448 {
449 struct ar *ar = video_drvdata(file);
450 struct v4l2_pix_format *pix = &fmt->fmt.pix;
451
452 if (pix->height <= AR_HEIGHT_QVGA || pix->width <= AR_WIDTH_QVGA) {
453 pix->height = AR_HEIGHT_QVGA;
454 pix->width = AR_WIDTH_QVGA;
455 pix->field = V4L2_FIELD_INTERLACED;
456 } else {
457 pix->height = AR_HEIGHT_VGA;
458 pix->width = AR_WIDTH_VGA;
459 pix->field = vga_interlace ? V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
460 }
461 pix->pixelformat = V4L2_PIX_FMT_YUV422P;
462 pix->bytesperline = ar->width;
463 pix->sizeimage = 2 * ar->width * ar->height;
464 /* Just a guess */
465 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
466 return 0;
467 }
468
469 static int ar_s_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
470 {
471 struct ar *ar = video_drvdata(file);
472 struct v4l2_pix_format *pix = &fmt->fmt.pix;
473 int ret = ar_try_fmt_vid_cap(file, fh, fmt);
474
475 if (ret)
476 return ret;
477 mutex_lock(&ar->lock);
478 ar->width = pix->width;
479 ar->height = pix->height;
480 if (ar->width == AR_WIDTH_VGA) {
481 ar->size = AR_SIZE_VGA;
482 ar->frame_bytes = AR_FRAME_BYTES_VGA;
483 ar->line_bytes = AR_LINE_BYTES_VGA;
484 if (vga_interlace)
485 ar->mode = AR_MODE_INTERLACE;
486 else
487 ar->mode = AR_MODE_NORMAL;
488 } else {
489 ar->size = AR_SIZE_QVGA;
490 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
491 ar->line_bytes = AR_LINE_BYTES_QVGA;
492 ar->mode = AR_MODE_INTERLACE;
493 }
494 /* Ok we figured out what to use from our wide choice */
495 mutex_unlock(&ar->lock);
496 return 0;
497 }
498
499 static int ar_enum_fmt_vid_cap(struct file *file, void *fh, struct v4l2_fmtdesc *fmt)
500 {
501 static struct v4l2_fmtdesc formats[] = {
502 { 0, 0, 0,
503 "YUV 4:2:2 Planar", V4L2_PIX_FMT_YUV422P,
504 { 0, 0, 0, 0 }
505 },
506 };
507 enum v4l2_buf_type type = fmt->type;
508
509 if (fmt->index > 0)
510 return -EINVAL;
511
512 *fmt = formats[fmt->index];
513 fmt->type = type;
514 return 0;
515 }
516
517 #if USE_INT
518 /*
519 * Interrupt handler
520 */
521 static void ar_interrupt(int irq, void *dev)
522 {
523 struct ar *ar = dev;
524 unsigned int line_count;
525 unsigned int line_number;
526 unsigned int arvcr1;
527
528 line_count = ar_inl(ARVHCOUNT); /* line number */
529 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
530 /* operations for interlace mode */
531 if (line_count < (AR_HEIGHT_VGA / 2)) /* even line */
532 line_number = (line_count << 1);
533 else /* odd line */
534 line_number =
535 (((line_count - (AR_HEIGHT_VGA / 2)) << 1) + 1);
536 } else {
537 line_number = line_count;
538 }
539
540 if (line_number == 0) {
541 /*
542 * It is an interrupt for line 0.
543 * we have to start capture.
544 */
545 disable_dma();
546 memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
547 enable_dma();
548 ar->start_capture = 1; /* during capture */
549 return;
550 }
551
552 if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
553 disable_dma();
554 memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
555
556 /*
557 * if captured all line of a frame, disable AR interrupt
558 * and wake a process up.
559 */
560 if (line_number == (ar->height - 1)) { /* end of line */
561
562 ar->start_capture = 0;
563
564 /* disable AR interrupt request */
565 arvcr1 = ar_inl(ARVCR1);
566 arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
567 ar_outl(arvcr1, ARVCR1); /* disable */
568 wake_up_interruptible(&ar->wait);
569 } else {
570 enable_dma();
571 }
572 }
573 }
574 #endif
575
576 /*
577 * ar_initialize()
578 * ar_initialize() is called by video_register_device() and
579 * initializes AR LSI and peripherals.
580 *
581 * -1 is returned in all failures.
582 * 0 is returned in success.
583 *
584 */
585 static int ar_initialize(struct ar *ar)
586 {
587 unsigned long cr = 0;
588 int i, found = 0;
589
590 DEBUG(1, "ar_initialize:\n");
591
592 /*
593 * initialize AR LSI
594 */
595 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
596 for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
597 cpu_relax();
598 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
599 for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
600 cpu_relax();
601
602 /* AR uses INT3 of CPU as interrupt pin. */
603 ar_outl(ARINTSEL_INT3, ARINTSEL);
604
605 if (ar->size == AR_SIZE_QVGA)
606 cr |= ARVCR1_QVGA;
607 if (ar->mode == AR_MODE_NORMAL)
608 cr |= ARVCR1_NORMAL;
609 ar_outl(cr, ARVCR1);
610
611 /*
612 * Initialize IIC so that CPU can communicate with AR LSI,
613 * and send boot commands to AR LSI.
614 */
615 init_iic();
616
617 for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
618 if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
619 found = 1;
620 break;
621 }
622 }
623
624 if (found == 0)
625 return -ENODEV;
626
627 v4l2_info(&ar->v4l2_dev, "Initializing ");
628
629 iic(2, 0x78, 0x11, 0x01, 0x00); /* start */
630 iic(3, 0x78, 0x12, 0x00, 0x06);
631 iic(3, 0x78, 0x12, 0x12, 0x30);
632 iic(3, 0x78, 0x12, 0x15, 0x58);
633 iic(3, 0x78, 0x12, 0x17, 0x30);
634 printk(KERN_CONT ".");
635 iic(3, 0x78, 0x12, 0x1a, 0x97);
636 iic(3, 0x78, 0x12, 0x1b, 0xff);
637 iic(3, 0x78, 0x12, 0x1c, 0xff);
638 iic(3, 0x78, 0x12, 0x26, 0x10);
639 iic(3, 0x78, 0x12, 0x27, 0x00);
640 printk(KERN_CONT ".");
641 iic(2, 0x78, 0x34, 0x02, 0x00);
642 iic(2, 0x78, 0x7a, 0x10, 0x00);
643 iic(2, 0x78, 0x80, 0x39, 0x00);
644 iic(2, 0x78, 0x81, 0xe6, 0x00);
645 iic(2, 0x78, 0x8d, 0x00, 0x00);
646 printk(KERN_CONT ".");
647 iic(2, 0x78, 0x8e, 0x0c, 0x00);
648 iic(2, 0x78, 0x8f, 0x00, 0x00);
649 iic(2, 0x78, 0x93, 0x01, 0x00);
650 iic(2, 0x78, 0x94, 0xcd, 0x00);
651 iic(2, 0x78, 0x95, 0x00, 0x00);
652 printk(KERN_CONT ".");
653 iic(2, 0x78, 0x96, 0xa0, 0x00);
654 iic(2, 0x78, 0x97, 0x00, 0x00);
655 iic(2, 0x78, 0x98, 0x60, 0x00);
656 iic(2, 0x78, 0x99, 0x01, 0x00);
657 iic(2, 0x78, 0x9a, 0x19, 0x00);
658 printk(KERN_CONT ".");
659 iic(2, 0x78, 0x9b, 0x02, 0x00);
660 iic(2, 0x78, 0x9c, 0xe8, 0x00);
661 iic(2, 0x78, 0x9d, 0x02, 0x00);
662 iic(2, 0x78, 0x9e, 0x2e, 0x00);
663 iic(2, 0x78, 0xb8, 0x78, 0x00);
664 iic(2, 0x78, 0xba, 0x05, 0x00);
665 printk(KERN_CONT ".");
666
667 /* color correction */
668 iic(3, 0x78, 0x49, 0x00, 0x95); /* a */
669 iic(3, 0x78, 0x49, 0x01, 0x96); /* b */
670 iic(3, 0x78, 0x49, 0x03, 0x85); /* c */
671 iic(3, 0x78, 0x49, 0x04, 0x97); /* d */
672 iic(3, 0x78, 0x49, 0x02, 0x7e); /* e(Lo) */
673 iic(3, 0x78, 0x49, 0x05, 0xa4); /* f(Lo) */
674 iic(3, 0x78, 0x49, 0x06, 0x04); /* e(Hi) */
675 iic(3, 0x78, 0x49, 0x07, 0x04); /* e(Hi) */
676 iic(2, 0x78, 0x48, 0x01, 0x00); /* on=1 off=0 */
677
678 printk(KERN_CONT ".");
679 iic(2, 0x78, 0x11, 0x00, 0x00); /* end */
680 printk(KERN_CONT " done\n");
681 return 0;
682 }
683
684
685 /****************************************************************************
686 *
687 * Video4Linux Module functions
688 *
689 ****************************************************************************/
690
691 static const struct v4l2_file_operations ar_fops = {
692 .owner = THIS_MODULE,
693 .read = ar_read,
694 .ioctl = video_ioctl2,
695 };
696
697 static const struct v4l2_ioctl_ops ar_ioctl_ops = {
698 .vidioc_querycap = ar_querycap,
699 .vidioc_g_input = ar_g_input,
700 .vidioc_s_input = ar_s_input,
701 .vidioc_enum_input = ar_enum_input,
702 .vidioc_enum_fmt_vid_cap = ar_enum_fmt_vid_cap,
703 .vidioc_g_fmt_vid_cap = ar_g_fmt_vid_cap,
704 .vidioc_s_fmt_vid_cap = ar_s_fmt_vid_cap,
705 .vidioc_try_fmt_vid_cap = ar_try_fmt_vid_cap,
706 };
707
708 #define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
709
710 static int __init ar_init(void)
711 {
712 struct ar *ar;
713 struct v4l2_device *v4l2_dev;
714 int ret;
715 int i;
716
717 ar = &ardev;
718 v4l2_dev = &ar->v4l2_dev;
719 strlcpy(v4l2_dev->name, "arv", sizeof(v4l2_dev->name));
720 v4l2_info(v4l2_dev, "Colour AR VGA driver %s\n", VERSION);
721
722 ret = v4l2_device_register(NULL, v4l2_dev);
723 if (ret < 0) {
724 v4l2_err(v4l2_dev, "Could not register v4l2_device\n");
725 return ret;
726 }
727 ret = -EIO;
728
729 #if USE_INT
730 /* allocate a DMA buffer for 1 line. */
731 ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
732 if (ar->line_buff == NULL || !ALIGN4(ar->line_buff)) {
733 v4l2_err(v4l2_dev, "buffer allocation failed for DMA.\n");
734 ret = -ENOMEM;
735 goto out_end;
736 }
737 #endif
738 /* allocate buffers for a frame */
739 for (i = 0; i < MAX_AR_HEIGHT; i++) {
740 ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
741 if (ar->frame[i] == NULL || !ALIGN4(ar->frame[i])) {
742 v4l2_err(v4l2_dev, "buffer allocation failed for frame.\n");
743 ret = -ENOMEM;
744 goto out_line_buff;
745 }
746 }
747
748 strlcpy(ar->vdev.name, "Colour AR VGA", sizeof(ar->vdev.name));
749 ar->vdev.v4l2_dev = v4l2_dev;
750 ar->vdev.fops = &ar_fops;
751 ar->vdev.ioctl_ops = &ar_ioctl_ops;
752 ar->vdev.release = video_device_release_empty;
753 video_set_drvdata(&ar->vdev, ar);
754
755 if (vga) {
756 ar->width = AR_WIDTH_VGA;
757 ar->height = AR_HEIGHT_VGA;
758 ar->size = AR_SIZE_VGA;
759 ar->frame_bytes = AR_FRAME_BYTES_VGA;
760 ar->line_bytes = AR_LINE_BYTES_VGA;
761 if (vga_interlace)
762 ar->mode = AR_MODE_INTERLACE;
763 else
764 ar->mode = AR_MODE_NORMAL;
765 } else {
766 ar->width = AR_WIDTH_QVGA;
767 ar->height = AR_HEIGHT_QVGA;
768 ar->size = AR_SIZE_QVGA;
769 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
770 ar->line_bytes = AR_LINE_BYTES_QVGA;
771 ar->mode = AR_MODE_INTERLACE;
772 }
773 mutex_init(&ar->lock);
774 init_waitqueue_head(&ar->wait);
775
776 #if USE_INT
777 if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
778 v4l2_err("request_irq(%d) failed.\n", M32R_IRQ_INT3);
779 ret = -EIO;
780 goto out_irq;
781 }
782 #endif
783
784 if (ar_initialize(ar) != 0) {
785 v4l2_err(v4l2_dev, "M64278 not found.\n");
786 ret = -ENODEV;
787 goto out_dev;
788 }
789
790 /*
791 * ok, we can initialize h/w according to parameters,
792 * so register video device as a frame grabber type.
793 * device is named "video[0-64]".
794 * video_register_device() initializes h/w using ar_initialize().
795 */
796 if (video_register_device(&ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
797 /* return -1, -ENFILE(full) or others */
798 v4l2_err(v4l2_dev, "register video (Colour AR) failed.\n");
799 ret = -ENODEV;
800 goto out_dev;
801 }
802
803 v4l2_info(v4l2_dev, "%s: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
804 video_device_node_name(&ar->vdev), M32R_IRQ_INT3, freq);
805
806 return 0;
807
808 out_dev:
809 #if USE_INT
810 free_irq(M32R_IRQ_INT3, ar);
811
812 out_irq:
813 #endif
814 for (i = 0; i < MAX_AR_HEIGHT; i++)
815 kfree(ar->frame[i]);
816
817 out_line_buff:
818 #if USE_INT
819 kfree(ar->line_buff);
820
821 out_end:
822 #endif
823 v4l2_device_unregister(&ar->v4l2_dev);
824 return ret;
825 }
826
827
828 static int __init ar_init_module(void)
829 {
830 freq = (boot_cpu_data.bus_clock / 1000000);
831 printk(KERN_INFO "arv: Bus clock %d\n", freq);
832 if (freq != 50 && freq != 75)
833 freq = DEFAULT_FREQ;
834 return ar_init();
835 }
836
837 static void __exit ar_cleanup_module(void)
838 {
839 struct ar *ar;
840 int i;
841
842 ar = &ardev;
843 video_unregister_device(&ar->vdev);
844 #if USE_INT
845 free_irq(M32R_IRQ_INT3, ar);
846 #endif
847 for (i = 0; i < MAX_AR_HEIGHT; i++)
848 kfree(ar->frame[i]);
849 #if USE_INT
850 kfree(ar->line_buff);
851 #endif
852 v4l2_device_unregister(&ar->v4l2_dev);
853 }
854
855 module_init(ar_init_module);
856 module_exit(ar_cleanup_module);
857
858 MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
859 MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
860 MODULE_LICENSE("GPL");
Tomato firmware and modifications.