2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include "radeon_drm.h"
31 #include "radeon_reg.h"
33 #include "radeon_asic.h"
36 #include "r200_reg_safe.h"
38 #include "r100_track.h"
40 static int r200_get_vtx_size_0(uint32_t vtx_fmt_0
)
45 if (vtx_fmt_0
& R200_VTX_Z0
)
47 if (vtx_fmt_0
& R200_VTX_W0
)
50 if (vtx_fmt_0
& (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT
))
51 vtx_size
+= (vtx_fmt_0
>> R200_VTX_WEIGHT_COUNT_SHIFT
) & 0x7;
52 if (vtx_fmt_0
& R200_VTX_PV_MATRIX_SEL
)
54 if (vtx_fmt_0
& R200_VTX_N0
)
56 if (vtx_fmt_0
& R200_VTX_POINT_SIZE
)
58 if (vtx_fmt_0
& R200_VTX_DISCRETE_FOG
)
60 if (vtx_fmt_0
& R200_VTX_SHININESS_0
)
62 if (vtx_fmt_0
& R200_VTX_SHININESS_1
)
64 for (i
= 0; i
< 8; i
++) {
65 int color_size
= (vtx_fmt_0
>> (11 + 2*i
)) & 0x3;
68 case 1: vtx_size
++; break;
69 case 2: vtx_size
+= 3; break;
70 case 3: vtx_size
+= 4; break;
73 if (vtx_fmt_0
& R200_VTX_XY1
)
75 if (vtx_fmt_0
& R200_VTX_Z1
)
77 if (vtx_fmt_0
& R200_VTX_W1
)
79 if (vtx_fmt_0
& R200_VTX_N1
)
84 int r200_copy_dma(struct radeon_device
*rdev
,
88 struct radeon_fence
*fence
)
95 /* radeon pitch is /64 */
96 size
= num_pages
<< PAGE_SHIFT
;
97 num_loops
= DIV_ROUND_UP(size
, 0x1FFFFF);
98 r
= radeon_ring_lock(rdev
, num_loops
* 4 + 64);
100 DRM_ERROR("radeon: moving bo (%d).\n", r
);
103 /* Must wait for 2D idle & clean before DMA or hangs might happen */
104 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
105 radeon_ring_write(rdev
, (1 << 16));
106 for (i
= 0; i
< num_loops
; i
++) {
108 if (cur_size
> 0x1FFFFF) {
112 radeon_ring_write(rdev
, PACKET0(0x720, 2));
113 radeon_ring_write(rdev
, src_offset
);
114 radeon_ring_write(rdev
, dst_offset
);
115 radeon_ring_write(rdev
, cur_size
| (1 << 31) | (1 << 30));
116 src_offset
+= cur_size
;
117 dst_offset
+= cur_size
;
119 radeon_ring_write(rdev
, PACKET0(RADEON_WAIT_UNTIL
, 0));
120 radeon_ring_write(rdev
, RADEON_WAIT_DMA_GUI_IDLE
);
122 r
= radeon_fence_emit(rdev
, fence
);
124 radeon_ring_unlock_commit(rdev
);
129 static int r200_get_vtx_size_1(uint32_t vtx_fmt_1
)
131 int vtx_size
, i
, tex_size
;
133 for (i
= 0; i
< 6; i
++) {
134 tex_size
= (vtx_fmt_1
>> (i
* 3)) & 0x7;
137 vtx_size
+= tex_size
;
142 int r200_packet0_check(struct radeon_cs_parser
*p
,
143 struct radeon_cs_packet
*pkt
,
144 unsigned idx
, unsigned reg
)
146 struct radeon_cs_reloc
*reloc
;
147 struct r100_cs_track
*track
;
148 volatile uint32_t *ib
;
157 track
= (struct r100_cs_track
*)p
->track
;
158 idx_value
= radeon_get_ib_value(p
, idx
);
160 case RADEON_CRTC_GUI_TRIG_VLINE
:
161 r
= r100_cs_packet_parse_vline(p
);
163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
165 r100_cs_dump_packet(p
, pkt
);
169 case RADEON_DST_PITCH_OFFSET
:
170 case RADEON_SRC_PITCH_OFFSET
:
171 r
= r100_reloc_pitch_offset(p
, pkt
, idx
, reg
);
175 case RADEON_RB3D_DEPTHOFFSET
:
176 r
= r100_cs_packet_next_reloc(p
, &reloc
);
178 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
180 r100_cs_dump_packet(p
, pkt
);
183 track
->zb
.robj
= reloc
->robj
;
184 track
->zb
.offset
= idx_value
;
185 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
187 case RADEON_RB3D_COLOROFFSET
:
188 r
= r100_cs_packet_next_reloc(p
, &reloc
);
190 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
192 r100_cs_dump_packet(p
, pkt
);
195 track
->cb
[0].robj
= reloc
->robj
;
196 track
->cb
[0].offset
= idx_value
;
197 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
199 case R200_PP_TXOFFSET_0
:
200 case R200_PP_TXOFFSET_1
:
201 case R200_PP_TXOFFSET_2
:
202 case R200_PP_TXOFFSET_3
:
203 case R200_PP_TXOFFSET_4
:
204 case R200_PP_TXOFFSET_5
:
205 i
= (reg
- R200_PP_TXOFFSET_0
) / 24;
206 r
= r100_cs_packet_next_reloc(p
, &reloc
);
208 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
210 r100_cs_dump_packet(p
, pkt
);
213 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
214 track
->textures
[i
].robj
= reloc
->robj
;
216 case R200_PP_CUBIC_OFFSET_F1_0
:
217 case R200_PP_CUBIC_OFFSET_F2_0
:
218 case R200_PP_CUBIC_OFFSET_F3_0
:
219 case R200_PP_CUBIC_OFFSET_F4_0
:
220 case R200_PP_CUBIC_OFFSET_F5_0
:
221 case R200_PP_CUBIC_OFFSET_F1_1
:
222 case R200_PP_CUBIC_OFFSET_F2_1
:
223 case R200_PP_CUBIC_OFFSET_F3_1
:
224 case R200_PP_CUBIC_OFFSET_F4_1
:
225 case R200_PP_CUBIC_OFFSET_F5_1
:
226 case R200_PP_CUBIC_OFFSET_F1_2
:
227 case R200_PP_CUBIC_OFFSET_F2_2
:
228 case R200_PP_CUBIC_OFFSET_F3_2
:
229 case R200_PP_CUBIC_OFFSET_F4_2
:
230 case R200_PP_CUBIC_OFFSET_F5_2
:
231 case R200_PP_CUBIC_OFFSET_F1_3
:
232 case R200_PP_CUBIC_OFFSET_F2_3
:
233 case R200_PP_CUBIC_OFFSET_F3_3
:
234 case R200_PP_CUBIC_OFFSET_F4_3
:
235 case R200_PP_CUBIC_OFFSET_F5_3
:
236 case R200_PP_CUBIC_OFFSET_F1_4
:
237 case R200_PP_CUBIC_OFFSET_F2_4
:
238 case R200_PP_CUBIC_OFFSET_F3_4
:
239 case R200_PP_CUBIC_OFFSET_F4_4
:
240 case R200_PP_CUBIC_OFFSET_F5_4
:
241 case R200_PP_CUBIC_OFFSET_F1_5
:
242 case R200_PP_CUBIC_OFFSET_F2_5
:
243 case R200_PP_CUBIC_OFFSET_F3_5
:
244 case R200_PP_CUBIC_OFFSET_F4_5
:
245 case R200_PP_CUBIC_OFFSET_F5_5
:
246 i
= (reg
- R200_PP_TXOFFSET_0
) / 24;
247 face
= (reg
- ((i
* 24) + R200_PP_TXOFFSET_0
)) / 4;
248 r
= r100_cs_packet_next_reloc(p
, &reloc
);
250 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
252 r100_cs_dump_packet(p
, pkt
);
255 track
->textures
[i
].cube_info
[face
- 1].offset
= idx_value
;
256 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
257 track
->textures
[i
].cube_info
[face
- 1].robj
= reloc
->robj
;
259 case RADEON_RE_WIDTH_HEIGHT
:
260 track
->maxy
= ((idx_value
>> 16) & 0x7FF);
262 case RADEON_RB3D_COLORPITCH
:
263 r
= r100_cs_packet_next_reloc(p
, &reloc
);
265 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
267 r100_cs_dump_packet(p
, pkt
);
271 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MACRO
)
272 tile_flags
|= RADEON_COLOR_TILE_ENABLE
;
273 if (reloc
->lobj
.tiling_flags
& RADEON_TILING_MICRO
)
274 tile_flags
|= RADEON_COLOR_MICROTILE_ENABLE
;
276 tmp
= idx_value
& ~(0x7 << 16);
280 track
->cb
[0].pitch
= idx_value
& RADEON_COLORPITCH_MASK
;
282 case RADEON_RB3D_DEPTHPITCH
:
283 track
->zb
.pitch
= idx_value
& RADEON_DEPTHPITCH_MASK
;
285 case RADEON_RB3D_CNTL
:
286 switch ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f) {
292 track
->cb
[0].cpp
= 1;
297 track
->cb
[0].cpp
= 2;
300 track
->cb
[0].cpp
= 4;
303 DRM_ERROR("Invalid color buffer format (%d) !\n",
304 ((idx_value
>> RADEON_RB3D_COLOR_FORMAT_SHIFT
) & 0x1f));
307 if (idx_value
& RADEON_DEPTHXY_OFFSET_ENABLE
) {
308 DRM_ERROR("No support for depth xy offset in kms\n");
312 track
->z_enabled
= !!(idx_value
& RADEON_Z_ENABLE
);
314 case RADEON_RB3D_ZSTENCILCNTL
:
315 switch (idx_value
& 0xf) {
331 case RADEON_RB3D_ZPASS_ADDR
:
332 r
= r100_cs_packet_next_reloc(p
, &reloc
);
334 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
336 r100_cs_dump_packet(p
, pkt
);
339 ib
[idx
] = idx_value
+ ((u32
)reloc
->lobj
.gpu_offset
);
343 uint32_t temp
= idx_value
>> 4;
344 for (i
= 0; i
< track
->num_texture
; i
++)
345 track
->textures
[i
].enabled
= !!(temp
& (1 << i
));
348 case RADEON_SE_VF_CNTL
:
349 track
->vap_vf_cntl
= idx_value
;
352 /* VAP_VF_MAX_VTX_INDX */
353 track
->max_indx
= idx_value
& 0x00FFFFFFUL
;
355 case R200_SE_VTX_FMT_0
:
356 track
->vtx_size
= r200_get_vtx_size_0(idx_value
);
358 case R200_SE_VTX_FMT_1
:
359 track
->vtx_size
+= r200_get_vtx_size_1(idx_value
);
361 case R200_PP_TXSIZE_0
:
362 case R200_PP_TXSIZE_1
:
363 case R200_PP_TXSIZE_2
:
364 case R200_PP_TXSIZE_3
:
365 case R200_PP_TXSIZE_4
:
366 case R200_PP_TXSIZE_5
:
367 i
= (reg
- R200_PP_TXSIZE_0
) / 32;
368 track
->textures
[i
].width
= (idx_value
& RADEON_TEX_USIZE_MASK
) + 1;
369 track
->textures
[i
].height
= ((idx_value
& RADEON_TEX_VSIZE_MASK
) >> RADEON_TEX_VSIZE_SHIFT
) + 1;
371 case R200_PP_TXPITCH_0
:
372 case R200_PP_TXPITCH_1
:
373 case R200_PP_TXPITCH_2
:
374 case R200_PP_TXPITCH_3
:
375 case R200_PP_TXPITCH_4
:
376 case R200_PP_TXPITCH_5
:
377 i
= (reg
- R200_PP_TXPITCH_0
) / 32;
378 track
->textures
[i
].pitch
= idx_value
+ 32;
380 case R200_PP_TXFILTER_0
:
381 case R200_PP_TXFILTER_1
:
382 case R200_PP_TXFILTER_2
:
383 case R200_PP_TXFILTER_3
:
384 case R200_PP_TXFILTER_4
:
385 case R200_PP_TXFILTER_5
:
386 i
= (reg
- R200_PP_TXFILTER_0
) / 32;
387 track
->textures
[i
].num_levels
= ((idx_value
& R200_MAX_MIP_LEVEL_MASK
)
388 >> R200_MAX_MIP_LEVEL_SHIFT
);
389 tmp
= (idx_value
>> 23) & 0x7;
390 if (tmp
== 2 || tmp
== 6)
391 track
->textures
[i
].roundup_w
= false;
392 tmp
= (idx_value
>> 27) & 0x7;
393 if (tmp
== 2 || tmp
== 6)
394 track
->textures
[i
].roundup_h
= false;
396 case R200_PP_TXMULTI_CTL_0
:
397 case R200_PP_TXMULTI_CTL_1
:
398 case R200_PP_TXMULTI_CTL_2
:
399 case R200_PP_TXMULTI_CTL_3
:
400 case R200_PP_TXMULTI_CTL_4
:
401 case R200_PP_TXMULTI_CTL_5
:
402 i
= (reg
- R200_PP_TXMULTI_CTL_0
) / 32;
404 case R200_PP_TXFORMAT_X_0
:
405 case R200_PP_TXFORMAT_X_1
:
406 case R200_PP_TXFORMAT_X_2
:
407 case R200_PP_TXFORMAT_X_3
:
408 case R200_PP_TXFORMAT_X_4
:
409 case R200_PP_TXFORMAT_X_5
:
410 i
= (reg
- R200_PP_TXFORMAT_X_0
) / 32;
411 track
->textures
[i
].txdepth
= idx_value
& 0x7;
412 tmp
= (idx_value
>> 16) & 0x3;
422 track
->textures
[i
].tex_coord_type
= 0;
426 track
->textures
[i
].tex_coord_type
= 2;
430 track
->textures
[i
].tex_coord_type
= 1;
434 case R200_PP_TXFORMAT_0
:
435 case R200_PP_TXFORMAT_1
:
436 case R200_PP_TXFORMAT_2
:
437 case R200_PP_TXFORMAT_3
:
438 case R200_PP_TXFORMAT_4
:
439 case R200_PP_TXFORMAT_5
:
440 i
= (reg
- R200_PP_TXFORMAT_0
) / 32;
441 if (idx_value
& R200_TXFORMAT_NON_POWER2
) {
442 track
->textures
[i
].use_pitch
= 1;
444 track
->textures
[i
].use_pitch
= 0;
445 track
->textures
[i
].width
= 1 << ((idx_value
>> RADEON_TXFORMAT_WIDTH_SHIFT
) & RADEON_TXFORMAT_WIDTH_MASK
);
446 track
->textures
[i
].height
= 1 << ((idx_value
>> RADEON_TXFORMAT_HEIGHT_SHIFT
) & RADEON_TXFORMAT_HEIGHT_MASK
);
448 if (idx_value
& R200_TXFORMAT_LOOKUP_DISABLE
)
449 track
->textures
[i
].lookup_disable
= true;
450 switch ((idx_value
& RADEON_TXFORMAT_FORMAT_MASK
)) {
451 case R200_TXFORMAT_I8
:
452 case R200_TXFORMAT_RGB332
:
453 case R200_TXFORMAT_Y8
:
454 track
->textures
[i
].cpp
= 1;
455 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
457 case R200_TXFORMAT_AI88
:
458 case R200_TXFORMAT_ARGB1555
:
459 case R200_TXFORMAT_RGB565
:
460 case R200_TXFORMAT_ARGB4444
:
461 case R200_TXFORMAT_VYUY422
:
462 case R200_TXFORMAT_YVYU422
:
463 case R200_TXFORMAT_LDVDU655
:
464 case R200_TXFORMAT_DVDU88
:
465 case R200_TXFORMAT_AVYU4444
:
466 track
->textures
[i
].cpp
= 2;
467 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
469 case R200_TXFORMAT_ARGB8888
:
470 case R200_TXFORMAT_RGBA8888
:
471 case R200_TXFORMAT_ABGR8888
:
472 case R200_TXFORMAT_BGR111110
:
473 case R200_TXFORMAT_LDVDU8888
:
474 track
->textures
[i
].cpp
= 4;
475 track
->textures
[i
].compress_format
= R100_TRACK_COMP_NONE
;
477 case R200_TXFORMAT_DXT1
:
478 track
->textures
[i
].cpp
= 1;
479 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
481 case R200_TXFORMAT_DXT23
:
482 case R200_TXFORMAT_DXT45
:
483 track
->textures
[i
].cpp
= 1;
484 track
->textures
[i
].compress_format
= R100_TRACK_COMP_DXT1
;
487 track
->textures
[i
].cube_info
[4].width
= 1 << ((idx_value
>> 16) & 0xf);
488 track
->textures
[i
].cube_info
[4].height
= 1 << ((idx_value
>> 20) & 0xf);
490 case R200_PP_CUBIC_FACES_0
:
491 case R200_PP_CUBIC_FACES_1
:
492 case R200_PP_CUBIC_FACES_2
:
493 case R200_PP_CUBIC_FACES_3
:
494 case R200_PP_CUBIC_FACES_4
:
495 case R200_PP_CUBIC_FACES_5
:
497 i
= (reg
- R200_PP_CUBIC_FACES_0
) / 32;
498 for (face
= 0; face
< 4; face
++) {
499 track
->textures
[i
].cube_info
[face
].width
= 1 << ((tmp
>> (face
* 8)) & 0xf);
500 track
->textures
[i
].cube_info
[face
].height
= 1 << ((tmp
>> ((face
* 8) + 4)) & 0xf);
504 printk(KERN_ERR
"Forbidden register 0x%04X in cs at %d\n",
511 void r200_set_safe_registers(struct radeon_device
*rdev
)
513 rdev
->config
.r100
.reg_safe_bm
= r200_reg_safe_bm
;
514 rdev
->config
.r100
.reg_safe_bm_size
= ARRAY_SIZE(r200_reg_safe_bm
);