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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / nouveau / nouveau_drv.h
blob3ba7901413aa8dcf304c6a0b9a8cdd65eaeccc54
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 16
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 u32 busy_placements[3];
80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
87 bool validate_mapped;
88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
96 struct nouveau_tile_reg *tile;
97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101 };
102
103 static inline struct nouveau_bo *
104 nouveau_bo(struct ttm_buffer_object *bo)
105 {
106 return container_of(bo, struct nouveau_bo, bo);
107 }
108
109 static inline struct nouveau_bo *
110 nouveau_gem_object(struct drm_gem_object *gem)
111 {
112 return gem ? gem->driver_private : NULL;
113 }
114
115 /* TODO: submit equivalent to TTM generic API upstream? */
116 static inline void __iomem *
117 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118 {
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124 }
125
126 enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129 };
130
131 #define NVOBJ_ENGINE_SW 0
132 #define NVOBJ_ENGINE_GR 1
133 #define NVOBJ_ENGINE_DISPLAY 2
134 #define NVOBJ_ENGINE_INT 0xdeadbeef
135
136 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
137 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
138 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
139 #define NVOBJ_FLAG_FAKE (1 << 3)
140 struct nouveau_gpuobj {
141 struct list_head list;
142
143 struct nouveau_channel *im_channel;
144 struct drm_mm_node *im_pramin;
145 struct nouveau_bo *im_backing;
146 uint32_t im_backing_start;
147 uint32_t *im_backing_suspend;
148 int im_bound;
149
150 uint32_t flags;
151 int refcount;
152
153 uint32_t engine;
154 uint32_t class;
155
156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
157 void *priv;
158 };
159
160 struct nouveau_gpuobj_ref {
161 struct list_head list;
162
163 struct nouveau_gpuobj *gpuobj;
164 uint32_t instance;
165
166 struct nouveau_channel *channel;
167 int handle;
168 };
169
170 struct nouveau_channel {
171 struct drm_device *dev;
172 int id;
173
174 /* owner of this fifo */
175 struct drm_file *file_priv;
176 /* mapping of the fifo itself */
177 struct drm_local_map *map;
178
179 /* mapping of the regs controling the fifo */
180 void __iomem *user;
181 uint32_t user_get;
182 uint32_t user_put;
183
184 /* Fencing */
185 struct {
186 /* lock protects the pending list only */
187 spinlock_t lock;
188 struct list_head pending;
189 uint32_t sequence;
190 uint32_t sequence_ack;
191 atomic_t last_sequence_irq;
192 } fence;
193
194 /* DMA push buffer */
195 struct nouveau_gpuobj_ref *pushbuf;
196 struct nouveau_bo *pushbuf_bo;
197 uint32_t pushbuf_base;
198
199 /* Notifier memory */
200 struct nouveau_bo *notifier_bo;
201 struct drm_mm notifier_heap;
202
203 /* PFIFO context */
204 struct nouveau_gpuobj_ref *ramfc;
205 struct nouveau_gpuobj_ref *cache;
206
207 /* PGRAPH context */
208 struct nouveau_gpuobj_ref *ramin_grctx;
209 void *pgraph_ctx;
210
211 /* NV50 VM */
212 struct nouveau_gpuobj *vm_pd;
213 struct nouveau_gpuobj_ref *vm_gart_pt;
214 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
215
216 /* Objects */
217 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
218 struct drm_mm ramin_heap; /* Private PRAMIN heap */
219 struct nouveau_gpuobj_ref *ramht; /* Hash table */
220 struct list_head ramht_refs; /* Objects referenced by RAMHT */
221
222 /* GPU object info for stuff used in-kernel (mm_enabled) */
223 uint32_t m2mf_ntfy;
224 uint32_t vram_handle;
225 uint32_t gart_handle;
226 bool accel_done;
227
228 /* Push buffer state (only for drm's channel on !mm_enabled) */
229 struct {
230 int max;
231 int free;
232 int cur;
233 int put;
234 /* access via pushbuf_bo */
235
236 int ib_base;
237 int ib_max;
238 int ib_free;
239 int ib_put;
240 } dma;
241
242 uint32_t sw_subchannel[8];
243
244 struct {
245 struct nouveau_gpuobj *vblsem;
246 uint32_t vblsem_offset;
247 uint32_t vblsem_rval;
248 struct list_head vbl_wait;
249 } nvsw;
250
251 struct {
252 bool active;
253 char name[32];
254 struct drm_info_list info;
255 } debugfs;
256 };
257
258 struct nouveau_instmem_engine {
259 void *priv;
260
261 int (*init)(struct drm_device *dev);
262 void (*takedown)(struct drm_device *dev);
263 int (*suspend)(struct drm_device *dev);
264 void (*resume)(struct drm_device *dev);
265
266 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
267 uint32_t *size);
268 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
269 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
270 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
271 void (*flush)(struct drm_device *);
272 };
273
274 struct nouveau_mc_engine {
275 int (*init)(struct drm_device *dev);
276 void (*takedown)(struct drm_device *dev);
277 };
278
279 struct nouveau_timer_engine {
280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
282 uint64_t (*read)(struct drm_device *dev);
283 };
284
285 struct nouveau_fb_engine {
286 int num_tiles;
287
288 int (*init)(struct drm_device *dev);
289 void (*takedown)(struct drm_device *dev);
290
291 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
292 uint32_t size, uint32_t pitch);
293 };
294
295 struct nouveau_fifo_engine {
296 int channels;
297
298 struct nouveau_gpuobj_ref *playlist[2];
299 int cur_playlist;
300
301 int (*init)(struct drm_device *);
302 void (*takedown)(struct drm_device *);
303
304 void (*disable)(struct drm_device *);
305 void (*enable)(struct drm_device *);
306 bool (*reassign)(struct drm_device *, bool enable);
307 bool (*cache_flush)(struct drm_device *dev);
308 bool (*cache_pull)(struct drm_device *dev, bool enable);
309
310 int (*channel_id)(struct drm_device *);
311
312 int (*create_context)(struct nouveau_channel *);
313 void (*destroy_context)(struct nouveau_channel *);
314 int (*load_context)(struct nouveau_channel *);
315 int (*unload_context)(struct drm_device *);
316 };
317
318 struct nouveau_pgraph_object_method {
319 int id;
320 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
321 uint32_t data);
322 };
323
324 struct nouveau_pgraph_object_class {
325 int id;
326 bool software;
327 struct nouveau_pgraph_object_method *methods;
328 };
329
330 struct nouveau_pgraph_engine {
331 struct nouveau_pgraph_object_class *grclass;
332 bool accel_blocked;
333 int grctx_size;
334
335 /* NV2x/NV3x context table (0x400780) */
336 struct nouveau_gpuobj_ref *ctx_table;
337
338 int (*init)(struct drm_device *);
339 void (*takedown)(struct drm_device *);
340
341 void (*fifo_access)(struct drm_device *, bool);
342
343 struct nouveau_channel *(*channel)(struct drm_device *);
344 int (*create_context)(struct nouveau_channel *);
345 void (*destroy_context)(struct nouveau_channel *);
346 int (*load_context)(struct nouveau_channel *);
347 int (*unload_context)(struct drm_device *);
348
349 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
350 uint32_t size, uint32_t pitch);
351 };
352
353 struct nouveau_display_engine {
354 int (*early_init)(struct drm_device *);
355 void (*late_takedown)(struct drm_device *);
356 int (*create)(struct drm_device *);
357 int (*init)(struct drm_device *);
358 void (*destroy)(struct drm_device *);
359 };
360
361 struct nouveau_gpio_engine {
362 int (*init)(struct drm_device *);
363 void (*takedown)(struct drm_device *);
364
365 int (*get)(struct drm_device *, enum dcb_gpio_tag);
366 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
367
368 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
369 };
370
371 struct nouveau_engine {
372 struct nouveau_instmem_engine instmem;
373 struct nouveau_mc_engine mc;
374 struct nouveau_timer_engine timer;
375 struct nouveau_fb_engine fb;
376 struct nouveau_pgraph_engine graph;
377 struct nouveau_fifo_engine fifo;
378 struct nouveau_display_engine display;
379 struct nouveau_gpio_engine gpio;
380 };
381
382 struct nouveau_pll_vals {
383 union {
384 struct {
385 #ifdef __BIG_ENDIAN
386 uint8_t N1, M1, N2, M2;
387 #else
388 uint8_t M1, N1, M2, N2;
389 #endif
390 };
391 struct {
392 uint16_t NM1, NM2;
393 } __attribute__((packed));
394 };
395 int log2P;
396
397 int refclk;
398 };
399
400 enum nv04_fp_display_regs {
401 FP_DISPLAY_END,
402 FP_TOTAL,
403 FP_CRTC,
404 FP_SYNC_START,
405 FP_SYNC_END,
406 FP_VALID_START,
407 FP_VALID_END
408 };
409
410 struct nv04_crtc_reg {
411 unsigned char MiscOutReg; /* */
412 uint8_t CRTC[0xa0];
413 uint8_t CR58[0x10];
414 uint8_t Sequencer[5];
415 uint8_t Graphics[9];
416 uint8_t Attribute[21];
417 unsigned char DAC[768]; /* Internal Colorlookuptable */
418
419 /* PCRTC regs */
420 uint32_t fb_start;
421 uint32_t crtc_cfg;
422 uint32_t cursor_cfg;
423 uint32_t gpio_ext;
424 uint32_t crtc_830;
425 uint32_t crtc_834;
426 uint32_t crtc_850;
427 uint32_t crtc_eng_ctrl;
428
429 /* PRAMDAC regs */
430 uint32_t nv10_cursync;
431 struct nouveau_pll_vals pllvals;
432 uint32_t ramdac_gen_ctrl;
433 uint32_t ramdac_630;
434 uint32_t ramdac_634;
435 uint32_t tv_setup;
436 uint32_t tv_vtotal;
437 uint32_t tv_vskew;
438 uint32_t tv_vsync_delay;
439 uint32_t tv_htotal;
440 uint32_t tv_hskew;
441 uint32_t tv_hsync_delay;
442 uint32_t tv_hsync_delay2;
443 uint32_t fp_horiz_regs[7];
444 uint32_t fp_vert_regs[7];
445 uint32_t dither;
446 uint32_t fp_control;
447 uint32_t dither_regs[6];
448 uint32_t fp_debug_0;
449 uint32_t fp_debug_1;
450 uint32_t fp_debug_2;
451 uint32_t fp_margin_color;
452 uint32_t ramdac_8c0;
453 uint32_t ramdac_a20;
454 uint32_t ramdac_a24;
455 uint32_t ramdac_a34;
456 uint32_t ctv_regs[38];
457 };
458
459 struct nv04_output_reg {
460 uint32_t output;
461 int head;
462 };
463
464 struct nv04_mode_state {
465 uint32_t bpp;
466 uint32_t width;
467 uint32_t height;
468 uint32_t interlace;
469 uint32_t repaint0;
470 uint32_t repaint1;
471 uint32_t screen;
472 uint32_t scale;
473 uint32_t dither;
474 uint32_t extra;
475 uint32_t fifo;
476 uint32_t pixel;
477 uint32_t horiz;
478 int arbitration0;
479 int arbitration1;
480 uint32_t pll;
481 uint32_t pllB;
482 uint32_t vpll;
483 uint32_t vpll2;
484 uint32_t vpllB;
485 uint32_t vpll2B;
486 uint32_t pllsel;
487 uint32_t sel_clk;
488 uint32_t general;
489 uint32_t crtcOwner;
490 uint32_t head;
491 uint32_t head2;
492 uint32_t cursorConfig;
493 uint32_t cursor0;
494 uint32_t cursor1;
495 uint32_t cursor2;
496 uint32_t timingH;
497 uint32_t timingV;
498 uint32_t displayV;
499 uint32_t crtcSync;
500
501 struct nv04_crtc_reg crtc_reg[2];
502 };
503
504 enum nouveau_card_type {
505 NV_04 = 0x00,
506 NV_10 = 0x10,
507 NV_20 = 0x20,
508 NV_30 = 0x30,
509 NV_40 = 0x40,
510 NV_50 = 0x50,
511 NV_C0 = 0xc0,
512 };
513
514 struct drm_nouveau_private {
515 struct drm_device *dev;
516
517 /* the card type, takes NV_* as values */
518 enum nouveau_card_type card_type;
519 /* exact chipset, derived from NV_PMC_BOOT_0 */
520 int chipset;
521 int flags;
522
523 void __iomem *mmio;
524 void __iomem *ramin;
525 uint32_t ramin_size;
526
527 struct nouveau_bo *vga_ram;
528
529 struct workqueue_struct *wq;
530 struct work_struct irq_work;
531 struct work_struct hpd_work;
532
533 struct {
534 spinlock_t lock;
535 uint32_t hpd0_bits;
536 uint32_t hpd1_bits;
537 } hpd_state;
538
539 struct list_head vbl_waiting;
540
541 struct {
542 struct drm_global_reference mem_global_ref;
543 struct ttm_bo_global_ref bo_global_ref;
544 struct ttm_bo_device bdev;
545 atomic_t validate_sequence;
546 } ttm;
547
548 int fifo_alloc_count;
549 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
550
551 struct nouveau_engine engine;
552 struct nouveau_channel *channel;
553
554 /* For PFIFO and PGRAPH. */
555 spinlock_t context_switch_lock;
556
557 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
558 struct nouveau_gpuobj *ramht;
559 uint32_t ramin_rsvd_vram;
560 uint32_t ramht_offset;
561 uint32_t ramht_size;
562 uint32_t ramht_bits;
563 uint32_t ramfc_offset;
564 uint32_t ramfc_size;
565 uint32_t ramro_offset;
566 uint32_t ramro_size;
567
568 struct {
569 enum {
570 NOUVEAU_GART_NONE = 0,
571 NOUVEAU_GART_AGP,
572 NOUVEAU_GART_SGDMA
573 } type;
574 uint64_t aper_base;
575 uint64_t aper_size;
576 uint64_t aper_free;
577
578 struct nouveau_gpuobj *sg_ctxdma;
579 struct page *sg_dummy_page;
580 dma_addr_t sg_dummy_bus;
581 } gart_info;
582
583 /* nv10-nv40 tiling regions */
584 struct {
585 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
586 spinlock_t lock;
587 } tile;
588
589 /* VRAM/fb configuration */
590 uint64_t vram_size;
591 uint64_t vram_sys_base;
592
593 uint64_t fb_phys;
594 uint64_t fb_available_size;
595 uint64_t fb_mappable_pages;
596 uint64_t fb_aper_free;
597 int fb_mtrr;
598
599 /* G8x/G9x virtual address space */
600 uint64_t vm_gart_base;
601 uint64_t vm_gart_size;
602 uint64_t vm_vram_base;
603 uint64_t vm_vram_size;
604 uint64_t vm_end;
605 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
606 int vm_vram_pt_nr;
607
608 struct drm_mm ramin_heap;
609
610 struct list_head gpuobj_list;
611
612 struct nvbios vbios;
613
614 struct nv04_mode_state mode_reg;
615 struct nv04_mode_state saved_reg;
616 uint32_t saved_vga_font[4][16384];
617 uint32_t crtc_owner;
618 uint32_t dac_users[4];
619
620 struct nouveau_suspend_resume {
621 uint32_t *ramin_copy;
622 } susres;
623
624 struct backlight_device *backlight;
625
626 struct nouveau_channel *evo;
627 struct {
628 struct dcb_entry *dcb;
629 u16 script;
630 u32 pclk;
631 } evo_irq;
632
633 struct {
634 struct dentry *channel_root;
635 } debugfs;
636
637 struct nouveau_fbdev *nfbdev;
638 struct apertures_struct *apertures;
639 };
640
641 static inline struct drm_nouveau_private *
642 nouveau_bdev(struct ttm_bo_device *bd)
643 {
644 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
645 }
646
647 static inline int
648 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
649 {
650 struct nouveau_bo *prev;
651
652 if (!pnvbo)
653 return -EINVAL;
654 prev = *pnvbo;
655
656 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
657 if (prev) {
658 struct ttm_buffer_object *bo = &prev->bo;
659
660 ttm_bo_unref(&bo);
661 }
662
663 return 0;
664 }
665
666 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
667 struct drm_nouveau_private *nv = dev->dev_private; \
668 if (!nouveau_channel_owner(dev, (cl), (id))) { \
669 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
670 DRM_CURRENTPID, (id)); \
671 return -EPERM; \
672 } \
673 (ch) = nv->fifos[(id)]; \
674 } while (0)
675
676 /* nouveau_drv.c */
677 extern int nouveau_noagp;
678 extern int nouveau_duallink;
679 extern int nouveau_uscript_lvds;
680 extern int nouveau_uscript_tmds;
681 extern int nouveau_vram_pushbuf;
682 extern int nouveau_vram_notify;
683 extern int nouveau_fbpercrtc;
684 extern int nouveau_tv_disable;
685 extern char *nouveau_tv_norm;
686 extern int nouveau_reg_debug;
687 extern char *nouveau_vbios;
688 extern int nouveau_ignorelid;
689 extern int nouveau_nofbaccel;
690 extern int nouveau_noaccel;
691 extern int nouveau_override_conntype;
692
693 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
694 extern int nouveau_pci_resume(struct pci_dev *pdev);
695
696 /* nouveau_state.c */
697 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
698 extern int nouveau_load(struct drm_device *, unsigned long flags);
699 extern int nouveau_firstopen(struct drm_device *);
700 extern void nouveau_lastclose(struct drm_device *);
701 extern int nouveau_unload(struct drm_device *);
702 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
703 struct drm_file *);
704 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
705 struct drm_file *);
706 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
707 uint32_t reg, uint32_t mask, uint32_t val);
708 extern bool nouveau_wait_for_idle(struct drm_device *);
709 extern int nouveau_card_init(struct drm_device *);
710
711 /* nouveau_mem.c */
712 extern int nouveau_mem_detect(struct drm_device *dev);
713 extern int nouveau_mem_init(struct drm_device *);
714 extern int nouveau_mem_init_agp(struct drm_device *);
715 extern int nouveau_mem_reset_agp(struct drm_device *);
716 extern void nouveau_mem_close(struct drm_device *);
717 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
718 uint32_t addr,
719 uint32_t size,
720 uint32_t pitch);
721 extern void nv10_mem_expire_tiling(struct drm_device *dev,
722 struct nouveau_tile_reg *tile,
723 struct nouveau_fence *fence);
724 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
725 uint32_t size, uint32_t flags,
726 uint64_t phys);
727 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
728 uint32_t size);
729
730 /* nouveau_notifier.c */
731 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
732 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
733 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
734 int cout, uint32_t *offset);
735 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
736 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
737 struct drm_file *);
738 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
739 struct drm_file *);
740
741 /* nouveau_channel.c */
742 extern struct drm_ioctl_desc nouveau_ioctls[];
743 extern int nouveau_max_ioctl;
744 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
745 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
746 int channel);
747 extern int nouveau_channel_alloc(struct drm_device *dev,
748 struct nouveau_channel **chan,
749 struct drm_file *file_priv,
750 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
751 extern void nouveau_channel_free(struct nouveau_channel *);
752
753 /* nouveau_object.c */
754 extern int nouveau_gpuobj_early_init(struct drm_device *);
755 extern int nouveau_gpuobj_init(struct drm_device *);
756 extern void nouveau_gpuobj_takedown(struct drm_device *);
757 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
758 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
759 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
760 extern void nouveau_gpuobj_resume(struct drm_device *dev);
761 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
762 uint32_t vram_h, uint32_t tt_h);
763 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
764 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
765 uint32_t size, int align, uint32_t flags,
766 struct nouveau_gpuobj **);
767 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
768 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
769 uint32_t handle, struct nouveau_gpuobj *,
770 struct nouveau_gpuobj_ref **);
771 extern int nouveau_gpuobj_ref_del(struct drm_device *,
772 struct nouveau_gpuobj_ref **);
773 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
774 struct nouveau_gpuobj_ref **ref_ret);
775 extern int nouveau_gpuobj_new_ref(struct drm_device *,
776 struct nouveau_channel *alloc_chan,
777 struct nouveau_channel *ref_chan,
778 uint32_t handle, uint32_t size, int align,
779 uint32_t flags, struct nouveau_gpuobj_ref **);
780 extern int nouveau_gpuobj_new_fake(struct drm_device *,
781 uint32_t p_offset, uint32_t b_offset,
782 uint32_t size, uint32_t flags,
783 struct nouveau_gpuobj **,
784 struct nouveau_gpuobj_ref**);
785 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
786 uint64_t offset, uint64_t size, int access,
787 int target, struct nouveau_gpuobj **);
788 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
789 uint64_t offset, uint64_t size,
790 int access, struct nouveau_gpuobj **,
791 uint32_t *o_ret);
792 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
793 struct nouveau_gpuobj **);
794 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
795 struct nouveau_gpuobj **);
796 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
797 struct drm_file *);
798 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
799 struct drm_file *);
800
801 /* nouveau_irq.c */
802 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
803 extern void nouveau_irq_preinstall(struct drm_device *);
804 extern int nouveau_irq_postinstall(struct drm_device *);
805 extern void nouveau_irq_uninstall(struct drm_device *);
806
807 /* nouveau_sgdma.c */
808 extern int nouveau_sgdma_init(struct drm_device *);
809 extern void nouveau_sgdma_takedown(struct drm_device *);
810 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
811 uint32_t *page);
812 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
813
814 /* nouveau_debugfs.c */
815 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
816 extern int nouveau_debugfs_init(struct drm_minor *);
817 extern void nouveau_debugfs_takedown(struct drm_minor *);
818 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
819 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
820 #else
821 static inline int
822 nouveau_debugfs_init(struct drm_minor *minor)
823 {
824 return 0;
825 }
826
827 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
828 {
829 }
830
831 static inline int
832 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
833 {
834 return 0;
835 }
836
837 static inline void
838 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
839 {
840 }
841 #endif
842
843 /* nouveau_dma.c */
844 extern void nouveau_dma_pre_init(struct nouveau_channel *);
845 extern int nouveau_dma_init(struct nouveau_channel *);
846 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
847
848 /* nouveau_acpi.c */
849 #define ROM_BIOS_PAGE 4096
850 #if defined(CONFIG_ACPI)
851 void nouveau_register_dsm_handler(void);
852 void nouveau_unregister_dsm_handler(void);
853 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
854 bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
855 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
856 #else
857 static inline void nouveau_register_dsm_handler(void) {}
858 static inline void nouveau_unregister_dsm_handler(void) {}
859 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
860 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
861 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
862 #endif
863
864 /* nouveau_backlight.c */
865 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
866 extern int nouveau_backlight_init(struct drm_device *);
867 extern void nouveau_backlight_exit(struct drm_device *);
868 #else
869 static inline int nouveau_backlight_init(struct drm_device *dev)
870 {
871 return 0;
872 }
873
874 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
875 #endif
876
877 /* nouveau_bios.c */
878 extern int nouveau_bios_init(struct drm_device *);
879 extern void nouveau_bios_takedown(struct drm_device *dev);
880 extern int nouveau_run_vbios_init(struct drm_device *);
881 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
882 struct dcb_entry *);
883 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
884 enum dcb_gpio_tag);
885 extern struct dcb_connector_table_entry *
886 nouveau_bios_connector_entry(struct drm_device *, int index);
887 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
888 struct pll_lims *);
889 extern int nouveau_bios_run_display_table(struct drm_device *,
890 struct dcb_entry *,
891 uint32_t script, int pxclk);
892 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
893 int *length);
894 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
895 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
896 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
897 bool *dl, bool *if_is_24bit);
898 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
899 int head, int pxclk);
900 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
901 enum LVDS_script, int pxclk);
902
903 /* nouveau_ttm.c */
904 int nouveau_ttm_global_init(struct drm_nouveau_private *);
905 void nouveau_ttm_global_release(struct drm_nouveau_private *);
906 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
907
908 /* nouveau_dp.c */
909 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
910 uint8_t *data, int data_nr);
911 bool nouveau_dp_detect(struct drm_encoder *);
912 bool nouveau_dp_link_train(struct drm_encoder *);
913
914 /* nv04_fb.c */
915 extern int nv04_fb_init(struct drm_device *);
916 extern void nv04_fb_takedown(struct drm_device *);
917
918 /* nv10_fb.c */
919 extern int nv10_fb_init(struct drm_device *);
920 extern void nv10_fb_takedown(struct drm_device *);
921 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
922 uint32_t, uint32_t);
923
924 /* nv30_fb.c */
925 extern int nv30_fb_init(struct drm_device *);
926 extern void nv30_fb_takedown(struct drm_device *);
927
928 /* nv40_fb.c */
929 extern int nv40_fb_init(struct drm_device *);
930 extern void nv40_fb_takedown(struct drm_device *);
931 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
932 uint32_t, uint32_t);
933
934 /* nv50_fb.c */
935 extern int nv50_fb_init(struct drm_device *);
936 extern void nv50_fb_takedown(struct drm_device *);
937
938 /* nvc0_fb.c */
939 extern int nvc0_fb_init(struct drm_device *);
940 extern void nvc0_fb_takedown(struct drm_device *);
941
942 /* nv04_fifo.c */
943 extern int nv04_fifo_init(struct drm_device *);
944 extern void nv04_fifo_disable(struct drm_device *);
945 extern void nv04_fifo_enable(struct drm_device *);
946 extern bool nv04_fifo_reassign(struct drm_device *, bool);
947 extern bool nv04_fifo_cache_flush(struct drm_device *);
948 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
949 extern int nv04_fifo_channel_id(struct drm_device *);
950 extern int nv04_fifo_create_context(struct nouveau_channel *);
951 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
952 extern int nv04_fifo_load_context(struct nouveau_channel *);
953 extern int nv04_fifo_unload_context(struct drm_device *);
954
955 /* nv10_fifo.c */
956 extern int nv10_fifo_init(struct drm_device *);
957 extern int nv10_fifo_channel_id(struct drm_device *);
958 extern int nv10_fifo_create_context(struct nouveau_channel *);
959 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
960 extern int nv10_fifo_load_context(struct nouveau_channel *);
961 extern int nv10_fifo_unload_context(struct drm_device *);
962
963 /* nv40_fifo.c */
964 extern int nv40_fifo_init(struct drm_device *);
965 extern int nv40_fifo_create_context(struct nouveau_channel *);
966 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
967 extern int nv40_fifo_load_context(struct nouveau_channel *);
968 extern int nv40_fifo_unload_context(struct drm_device *);
969
970 /* nv50_fifo.c */
971 extern int nv50_fifo_init(struct drm_device *);
972 extern void nv50_fifo_takedown(struct drm_device *);
973 extern int nv50_fifo_channel_id(struct drm_device *);
974 extern int nv50_fifo_create_context(struct nouveau_channel *);
975 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
976 extern int nv50_fifo_load_context(struct nouveau_channel *);
977 extern int nv50_fifo_unload_context(struct drm_device *);
978
979 /* nvc0_fifo.c */
980 extern int nvc0_fifo_init(struct drm_device *);
981 extern void nvc0_fifo_takedown(struct drm_device *);
982 extern void nvc0_fifo_disable(struct drm_device *);
983 extern void nvc0_fifo_enable(struct drm_device *);
984 extern bool nvc0_fifo_reassign(struct drm_device *, bool);
985 extern bool nvc0_fifo_cache_flush(struct drm_device *);
986 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
987 extern int nvc0_fifo_channel_id(struct drm_device *);
988 extern int nvc0_fifo_create_context(struct nouveau_channel *);
989 extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
990 extern int nvc0_fifo_load_context(struct nouveau_channel *);
991 extern int nvc0_fifo_unload_context(struct drm_device *);
992
993 /* nv04_graph.c */
994 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
995 extern int nv04_graph_init(struct drm_device *);
996 extern void nv04_graph_takedown(struct drm_device *);
997 extern void nv04_graph_fifo_access(struct drm_device *, bool);
998 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
999 extern int nv04_graph_create_context(struct nouveau_channel *);
1000 extern void nv04_graph_destroy_context(struct nouveau_channel *);
1001 extern int nv04_graph_load_context(struct nouveau_channel *);
1002 extern int nv04_graph_unload_context(struct drm_device *);
1003 extern void nv04_graph_context_switch(struct drm_device *);
1004
1005 /* nv10_graph.c */
1006 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1007 extern int nv10_graph_init(struct drm_device *);
1008 extern void nv10_graph_takedown(struct drm_device *);
1009 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1010 extern int nv10_graph_create_context(struct nouveau_channel *);
1011 extern void nv10_graph_destroy_context(struct nouveau_channel *);
1012 extern int nv10_graph_load_context(struct nouveau_channel *);
1013 extern int nv10_graph_unload_context(struct drm_device *);
1014 extern void nv10_graph_context_switch(struct drm_device *);
1015 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1016 uint32_t, uint32_t);
1017
1018 /* nv20_graph.c */
1019 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1020 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1021 extern int nv20_graph_create_context(struct nouveau_channel *);
1022 extern void nv20_graph_destroy_context(struct nouveau_channel *);
1023 extern int nv20_graph_load_context(struct nouveau_channel *);
1024 extern int nv20_graph_unload_context(struct drm_device *);
1025 extern int nv20_graph_init(struct drm_device *);
1026 extern void nv20_graph_takedown(struct drm_device *);
1027 extern int nv30_graph_init(struct drm_device *);
1028 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1029 uint32_t, uint32_t);
1030
1031 /* nv40_graph.c */
1032 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1033 extern int nv40_graph_init(struct drm_device *);
1034 extern void nv40_graph_takedown(struct drm_device *);
1035 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1036 extern int nv40_graph_create_context(struct nouveau_channel *);
1037 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1038 extern int nv40_graph_load_context(struct nouveau_channel *);
1039 extern int nv40_graph_unload_context(struct drm_device *);
1040 extern void nv40_grctx_init(struct nouveau_grctx *);
1041 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1042 uint32_t, uint32_t);
1043
1044 /* nv50_graph.c */
1045 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1046 extern int nv50_graph_init(struct drm_device *);
1047 extern void nv50_graph_takedown(struct drm_device *);
1048 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1049 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1050 extern int nv50_graph_create_context(struct nouveau_channel *);
1051 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1052 extern int nv50_graph_load_context(struct nouveau_channel *);
1053 extern int nv50_graph_unload_context(struct drm_device *);
1054 extern void nv50_graph_context_switch(struct drm_device *);
1055 extern int nv50_grctx_init(struct nouveau_grctx *);
1056
1057 /* nvc0_graph.c */
1058 extern int nvc0_graph_init(struct drm_device *);
1059 extern void nvc0_graph_takedown(struct drm_device *);
1060 extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1061 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1062 extern int nvc0_graph_create_context(struct nouveau_channel *);
1063 extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1064 extern int nvc0_graph_load_context(struct nouveau_channel *);
1065 extern int nvc0_graph_unload_context(struct drm_device *);
1066
1067 /* nv04_instmem.c */
1068 extern int nv04_instmem_init(struct drm_device *);
1069 extern void nv04_instmem_takedown(struct drm_device *);
1070 extern int nv04_instmem_suspend(struct drm_device *);
1071 extern void nv04_instmem_resume(struct drm_device *);
1072 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1073 uint32_t *size);
1074 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1075 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1076 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1077 extern void nv04_instmem_flush(struct drm_device *);
1078
1079 /* nv50_instmem.c */
1080 extern int nv50_instmem_init(struct drm_device *);
1081 extern void nv50_instmem_takedown(struct drm_device *);
1082 extern int nv50_instmem_suspend(struct drm_device *);
1083 extern void nv50_instmem_resume(struct drm_device *);
1084 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1085 uint32_t *size);
1086 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1087 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1088 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1089 extern void nv50_instmem_flush(struct drm_device *);
1090 extern void nv84_instmem_flush(struct drm_device *);
1091 extern void nv50_vm_flush(struct drm_device *, int engine);
1092
1093 /* nvc0_instmem.c */
1094 extern int nvc0_instmem_init(struct drm_device *);
1095 extern void nvc0_instmem_takedown(struct drm_device *);
1096 extern int nvc0_instmem_suspend(struct drm_device *);
1097 extern void nvc0_instmem_resume(struct drm_device *);
1098 extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1099 uint32_t *size);
1100 extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1101 extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1102 extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1103 extern void nvc0_instmem_flush(struct drm_device *);
1104
1105 /* nv04_mc.c */
1106 extern int nv04_mc_init(struct drm_device *);
1107 extern void nv04_mc_takedown(struct drm_device *);
1108
1109 /* nv40_mc.c */
1110 extern int nv40_mc_init(struct drm_device *);
1111 extern void nv40_mc_takedown(struct drm_device *);
1112
1113 /* nv50_mc.c */
1114 extern int nv50_mc_init(struct drm_device *);
1115 extern void nv50_mc_takedown(struct drm_device *);
1116
1117 /* nv04_timer.c */
1118 extern int nv04_timer_init(struct drm_device *);
1119 extern uint64_t nv04_timer_read(struct drm_device *);
1120 extern void nv04_timer_takedown(struct drm_device *);
1121
1122 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1123 unsigned long arg);
1124
1125 /* nv04_dac.c */
1126 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
1127 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1128 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1129 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1130 extern bool nv04_dac_in_use(struct drm_encoder *encoder);
1131
1132 /* nv04_dfp.c */
1133 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
1134 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1135 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1136 int head, bool dl);
1137 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1138 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1139
1140 /* nv04_tv.c */
1141 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1142 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
1143
1144 /* nv17_tv.c */
1145 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
1146
1147 /* nv04_display.c */
1148 extern int nv04_display_early_init(struct drm_device *);
1149 extern void nv04_display_late_takedown(struct drm_device *);
1150 extern int nv04_display_create(struct drm_device *);
1151 extern int nv04_display_init(struct drm_device *);
1152 extern void nv04_display_destroy(struct drm_device *);
1153
1154 /* nv04_crtc.c */
1155 extern int nv04_crtc_create(struct drm_device *, int index);
1156
1157 /* nouveau_bo.c */
1158 extern struct ttm_bo_driver nouveau_bo_driver;
1159 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1160 int size, int align, uint32_t flags,
1161 uint32_t tile_mode, uint32_t tile_flags,
1162 bool no_vm, bool mappable, struct nouveau_bo **);
1163 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1164 extern int nouveau_bo_unpin(struct nouveau_bo *);
1165 extern int nouveau_bo_map(struct nouveau_bo *);
1166 extern void nouveau_bo_unmap(struct nouveau_bo *);
1167 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1168 uint32_t busy);
1169 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1170 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1171 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1172 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1173 extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
1174
1175 /* nouveau_fence.c */
1176 struct nouveau_fence;
1177 extern int nouveau_fence_init(struct nouveau_channel *);
1178 extern void nouveau_fence_fini(struct nouveau_channel *);
1179 extern void nouveau_fence_update(struct nouveau_channel *);
1180 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1181 bool emit);
1182 extern int nouveau_fence_emit(struct nouveau_fence *);
1183 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1184 extern bool nouveau_fence_signalled(void *obj, void *arg);
1185 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1186 extern int nouveau_fence_flush(void *obj, void *arg);
1187 extern void nouveau_fence_unref(void **obj);
1188 extern void *nouveau_fence_ref(void *obj);
1189
1190 /* nouveau_gem.c */
1191 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1192 int size, int align, uint32_t flags,
1193 uint32_t tile_mode, uint32_t tile_flags,
1194 bool no_vm, bool mappable, struct nouveau_bo **);
1195 extern int nouveau_gem_object_new(struct drm_gem_object *);
1196 extern void nouveau_gem_object_del(struct drm_gem_object *);
1197 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1198 struct drm_file *);
1199 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1200 struct drm_file *);
1201 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1202 struct drm_file *);
1203 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1204 struct drm_file *);
1205 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1206 struct drm_file *);
1207
1208 /* nv10_gpio.c */
1209 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1210 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1211
1212 /* nv50_gpio.c */
1213 int nv50_gpio_init(struct drm_device *dev);
1214 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1215 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1216 void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
1217
1218 /* nv50_calc. */
1219 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1220 int *N1, int *M1, int *N2, int *M2, int *P);
1221 int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1222 int clk, int *N, int *fN, int *M, int *P);
1223
1224 #ifndef ioread32_native
1225 #ifdef __BIG_ENDIAN
1226 #define ioread16_native ioread16be
1227 #define iowrite16_native iowrite16be
1228 #define ioread32_native ioread32be
1229 #define iowrite32_native iowrite32be
1230 #else /* def __BIG_ENDIAN */
1231 #define ioread16_native ioread16
1232 #define iowrite16_native iowrite16
1233 #define ioread32_native ioread32
1234 #define iowrite32_native iowrite32
1235 #endif /* def __BIG_ENDIAN else */
1236 #endif /* !ioread32_native */
1237
1238 /* channel control reg access */
1239 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1240 {
1241 return ioread32_native(chan->user + reg);
1242 }
1243
1244 static inline void nvchan_wr32(struct nouveau_channel *chan,
1245 unsigned reg, u32 val)
1246 {
1247 iowrite32_native(val, chan->user + reg);
1248 }
1249
1250 /* register access */
1251 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1252 {
1253 struct drm_nouveau_private *dev_priv = dev->dev_private;
1254 return ioread32_native(dev_priv->mmio + reg);
1255 }
1256
1257 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1258 {
1259 struct drm_nouveau_private *dev_priv = dev->dev_private;
1260 iowrite32_native(val, dev_priv->mmio + reg);
1261 }
1262
1263 static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
1264 {
1265 u32 tmp = nv_rd32(dev, reg);
1266 tmp &= ~mask;
1267 tmp |= val;
1268 nv_wr32(dev, reg, tmp);
1269 }
1270
1271 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1272 {
1273 struct drm_nouveau_private *dev_priv = dev->dev_private;
1274 return ioread8(dev_priv->mmio + reg);
1275 }
1276
1277 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1278 {
1279 struct drm_nouveau_private *dev_priv = dev->dev_private;
1280 iowrite8(val, dev_priv->mmio + reg);
1281 }
1282
1283 #define nv_wait(reg, mask, val) \
1284 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1285
1286 /* PRAMIN access */
1287 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1288 {
1289 struct drm_nouveau_private *dev_priv = dev->dev_private;
1290 return ioread32_native(dev_priv->ramin + offset);
1291 }
1292
1293 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1294 {
1295 struct drm_nouveau_private *dev_priv = dev->dev_private;
1296 iowrite32_native(val, dev_priv->ramin + offset);
1297 }
1298
1299 /* object access */
1300 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1301 unsigned index)
1302 {
1303 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1304 }
1305
1306 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1307 unsigned index, u32 val)
1308 {
1309 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1310 }
1311
1312 /*
1313 * Logging
1314 * Argument d is (struct drm_device *).
1315 */
1316 #define NV_PRINTK(level, d, fmt, arg...) \
1317 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1318 pci_name(d->pdev), ##arg)
1319 #ifndef NV_DEBUG_NOTRACE
1320 #define NV_DEBUG(d, fmt, arg...) do { \
1321 if (drm_debug & DRM_UT_DRIVER) { \
1322 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1323 __LINE__, ##arg); \
1324 } \
1325 } while (0)
1326 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1327 if (drm_debug & DRM_UT_KMS) { \
1328 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1329 __LINE__, ##arg); \
1330 } \
1331 } while (0)
1332 #else
1333 #define NV_DEBUG(d, fmt, arg...) do { \
1334 if (drm_debug & DRM_UT_DRIVER) \
1335 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1336 } while (0)
1337 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1338 if (drm_debug & DRM_UT_KMS) \
1339 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1340 } while (0)
1341 #endif
1342 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1343 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1344 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1345 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1346 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1347
1348 /* nouveau_reg_debug bitmask */
1349 enum {
1350 NOUVEAU_REG_DEBUG_MC = 0x1,
1351 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1352 NOUVEAU_REG_DEBUG_FB = 0x4,
1353 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1354 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1355 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1356 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1357 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1358 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1359 NOUVEAU_REG_DEBUG_EVO = 0x200,
1360 };
1361
1362 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1363 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1364 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1365 } while (0)
1366
1367 static inline bool
1368 nv_two_heads(struct drm_device *dev)
1369 {
1370 struct drm_nouveau_private *dev_priv = dev->dev_private;
1371 const int impl = dev->pci_device & 0x0ff0;
1372
1373 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1374 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1375 return true;
1376
1377 return false;
1378 }
1379
1380 static inline bool
1381 nv_gf4_disp_arch(struct drm_device *dev)
1382 {
1383 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1384 }
1385
1386 static inline bool
1387 nv_two_reg_pll(struct drm_device *dev)
1388 {
1389 struct drm_nouveau_private *dev_priv = dev->dev_private;
1390 const int impl = dev->pci_device & 0x0ff0;
1391
1392 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1393 return true;
1394 return false;
1395 }
1396
1397 static inline bool
1398 nv_match_device(struct drm_device *dev, unsigned device,
1399 unsigned sub_vendor, unsigned sub_device)
1400 {
1401 return dev->pdev->device == device &&
1402 dev->pdev->subsystem_vendor == sub_vendor &&
1403 dev->pdev->subsystem_device == sub_device;
1404 }
1405
1406 #define NV_SW 0x0000506e
1407 #define NV_SW_DMA_SEMAPHORE 0x00000060
1408 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1409 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1410 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1411 #define NV_SW_DMA_VBLSEM 0x0000018c
1412 #define NV_SW_VBLSEM_OFFSET 0x00000400
1413 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1414 #define NV_SW_VBLSEM_RELEASE 0x00000408
1415
1416 #endif /* __NOUVEAU_DRV_H__ */
Tomato firmware and modifications.