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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / gpu / drm / i915 / intel_display.c
blobf287ee3ea13108ef252adf8fef918a8a6d006ac2
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct drm_encoder *l_entry;
752
753 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
754 if (l_entry && l_entry->crtc == crtc) {
755 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
756 if (intel_encoder->type == type)
757 return true;
758 }
759 }
760 return false;
761 }
762
763 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 /**
765 * Returns whether the given set of divisors are valid for a given refclk with
766 * the given connectors.
767 */
768
769 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
770 {
771 const intel_limit_t *limit = intel_limit (crtc);
772 struct drm_device *dev = crtc->dev;
773
774 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
775 INTELPllInvalid ("p1 out of range\n");
776 if (clock->p < limit->p.min || limit->p.max < clock->p)
777 INTELPllInvalid ("p out of range\n");
778 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
779 INTELPllInvalid ("m2 out of range\n");
780 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
781 INTELPllInvalid ("m1 out of range\n");
782 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
783 INTELPllInvalid ("m1 <= m2\n");
784 if (clock->m < limit->m.min || limit->m.max < clock->m)
785 INTELPllInvalid ("m out of range\n");
786 if (clock->n < limit->n.min || limit->n.max < clock->n)
787 INTELPllInvalid ("n out of range\n");
788 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
789 INTELPllInvalid ("vco out of range\n");
790 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
791 INTELPllInvalid ("dot out of range\n");
792
793 return true;
794 }
795
796 static bool
797 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
798 int target, int refclk, intel_clock_t *best_clock)
799
800 {
801 struct drm_device *dev = crtc->dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 intel_clock_t clock;
804 int err = target;
805
806 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
807 (I915_READ(LVDS)) != 0) {
808 /*
809 * For LVDS, if the panel is on, just rely on its current
810 * settings for dual-channel. We haven't figured out how to
811 * reliably set up different single/dual channel state, if we
812 * even can.
813 */
814 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
815 LVDS_CLKB_POWER_UP)
816 clock.p2 = limit->p2.p2_fast;
817 else
818 clock.p2 = limit->p2.p2_slow;
819 } else {
820 if (target < limit->p2.dot_limit)
821 clock.p2 = limit->p2.p2_slow;
822 else
823 clock.p2 = limit->p2.p2_fast;
824 }
825
826 memset (best_clock, 0, sizeof (*best_clock));
827
828 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
829 clock.m1++) {
830 for (clock.m2 = limit->m2.min;
831 clock.m2 <= limit->m2.max; clock.m2++) {
832 /* m1 is always 0 in Pineview */
833 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
834 break;
835 for (clock.n = limit->n.min;
836 clock.n <= limit->n.max; clock.n++) {
837 for (clock.p1 = limit->p1.min;
838 clock.p1 <= limit->p1.max; clock.p1++) {
839 int this_err;
840
841 intel_clock(dev, refclk, &clock);
842
843 if (!intel_PLL_is_valid(crtc, &clock))
844 continue;
845
846 this_err = abs(clock.dot - target);
847 if (this_err < err) {
848 *best_clock = clock;
849 err = this_err;
850 }
851 }
852 }
853 }
854 }
855
856 return (err != target);
857 }
858
859 static bool
860 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862 {
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870 found = false;
871
872 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
873 int lvds_reg;
874
875 if (HAS_PCH_SPLIT(dev))
876 lvds_reg = PCH_LVDS;
877 else
878 lvds_reg = LVDS;
879 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
880 LVDS_CLKB_POWER_UP)
881 clock.p2 = limit->p2.p2_fast;
882 else
883 clock.p2 = limit->p2.p2_slow;
884 } else {
885 if (target < limit->p2.dot_limit)
886 clock.p2 = limit->p2.p2_slow;
887 else
888 clock.p2 = limit->p2.p2_fast;
889 }
890
891 memset(best_clock, 0, sizeof(*best_clock));
892 max_n = limit->n.max;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
895 /* based on hardware requirement, prefere larger m1,m2 */
896 for (clock.m1 = limit->m1.max;
897 clock.m1 >= limit->m1.min; clock.m1--) {
898 for (clock.m2 = limit->m2.max;
899 clock.m2 >= limit->m2.min; clock.m2--) {
900 for (clock.p1 = limit->p1.max;
901 clock.p1 >= limit->p1.min; clock.p1--) {
902 int this_err;
903
904 intel_clock(dev, refclk, &clock);
905 if (!intel_PLL_is_valid(crtc, &clock))
906 continue;
907 this_err = abs(clock.dot - target) ;
908 if (this_err < err_most) {
909 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 }
914 }
915 }
916 }
917 }
918 return found;
919 }
920
921 static bool
922 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
923 int target, int refclk, intel_clock_t *best_clock)
924 {
925 struct drm_device *dev = crtc->dev;
926 intel_clock_t clock;
927
928 /* return directly when it is eDP */
929 if (HAS_eDP)
930 return true;
931
932 if (target < 200000) {
933 clock.n = 1;
934 clock.p1 = 2;
935 clock.p2 = 10;
936 clock.m1 = 12;
937 clock.m2 = 9;
938 } else {
939 clock.n = 2;
940 clock.p1 = 1;
941 clock.p2 = 10;
942 clock.m1 = 14;
943 clock.m2 = 8;
944 }
945 intel_clock(dev, refclk, &clock);
946 memcpy(best_clock, &clock, sizeof(intel_clock_t));
947 return true;
948 }
949
950 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
951 static bool
952 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
953 int target, int refclk, intel_clock_t *best_clock)
954 {
955 intel_clock_t clock;
956 if (target < 200000) {
957 clock.p1 = 2;
958 clock.p2 = 10;
959 clock.n = 2;
960 clock.m1 = 23;
961 clock.m2 = 8;
962 } else {
963 clock.p1 = 1;
964 clock.p2 = 10;
965 clock.n = 1;
966 clock.m1 = 14;
967 clock.m2 = 2;
968 }
969 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
970 clock.p = (clock.p1 * clock.p2);
971 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
972 clock.vco = 0;
973 memcpy(best_clock, &clock, sizeof(intel_clock_t));
974 return true;
975 }
976
977 /**
978 * intel_wait_for_vblank - wait for vblank on a given pipe
979 * @dev: drm device
980 * @pipe: pipe to wait for
981 *
982 * Wait for vblank to occur on a given pipe. Needed for various bits of
983 * mode setting code.
984 */
985 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
986 {
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
989
990 /* Clear existing vblank status. Note this will clear any other
991 * sticky status fields as well.
992 *
993 * This races with i915_driver_irq_handler() with the result
994 * that either function could miss a vblank event. Here it is not
995 * fatal, as we will either wait upon the next vblank interrupt or
996 * timeout. Generally speaking intel_wait_for_vblank() is only
997 * called during modeset at which time the GPU should be idle and
998 * should *not* be performing page flips and thus not waiting on
999 * vblanks...
1000 * Currently, the result of us stealing a vblank from the irq
1001 * handler is that a single frame will be skipped during swapbuffers.
1002 */
1003 I915_WRITE(pipestat_reg,
1004 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1005
1006 /* Wait for vblank interrupt bit to set */
1007 if (wait_for((I915_READ(pipestat_reg) &
1008 PIPE_VBLANK_INTERRUPT_STATUS),
1009 50, 0))
1010 DRM_DEBUG_KMS("vblank wait timed out\n");
1011 }
1012
1013 /*
1014 * intel_wait_for_pipe_off - wait for pipe to turn off
1015 * @dev: drm device
1016 * @pipe: pipe to wait for
1017 *
1018 * After disabling a pipe, we can't wait for vblank in the usual way,
1019 * spinning on the vblank interrupt status bit, since we won't actually
1020 * see an interrupt when the pipe is disabled.
1021 *
1022 * On Gen4 and above:
1023 * wait for the pipe register state bit to turn off
1024 *
1025 * Otherwise:
1026 * wait for the display line value to settle (it usually
1027 * ends up stopping at the start of the next frame).
1028 *
1029 */
1030 static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1031 {
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033
1034 if (INTEL_INFO(dev)->gen >= 4) {
1035 int pipeconf_reg = (pipe == 0 ? PIPEACONF : PIPEBCONF);
1036
1037 /* Wait for the Pipe State to go off */
1038 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0,
1039 100, 0))
1040 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1041 } else {
1042 u32 last_line;
1043 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1044 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1045
1046 /* Wait for the display line to settle */
1047 do {
1048 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1049 mdelay(5);
1050 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1051 time_after(timeout, jiffies));
1052 if (time_after(jiffies, timeout))
1053 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1054 }
1055 }
1056
1057 /* Parameters have changed, update FBC info */
1058 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1059 {
1060 struct drm_device *dev = crtc->dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct drm_framebuffer *fb = crtc->fb;
1063 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1064 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066 int plane, i;
1067 u32 fbc_ctl, fbc_ctl2;
1068
1069 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1070
1071 if (fb->pitch < dev_priv->cfb_pitch)
1072 dev_priv->cfb_pitch = fb->pitch;
1073
1074 /* FBC_CTL wants 64B units */
1075 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1076 dev_priv->cfb_fence = obj_priv->fence_reg;
1077 dev_priv->cfb_plane = intel_crtc->plane;
1078 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1079
1080 /* Clear old tags */
1081 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1082 I915_WRITE(FBC_TAG + (i * 4), 0);
1083
1084 /* Set it up... */
1085 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1086 if (obj_priv->tiling_mode != I915_TILING_NONE)
1087 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1088 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1089 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1090
1091 /* enable it... */
1092 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1093 if (IS_I945GM(dev))
1094 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1095 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1096 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1097 if (obj_priv->tiling_mode != I915_TILING_NONE)
1098 fbc_ctl |= dev_priv->cfb_fence;
1099 I915_WRITE(FBC_CONTROL, fbc_ctl);
1100
1101 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1102 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1103 }
1104
1105 void i8xx_disable_fbc(struct drm_device *dev)
1106 {
1107 struct drm_i915_private *dev_priv = dev->dev_private;
1108 u32 fbc_ctl;
1109
1110 if (!I915_HAS_FBC(dev))
1111 return;
1112
1113 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1114 return; /* Already off, just return */
1115
1116 /* Disable compression */
1117 fbc_ctl = I915_READ(FBC_CONTROL);
1118 fbc_ctl &= ~FBC_CTL_EN;
1119 I915_WRITE(FBC_CONTROL, fbc_ctl);
1120
1121 /* Wait for compressing bit to clear */
1122 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1123 DRM_DEBUG_KMS("FBC idle timed out\n");
1124 return;
1125 }
1126
1127 DRM_DEBUG_KMS("disabled FBC\n");
1128 }
1129
1130 static bool i8xx_fbc_enabled(struct drm_device *dev)
1131 {
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133
1134 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1135 }
1136
1137 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1138 {
1139 struct drm_device *dev = crtc->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 struct drm_framebuffer *fb = crtc->fb;
1142 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1143 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1145 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1146 DPFC_CTL_PLANEB);
1147 unsigned long stall_watermark = 200;
1148 u32 dpfc_ctl;
1149
1150 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1151 dev_priv->cfb_fence = obj_priv->fence_reg;
1152 dev_priv->cfb_plane = intel_crtc->plane;
1153
1154 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1155 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1156 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1157 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1158 } else {
1159 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1160 }
1161
1162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1163 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1164 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1165 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1166 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1167
1168 /* enable it... */
1169 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1170
1171 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1172 }
1173
1174 void g4x_disable_fbc(struct drm_device *dev)
1175 {
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 dpfc_ctl;
1178
1179 /* Disable compression */
1180 dpfc_ctl = I915_READ(DPFC_CONTROL);
1181 dpfc_ctl &= ~DPFC_CTL_EN;
1182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1183
1184 DRM_DEBUG_KMS("disabled FBC\n");
1185 }
1186
1187 static bool g4x_fbc_enabled(struct drm_device *dev)
1188 {
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1192 }
1193
1194 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1195 {
1196 struct drm_device *dev = crtc->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 struct drm_framebuffer *fb = crtc->fb;
1199 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1200 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1202 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1203 DPFC_CTL_PLANEB;
1204 unsigned long stall_watermark = 200;
1205 u32 dpfc_ctl;
1206
1207 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1208 dev_priv->cfb_fence = obj_priv->fence_reg;
1209 dev_priv->cfb_plane = intel_crtc->plane;
1210
1211 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1212 dpfc_ctl &= DPFC_RESERVED;
1213 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1214 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1215 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1216 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1217 } else {
1218 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1219 }
1220
1221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1222 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1223 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1224 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1225 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1226 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1227 /* enable it... */
1228 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1229 DPFC_CTL_EN);
1230
1231 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1232 }
1233
1234 void ironlake_disable_fbc(struct drm_device *dev)
1235 {
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 dpfc_ctl;
1238
1239 /* Disable compression */
1240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1241 dpfc_ctl &= ~DPFC_CTL_EN;
1242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1243
1244 DRM_DEBUG_KMS("disabled FBC\n");
1245 }
1246
1247 static bool ironlake_fbc_enabled(struct drm_device *dev)
1248 {
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1250
1251 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1252 }
1253
1254 bool intel_fbc_enabled(struct drm_device *dev)
1255 {
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1257
1258 if (!dev_priv->display.fbc_enabled)
1259 return false;
1260
1261 return dev_priv->display.fbc_enabled(dev);
1262 }
1263
1264 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1265 {
1266 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1267
1268 if (!dev_priv->display.enable_fbc)
1269 return;
1270
1271 dev_priv->display.enable_fbc(crtc, interval);
1272 }
1273
1274 void intel_disable_fbc(struct drm_device *dev)
1275 {
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277
1278 if (!dev_priv->display.disable_fbc)
1279 return;
1280
1281 dev_priv->display.disable_fbc(dev);
1282 }
1283
1284 /**
1285 * intel_update_fbc - enable/disable FBC as needed
1286 * @crtc: CRTC to point the compressor at
1287 * @mode: mode in use
1288 *
1289 * Set up the framebuffer compression hardware at mode set time. We
1290 * enable it if possible:
1291 * - plane A only (on pre-965)
1292 * - no pixel mulitply/line duplication
1293 * - no alpha buffer discard
1294 * - no dual wide
1295 * - framebuffer <= 2048 in width, 1536 in height
1296 *
1297 * We can't assume that any compression will take place (worst case),
1298 * so the compressed buffer has to be the same size as the uncompressed
1299 * one. It also must reside (along with the line length buffer) in
1300 * stolen memory.
1301 *
1302 * We need to enable/disable FBC on a global basis.
1303 */
1304 static void intel_update_fbc(struct drm_crtc *crtc,
1305 struct drm_display_mode *mode)
1306 {
1307 struct drm_device *dev = crtc->dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 struct drm_framebuffer *fb = crtc->fb;
1310 struct intel_framebuffer *intel_fb;
1311 struct drm_i915_gem_object *obj_priv;
1312 struct drm_crtc *tmp_crtc;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 int plane = intel_crtc->plane;
1315 int crtcs_enabled = 0;
1316
1317 DRM_DEBUG_KMS("\n");
1318
1319 if (!i915_powersave)
1320 return;
1321
1322 if (!I915_HAS_FBC(dev))
1323 return;
1324
1325 if (!crtc->fb)
1326 return;
1327
1328 intel_fb = to_intel_framebuffer(fb);
1329 obj_priv = to_intel_bo(intel_fb->obj);
1330
1331 /*
1332 * If FBC is already on, we just have to verify that we can
1333 * keep it that way...
1334 * Need to disable if:
1335 * - more than one pipe is active
1336 * - changing FBC params (stride, fence, mode)
1337 * - new fb is too large to fit in compressed buffer
1338 * - going to an unsupported config (interlace, pixel multiply, etc.)
1339 */
1340 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1341 if (tmp_crtc->enabled)
1342 crtcs_enabled++;
1343 }
1344 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1345 if (crtcs_enabled > 1) {
1346 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1347 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1348 goto out_disable;
1349 }
1350 if (intel_fb->obj->size > dev_priv->cfb_size) {
1351 DRM_DEBUG_KMS("framebuffer too large, disabling "
1352 "compression\n");
1353 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1354 goto out_disable;
1355 }
1356 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1357 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1358 DRM_DEBUG_KMS("mode incompatible with compression, "
1359 "disabling\n");
1360 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1361 goto out_disable;
1362 }
1363 if ((mode->hdisplay > 2048) ||
1364 (mode->vdisplay > 1536)) {
1365 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1366 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1367 goto out_disable;
1368 }
1369 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1370 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1371 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1372 goto out_disable;
1373 }
1374 if (obj_priv->tiling_mode != I915_TILING_X) {
1375 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1376 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1377 goto out_disable;
1378 }
1379
1380 /* If the kernel debugger is active, always disable compression */
1381 if (in_dbg_master())
1382 goto out_disable;
1383
1384 if (intel_fbc_enabled(dev)) {
1385 /* We can re-enable it in this case, but need to update pitch */
1386 if ((fb->pitch > dev_priv->cfb_pitch) ||
1387 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1388 (plane != dev_priv->cfb_plane))
1389 intel_disable_fbc(dev);
1390 }
1391
1392 /* Now try to turn it back on if possible */
1393 if (!intel_fbc_enabled(dev))
1394 intel_enable_fbc(crtc, 500);
1395
1396 return;
1397
1398 out_disable:
1399 /* Multiple disables should be harmless */
1400 if (intel_fbc_enabled(dev)) {
1401 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1402 intel_disable_fbc(dev);
1403 }
1404 }
1405
1406 int
1407 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1408 {
1409 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1410 u32 alignment;
1411 int ret;
1412
1413 switch (obj_priv->tiling_mode) {
1414 case I915_TILING_NONE:
1415 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1416 alignment = 128 * 1024;
1417 else if (IS_I965G(dev))
1418 alignment = 4 * 1024;
1419 else
1420 alignment = 64 * 1024;
1421 break;
1422 case I915_TILING_X:
1423 /* pin() will align the object as required by fence */
1424 alignment = 0;
1425 break;
1426 case I915_TILING_Y:
1427 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1428 return -EINVAL;
1429 default:
1430 BUG();
1431 }
1432
1433 ret = i915_gem_object_pin(obj, alignment);
1434 if (ret != 0)
1435 return ret;
1436
1437 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1438 * fence, whereas 965+ only requires a fence if using
1439 * framebuffer compression. For simplicity, we always install
1440 * a fence as the cost is not that onerous.
1441 */
1442 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1443 obj_priv->tiling_mode != I915_TILING_NONE) {
1444 ret = i915_gem_object_get_fence_reg(obj);
1445 if (ret != 0) {
1446 i915_gem_object_unpin(obj);
1447 return ret;
1448 }
1449 }
1450
1451 return 0;
1452 }
1453
1454 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1455 static int
1456 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1457 int x, int y)
1458 {
1459 struct drm_device *dev = crtc->dev;
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1462 struct intel_framebuffer *intel_fb;
1463 struct drm_i915_gem_object *obj_priv;
1464 struct drm_gem_object *obj;
1465 int plane = intel_crtc->plane;
1466 unsigned long Start, Offset;
1467 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1468 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1469 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1470 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1471 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1472 u32 dspcntr;
1473
1474 switch (plane) {
1475 case 0:
1476 case 1:
1477 break;
1478 default:
1479 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1480 return -EINVAL;
1481 }
1482
1483 intel_fb = to_intel_framebuffer(fb);
1484 obj = intel_fb->obj;
1485 obj_priv = to_intel_bo(obj);
1486
1487 dspcntr = I915_READ(dspcntr_reg);
1488 /* Mask out pixel format bits in case we change it */
1489 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1490 switch (fb->bits_per_pixel) {
1491 case 8:
1492 dspcntr |= DISPPLANE_8BPP;
1493 break;
1494 case 16:
1495 if (fb->depth == 15)
1496 dspcntr |= DISPPLANE_15_16BPP;
1497 else
1498 dspcntr |= DISPPLANE_16BPP;
1499 break;
1500 case 24:
1501 case 32:
1502 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1503 break;
1504 default:
1505 DRM_ERROR("Unknown color depth\n");
1506 return -EINVAL;
1507 }
1508 if (IS_I965G(dev)) {
1509 if (obj_priv->tiling_mode != I915_TILING_NONE)
1510 dspcntr |= DISPPLANE_TILED;
1511 else
1512 dspcntr &= ~DISPPLANE_TILED;
1513 }
1514
1515 if (HAS_PCH_SPLIT(dev))
1516 /* must disable */
1517 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1518
1519 I915_WRITE(dspcntr_reg, dspcntr);
1520
1521 Start = obj_priv->gtt_offset;
1522 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1523
1524 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1525 Start, Offset, x, y, fb->pitch);
1526 I915_WRITE(dspstride, fb->pitch);
1527 if (IS_I965G(dev)) {
1528 I915_WRITE(dspsurf, Start);
1529 I915_WRITE(dsptileoff, (y << 16) | x);
1530 I915_WRITE(dspbase, Offset);
1531 } else {
1532 I915_WRITE(dspbase, Start + Offset);
1533 }
1534 POSTING_READ(dspbase);
1535
1536 if (IS_I965G(dev) || plane == 0)
1537 intel_update_fbc(crtc, &crtc->mode);
1538
1539 intel_wait_for_vblank(dev, intel_crtc->pipe);
1540 intel_increase_pllclock(crtc, true);
1541
1542 return 0;
1543 }
1544
1545 static int
1546 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1547 struct drm_framebuffer *old_fb)
1548 {
1549 struct drm_device *dev = crtc->dev;
1550 struct drm_i915_master_private *master_priv;
1551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1552 struct intel_framebuffer *intel_fb;
1553 struct drm_i915_gem_object *obj_priv;
1554 struct drm_gem_object *obj;
1555 int pipe = intel_crtc->pipe;
1556 int plane = intel_crtc->plane;
1557 int ret;
1558
1559 /* no fb bound */
1560 if (!crtc->fb) {
1561 DRM_DEBUG_KMS("No FB bound\n");
1562 return 0;
1563 }
1564
1565 switch (plane) {
1566 case 0:
1567 case 1:
1568 break;
1569 default:
1570 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1571 return -EINVAL;
1572 }
1573
1574 intel_fb = to_intel_framebuffer(crtc->fb);
1575 obj = intel_fb->obj;
1576 obj_priv = to_intel_bo(obj);
1577
1578 mutex_lock(&dev->struct_mutex);
1579 ret = intel_pin_and_fence_fb_obj(dev, obj);
1580 if (ret != 0) {
1581 mutex_unlock(&dev->struct_mutex);
1582 return ret;
1583 }
1584
1585 ret = i915_gem_object_set_to_display_plane(obj);
1586 if (ret != 0) {
1587 i915_gem_object_unpin(obj);
1588 mutex_unlock(&dev->struct_mutex);
1589 return ret;
1590 }
1591
1592 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1593 if (ret) {
1594 i915_gem_object_unpin(obj);
1595 mutex_unlock(&dev->struct_mutex);
1596 return ret;
1597 }
1598
1599 if (old_fb) {
1600 intel_fb = to_intel_framebuffer(old_fb);
1601 obj_priv = to_intel_bo(intel_fb->obj);
1602 i915_gem_object_unpin(intel_fb->obj);
1603 }
1604
1605 mutex_unlock(&dev->struct_mutex);
1606
1607 if (!dev->primary->master)
1608 return 0;
1609
1610 master_priv = dev->primary->master->driver_priv;
1611 if (!master_priv->sarea_priv)
1612 return 0;
1613
1614 if (pipe) {
1615 master_priv->sarea_priv->pipeB_x = x;
1616 master_priv->sarea_priv->pipeB_y = y;
1617 } else {
1618 master_priv->sarea_priv->pipeA_x = x;
1619 master_priv->sarea_priv->pipeA_y = y;
1620 }
1621
1622 return 0;
1623 }
1624
1625 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1626 {
1627 struct drm_device *dev = crtc->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 u32 dpa_ctl;
1630
1631 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1632 dpa_ctl = I915_READ(DP_A);
1633 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1634
1635 if (clock < 200000) {
1636 u32 temp;
1637 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1638 temp = I915_READ(0x4600c);
1639 temp &= 0xffff0000;
1640 I915_WRITE(0x4600c, temp | 0x8124);
1641
1642 temp = I915_READ(0x46010);
1643 I915_WRITE(0x46010, temp | 1);
1644
1645 temp = I915_READ(0x46034);
1646 I915_WRITE(0x46034, temp | (1 << 24));
1647 } else {
1648 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1649 }
1650 I915_WRITE(DP_A, dpa_ctl);
1651
1652 udelay(500);
1653 }
1654
1655 /* The FDI link training functions for ILK/Ibexpeak. */
1656 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1657 {
1658 struct drm_device *dev = crtc->dev;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1661 int pipe = intel_crtc->pipe;
1662 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1663 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1664 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1665 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1666 u32 temp, tries = 0;
1667
1668 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1669 for train result */
1670 temp = I915_READ(fdi_rx_imr_reg);
1671 temp &= ~FDI_RX_SYMBOL_LOCK;
1672 temp &= ~FDI_RX_BIT_LOCK;
1673 I915_WRITE(fdi_rx_imr_reg, temp);
1674 I915_READ(fdi_rx_imr_reg);
1675 udelay(150);
1676
1677 /* enable CPU FDI TX and PCH FDI RX */
1678 temp = I915_READ(fdi_tx_reg);
1679 temp |= FDI_TX_ENABLE;
1680 temp &= ~(7 << 19);
1681 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1682 temp &= ~FDI_LINK_TRAIN_NONE;
1683 temp |= FDI_LINK_TRAIN_PATTERN_1;
1684 I915_WRITE(fdi_tx_reg, temp);
1685 I915_READ(fdi_tx_reg);
1686
1687 temp = I915_READ(fdi_rx_reg);
1688 temp &= ~FDI_LINK_TRAIN_NONE;
1689 temp |= FDI_LINK_TRAIN_PATTERN_1;
1690 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1691 I915_READ(fdi_rx_reg);
1692 udelay(150);
1693
1694 for (tries = 0; tries < 5; tries++) {
1695 temp = I915_READ(fdi_rx_iir_reg);
1696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1697
1698 if ((temp & FDI_RX_BIT_LOCK)) {
1699 DRM_DEBUG_KMS("FDI train 1 done.\n");
1700 I915_WRITE(fdi_rx_iir_reg,
1701 temp | FDI_RX_BIT_LOCK);
1702 break;
1703 }
1704 }
1705 if (tries == 5)
1706 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1707
1708 /* Train 2 */
1709 temp = I915_READ(fdi_tx_reg);
1710 temp &= ~FDI_LINK_TRAIN_NONE;
1711 temp |= FDI_LINK_TRAIN_PATTERN_2;
1712 I915_WRITE(fdi_tx_reg, temp);
1713
1714 temp = I915_READ(fdi_rx_reg);
1715 temp &= ~FDI_LINK_TRAIN_NONE;
1716 temp |= FDI_LINK_TRAIN_PATTERN_2;
1717 I915_WRITE(fdi_rx_reg, temp);
1718 udelay(150);
1719
1720 tries = 0;
1721
1722 for (tries = 0; tries < 5; tries++) {
1723 temp = I915_READ(fdi_rx_iir_reg);
1724 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1725
1726 if (temp & FDI_RX_SYMBOL_LOCK) {
1727 I915_WRITE(fdi_rx_iir_reg,
1728 temp | FDI_RX_SYMBOL_LOCK);
1729 DRM_DEBUG_KMS("FDI train 2 done.\n");
1730 break;
1731 }
1732 }
1733 if (tries == 5)
1734 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1735
1736 DRM_DEBUG_KMS("FDI train done\n");
1737 }
1738
1739 static int snb_b_fdi_train_param [] = {
1740 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1741 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1742 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1743 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1744 };
1745
1746 /* The FDI link training functions for SNB/Cougarpoint. */
1747 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1748 {
1749 struct drm_device *dev = crtc->dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1752 int pipe = intel_crtc->pipe;
1753 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1754 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1755 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1756 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1757 u32 temp, i;
1758
1759 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1760 for train result */
1761 temp = I915_READ(fdi_rx_imr_reg);
1762 temp &= ~FDI_RX_SYMBOL_LOCK;
1763 temp &= ~FDI_RX_BIT_LOCK;
1764 I915_WRITE(fdi_rx_imr_reg, temp);
1765 I915_READ(fdi_rx_imr_reg);
1766 udelay(150);
1767
1768 /* enable CPU FDI TX and PCH FDI RX */
1769 temp = I915_READ(fdi_tx_reg);
1770 temp |= FDI_TX_ENABLE;
1771 temp &= ~(7 << 19);
1772 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1773 temp &= ~FDI_LINK_TRAIN_NONE;
1774 temp |= FDI_LINK_TRAIN_PATTERN_1;
1775 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1776 /* SNB-B */
1777 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1778 I915_WRITE(fdi_tx_reg, temp);
1779 I915_READ(fdi_tx_reg);
1780
1781 temp = I915_READ(fdi_rx_reg);
1782 if (HAS_PCH_CPT(dev)) {
1783 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1784 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1785 } else {
1786 temp &= ~FDI_LINK_TRAIN_NONE;
1787 temp |= FDI_LINK_TRAIN_PATTERN_1;
1788 }
1789 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1790 I915_READ(fdi_rx_reg);
1791 udelay(150);
1792
1793 for (i = 0; i < 4; i++ ) {
1794 temp = I915_READ(fdi_tx_reg);
1795 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1796 temp |= snb_b_fdi_train_param[i];
1797 I915_WRITE(fdi_tx_reg, temp);
1798 udelay(500);
1799
1800 temp = I915_READ(fdi_rx_iir_reg);
1801 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1802
1803 if (temp & FDI_RX_BIT_LOCK) {
1804 I915_WRITE(fdi_rx_iir_reg,
1805 temp | FDI_RX_BIT_LOCK);
1806 DRM_DEBUG_KMS("FDI train 1 done.\n");
1807 break;
1808 }
1809 }
1810 if (i == 4)
1811 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1812
1813 /* Train 2 */
1814 temp = I915_READ(fdi_tx_reg);
1815 temp &= ~FDI_LINK_TRAIN_NONE;
1816 temp |= FDI_LINK_TRAIN_PATTERN_2;
1817 if (IS_GEN6(dev)) {
1818 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1819 /* SNB-B */
1820 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1821 }
1822 I915_WRITE(fdi_tx_reg, temp);
1823
1824 temp = I915_READ(fdi_rx_reg);
1825 if (HAS_PCH_CPT(dev)) {
1826 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1827 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1828 } else {
1829 temp &= ~FDI_LINK_TRAIN_NONE;
1830 temp |= FDI_LINK_TRAIN_PATTERN_2;
1831 }
1832 I915_WRITE(fdi_rx_reg, temp);
1833 udelay(150);
1834
1835 for (i = 0; i < 4; i++ ) {
1836 temp = I915_READ(fdi_tx_reg);
1837 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1838 temp |= snb_b_fdi_train_param[i];
1839 I915_WRITE(fdi_tx_reg, temp);
1840 udelay(500);
1841
1842 temp = I915_READ(fdi_rx_iir_reg);
1843 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1844
1845 if (temp & FDI_RX_SYMBOL_LOCK) {
1846 I915_WRITE(fdi_rx_iir_reg,
1847 temp | FDI_RX_SYMBOL_LOCK);
1848 DRM_DEBUG_KMS("FDI train 2 done.\n");
1849 break;
1850 }
1851 }
1852 if (i == 4)
1853 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1854
1855 DRM_DEBUG_KMS("FDI train done.\n");
1856 }
1857
1858 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1859 {
1860 struct drm_device *dev = crtc->dev;
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1863 int pipe = intel_crtc->pipe;
1864 int plane = intel_crtc->plane;
1865 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1866 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1867 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1868 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1869 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1870 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1871 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1872 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1873 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1874 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1875 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1876 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1877 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1878 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1879 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1880 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1881 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1882 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1883 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1884 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1885 u32 temp;
1886 u32 pipe_bpc;
1887
1888 temp = I915_READ(pipeconf_reg);
1889 pipe_bpc = temp & PIPE_BPC_MASK;
1890
1891 switch (mode) {
1892 case DRM_MODE_DPMS_ON:
1893 case DRM_MODE_DPMS_STANDBY:
1894 case DRM_MODE_DPMS_SUSPEND:
1895 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1896
1897 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1898 temp = I915_READ(PCH_LVDS);
1899 if ((temp & LVDS_PORT_EN) == 0) {
1900 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1901 POSTING_READ(PCH_LVDS);
1902 }
1903 }
1904
1905 if (!HAS_eDP) {
1906
1907 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1908 temp = I915_READ(fdi_rx_reg);
1909 /*
1910 * make the BPC in FDI Rx be consistent with that in
1911 * pipeconf reg.
1912 */
1913 temp &= ~(0x7 << 16);
1914 temp |= (pipe_bpc << 11);
1915 temp &= ~(7 << 19);
1916 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1917 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1918 I915_READ(fdi_rx_reg);
1919 udelay(200);
1920
1921 /* Switch from Rawclk to PCDclk */
1922 temp = I915_READ(fdi_rx_reg);
1923 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1924 I915_READ(fdi_rx_reg);
1925 udelay(200);
1926
1927 /* Enable CPU FDI TX PLL, always on for Ironlake */
1928 temp = I915_READ(fdi_tx_reg);
1929 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1930 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1931 I915_READ(fdi_tx_reg);
1932 udelay(100);
1933 }
1934 }
1935
1936 /* Enable panel fitting for LVDS */
1937 if (dev_priv->pch_pf_size &&
1938 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1939 || HAS_eDP || intel_pch_has_edp(crtc))) {
1940 /* Force use of hard-coded filter coefficients
1941 * as some pre-programmed values are broken,
1942 * e.g. x201.
1943 */
1944 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1945 PF_ENABLE | PF_FILTER_MED_3x3);
1946 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1947 dev_priv->pch_pf_pos);
1948 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1949 dev_priv->pch_pf_size);
1950 }
1951
1952 /* Enable CPU pipe */
1953 temp = I915_READ(pipeconf_reg);
1954 if ((temp & PIPEACONF_ENABLE) == 0) {
1955 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1956 I915_READ(pipeconf_reg);
1957 udelay(100);
1958 }
1959
1960 /* configure and enable CPU plane */
1961 temp = I915_READ(dspcntr_reg);
1962 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1963 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1964 /* Flush the plane changes */
1965 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1966 }
1967
1968 if (!HAS_eDP) {
1969 /* For PCH output, training FDI link */
1970 if (IS_GEN6(dev))
1971 gen6_fdi_link_train(crtc);
1972 else
1973 ironlake_fdi_link_train(crtc);
1974
1975 /* enable PCH DPLL */
1976 temp = I915_READ(pch_dpll_reg);
1977 if ((temp & DPLL_VCO_ENABLE) == 0) {
1978 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1979 I915_READ(pch_dpll_reg);
1980 }
1981 udelay(200);
1982
1983 if (HAS_PCH_CPT(dev)) {
1984 /* Be sure PCH DPLL SEL is set */
1985 temp = I915_READ(PCH_DPLL_SEL);
1986 if (trans_dpll_sel == 0 &&
1987 (temp & TRANSA_DPLL_ENABLE) == 0)
1988 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1989 else if (trans_dpll_sel == 1 &&
1990 (temp & TRANSB_DPLL_ENABLE) == 0)
1991 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1992 I915_WRITE(PCH_DPLL_SEL, temp);
1993 I915_READ(PCH_DPLL_SEL);
1994 }
1995
1996 /* set transcoder timing */
1997 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1998 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1999 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2000
2001 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2002 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2003 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2004
2005 /* enable normal train */
2006 temp = I915_READ(fdi_tx_reg);
2007 temp &= ~FDI_LINK_TRAIN_NONE;
2008 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2009 FDI_TX_ENHANCE_FRAME_ENABLE);
2010 I915_READ(fdi_tx_reg);
2011
2012 temp = I915_READ(fdi_rx_reg);
2013 if (HAS_PCH_CPT(dev)) {
2014 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2015 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2016 } else {
2017 temp &= ~FDI_LINK_TRAIN_NONE;
2018 temp |= FDI_LINK_TRAIN_NONE;
2019 }
2020 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2021 I915_READ(fdi_rx_reg);
2022
2023 /* wait one idle pattern time */
2024 udelay(100);
2025
2026 /* For PCH DP, enable TRANS_DP_CTL */
2027 if (HAS_PCH_CPT(dev) &&
2028 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2029 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2030 int reg;
2031
2032 reg = I915_READ(trans_dp_ctl);
2033 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2034 TRANS_DP_SYNC_MASK |
2035 TRANS_DP_BPC_MASK);
2036 reg |= (TRANS_DP_OUTPUT_ENABLE |
2037 TRANS_DP_ENH_FRAMING);
2038 reg |= TRANS_DP_8BPC;
2039
2040 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2041 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2042 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2043 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2044
2045 switch (intel_trans_dp_port_sel(crtc)) {
2046 case PCH_DP_B:
2047 reg |= TRANS_DP_PORT_SEL_B;
2048 break;
2049 case PCH_DP_C:
2050 reg |= TRANS_DP_PORT_SEL_C;
2051 break;
2052 case PCH_DP_D:
2053 reg |= TRANS_DP_PORT_SEL_D;
2054 break;
2055 default:
2056 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2057 reg |= TRANS_DP_PORT_SEL_B;
2058 break;
2059 }
2060
2061 I915_WRITE(trans_dp_ctl, reg);
2062 POSTING_READ(trans_dp_ctl);
2063 }
2064
2065 /* enable PCH transcoder */
2066 temp = I915_READ(transconf_reg);
2067 /*
2068 * make the BPC in transcoder be consistent with
2069 * that in pipeconf reg.
2070 */
2071 temp &= ~PIPE_BPC_MASK;
2072 temp |= pipe_bpc;
2073 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2074 I915_READ(transconf_reg);
2075
2076 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2077 DRM_ERROR("failed to enable transcoder\n");
2078 }
2079
2080 intel_crtc_load_lut(crtc);
2081
2082 intel_update_fbc(crtc, &crtc->mode);
2083 break;
2084
2085 case DRM_MODE_DPMS_OFF:
2086 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2087
2088 drm_vblank_off(dev, pipe);
2089 /* Disable display plane */
2090 temp = I915_READ(dspcntr_reg);
2091 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2092 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2093 /* Flush the plane changes */
2094 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2095 I915_READ(dspbase_reg);
2096 }
2097
2098 if (dev_priv->cfb_plane == plane &&
2099 dev_priv->display.disable_fbc)
2100 dev_priv->display.disable_fbc(dev);
2101
2102 /* disable cpu pipe, disable after all planes disabled */
2103 temp = I915_READ(pipeconf_reg);
2104 if ((temp & PIPEACONF_ENABLE) != 0) {
2105 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2106
2107 /* wait for cpu pipe off, pipe state */
2108 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2109 DRM_ERROR("failed to turn off cpu pipe\n");
2110 } else
2111 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2112
2113 udelay(100);
2114
2115 /* Disable PF */
2116 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2117 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2118
2119 /* disable CPU FDI tx and PCH FDI rx */
2120 temp = I915_READ(fdi_tx_reg);
2121 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2122 I915_READ(fdi_tx_reg);
2123
2124 temp = I915_READ(fdi_rx_reg);
2125 /* BPC in FDI rx is consistent with that in pipeconf */
2126 temp &= ~(0x07 << 16);
2127 temp |= (pipe_bpc << 11);
2128 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2129 I915_READ(fdi_rx_reg);
2130
2131 udelay(100);
2132
2133 /* still set train pattern 1 */
2134 temp = I915_READ(fdi_tx_reg);
2135 temp &= ~FDI_LINK_TRAIN_NONE;
2136 temp |= FDI_LINK_TRAIN_PATTERN_1;
2137 I915_WRITE(fdi_tx_reg, temp);
2138 POSTING_READ(fdi_tx_reg);
2139
2140 temp = I915_READ(fdi_rx_reg);
2141 if (HAS_PCH_CPT(dev)) {
2142 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2143 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2144 } else {
2145 temp &= ~FDI_LINK_TRAIN_NONE;
2146 temp |= FDI_LINK_TRAIN_PATTERN_1;
2147 }
2148 I915_WRITE(fdi_rx_reg, temp);
2149 POSTING_READ(fdi_rx_reg);
2150
2151 udelay(100);
2152
2153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2154 temp = I915_READ(PCH_LVDS);
2155 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2156 I915_READ(PCH_LVDS);
2157 udelay(100);
2158 }
2159
2160 /* disable PCH transcoder */
2161 temp = I915_READ(transconf_reg);
2162 if ((temp & TRANS_ENABLE) != 0) {
2163 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2164
2165 /* wait for PCH transcoder off, transcoder state */
2166 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2167 DRM_ERROR("failed to disable transcoder\n");
2168 }
2169
2170 temp = I915_READ(transconf_reg);
2171 /* BPC in transcoder is consistent with that in pipeconf */
2172 temp &= ~PIPE_BPC_MASK;
2173 temp |= pipe_bpc;
2174 I915_WRITE(transconf_reg, temp);
2175 I915_READ(transconf_reg);
2176 udelay(100);
2177
2178 if (HAS_PCH_CPT(dev)) {
2179 /* disable TRANS_DP_CTL */
2180 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2181 int reg;
2182
2183 reg = I915_READ(trans_dp_ctl);
2184 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2185 I915_WRITE(trans_dp_ctl, reg);
2186 POSTING_READ(trans_dp_ctl);
2187
2188 /* disable DPLL_SEL */
2189 temp = I915_READ(PCH_DPLL_SEL);
2190 if (trans_dpll_sel == 0)
2191 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2192 else
2193 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2194 I915_WRITE(PCH_DPLL_SEL, temp);
2195 I915_READ(PCH_DPLL_SEL);
2196
2197 }
2198
2199 /* disable PCH DPLL */
2200 temp = I915_READ(pch_dpll_reg);
2201 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2202 I915_READ(pch_dpll_reg);
2203
2204 /* Switch from PCDclk to Rawclk */
2205 temp = I915_READ(fdi_rx_reg);
2206 temp &= ~FDI_SEL_PCDCLK;
2207 I915_WRITE(fdi_rx_reg, temp);
2208 I915_READ(fdi_rx_reg);
2209
2210 /* Disable CPU FDI TX PLL */
2211 temp = I915_READ(fdi_tx_reg);
2212 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2213 I915_READ(fdi_tx_reg);
2214 udelay(100);
2215
2216 temp = I915_READ(fdi_rx_reg);
2217 temp &= ~FDI_RX_PLL_ENABLE;
2218 I915_WRITE(fdi_rx_reg, temp);
2219 I915_READ(fdi_rx_reg);
2220
2221 /* Wait for the clocks to turn off. */
2222 udelay(100);
2223 break;
2224 }
2225 }
2226
2227 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2228 {
2229 struct intel_overlay *overlay;
2230 int ret;
2231
2232 if (!enable && intel_crtc->overlay) {
2233 overlay = intel_crtc->overlay;
2234 mutex_lock(&overlay->dev->struct_mutex);
2235 for (;;) {
2236 ret = intel_overlay_switch_off(overlay);
2237 if (ret == 0)
2238 break;
2239
2240 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2241 if (ret != 0) {
2242 /* overlay doesn't react anymore. Usually
2243 * results in a black screen and an unkillable
2244 * X server. */
2245 BUG();
2246 overlay->hw_wedged = HW_WEDGED;
2247 break;
2248 }
2249 }
2250 mutex_unlock(&overlay->dev->struct_mutex);
2251 }
2252 /* Let userspace switch the overlay on again. In most cases userspace
2253 * has to recompute where to put it anyway. */
2254
2255 return;
2256 }
2257
2258 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2259 {
2260 struct drm_device *dev = crtc->dev;
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263 int pipe = intel_crtc->pipe;
2264 int plane = intel_crtc->plane;
2265 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2266 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2267 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2268 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2269 u32 temp;
2270
2271 switch (mode) {
2272 case DRM_MODE_DPMS_ON:
2273 case DRM_MODE_DPMS_STANDBY:
2274 case DRM_MODE_DPMS_SUSPEND:
2275 /* Enable the DPLL */
2276 temp = I915_READ(dpll_reg);
2277 if ((temp & DPLL_VCO_ENABLE) == 0) {
2278 I915_WRITE(dpll_reg, temp);
2279 I915_READ(dpll_reg);
2280 /* Wait for the clocks to stabilize. */
2281 udelay(150);
2282 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2283 I915_READ(dpll_reg);
2284 /* Wait for the clocks to stabilize. */
2285 udelay(150);
2286 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2287 I915_READ(dpll_reg);
2288 /* Wait for the clocks to stabilize. */
2289 udelay(150);
2290 }
2291
2292 /* Enable the pipe */
2293 temp = I915_READ(pipeconf_reg);
2294 if ((temp & PIPEACONF_ENABLE) == 0)
2295 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2296
2297 /* Enable the plane */
2298 temp = I915_READ(dspcntr_reg);
2299 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2300 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2301 /* Flush the plane changes */
2302 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2303 }
2304
2305 intel_crtc_load_lut(crtc);
2306
2307 if ((IS_I965G(dev) || plane == 0))
2308 intel_update_fbc(crtc, &crtc->mode);
2309
2310 /* Give the overlay scaler a chance to enable if it's on this pipe */
2311 intel_crtc_dpms_overlay(intel_crtc, true);
2312 break;
2313 case DRM_MODE_DPMS_OFF:
2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2315 intel_crtc_dpms_overlay(intel_crtc, false);
2316 drm_vblank_off(dev, pipe);
2317
2318 if (dev_priv->cfb_plane == plane &&
2319 dev_priv->display.disable_fbc)
2320 dev_priv->display.disable_fbc(dev);
2321
2322 /* Disable display plane */
2323 temp = I915_READ(dspcntr_reg);
2324 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2325 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2326 /* Flush the plane changes */
2327 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2328 I915_READ(dspbase_reg);
2329 }
2330
2331 /* Don't disable pipe A or pipe A PLLs if needed */
2332 if (pipeconf_reg == PIPEACONF &&
2333 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) {
2334 /* Wait for vblank for the disable to take effect */
2335 intel_wait_for_vblank(dev, pipe);
2336 goto skip_pipe_off;
2337 }
2338
2339 /* Next, disable display pipes */
2340 temp = I915_READ(pipeconf_reg);
2341 if ((temp & PIPEACONF_ENABLE) != 0) {
2342 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2343 I915_READ(pipeconf_reg);
2344 }
2345
2346 /* Wait for the pipe to turn off */
2347 intel_wait_for_pipe_off(dev, pipe);
2348
2349 temp = I915_READ(dpll_reg);
2350 if ((temp & DPLL_VCO_ENABLE) != 0) {
2351 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2352 I915_READ(dpll_reg);
2353 }
2354 skip_pipe_off:
2355 /* Wait for the clocks to turn off. */
2356 udelay(150);
2357 break;
2358 }
2359 }
2360
2361 /**
2362 * Sets the power management mode of the pipe and plane.
2363 */
2364 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2365 {
2366 struct drm_device *dev = crtc->dev;
2367 struct drm_i915_private *dev_priv = dev->dev_private;
2368 struct drm_i915_master_private *master_priv;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
2371 bool enabled;
2372
2373 if (intel_crtc->dpms_mode == mode)
2374 return;
2375
2376 intel_crtc->dpms_mode = mode;
2377 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2378
2379 /* When switching on the display, ensure that SR is disabled
2380 * with multiple pipes prior to enabling to new pipe.
2381 *
2382 * When switching off the display, make sure the cursor is
2383 * properly hidden prior to disabling the pipe.
2384 */
2385 if (mode == DRM_MODE_DPMS_ON)
2386 intel_update_watermarks(dev);
2387 else
2388 intel_crtc_update_cursor(crtc);
2389
2390 dev_priv->display.dpms(crtc, mode);
2391
2392 if (mode == DRM_MODE_DPMS_ON)
2393 intel_crtc_update_cursor(crtc);
2394 else
2395 intel_update_watermarks(dev);
2396
2397 if (!dev->primary->master)
2398 return;
2399
2400 master_priv = dev->primary->master->driver_priv;
2401 if (!master_priv->sarea_priv)
2402 return;
2403
2404 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2405
2406 switch (pipe) {
2407 case 0:
2408 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2409 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2410 break;
2411 case 1:
2412 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2413 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2414 break;
2415 default:
2416 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2417 break;
2418 }
2419 }
2420
2421 static void intel_crtc_prepare (struct drm_crtc *crtc)
2422 {
2423 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2424 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2425 }
2426
2427 static void intel_crtc_commit (struct drm_crtc *crtc)
2428 {
2429 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2430 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2431 }
2432
2433 void intel_encoder_prepare (struct drm_encoder *encoder)
2434 {
2435 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2436 /* lvds has its own version of prepare see intel_lvds_prepare */
2437 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2438 }
2439
2440 void intel_encoder_commit (struct drm_encoder *encoder)
2441 {
2442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2443 /* lvds has its own version of commit see intel_lvds_commit */
2444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2445 }
2446
2447 void intel_encoder_destroy(struct drm_encoder *encoder)
2448 {
2449 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2450
2451 if (intel_encoder->ddc_bus)
2452 intel_i2c_destroy(intel_encoder->ddc_bus);
2453
2454 if (intel_encoder->i2c_bus)
2455 intel_i2c_destroy(intel_encoder->i2c_bus);
2456
2457 drm_encoder_cleanup(encoder);
2458 kfree(intel_encoder);
2459 }
2460
2461 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2462 struct drm_display_mode *mode,
2463 struct drm_display_mode *adjusted_mode)
2464 {
2465 struct drm_device *dev = crtc->dev;
2466
2467 if (HAS_PCH_SPLIT(dev)) {
2468 /* FDI link clock is fixed at 2.7G */
2469 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2470 return false;
2471 }
2472
2473 if (adjusted_mode->crtc_htotal == 0)
2474 drm_mode_set_crtcinfo(adjusted_mode, 0);
2475
2476 return true;
2477 }
2478
2479 static int i945_get_display_clock_speed(struct drm_device *dev)
2480 {
2481 return 400000;
2482 }
2483
2484 static int i915_get_display_clock_speed(struct drm_device *dev)
2485 {
2486 return 333000;
2487 }
2488
2489 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2490 {
2491 return 200000;
2492 }
2493
2494 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2495 {
2496 u16 gcfgc = 0;
2497
2498 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2499
2500 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2501 return 133000;
2502 else {
2503 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2504 case GC_DISPLAY_CLOCK_333_MHZ:
2505 return 333000;
2506 default:
2507 case GC_DISPLAY_CLOCK_190_200_MHZ:
2508 return 190000;
2509 }
2510 }
2511 }
2512
2513 static int i865_get_display_clock_speed(struct drm_device *dev)
2514 {
2515 return 266000;
2516 }
2517
2518 static int i855_get_display_clock_speed(struct drm_device *dev)
2519 {
2520 u16 hpllcc = 0;
2521 /* Assume that the hardware is in the high speed state. This
2522 * should be the default.
2523 */
2524 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2525 case GC_CLOCK_133_200:
2526 case GC_CLOCK_100_200:
2527 return 200000;
2528 case GC_CLOCK_166_250:
2529 return 250000;
2530 case GC_CLOCK_100_133:
2531 return 133000;
2532 }
2533
2534 /* Shouldn't happen */
2535 return 0;
2536 }
2537
2538 static int i830_get_display_clock_speed(struct drm_device *dev)
2539 {
2540 return 133000;
2541 }
2542
2543 /**
2544 * Return the pipe currently connected to the panel fitter,
2545 * or -1 if the panel fitter is not present or not in use
2546 */
2547 int intel_panel_fitter_pipe (struct drm_device *dev)
2548 {
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 u32 pfit_control;
2551
2552 /* i830 doesn't have a panel fitter */
2553 if (IS_I830(dev))
2554 return -1;
2555
2556 pfit_control = I915_READ(PFIT_CONTROL);
2557
2558 /* See if the panel fitter is in use */
2559 if ((pfit_control & PFIT_ENABLE) == 0)
2560 return -1;
2561
2562 /* 965 can place panel fitter on either pipe */
2563 if (IS_I965G(dev))
2564 return (pfit_control >> 29) & 0x3;
2565
2566 /* older chips can only use pipe 1 */
2567 return 1;
2568 }
2569
2570 struct fdi_m_n {
2571 u32 tu;
2572 u32 gmch_m;
2573 u32 gmch_n;
2574 u32 link_m;
2575 u32 link_n;
2576 };
2577
2578 static void
2579 fdi_reduce_ratio(u32 *num, u32 *den)
2580 {
2581 while (*num > 0xffffff || *den > 0xffffff) {
2582 *num >>= 1;
2583 *den >>= 1;
2584 }
2585 }
2586
2587 #define DATA_N 0x800000
2588 #define LINK_N 0x80000
2589
2590 static void
2591 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2592 int link_clock, struct fdi_m_n *m_n)
2593 {
2594 u64 temp;
2595
2596 m_n->tu = 64; /* default size */
2597
2598 temp = (u64) DATA_N * pixel_clock;
2599 temp = div_u64(temp, link_clock);
2600 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2601 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2602 m_n->gmch_n = DATA_N;
2603 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2604
2605 temp = (u64) LINK_N * pixel_clock;
2606 m_n->link_m = div_u64(temp, link_clock);
2607 m_n->link_n = LINK_N;
2608 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2609 }
2610
2611
2612 struct intel_watermark_params {
2613 unsigned long fifo_size;
2614 unsigned long max_wm;
2615 unsigned long default_wm;
2616 unsigned long guard_size;
2617 unsigned long cacheline_size;
2618 };
2619
2620 /* Pineview has different values for various configs */
2621 static struct intel_watermark_params pineview_display_wm = {
2622 PINEVIEW_DISPLAY_FIFO,
2623 PINEVIEW_MAX_WM,
2624 PINEVIEW_DFT_WM,
2625 PINEVIEW_GUARD_WM,
2626 PINEVIEW_FIFO_LINE_SIZE
2627 };
2628 static struct intel_watermark_params pineview_display_hplloff_wm = {
2629 PINEVIEW_DISPLAY_FIFO,
2630 PINEVIEW_MAX_WM,
2631 PINEVIEW_DFT_HPLLOFF_WM,
2632 PINEVIEW_GUARD_WM,
2633 PINEVIEW_FIFO_LINE_SIZE
2634 };
2635 static struct intel_watermark_params pineview_cursor_wm = {
2636 PINEVIEW_CURSOR_FIFO,
2637 PINEVIEW_CURSOR_MAX_WM,
2638 PINEVIEW_CURSOR_DFT_WM,
2639 PINEVIEW_CURSOR_GUARD_WM,
2640 PINEVIEW_FIFO_LINE_SIZE,
2641 };
2642 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2643 PINEVIEW_CURSOR_FIFO,
2644 PINEVIEW_CURSOR_MAX_WM,
2645 PINEVIEW_CURSOR_DFT_WM,
2646 PINEVIEW_CURSOR_GUARD_WM,
2647 PINEVIEW_FIFO_LINE_SIZE
2648 };
2649 static struct intel_watermark_params g4x_wm_info = {
2650 G4X_FIFO_SIZE,
2651 G4X_MAX_WM,
2652 G4X_MAX_WM,
2653 2,
2654 G4X_FIFO_LINE_SIZE,
2655 };
2656 static struct intel_watermark_params g4x_cursor_wm_info = {
2657 I965_CURSOR_FIFO,
2658 I965_CURSOR_MAX_WM,
2659 I965_CURSOR_DFT_WM,
2660 2,
2661 G4X_FIFO_LINE_SIZE,
2662 };
2663 static struct intel_watermark_params i965_cursor_wm_info = {
2664 I965_CURSOR_FIFO,
2665 I965_CURSOR_MAX_WM,
2666 I965_CURSOR_DFT_WM,
2667 2,
2668 I915_FIFO_LINE_SIZE,
2669 };
2670 static struct intel_watermark_params i945_wm_info = {
2671 I945_FIFO_SIZE,
2672 I915_MAX_WM,
2673 1,
2674 2,
2675 I915_FIFO_LINE_SIZE
2676 };
2677 static struct intel_watermark_params i915_wm_info = {
2678 I915_FIFO_SIZE,
2679 I915_MAX_WM,
2680 1,
2681 2,
2682 I915_FIFO_LINE_SIZE
2683 };
2684 static struct intel_watermark_params i855_wm_info = {
2685 I855GM_FIFO_SIZE,
2686 I915_MAX_WM,
2687 1,
2688 2,
2689 I830_FIFO_LINE_SIZE
2690 };
2691 static struct intel_watermark_params i830_wm_info = {
2692 I830_FIFO_SIZE,
2693 I915_MAX_WM,
2694 1,
2695 2,
2696 I830_FIFO_LINE_SIZE
2697 };
2698
2699 static struct intel_watermark_params ironlake_display_wm_info = {
2700 ILK_DISPLAY_FIFO,
2701 ILK_DISPLAY_MAXWM,
2702 ILK_DISPLAY_DFTWM,
2703 2,
2704 ILK_FIFO_LINE_SIZE
2705 };
2706
2707 static struct intel_watermark_params ironlake_cursor_wm_info = {
2708 ILK_CURSOR_FIFO,
2709 ILK_CURSOR_MAXWM,
2710 ILK_CURSOR_DFTWM,
2711 2,
2712 ILK_FIFO_LINE_SIZE
2713 };
2714
2715 static struct intel_watermark_params ironlake_display_srwm_info = {
2716 ILK_DISPLAY_SR_FIFO,
2717 ILK_DISPLAY_MAX_SRWM,
2718 ILK_DISPLAY_DFT_SRWM,
2719 2,
2720 ILK_FIFO_LINE_SIZE
2721 };
2722
2723 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2724 ILK_CURSOR_SR_FIFO,
2725 ILK_CURSOR_MAX_SRWM,
2726 ILK_CURSOR_DFT_SRWM,
2727 2,
2728 ILK_FIFO_LINE_SIZE
2729 };
2730
2731 /**
2732 * intel_calculate_wm - calculate watermark level
2733 * @clock_in_khz: pixel clock
2734 * @wm: chip FIFO params
2735 * @pixel_size: display pixel size
2736 * @latency_ns: memory latency for the platform
2737 *
2738 * Calculate the watermark level (the level at which the display plane will
2739 * start fetching from memory again). Each chip has a different display
2740 * FIFO size and allocation, so the caller needs to figure that out and pass
2741 * in the correct intel_watermark_params structure.
2742 *
2743 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2744 * on the pixel size. When it reaches the watermark level, it'll start
2745 * fetching FIFO line sized based chunks from memory until the FIFO fills
2746 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2747 * will occur, and a display engine hang could result.
2748 */
2749 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2750 struct intel_watermark_params *wm,
2751 int pixel_size,
2752 unsigned long latency_ns)
2753 {
2754 long entries_required, wm_size;
2755
2756 /*
2757 * Note: we need to make sure we don't overflow for various clock &
2758 * latency values.
2759 * clocks go from a few thousand to several hundred thousand.
2760 * latency is usually a few thousand
2761 */
2762 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2763 1000;
2764 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2765
2766 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2767
2768 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2769
2770 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2771
2772 /* Don't promote wm_size to unsigned... */
2773 if (wm_size > (long)wm->max_wm)
2774 wm_size = wm->max_wm;
2775 if (wm_size <= 0)
2776 wm_size = wm->default_wm;
2777 return wm_size;
2778 }
2779
2780 struct cxsr_latency {
2781 int is_desktop;
2782 int is_ddr3;
2783 unsigned long fsb_freq;
2784 unsigned long mem_freq;
2785 unsigned long display_sr;
2786 unsigned long display_hpll_disable;
2787 unsigned long cursor_sr;
2788 unsigned long cursor_hpll_disable;
2789 };
2790
2791 static const struct cxsr_latency cxsr_latency_table[] = {
2792 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2793 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2794 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2795 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2796 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2797
2798 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2799 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2800 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2801 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2802 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2803
2804 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2805 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2806 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2807 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2808 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2809
2810 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2811 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2812 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2813 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2814 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2815
2816 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2817 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2818 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2819 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2820 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2821
2822 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2823 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2824 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2825 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2826 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2827 };
2828
2829 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2830 int is_ddr3,
2831 int fsb,
2832 int mem)
2833 {
2834 const struct cxsr_latency *latency;
2835 int i;
2836
2837 if (fsb == 0 || mem == 0)
2838 return NULL;
2839
2840 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2841 latency = &cxsr_latency_table[i];
2842 if (is_desktop == latency->is_desktop &&
2843 is_ddr3 == latency->is_ddr3 &&
2844 fsb == latency->fsb_freq && mem == latency->mem_freq)
2845 return latency;
2846 }
2847
2848 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2849
2850 return NULL;
2851 }
2852
2853 static void pineview_disable_cxsr(struct drm_device *dev)
2854 {
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857 /* deactivate cxsr */
2858 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2859 }
2860
2861 /*
2862 * Latency for FIFO fetches is dependent on several factors:
2863 * - memory configuration (speed, channels)
2864 * - chipset
2865 * - current MCH state
2866 * It can be fairly high in some situations, so here we assume a fairly
2867 * pessimal value. It's a tradeoff between extra memory fetches (if we
2868 * set this value too high, the FIFO will fetch frequently to stay full)
2869 * and power consumption (set it too low to save power and we might see
2870 * FIFO underruns and display "flicker").
2871 *
2872 * A value of 5us seems to be a good balance; safe for very low end
2873 * platforms but not overly aggressive on lower latency configs.
2874 */
2875 static const int latency_ns = 5000;
2876
2877 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2878 {
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2880 uint32_t dsparb = I915_READ(DSPARB);
2881 int size;
2882
2883 size = dsparb & 0x7f;
2884 if (plane)
2885 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2886
2887 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2888 plane ? "B" : "A", size);
2889
2890 return size;
2891 }
2892
2893 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2894 {
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 uint32_t dsparb = I915_READ(DSPARB);
2897 int size;
2898
2899 size = dsparb & 0x1ff;
2900 if (plane)
2901 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2902 size >>= 1; /* Convert to cachelines */
2903
2904 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2905 plane ? "B" : "A", size);
2906
2907 return size;
2908 }
2909
2910 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2911 {
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 uint32_t dsparb = I915_READ(DSPARB);
2914 int size;
2915
2916 size = dsparb & 0x7f;
2917 size >>= 2; /* Convert to cachelines */
2918
2919 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2920 plane ? "B" : "A",
2921 size);
2922
2923 return size;
2924 }
2925
2926 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2927 {
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 uint32_t dsparb = I915_READ(DSPARB);
2930 int size;
2931
2932 size = dsparb & 0x7f;
2933 size >>= 1; /* Convert to cachelines */
2934
2935 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2936 plane ? "B" : "A", size);
2937
2938 return size;
2939 }
2940
2941 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2942 int planeb_clock, int sr_hdisplay, int unused,
2943 int pixel_size)
2944 {
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946 const struct cxsr_latency *latency;
2947 u32 reg;
2948 unsigned long wm;
2949 int sr_clock;
2950
2951 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
2952 dev_priv->fsb_freq, dev_priv->mem_freq);
2953 if (!latency) {
2954 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2955 pineview_disable_cxsr(dev);
2956 return;
2957 }
2958
2959 if (!planea_clock || !planeb_clock) {
2960 sr_clock = planea_clock ? planea_clock : planeb_clock;
2961
2962 /* Display SR */
2963 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2964 pixel_size, latency->display_sr);
2965 reg = I915_READ(DSPFW1);
2966 reg &= ~DSPFW_SR_MASK;
2967 reg |= wm << DSPFW_SR_SHIFT;
2968 I915_WRITE(DSPFW1, reg);
2969 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2970
2971 /* cursor SR */
2972 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2973 pixel_size, latency->cursor_sr);
2974 reg = I915_READ(DSPFW3);
2975 reg &= ~DSPFW_CURSOR_SR_MASK;
2976 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2977 I915_WRITE(DSPFW3, reg);
2978
2979 /* Display HPLL off SR */
2980 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2981 pixel_size, latency->display_hpll_disable);
2982 reg = I915_READ(DSPFW3);
2983 reg &= ~DSPFW_HPLL_SR_MASK;
2984 reg |= wm & DSPFW_HPLL_SR_MASK;
2985 I915_WRITE(DSPFW3, reg);
2986
2987 /* cursor HPLL off SR */
2988 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2989 pixel_size, latency->cursor_hpll_disable);
2990 reg = I915_READ(DSPFW3);
2991 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2992 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2993 I915_WRITE(DSPFW3, reg);
2994 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2995
2996 /* activate cxsr */
2997 I915_WRITE(DSPFW3,
2998 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
2999 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3000 } else {
3001 pineview_disable_cxsr(dev);
3002 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3003 }
3004 }
3005
3006 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3007 int planeb_clock, int sr_hdisplay, int sr_htotal,
3008 int pixel_size)
3009 {
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 int total_size, cacheline_size;
3012 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3013 struct intel_watermark_params planea_params, planeb_params;
3014 unsigned long line_time_us;
3015 int sr_clock, sr_entries = 0, entries_required;
3016
3017 /* Create copies of the base settings for each pipe */
3018 planea_params = planeb_params = g4x_wm_info;
3019
3020 /* Grab a couple of global values before we overwrite them */
3021 total_size = planea_params.fifo_size;
3022 cacheline_size = planea_params.cacheline_size;
3023
3024 /*
3025 * Note: we need to make sure we don't overflow for various clock &
3026 * latency values.
3027 * clocks go from a few thousand to several hundred thousand.
3028 * latency is usually a few thousand
3029 */
3030 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3031 1000;
3032 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3033 planea_wm = entries_required + planea_params.guard_size;
3034
3035 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3036 1000;
3037 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3038 planeb_wm = entries_required + planeb_params.guard_size;
3039
3040 cursora_wm = cursorb_wm = 16;
3041 cursor_sr = 32;
3042
3043 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3044
3045 /* Calc sr entries for one plane configs */
3046 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3047 /* self-refresh has much higher latency */
3048 static const int sr_latency_ns = 12000;
3049
3050 sr_clock = planea_clock ? planea_clock : planeb_clock;
3051 line_time_us = ((sr_htotal * 1000) / sr_clock);
3052
3053 /* Use ns/us then divide to preserve precision */
3054 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3055 pixel_size * sr_hdisplay;
3056 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3057
3058 entries_required = (((sr_latency_ns / line_time_us) +
3059 1000) / 1000) * pixel_size * 64;
3060 entries_required = DIV_ROUND_UP(entries_required,
3061 g4x_cursor_wm_info.cacheline_size);
3062 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3063
3064 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3065 cursor_sr = g4x_cursor_wm_info.max_wm;
3066 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3067 "cursor %d\n", sr_entries, cursor_sr);
3068
3069 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3070 } else {
3071 /* Turn off self refresh if both pipes are enabled */
3072 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3073 & ~FW_BLC_SELF_EN);
3074 }
3075
3076 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3077 planea_wm, planeb_wm, sr_entries);
3078
3079 planea_wm &= 0x3f;
3080 planeb_wm &= 0x3f;
3081
3082 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3083 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3084 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3085 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3086 (cursora_wm << DSPFW_CURSORA_SHIFT));
3087 /* HPLL off in SR has some issues on G4x... disable it */
3088 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3089 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3090 }
3091
3092 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3093 int planeb_clock, int sr_hdisplay, int sr_htotal,
3094 int pixel_size)
3095 {
3096 struct drm_i915_private *dev_priv = dev->dev_private;
3097 unsigned long line_time_us;
3098 int sr_clock, sr_entries, srwm = 1;
3099 int cursor_sr = 16;
3100
3101 /* Calc sr entries for one plane configs */
3102 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3103 /* self-refresh has much higher latency */
3104 static const int sr_latency_ns = 12000;
3105
3106 sr_clock = planea_clock ? planea_clock : planeb_clock;
3107 line_time_us = ((sr_htotal * 1000) / sr_clock);
3108
3109 /* Use ns/us then divide to preserve precision */
3110 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3111 pixel_size * sr_hdisplay;
3112 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3113 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3114 srwm = I965_FIFO_SIZE - sr_entries;
3115 if (srwm < 0)
3116 srwm = 1;
3117 srwm &= 0x1ff;
3118
3119 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3120 pixel_size * 64;
3121 sr_entries = DIV_ROUND_UP(sr_entries,
3122 i965_cursor_wm_info.cacheline_size);
3123 cursor_sr = i965_cursor_wm_info.fifo_size -
3124 (sr_entries + i965_cursor_wm_info.guard_size);
3125
3126 if (cursor_sr > i965_cursor_wm_info.max_wm)
3127 cursor_sr = i965_cursor_wm_info.max_wm;
3128
3129 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3130 "cursor %d\n", srwm, cursor_sr);
3131
3132 if (IS_I965GM(dev))
3133 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3134 } else {
3135 /* Turn off self refresh if both pipes are enabled */
3136 if (IS_I965GM(dev))
3137 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3138 & ~FW_BLC_SELF_EN);
3139 }
3140
3141 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3142 srwm);
3143
3144 /* 965 has limitations... */
3145 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3146 (8 << 0));
3147 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3148 /* update cursor SR watermark */
3149 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3150 }
3151
3152 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3153 int planeb_clock, int sr_hdisplay, int sr_htotal,
3154 int pixel_size)
3155 {
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 uint32_t fwater_lo;
3158 uint32_t fwater_hi;
3159 int total_size, cacheline_size, cwm, srwm = 1;
3160 int planea_wm, planeb_wm;
3161 struct intel_watermark_params planea_params, planeb_params;
3162 unsigned long line_time_us;
3163 int sr_clock, sr_entries = 0;
3164
3165 /* Create copies of the base settings for each pipe */
3166 if (IS_I965GM(dev) || IS_I945GM(dev))
3167 planea_params = planeb_params = i945_wm_info;
3168 else if (IS_I9XX(dev))
3169 planea_params = planeb_params = i915_wm_info;
3170 else
3171 planea_params = planeb_params = i855_wm_info;
3172
3173 /* Grab a couple of global values before we overwrite them */
3174 total_size = planea_params.fifo_size;
3175 cacheline_size = planea_params.cacheline_size;
3176
3177 /* Update per-plane FIFO sizes */
3178 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3179 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3180
3181 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3182 pixel_size, latency_ns);
3183 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3184 pixel_size, latency_ns);
3185 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3186
3187 /*
3188 * Overlay gets an aggressive default since video jitter is bad.
3189 */
3190 cwm = 2;
3191
3192 /* Calc sr entries for one plane configs */
3193 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3194 (!planea_clock || !planeb_clock)) {
3195 /* self-refresh has much higher latency */
3196 static const int sr_latency_ns = 6000;
3197
3198 sr_clock = planea_clock ? planea_clock : planeb_clock;
3199 line_time_us = ((sr_htotal * 1000) / sr_clock);
3200
3201 /* Use ns/us then divide to preserve precision */
3202 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3203 pixel_size * sr_hdisplay;
3204 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3205 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3206 srwm = total_size - sr_entries;
3207 if (srwm < 0)
3208 srwm = 1;
3209
3210 if (IS_I945G(dev) || IS_I945GM(dev))
3211 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3212 else if (IS_I915GM(dev)) {
3213 /* 915M has a smaller SRWM field */
3214 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3215 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3216 }
3217 } else {
3218 /* Turn off self refresh if both pipes are enabled */
3219 if (IS_I945G(dev) || IS_I945GM(dev)) {
3220 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3221 & ~FW_BLC_SELF_EN);
3222 } else if (IS_I915GM(dev)) {
3223 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3224 }
3225 }
3226
3227 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3228 planea_wm, planeb_wm, cwm, srwm);
3229
3230 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3231 fwater_hi = (cwm & 0x1f);
3232
3233 /* Set request length to 8 cachelines per fetch */
3234 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3235 fwater_hi = fwater_hi | (1 << 8);
3236
3237 I915_WRITE(FW_BLC, fwater_lo);
3238 I915_WRITE(FW_BLC2, fwater_hi);
3239 }
3240
3241 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3242 int unused2, int unused3, int pixel_size)
3243 {
3244 struct drm_i915_private *dev_priv = dev->dev_private;
3245 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3246 int planea_wm;
3247
3248 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3249
3250 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3251 pixel_size, latency_ns);
3252 fwater_lo |= (3<<8) | planea_wm;
3253
3254 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3255
3256 I915_WRITE(FW_BLC, fwater_lo);
3257 }
3258
3259 #define ILK_LP0_PLANE_LATENCY 700
3260 #define ILK_LP0_CURSOR_LATENCY 1300
3261
3262 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3263 int planeb_clock, int sr_hdisplay, int sr_htotal,
3264 int pixel_size)
3265 {
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3268 int sr_wm, cursor_wm;
3269 unsigned long line_time_us;
3270 int sr_clock, entries_required;
3271 u32 reg_value;
3272 int line_count;
3273 int planea_htotal = 0, planeb_htotal = 0;
3274 struct drm_crtc *crtc;
3275
3276 /* Need htotal for all active display plane */
3277 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3279 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3280 if (intel_crtc->plane == 0)
3281 planea_htotal = crtc->mode.htotal;
3282 else
3283 planeb_htotal = crtc->mode.htotal;
3284 }
3285 }
3286
3287 /* Calculate and update the watermark for plane A */
3288 if (planea_clock) {
3289 entries_required = ((planea_clock / 1000) * pixel_size *
3290 ILK_LP0_PLANE_LATENCY) / 1000;
3291 entries_required = DIV_ROUND_UP(entries_required,
3292 ironlake_display_wm_info.cacheline_size);
3293 planea_wm = entries_required +
3294 ironlake_display_wm_info.guard_size;
3295
3296 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3297 planea_wm = ironlake_display_wm_info.max_wm;
3298
3299 /* Use the large buffer method to calculate cursor watermark */
3300 line_time_us = (planea_htotal * 1000) / planea_clock;
3301
3302 /* Use ns/us then divide to preserve precision */
3303 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3304
3305 /* calculate the cursor watermark for cursor A */
3306 entries_required = line_count * 64 * pixel_size;
3307 entries_required = DIV_ROUND_UP(entries_required,
3308 ironlake_cursor_wm_info.cacheline_size);
3309 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3310 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3311 cursora_wm = ironlake_cursor_wm_info.max_wm;
3312
3313 reg_value = I915_READ(WM0_PIPEA_ILK);
3314 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3315 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3316 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3317 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3318 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3319 "cursor: %d\n", planea_wm, cursora_wm);
3320 }
3321 /* Calculate and update the watermark for plane B */
3322 if (planeb_clock) {
3323 entries_required = ((planeb_clock / 1000) * pixel_size *
3324 ILK_LP0_PLANE_LATENCY) / 1000;
3325 entries_required = DIV_ROUND_UP(entries_required,
3326 ironlake_display_wm_info.cacheline_size);
3327 planeb_wm = entries_required +
3328 ironlake_display_wm_info.guard_size;
3329
3330 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3331 planeb_wm = ironlake_display_wm_info.max_wm;
3332
3333 /* Use the large buffer method to calculate cursor watermark */
3334 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3335
3336 /* Use ns/us then divide to preserve precision */
3337 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3338
3339 /* calculate the cursor watermark for cursor B */
3340 entries_required = line_count * 64 * pixel_size;
3341 entries_required = DIV_ROUND_UP(entries_required,
3342 ironlake_cursor_wm_info.cacheline_size);
3343 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3344 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3345 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3346
3347 reg_value = I915_READ(WM0_PIPEB_ILK);
3348 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3349 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3350 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3351 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3352 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3353 "cursor: %d\n", planeb_wm, cursorb_wm);
3354 }
3355
3356 /*
3357 * Calculate and update the self-refresh watermark only when one
3358 * display plane is used.
3359 */
3360 if (!planea_clock || !planeb_clock) {
3361
3362 /* Read the self-refresh latency. The unit is 0.5us */
3363 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3364
3365 sr_clock = planea_clock ? planea_clock : planeb_clock;
3366 line_time_us = ((sr_htotal * 1000) / sr_clock);
3367
3368 /* Use ns/us then divide to preserve precision */
3369 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3370 / 1000;
3371
3372 /* calculate the self-refresh watermark for display plane */
3373 entries_required = line_count * sr_hdisplay * pixel_size;
3374 entries_required = DIV_ROUND_UP(entries_required,
3375 ironlake_display_srwm_info.cacheline_size);
3376 sr_wm = entries_required +
3377 ironlake_display_srwm_info.guard_size;
3378
3379 /* calculate the self-refresh watermark for display cursor */
3380 entries_required = line_count * pixel_size * 64;
3381 entries_required = DIV_ROUND_UP(entries_required,
3382 ironlake_cursor_srwm_info.cacheline_size);
3383 cursor_wm = entries_required +
3384 ironlake_cursor_srwm_info.guard_size;
3385
3386 /* configure watermark and enable self-refresh */
3387 reg_value = I915_READ(WM1_LP_ILK);
3388 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3389 WM1_LP_CURSOR_MASK);
3390 reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3391 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3392
3393 I915_WRITE(WM1_LP_ILK, reg_value);
3394 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3395 "cursor %d\n", sr_wm, cursor_wm);
3396
3397 } else {
3398 /* Turn off self refresh if both pipes are enabled */
3399 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3400 }
3401 }
3402 /**
3403 * intel_update_watermarks - update FIFO watermark values based on current modes
3404 *
3405 * Calculate watermark values for the various WM regs based on current mode
3406 * and plane configuration.
3407 *
3408 * There are several cases to deal with here:
3409 * - normal (i.e. non-self-refresh)
3410 * - self-refresh (SR) mode
3411 * - lines are large relative to FIFO size (buffer can hold up to 2)
3412 * - lines are small relative to FIFO size (buffer can hold more than 2
3413 * lines), so need to account for TLB latency
3414 *
3415 * The normal calculation is:
3416 * watermark = dotclock * bytes per pixel * latency
3417 * where latency is platform & configuration dependent (we assume pessimal
3418 * values here).
3419 *
3420 * The SR calculation is:
3421 * watermark = (trunc(latency/line time)+1) * surface width *
3422 * bytes per pixel
3423 * where
3424 * line time = htotal / dotclock
3425 * surface width = hdisplay for normal plane and 64 for cursor
3426 * and latency is assumed to be high, as above.
3427 *
3428 * The final value programmed to the register should always be rounded up,
3429 * and include an extra 2 entries to account for clock crossings.
3430 *
3431 * We don't use the sprite, so we can ignore that. And on Crestline we have
3432 * to set the non-SR watermarks to 8.
3433 */
3434 static void intel_update_watermarks(struct drm_device *dev)
3435 {
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 struct drm_crtc *crtc;
3438 int sr_hdisplay = 0;
3439 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3440 int enabled = 0, pixel_size = 0;
3441 int sr_htotal = 0;
3442
3443 if (!dev_priv->display.update_wm)
3444 return;
3445
3446 /* Get the clock config from both planes */
3447 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3449 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3450 enabled++;
3451 if (intel_crtc->plane == 0) {
3452 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3453 intel_crtc->pipe, crtc->mode.clock);
3454 planea_clock = crtc->mode.clock;
3455 } else {
3456 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3457 intel_crtc->pipe, crtc->mode.clock);
3458 planeb_clock = crtc->mode.clock;
3459 }
3460 sr_hdisplay = crtc->mode.hdisplay;
3461 sr_clock = crtc->mode.clock;
3462 sr_htotal = crtc->mode.htotal;
3463 if (crtc->fb)
3464 pixel_size = crtc->fb->bits_per_pixel / 8;
3465 else
3466 pixel_size = 4; /* by default */
3467 }
3468 }
3469
3470 if (enabled <= 0)
3471 return;
3472
3473 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3474 sr_hdisplay, sr_htotal, pixel_size);
3475 }
3476
3477 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3478 struct drm_display_mode *mode,
3479 struct drm_display_mode *adjusted_mode,
3480 int x, int y,
3481 struct drm_framebuffer *old_fb)
3482 {
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3486 int pipe = intel_crtc->pipe;
3487 int plane = intel_crtc->plane;
3488 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3489 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3490 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3491 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3492 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3493 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3494 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3495 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3496 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3497 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3498 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3499 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3500 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3501 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3502 int refclk, num_connectors = 0;
3503 intel_clock_t clock, reduced_clock;
3504 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3505 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3506 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3507 struct intel_encoder *has_edp_encoder = NULL;
3508 struct drm_mode_config *mode_config = &dev->mode_config;
3509 struct drm_encoder *encoder;
3510 const intel_limit_t *limit;
3511 int ret;
3512 struct fdi_m_n m_n = {0};
3513 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3514 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3515 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3516 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3517 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3518 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3519 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3520 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3521 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3522 int lvds_reg = LVDS;
3523 u32 temp;
3524 int sdvo_pixel_multiply;
3525 int target_clock;
3526
3527 drm_vblank_pre_modeset(dev, pipe);
3528
3529 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3530 struct intel_encoder *intel_encoder;
3531
3532 if (encoder->crtc != crtc)
3533 continue;
3534
3535 intel_encoder = enc_to_intel_encoder(encoder);
3536 switch (intel_encoder->type) {
3537 case INTEL_OUTPUT_LVDS:
3538 is_lvds = true;
3539 break;
3540 case INTEL_OUTPUT_SDVO:
3541 case INTEL_OUTPUT_HDMI:
3542 is_sdvo = true;
3543 if (intel_encoder->needs_tv_clock)
3544 is_tv = true;
3545 break;
3546 case INTEL_OUTPUT_DVO:
3547 is_dvo = true;
3548 break;
3549 case INTEL_OUTPUT_TVOUT:
3550 is_tv = true;
3551 break;
3552 case INTEL_OUTPUT_ANALOG:
3553 is_crt = true;
3554 break;
3555 case INTEL_OUTPUT_DISPLAYPORT:
3556 is_dp = true;
3557 break;
3558 case INTEL_OUTPUT_EDP:
3559 has_edp_encoder = intel_encoder;
3560 break;
3561 }
3562
3563 num_connectors++;
3564 }
3565
3566 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3567 refclk = dev_priv->lvds_ssc_freq * 1000;
3568 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3569 refclk / 1000);
3570 } else if (IS_I9XX(dev)) {
3571 refclk = 96000;
3572 if (HAS_PCH_SPLIT(dev))
3573 refclk = 120000; /* 120Mhz refclk */
3574 } else {
3575 refclk = 48000;
3576 }
3577
3578
3579 /*
3580 * Returns a set of divisors for the desired target clock with the given
3581 * refclk, or FALSE. The returned values represent the clock equation:
3582 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3583 */
3584 limit = intel_limit(crtc);
3585 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3586 if (!ok) {
3587 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3588 drm_vblank_post_modeset(dev, pipe);
3589 return -EINVAL;
3590 }
3591
3592 /* Ensure that the cursor is valid for the new mode before changing... */
3593 intel_crtc_update_cursor(crtc);
3594
3595 if (is_lvds && dev_priv->lvds_downclock_avail) {
3596 has_reduced_clock = limit->find_pll(limit, crtc,
3597 dev_priv->lvds_downclock,
3598 refclk,
3599 &reduced_clock);
3600 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3601 /*
3602 * If the different P is found, it means that we can't
3603 * switch the display clock by using the FP0/FP1.
3604 * In such case we will disable the LVDS downclock
3605 * feature.
3606 */
3607 DRM_DEBUG_KMS("Different P is found for "
3608 "LVDS clock/downclock\n");
3609 has_reduced_clock = 0;
3610 }
3611 }
3612 /* SDVO TV has fixed PLL values depend on its clock range,
3613 this mirrors vbios setting. */
3614 if (is_sdvo && is_tv) {
3615 if (adjusted_mode->clock >= 100000
3616 && adjusted_mode->clock < 140500) {
3617 clock.p1 = 2;
3618 clock.p2 = 10;
3619 clock.n = 3;
3620 clock.m1 = 16;
3621 clock.m2 = 8;
3622 } else if (adjusted_mode->clock >= 140500
3623 && adjusted_mode->clock <= 200000) {
3624 clock.p1 = 1;
3625 clock.p2 = 10;
3626 clock.n = 6;
3627 clock.m1 = 12;
3628 clock.m2 = 8;
3629 }
3630 }
3631
3632 /* FDI link */
3633 if (HAS_PCH_SPLIT(dev)) {
3634 int lane = 0, link_bw, bpp;
3635 /* eDP doesn't require FDI link, so just set DP M/N
3636 according to current link config */
3637 if (has_edp_encoder) {
3638 target_clock = mode->clock;
3639 intel_edp_link_config(has_edp_encoder,
3640 &lane, &link_bw);
3641 } else {
3642 /* DP over FDI requires target mode clock
3643 instead of link clock */
3644 if (is_dp)
3645 target_clock = mode->clock;
3646 else
3647 target_clock = adjusted_mode->clock;
3648 link_bw = 270000;
3649 }
3650
3651 /* determine panel color depth */
3652 temp = I915_READ(pipeconf_reg);
3653 temp &= ~PIPE_BPC_MASK;
3654 if (is_lvds) {
3655 int lvds_reg = I915_READ(PCH_LVDS);
3656 /* the BPC will be 6 if it is 18-bit LVDS panel */
3657 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3658 temp |= PIPE_8BPC;
3659 else
3660 temp |= PIPE_6BPC;
3661 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3662 switch (dev_priv->edp_bpp/3) {
3663 case 8:
3664 temp |= PIPE_8BPC;
3665 break;
3666 case 10:
3667 temp |= PIPE_10BPC;
3668 break;
3669 case 6:
3670 temp |= PIPE_6BPC;
3671 break;
3672 case 12:
3673 temp |= PIPE_12BPC;
3674 break;
3675 }
3676 } else
3677 temp |= PIPE_8BPC;
3678 I915_WRITE(pipeconf_reg, temp);
3679 I915_READ(pipeconf_reg);
3680
3681 switch (temp & PIPE_BPC_MASK) {
3682 case PIPE_8BPC:
3683 bpp = 24;
3684 break;
3685 case PIPE_10BPC:
3686 bpp = 30;
3687 break;
3688 case PIPE_6BPC:
3689 bpp = 18;
3690 break;
3691 case PIPE_12BPC:
3692 bpp = 36;
3693 break;
3694 default:
3695 DRM_ERROR("unknown pipe bpc value\n");
3696 bpp = 24;
3697 }
3698
3699 if (!lane) {
3700 /*
3701 * Account for spread spectrum to avoid
3702 * oversubscribing the link. Max center spread
3703 * is 2.5%; use 5% for safety's sake.
3704 */
3705 u32 bps = target_clock * bpp * 21 / 20;
3706 lane = bps / (link_bw * 8) + 1;
3707 }
3708
3709 intel_crtc->fdi_lanes = lane;
3710
3711 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3712 }
3713
3714 /* Ironlake: try to setup display ref clock before DPLL
3715 * enabling. This is only under driver's control after
3716 * PCH B stepping, previous chipset stepping should be
3717 * ignoring this setting.
3718 */
3719 if (HAS_PCH_SPLIT(dev)) {
3720 temp = I915_READ(PCH_DREF_CONTROL);
3721 /* Always enable nonspread source */
3722 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3723 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3724 I915_WRITE(PCH_DREF_CONTROL, temp);
3725 POSTING_READ(PCH_DREF_CONTROL);
3726
3727 temp &= ~DREF_SSC_SOURCE_MASK;
3728 temp |= DREF_SSC_SOURCE_ENABLE;
3729 I915_WRITE(PCH_DREF_CONTROL, temp);
3730 POSTING_READ(PCH_DREF_CONTROL);
3731
3732 udelay(200);
3733
3734 if (has_edp_encoder) {
3735 if (dev_priv->lvds_use_ssc) {
3736 temp |= DREF_SSC1_ENABLE;
3737 I915_WRITE(PCH_DREF_CONTROL, temp);
3738 POSTING_READ(PCH_DREF_CONTROL);
3739
3740 udelay(200);
3741
3742 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3743 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3744 I915_WRITE(PCH_DREF_CONTROL, temp);
3745 POSTING_READ(PCH_DREF_CONTROL);
3746 } else {
3747 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3748 I915_WRITE(PCH_DREF_CONTROL, temp);
3749 POSTING_READ(PCH_DREF_CONTROL);
3750 }
3751 }
3752 }
3753
3754 if (IS_PINEVIEW(dev)) {
3755 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3756 if (has_reduced_clock)
3757 fp2 = (1 << reduced_clock.n) << 16 |
3758 reduced_clock.m1 << 8 | reduced_clock.m2;
3759 } else {
3760 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3761 if (has_reduced_clock)
3762 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3763 reduced_clock.m2;
3764 }
3765
3766 if (!HAS_PCH_SPLIT(dev))
3767 dpll = DPLL_VGA_MODE_DIS;
3768
3769 if (IS_I9XX(dev)) {
3770 if (is_lvds)
3771 dpll |= DPLLB_MODE_LVDS;
3772 else
3773 dpll |= DPLLB_MODE_DAC_SERIAL;
3774 if (is_sdvo) {
3775 dpll |= DPLL_DVO_HIGH_SPEED;
3776 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3777 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3778 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3779 else if (HAS_PCH_SPLIT(dev))
3780 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3781 }
3782 if (is_dp)
3783 dpll |= DPLL_DVO_HIGH_SPEED;
3784
3785 /* compute bitmask from p1 value */
3786 if (IS_PINEVIEW(dev))
3787 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3788 else {
3789 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3790 /* also FPA1 */
3791 if (HAS_PCH_SPLIT(dev))
3792 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3793 if (IS_G4X(dev) && has_reduced_clock)
3794 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3795 }
3796 switch (clock.p2) {
3797 case 5:
3798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3799 break;
3800 case 7:
3801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3802 break;
3803 case 10:
3804 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3805 break;
3806 case 14:
3807 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3808 break;
3809 }
3810 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3811 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3812 } else {
3813 if (is_lvds) {
3814 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3815 } else {
3816 if (clock.p1 == 2)
3817 dpll |= PLL_P1_DIVIDE_BY_TWO;
3818 else
3819 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3820 if (clock.p2 == 4)
3821 dpll |= PLL_P2_DIVIDE_BY_4;
3822 }
3823 }
3824
3825 if (is_sdvo && is_tv)
3826 dpll |= PLL_REF_INPUT_TVCLKINBC;
3827 else if (is_tv)
3828 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3829 dpll |= 3;
3830 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3831 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3832 else
3833 dpll |= PLL_REF_INPUT_DREFCLK;
3834
3835 /* setup pipeconf */
3836 pipeconf = I915_READ(pipeconf_reg);
3837
3838 /* Set up the display plane register */
3839 dspcntr = DISPPLANE_GAMMA_ENABLE;
3840
3841 /* Ironlake's plane is forced to pipe, bit 24 is to
3842 enable color space conversion */
3843 if (!HAS_PCH_SPLIT(dev)) {
3844 if (pipe == 0)
3845 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3846 else
3847 dspcntr |= DISPPLANE_SEL_PIPE_B;
3848 }
3849
3850 if (pipe == 0 && !IS_I965G(dev)) {
3851 if (mode->clock >
3852 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3853 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3854 else
3855 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3856 }
3857
3858 dspcntr |= DISPLAY_PLANE_ENABLE;
3859 pipeconf |= PIPEACONF_ENABLE;
3860 dpll |= DPLL_VCO_ENABLE;
3861
3862
3863 /* Disable the panel fitter if it was on our pipe */
3864 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3865 I915_WRITE(PFIT_CONTROL, 0);
3866
3867 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3868 drm_mode_debug_printmodeline(mode);
3869
3870 /* assign to Ironlake registers */
3871 if (HAS_PCH_SPLIT(dev)) {
3872 fp_reg = pch_fp_reg;
3873 dpll_reg = pch_dpll_reg;
3874 }
3875
3876 if (!has_edp_encoder) {
3877 I915_WRITE(fp_reg, fp);
3878 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3879 I915_READ(dpll_reg);
3880 udelay(150);
3881 }
3882
3883 /* enable transcoder DPLL */
3884 if (HAS_PCH_CPT(dev)) {
3885 temp = I915_READ(PCH_DPLL_SEL);
3886 if (trans_dpll_sel == 0)
3887 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3888 else
3889 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3890 I915_WRITE(PCH_DPLL_SEL, temp);
3891 I915_READ(PCH_DPLL_SEL);
3892 udelay(150);
3893 }
3894
3895 if (HAS_PCH_SPLIT(dev)) {
3896 pipeconf &= ~PIPE_ENABLE_DITHER;
3897 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3898 }
3899
3900 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3901 * This is an exception to the general rule that mode_set doesn't turn
3902 * things on.
3903 */
3904 if (is_lvds) {
3905 u32 lvds;
3906
3907 if (HAS_PCH_SPLIT(dev))
3908 lvds_reg = PCH_LVDS;
3909
3910 lvds = I915_READ(lvds_reg);
3911 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3912 if (pipe == 1) {
3913 if (HAS_PCH_CPT(dev))
3914 lvds |= PORT_TRANS_B_SEL_CPT;
3915 else
3916 lvds |= LVDS_PIPEB_SELECT;
3917 } else {
3918 if (HAS_PCH_CPT(dev))
3919 lvds &= ~PORT_TRANS_SEL_MASK;
3920 else
3921 lvds &= ~LVDS_PIPEB_SELECT;
3922 }
3923 /* set the corresponsding LVDS_BORDER bit */
3924 lvds |= dev_priv->lvds_border_bits;
3925 /* Set the B0-B3 data pairs corresponding to whether we're going to
3926 * set the DPLLs for dual-channel mode or not.
3927 */
3928 if (clock.p2 == 7)
3929 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3930 else
3931 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3932
3933 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3934 * appropriately here, but we need to look more thoroughly into how
3935 * panels behave in the two modes.
3936 */
3937 /* set the dithering flag */
3938 if (IS_I965G(dev)) {
3939 if (dev_priv->lvds_dither) {
3940 if (HAS_PCH_SPLIT(dev)) {
3941 pipeconf |= PIPE_ENABLE_DITHER;
3942 pipeconf |= PIPE_DITHER_TYPE_ST01;
3943 } else
3944 lvds |= LVDS_ENABLE_DITHER;
3945 } else {
3946 if (!HAS_PCH_SPLIT(dev)) {
3947 lvds &= ~LVDS_ENABLE_DITHER;
3948 }
3949 }
3950 }
3951 I915_WRITE(lvds_reg, lvds);
3952 I915_READ(lvds_reg);
3953 }
3954 if (is_dp)
3955 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3956 else if (HAS_PCH_SPLIT(dev)) {
3957 /* For non-DP output, clear any trans DP clock recovery setting.*/
3958 if (pipe == 0) {
3959 I915_WRITE(TRANSA_DATA_M1, 0);
3960 I915_WRITE(TRANSA_DATA_N1, 0);
3961 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3962 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3963 } else {
3964 I915_WRITE(TRANSB_DATA_M1, 0);
3965 I915_WRITE(TRANSB_DATA_N1, 0);
3966 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3967 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3968 }
3969 }
3970
3971 if (!has_edp_encoder) {
3972 I915_WRITE(fp_reg, fp);
3973 I915_WRITE(dpll_reg, dpll);
3974 I915_READ(dpll_reg);
3975 /* Wait for the clocks to stabilize. */
3976 udelay(150);
3977
3978 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3979 if (is_sdvo) {
3980 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3981 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3982 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3983 } else
3984 I915_WRITE(dpll_md_reg, 0);
3985 } else {
3986 /* write it again -- the BIOS does, after all */
3987 I915_WRITE(dpll_reg, dpll);
3988 }
3989 I915_READ(dpll_reg);
3990 /* Wait for the clocks to stabilize. */
3991 udelay(150);
3992 }
3993
3994 if (is_lvds && has_reduced_clock && i915_powersave) {
3995 I915_WRITE(fp_reg + 4, fp2);
3996 intel_crtc->lowfreq_avail = true;
3997 if (HAS_PIPE_CXSR(dev)) {
3998 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3999 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4000 }
4001 } else {
4002 I915_WRITE(fp_reg + 4, fp);
4003 intel_crtc->lowfreq_avail = false;
4004 if (HAS_PIPE_CXSR(dev)) {
4005 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4006 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4007 }
4008 }
4009
4010 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4011 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4012 /* the chip adds 2 halflines automatically */
4013 adjusted_mode->crtc_vdisplay -= 1;
4014 adjusted_mode->crtc_vtotal -= 1;
4015 adjusted_mode->crtc_vblank_start -= 1;
4016 adjusted_mode->crtc_vblank_end -= 1;
4017 adjusted_mode->crtc_vsync_end -= 1;
4018 adjusted_mode->crtc_vsync_start -= 1;
4019 } else
4020 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4021
4022 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4023 ((adjusted_mode->crtc_htotal - 1) << 16));
4024 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4025 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4026 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4027 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4028 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4029 ((adjusted_mode->crtc_vtotal - 1) << 16));
4030 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4031 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4032 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4033 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4034 /* pipesrc and dspsize control the size that is scaled from, which should
4035 * always be the user's requested size.
4036 */
4037 if (!HAS_PCH_SPLIT(dev)) {
4038 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4039 (mode->hdisplay - 1));
4040 I915_WRITE(dsppos_reg, 0);
4041 }
4042 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4043
4044 if (HAS_PCH_SPLIT(dev)) {
4045 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4046 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4047 I915_WRITE(link_m1_reg, m_n.link_m);
4048 I915_WRITE(link_n1_reg, m_n.link_n);
4049
4050 if (has_edp_encoder) {
4051 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4052 } else {
4053 /* enable FDI RX PLL too */
4054 temp = I915_READ(fdi_rx_reg);
4055 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4056 I915_READ(fdi_rx_reg);
4057 udelay(200);
4058
4059 /* enable FDI TX PLL too */
4060 temp = I915_READ(fdi_tx_reg);
4061 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4062 I915_READ(fdi_tx_reg);
4063
4064 /* enable FDI RX PCDCLK */
4065 temp = I915_READ(fdi_rx_reg);
4066 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4067 I915_READ(fdi_rx_reg);
4068 udelay(200);
4069 }
4070 }
4071
4072 I915_WRITE(pipeconf_reg, pipeconf);
4073 I915_READ(pipeconf_reg);
4074
4075 intel_wait_for_vblank(dev, pipe);
4076
4077 if (IS_IRONLAKE(dev)) {
4078 /* enable address swizzle for tiling buffer */
4079 temp = I915_READ(DISP_ARB_CTL);
4080 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4081 }
4082
4083 I915_WRITE(dspcntr_reg, dspcntr);
4084
4085 /* Flush the plane changes */
4086 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4087
4088 intel_update_watermarks(dev);
4089
4090 drm_vblank_post_modeset(dev, pipe);
4091
4092 return ret;
4093 }
4094
4095 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4096 void intel_crtc_load_lut(struct drm_crtc *crtc)
4097 {
4098 struct drm_device *dev = crtc->dev;
4099 struct drm_i915_private *dev_priv = dev->dev_private;
4100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4101 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4102 int i;
4103
4104 /* The clocks have to be on to load the palette. */
4105 if (!crtc->enabled)
4106 return;
4107
4108 /* use legacy palette for Ironlake */
4109 if (HAS_PCH_SPLIT(dev))
4110 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4111 LGC_PALETTE_B;
4112
4113 for (i = 0; i < 256; i++) {
4114 I915_WRITE(palreg + 4 * i,
4115 (intel_crtc->lut_r[i] << 16) |
4116 (intel_crtc->lut_g[i] << 8) |
4117 intel_crtc->lut_b[i]);
4118 }
4119 }
4120
4121 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4122 {
4123 struct drm_device *dev = crtc->dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4126 bool visible = base != 0;
4127 u32 cntl;
4128
4129 if (intel_crtc->cursor_visible == visible)
4130 return;
4131
4132 cntl = I915_READ(CURACNTR);
4133 if (visible) {
4134 /* On these chipsets we can only modify the base whilst
4135 * the cursor is disabled.
4136 */
4137 I915_WRITE(CURABASE, base);
4138
4139 cntl &= ~(CURSOR_FORMAT_MASK);
4140 cntl |= CURSOR_ENABLE |
4141 CURSOR_GAMMA_ENABLE |
4142 CURSOR_FORMAT_ARGB;
4143 } else
4144 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4145 I915_WRITE(CURACNTR, cntl);
4146
4147 intel_crtc->cursor_visible = visible;
4148 }
4149
4150 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4151 {
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 int pipe = intel_crtc->pipe;
4156 bool visible = base != 0;
4157
4158 if (intel_crtc->cursor_visible != visible) {
4159 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4160 if (base) {
4161 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4162 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4163 cntl |= pipe << 28; /* Connect to correct pipe */
4164 } else {
4165 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4166 cntl |= CURSOR_MODE_DISABLE;
4167 }
4168 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4169
4170 intel_crtc->cursor_visible = visible;
4171 }
4172 /* and commit changes on next vblank */
4173 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4174 }
4175
4176 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4177 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4178 {
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4182 int pipe = intel_crtc->pipe;
4183 int x = intel_crtc->cursor_x;
4184 int y = intel_crtc->cursor_y;
4185 u32 base, pos;
4186 bool visible;
4187
4188 pos = 0;
4189
4190 if (intel_crtc->cursor_on && crtc->fb) {
4191 base = intel_crtc->cursor_addr;
4192 if (x > (int) crtc->fb->width)
4193 base = 0;
4194
4195 if (y > (int) crtc->fb->height)
4196 base = 0;
4197 } else
4198 base = 0;
4199
4200 if (x < 0) {
4201 if (x + intel_crtc->cursor_width < 0)
4202 base = 0;
4203
4204 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4205 x = -x;
4206 }
4207 pos |= x << CURSOR_X_SHIFT;
4208
4209 if (y < 0) {
4210 if (y + intel_crtc->cursor_height < 0)
4211 base = 0;
4212
4213 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4214 y = -y;
4215 }
4216 pos |= y << CURSOR_Y_SHIFT;
4217
4218 visible = base != 0;
4219 if (!visible && !intel_crtc->cursor_visible)
4220 return;
4221
4222 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4223 if (IS_845G(dev) || IS_I865G(dev))
4224 i845_update_cursor(crtc, base);
4225 else
4226 i9xx_update_cursor(crtc, base);
4227
4228 if (visible)
4229 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4230 }
4231
4232 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4233 struct drm_file *file_priv,
4234 uint32_t handle,
4235 uint32_t width, uint32_t height)
4236 {
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240 struct drm_gem_object *bo;
4241 struct drm_i915_gem_object *obj_priv;
4242 uint32_t addr;
4243 int ret;
4244
4245 DRM_DEBUG_KMS("\n");
4246
4247 /* if we want to turn off the cursor ignore width and height */
4248 if (!handle) {
4249 DRM_DEBUG_KMS("cursor off\n");
4250 addr = 0;
4251 bo = NULL;
4252 mutex_lock(&dev->struct_mutex);
4253 goto finish;
4254 }
4255
4256 /* Currently we only support 64x64 cursors */
4257 if (width != 64 || height != 64) {
4258 DRM_ERROR("we currently only support 64x64 cursors\n");
4259 return -EINVAL;
4260 }
4261
4262 bo = drm_gem_object_lookup(dev, file_priv, handle);
4263 if (!bo)
4264 return -ENOENT;
4265
4266 obj_priv = to_intel_bo(bo);
4267
4268 if (bo->size < width * height * 4) {
4269 DRM_ERROR("buffer is to small\n");
4270 ret = -ENOMEM;
4271 goto fail;
4272 }
4273
4274 /* we only need to pin inside GTT if cursor is non-phy */
4275 mutex_lock(&dev->struct_mutex);
4276 if (!dev_priv->info->cursor_needs_physical) {
4277 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4278 if (ret) {
4279 DRM_ERROR("failed to pin cursor bo\n");
4280 goto fail_locked;
4281 }
4282
4283 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4284 if (ret) {
4285 DRM_ERROR("failed to move cursor bo into the GTT\n");
4286 goto fail_unpin;
4287 }
4288
4289 addr = obj_priv->gtt_offset;
4290 } else {
4291 int align = IS_I830(dev) ? 16 * 1024 : 256;
4292 ret = i915_gem_attach_phys_object(dev, bo,
4293 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4294 align);
4295 if (ret) {
4296 DRM_ERROR("failed to attach phys object\n");
4297 goto fail_locked;
4298 }
4299 addr = obj_priv->phys_obj->handle->busaddr;
4300 }
4301
4302 if (!IS_I9XX(dev))
4303 I915_WRITE(CURSIZE, (height << 12) | width);
4304
4305 finish:
4306 if (intel_crtc->cursor_bo) {
4307 if (dev_priv->info->cursor_needs_physical) {
4308 if (intel_crtc->cursor_bo != bo)
4309 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4310 } else
4311 i915_gem_object_unpin(intel_crtc->cursor_bo);
4312 drm_gem_object_unreference(intel_crtc->cursor_bo);
4313 }
4314
4315 mutex_unlock(&dev->struct_mutex);
4316
4317 intel_crtc->cursor_addr = addr;
4318 intel_crtc->cursor_bo = bo;
4319 intel_crtc->cursor_width = width;
4320 intel_crtc->cursor_height = height;
4321
4322 intel_crtc_update_cursor(crtc);
4323
4324 return 0;
4325 fail_unpin:
4326 i915_gem_object_unpin(bo);
4327 fail_locked:
4328 mutex_unlock(&dev->struct_mutex);
4329 fail:
4330 drm_gem_object_unreference_unlocked(bo);
4331 return ret;
4332 }
4333
4334 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4335 {
4336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4337
4338 intel_crtc->cursor_x = x;
4339 intel_crtc->cursor_y = y;
4340
4341 intel_crtc_update_cursor(crtc);
4342
4343 return 0;
4344 }
4345
4346 /** Sets the color ramps on behalf of RandR */
4347 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4348 u16 blue, int regno)
4349 {
4350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351
4352 intel_crtc->lut_r[regno] = red >> 8;
4353 intel_crtc->lut_g[regno] = green >> 8;
4354 intel_crtc->lut_b[regno] = blue >> 8;
4355 }
4356
4357 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4358 u16 *blue, int regno)
4359 {
4360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4361
4362 *red = intel_crtc->lut_r[regno] << 8;
4363 *green = intel_crtc->lut_g[regno] << 8;
4364 *blue = intel_crtc->lut_b[regno] << 8;
4365 }
4366
4367 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4368 u16 *blue, uint32_t start, uint32_t size)
4369 {
4370 int end = (start + size > 256) ? 256 : start + size, i;
4371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372
4373 for (i = start; i < end; i++) {
4374 intel_crtc->lut_r[i] = red[i] >> 8;
4375 intel_crtc->lut_g[i] = green[i] >> 8;
4376 intel_crtc->lut_b[i] = blue[i] >> 8;
4377 }
4378
4379 intel_crtc_load_lut(crtc);
4380 }
4381
4382 /**
4383 * Get a pipe with a simple mode set on it for doing load-based monitor
4384 * detection.
4385 *
4386 * It will be up to the load-detect code to adjust the pipe as appropriate for
4387 * its requirements. The pipe will be connected to no other encoders.
4388 *
4389 * Currently this code will only succeed if there is a pipe with no encoders
4390 * configured for it. In the future, it could choose to temporarily disable
4391 * some outputs to free up a pipe for its use.
4392 *
4393 * \return crtc, or NULL if no pipes are available.
4394 */
4395
4396 /* VESA 640x480x72Hz mode to set on the pipe */
4397 static struct drm_display_mode load_detect_mode = {
4398 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4399 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4400 };
4401
4402 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4403 struct drm_connector *connector,
4404 struct drm_display_mode *mode,
4405 int *dpms_mode)
4406 {
4407 struct intel_crtc *intel_crtc;
4408 struct drm_crtc *possible_crtc;
4409 struct drm_crtc *supported_crtc =NULL;
4410 struct drm_encoder *encoder = &intel_encoder->enc;
4411 struct drm_crtc *crtc = NULL;
4412 struct drm_device *dev = encoder->dev;
4413 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4414 struct drm_crtc_helper_funcs *crtc_funcs;
4415 int i = -1;
4416
4417 /*
4418 * Algorithm gets a little messy:
4419 * - if the connector already has an assigned crtc, use it (but make
4420 * sure it's on first)
4421 * - try to find the first unused crtc that can drive this connector,
4422 * and use that if we find one
4423 * - if there are no unused crtcs available, try to use the first
4424 * one we found that supports the connector
4425 */
4426
4427 /* See if we already have a CRTC for this connector */
4428 if (encoder->crtc) {
4429 crtc = encoder->crtc;
4430 /* Make sure the crtc and connector are running */
4431 intel_crtc = to_intel_crtc(crtc);
4432 *dpms_mode = intel_crtc->dpms_mode;
4433 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4434 crtc_funcs = crtc->helper_private;
4435 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4436 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4437 }
4438 return crtc;
4439 }
4440
4441 /* Find an unused one (if possible) */
4442 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4443 i++;
4444 if (!(encoder->possible_crtcs & (1 << i)))
4445 continue;
4446 if (!possible_crtc->enabled) {
4447 crtc = possible_crtc;
4448 break;
4449 }
4450 if (!supported_crtc)
4451 supported_crtc = possible_crtc;
4452 }
4453
4454 /*
4455 * If we didn't find an unused CRTC, don't use any.
4456 */
4457 if (!crtc) {
4458 return NULL;
4459 }
4460
4461 encoder->crtc = crtc;
4462 connector->encoder = encoder;
4463 intel_encoder->load_detect_temp = true;
4464
4465 intel_crtc = to_intel_crtc(crtc);
4466 *dpms_mode = intel_crtc->dpms_mode;
4467
4468 if (!crtc->enabled) {
4469 if (!mode)
4470 mode = &load_detect_mode;
4471 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4472 } else {
4473 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4474 crtc_funcs = crtc->helper_private;
4475 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4476 }
4477
4478 /* Add this connector to the crtc */
4479 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4480 encoder_funcs->commit(encoder);
4481 }
4482 /* let the connector get through one full cycle before testing */
4483 intel_wait_for_vblank(dev, intel_crtc->pipe);
4484
4485 return crtc;
4486 }
4487
4488 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4489 struct drm_connector *connector, int dpms_mode)
4490 {
4491 struct drm_encoder *encoder = &intel_encoder->enc;
4492 struct drm_device *dev = encoder->dev;
4493 struct drm_crtc *crtc = encoder->crtc;
4494 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4495 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4496
4497 if (intel_encoder->load_detect_temp) {
4498 encoder->crtc = NULL;
4499 connector->encoder = NULL;
4500 intel_encoder->load_detect_temp = false;
4501 crtc->enabled = drm_helper_crtc_in_use(crtc);
4502 drm_helper_disable_unused_functions(dev);
4503 }
4504
4505 /* Switch crtc and encoder back off if necessary */
4506 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4507 if (encoder->crtc == crtc)
4508 encoder_funcs->dpms(encoder, dpms_mode);
4509 crtc_funcs->dpms(crtc, dpms_mode);
4510 }
4511 }
4512
4513 /* Returns the clock of the currently programmed mode of the given pipe. */
4514 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4515 {
4516 struct drm_i915_private *dev_priv = dev->dev_private;
4517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518 int pipe = intel_crtc->pipe;
4519 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4520 u32 fp;
4521 intel_clock_t clock;
4522
4523 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4524 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4525 else
4526 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4527
4528 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4529 if (IS_PINEVIEW(dev)) {
4530 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4531 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4532 } else {
4533 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4534 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4535 }
4536
4537 if (IS_I9XX(dev)) {
4538 if (IS_PINEVIEW(dev))
4539 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4540 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4541 else
4542 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4543 DPLL_FPA01_P1_POST_DIV_SHIFT);
4544
4545 switch (dpll & DPLL_MODE_MASK) {
4546 case DPLLB_MODE_DAC_SERIAL:
4547 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4548 5 : 10;
4549 break;
4550 case DPLLB_MODE_LVDS:
4551 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4552 7 : 14;
4553 break;
4554 default:
4555 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4556 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4557 return 0;
4558 }
4559
4560 intel_clock(dev, 96000, &clock);
4561 } else {
4562 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4563
4564 if (is_lvds) {
4565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4566 DPLL_FPA01_P1_POST_DIV_SHIFT);
4567 clock.p2 = 14;
4568
4569 if ((dpll & PLL_REF_INPUT_MASK) ==
4570 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4571 intel_clock(dev, 66000, &clock);
4572 } else
4573 intel_clock(dev, 48000, &clock);
4574 } else {
4575 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4576 clock.p1 = 2;
4577 else {
4578 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4579 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4580 }
4581 if (dpll & PLL_P2_DIVIDE_BY_4)
4582 clock.p2 = 4;
4583 else
4584 clock.p2 = 2;
4585
4586 intel_clock(dev, 48000, &clock);
4587 }
4588 }
4589
4590
4591 return clock.dot;
4592 }
4593
4594 /** Returns the currently programmed mode of the given pipe. */
4595 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4596 struct drm_crtc *crtc)
4597 {
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4600 int pipe = intel_crtc->pipe;
4601 struct drm_display_mode *mode;
4602 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4603 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4604 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4605 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4606
4607 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4608 if (!mode)
4609 return NULL;
4610
4611 mode->clock = intel_crtc_clock_get(dev, crtc);
4612 mode->hdisplay = (htot & 0xffff) + 1;
4613 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4614 mode->hsync_start = (hsync & 0xffff) + 1;
4615 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4616 mode->vdisplay = (vtot & 0xffff) + 1;
4617 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4618 mode->vsync_start = (vsync & 0xffff) + 1;
4619 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4620
4621 drm_mode_set_name(mode);
4622 drm_mode_set_crtcinfo(mode, 0);
4623
4624 return mode;
4625 }
4626
4627 #define GPU_IDLE_TIMEOUT 500 /* ms */
4628
4629 /* When this timer fires, we've been idle for awhile */
4630 static void intel_gpu_idle_timer(unsigned long arg)
4631 {
4632 struct drm_device *dev = (struct drm_device *)arg;
4633 drm_i915_private_t *dev_priv = dev->dev_private;
4634
4635 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4636
4637 dev_priv->busy = false;
4638
4639 queue_work(dev_priv->wq, &dev_priv->idle_work);
4640 }
4641
4642 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4643
4644 static void intel_crtc_idle_timer(unsigned long arg)
4645 {
4646 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4647 struct drm_crtc *crtc = &intel_crtc->base;
4648 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4649
4650 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4651
4652 intel_crtc->busy = false;
4653
4654 queue_work(dev_priv->wq, &dev_priv->idle_work);
4655 }
4656
4657 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4658 {
4659 struct drm_device *dev = crtc->dev;
4660 drm_i915_private_t *dev_priv = dev->dev_private;
4661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 int pipe = intel_crtc->pipe;
4663 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4664 int dpll = I915_READ(dpll_reg);
4665
4666 if (HAS_PCH_SPLIT(dev))
4667 return;
4668
4669 if (!dev_priv->lvds_downclock_avail)
4670 return;
4671
4672 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4673 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4674
4675 /* Unlock panel regs */
4676 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4677 PANEL_UNLOCK_REGS);
4678
4679 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4680 I915_WRITE(dpll_reg, dpll);
4681 dpll = I915_READ(dpll_reg);
4682 intel_wait_for_vblank(dev, pipe);
4683 dpll = I915_READ(dpll_reg);
4684 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4685 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4686
4687 /* ...and lock them again */
4688 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4689 }
4690
4691 /* Schedule downclock */
4692 if (schedule)
4693 mod_timer(&intel_crtc->idle_timer, jiffies +
4694 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4695 }
4696
4697 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4698 {
4699 struct drm_device *dev = crtc->dev;
4700 drm_i915_private_t *dev_priv = dev->dev_private;
4701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4702 int pipe = intel_crtc->pipe;
4703 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4704 int dpll = I915_READ(dpll_reg);
4705
4706 if (HAS_PCH_SPLIT(dev))
4707 return;
4708
4709 if (!dev_priv->lvds_downclock_avail)
4710 return;
4711
4712 /*
4713 * Since this is called by a timer, we should never get here in
4714 * the manual case.
4715 */
4716 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4717 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4718
4719 /* Unlock panel regs */
4720 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4721 PANEL_UNLOCK_REGS);
4722
4723 dpll |= DISPLAY_RATE_SELECT_FPA1;
4724 I915_WRITE(dpll_reg, dpll);
4725 dpll = I915_READ(dpll_reg);
4726 intel_wait_for_vblank(dev, pipe);
4727 dpll = I915_READ(dpll_reg);
4728 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4729 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4730
4731 /* ...and lock them again */
4732 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4733 }
4734
4735 }
4736
4737 /**
4738 * intel_idle_update - adjust clocks for idleness
4739 * @work: work struct
4740 *
4741 * Either the GPU or display (or both) went idle. Check the busy status
4742 * here and adjust the CRTC and GPU clocks as necessary.
4743 */
4744 static void intel_idle_update(struct work_struct *work)
4745 {
4746 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4747 idle_work);
4748 struct drm_device *dev = dev_priv->dev;
4749 struct drm_crtc *crtc;
4750 struct intel_crtc *intel_crtc;
4751 int enabled = 0;
4752
4753 if (!i915_powersave)
4754 return;
4755
4756 mutex_lock(&dev->struct_mutex);
4757
4758 i915_update_gfx_val(dev_priv);
4759
4760 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4761 /* Skip inactive CRTCs */
4762 if (!crtc->fb)
4763 continue;
4764
4765 enabled++;
4766 intel_crtc = to_intel_crtc(crtc);
4767 if (!intel_crtc->busy)
4768 intel_decrease_pllclock(crtc);
4769 }
4770
4771 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4772 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4773 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4774 }
4775
4776 mutex_unlock(&dev->struct_mutex);
4777 }
4778
4779 /**
4780 * intel_mark_busy - mark the GPU and possibly the display busy
4781 * @dev: drm device
4782 * @obj: object we're operating on
4783 *
4784 * Callers can use this function to indicate that the GPU is busy processing
4785 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4786 * buffer), we'll also mark the display as busy, so we know to increase its
4787 * clock frequency.
4788 */
4789 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4790 {
4791 drm_i915_private_t *dev_priv = dev->dev_private;
4792 struct drm_crtc *crtc = NULL;
4793 struct intel_framebuffer *intel_fb;
4794 struct intel_crtc *intel_crtc;
4795
4796 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4797 return;
4798
4799 if (!dev_priv->busy) {
4800 if (IS_I945G(dev) || IS_I945GM(dev)) {
4801 u32 fw_blc_self;
4802
4803 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4804 fw_blc_self = I915_READ(FW_BLC_SELF);
4805 fw_blc_self &= ~FW_BLC_SELF_EN;
4806 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4807 }
4808 dev_priv->busy = true;
4809 } else
4810 mod_timer(&dev_priv->idle_timer, jiffies +
4811 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4812
4813 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4814 if (!crtc->fb)
4815 continue;
4816
4817 intel_crtc = to_intel_crtc(crtc);
4818 intel_fb = to_intel_framebuffer(crtc->fb);
4819 if (intel_fb->obj == obj) {
4820 if (!intel_crtc->busy) {
4821 if (IS_I945G(dev) || IS_I945GM(dev)) {
4822 u32 fw_blc_self;
4823
4824 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4825 fw_blc_self = I915_READ(FW_BLC_SELF);
4826 fw_blc_self &= ~FW_BLC_SELF_EN;
4827 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4828 }
4829 /* Non-busy -> busy, upclock */
4830 intel_increase_pllclock(crtc, true);
4831 intel_crtc->busy = true;
4832 } else {
4833 /* Busy -> busy, put off timer */
4834 mod_timer(&intel_crtc->idle_timer, jiffies +
4835 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4836 }
4837 }
4838 }
4839 }
4840
4841 static void intel_crtc_destroy(struct drm_crtc *crtc)
4842 {
4843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844
4845 drm_crtc_cleanup(crtc);
4846 kfree(intel_crtc);
4847 }
4848
4849 static void intel_unpin_work_fn(struct work_struct *__work)
4850 {
4851 struct intel_unpin_work *work =
4852 container_of(__work, struct intel_unpin_work, work);
4853
4854 mutex_lock(&work->dev->struct_mutex);
4855 i915_gem_object_unpin(work->old_fb_obj);
4856 drm_gem_object_unreference(work->pending_flip_obj);
4857 drm_gem_object_unreference(work->old_fb_obj);
4858 mutex_unlock(&work->dev->struct_mutex);
4859 kfree(work);
4860 }
4861
4862 static void do_intel_finish_page_flip(struct drm_device *dev,
4863 struct drm_crtc *crtc)
4864 {
4865 drm_i915_private_t *dev_priv = dev->dev_private;
4866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4867 struct intel_unpin_work *work;
4868 struct drm_i915_gem_object *obj_priv;
4869 struct drm_pending_vblank_event *e;
4870 struct timeval now;
4871 unsigned long flags;
4872
4873 /* Ignore early vblank irqs */
4874 if (intel_crtc == NULL)
4875 return;
4876
4877 spin_lock_irqsave(&dev->event_lock, flags);
4878 work = intel_crtc->unpin_work;
4879 if (work == NULL || !work->pending) {
4880 spin_unlock_irqrestore(&dev->event_lock, flags);
4881 return;
4882 }
4883
4884 intel_crtc->unpin_work = NULL;
4885 drm_vblank_put(dev, intel_crtc->pipe);
4886
4887 if (work->event) {
4888 e = work->event;
4889 do_gettimeofday(&now);
4890 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4891 e->event.tv_sec = now.tv_sec;
4892 e->event.tv_usec = now.tv_usec;
4893 list_add_tail(&e->base.link,
4894 &e->base.file_priv->event_list);
4895 wake_up_interruptible(&e->base.file_priv->event_wait);
4896 }
4897
4898 spin_unlock_irqrestore(&dev->event_lock, flags);
4899
4900 obj_priv = to_intel_bo(work->pending_flip_obj);
4901
4902 /* Initial scanout buffer will have a 0 pending flip count */
4903 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4904 atomic_dec_and_test(&obj_priv->pending_flip))
4905 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4906 schedule_work(&work->work);
4907
4908 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4909 }
4910
4911 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4912 {
4913 drm_i915_private_t *dev_priv = dev->dev_private;
4914 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4915
4916 do_intel_finish_page_flip(dev, crtc);
4917 }
4918
4919 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4920 {
4921 drm_i915_private_t *dev_priv = dev->dev_private;
4922 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4923
4924 do_intel_finish_page_flip(dev, crtc);
4925 }
4926
4927 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4928 {
4929 drm_i915_private_t *dev_priv = dev->dev_private;
4930 struct intel_crtc *intel_crtc =
4931 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4932 unsigned long flags;
4933
4934 spin_lock_irqsave(&dev->event_lock, flags);
4935 if (intel_crtc->unpin_work) {
4936 if ((++intel_crtc->unpin_work->pending) > 1)
4937 DRM_ERROR("Prepared flip multiple times\n");
4938 } else {
4939 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4940 }
4941 spin_unlock_irqrestore(&dev->event_lock, flags);
4942 }
4943
4944 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4945 struct drm_framebuffer *fb,
4946 struct drm_pending_vblank_event *event)
4947 {
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_framebuffer *intel_fb;
4951 struct drm_i915_gem_object *obj_priv;
4952 struct drm_gem_object *obj;
4953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4954 struct intel_unpin_work *work;
4955 unsigned long flags, offset;
4956 int pipe = intel_crtc->pipe;
4957 u32 pf, pipesrc;
4958 int ret;
4959
4960 work = kzalloc(sizeof *work, GFP_KERNEL);
4961 if (work == NULL)
4962 return -ENOMEM;
4963
4964 work->event = event;
4965 work->dev = crtc->dev;
4966 intel_fb = to_intel_framebuffer(crtc->fb);
4967 work->old_fb_obj = intel_fb->obj;
4968 INIT_WORK(&work->work, intel_unpin_work_fn);
4969
4970 /* We borrow the event spin lock for protecting unpin_work */
4971 spin_lock_irqsave(&dev->event_lock, flags);
4972 if (intel_crtc->unpin_work) {
4973 spin_unlock_irqrestore(&dev->event_lock, flags);
4974 kfree(work);
4975
4976 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4977 return -EBUSY;
4978 }
4979 intel_crtc->unpin_work = work;
4980 spin_unlock_irqrestore(&dev->event_lock, flags);
4981
4982 intel_fb = to_intel_framebuffer(fb);
4983 obj = intel_fb->obj;
4984
4985 mutex_lock(&dev->struct_mutex);
4986 ret = intel_pin_and_fence_fb_obj(dev, obj);
4987 if (ret)
4988 goto cleanup_work;
4989
4990 /* Reference the objects for the scheduled work. */
4991 drm_gem_object_reference(work->old_fb_obj);
4992 drm_gem_object_reference(obj);
4993
4994 crtc->fb = fb;
4995 ret = i915_gem_object_flush_write_domain(obj);
4996 if (ret)
4997 goto cleanup_objs;
4998
4999 ret = drm_vblank_get(dev, intel_crtc->pipe);
5000 if (ret)
5001 goto cleanup_objs;
5002
5003 obj_priv = to_intel_bo(obj);
5004 atomic_inc(&obj_priv->pending_flip);
5005 work->pending_flip_obj = obj;
5006
5007 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5008 u32 flip_mask;
5009
5010 if (intel_crtc->plane)
5011 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5012 else
5013 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5014
5015 BEGIN_LP_RING(2);
5016 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5017 OUT_RING(0);
5018 ADVANCE_LP_RING();
5019 }
5020
5021 work->enable_stall_check = true;
5022
5023 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5024 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5025
5026 BEGIN_LP_RING(4);
5027 switch(INTEL_INFO(dev)->gen) {
5028 case 2:
5029 OUT_RING(MI_DISPLAY_FLIP |
5030 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5031 OUT_RING(fb->pitch);
5032 OUT_RING(obj_priv->gtt_offset + offset);
5033 OUT_RING(MI_NOOP);
5034 break;
5035
5036 case 3:
5037 OUT_RING(MI_DISPLAY_FLIP_I915 |
5038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5039 OUT_RING(fb->pitch);
5040 OUT_RING(obj_priv->gtt_offset + offset);
5041 OUT_RING(MI_NOOP);
5042 break;
5043
5044 case 4:
5045 case 5:
5046 /* i965+ uses the linear or tiled offsets from the
5047 * Display Registers (which do not change across a page-flip)
5048 * so we need only reprogram the base address.
5049 */
5050 OUT_RING(MI_DISPLAY_FLIP |
5051 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5052 OUT_RING(fb->pitch);
5053 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5054
5055 pf = 0;
5056 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5057 OUT_RING(pf | pipesrc);
5058 break;
5059
5060 case 6:
5061 OUT_RING(MI_DISPLAY_FLIP |
5062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5063 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5064 OUT_RING(obj_priv->gtt_offset);
5065
5066 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5067 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5068 OUT_RING(pf | pipesrc);
5069 break;
5070 }
5071 ADVANCE_LP_RING();
5072
5073 mutex_unlock(&dev->struct_mutex);
5074
5075 trace_i915_flip_request(intel_crtc->plane, obj);
5076
5077 return 0;
5078
5079 cleanup_objs:
5080 drm_gem_object_unreference(work->old_fb_obj);
5081 drm_gem_object_unreference(obj);
5082 cleanup_work:
5083 mutex_unlock(&dev->struct_mutex);
5084
5085 spin_lock_irqsave(&dev->event_lock, flags);
5086 intel_crtc->unpin_work = NULL;
5087 spin_unlock_irqrestore(&dev->event_lock, flags);
5088
5089 kfree(work);
5090
5091 return ret;
5092 }
5093
5094 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5095 .dpms = intel_crtc_dpms,
5096 .mode_fixup = intel_crtc_mode_fixup,
5097 .mode_set = intel_crtc_mode_set,
5098 .mode_set_base = intel_pipe_set_base,
5099 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5100 .prepare = intel_crtc_prepare,
5101 .commit = intel_crtc_commit,
5102 .load_lut = intel_crtc_load_lut,
5103 };
5104
5105 static const struct drm_crtc_funcs intel_crtc_funcs = {
5106 .cursor_set = intel_crtc_cursor_set,
5107 .cursor_move = intel_crtc_cursor_move,
5108 .gamma_set = intel_crtc_gamma_set,
5109 .set_config = drm_crtc_helper_set_config,
5110 .destroy = intel_crtc_destroy,
5111 .page_flip = intel_crtc_page_flip,
5112 };
5113
5114
5115 static void intel_crtc_init(struct drm_device *dev, int pipe)
5116 {
5117 drm_i915_private_t *dev_priv = dev->dev_private;
5118 struct intel_crtc *intel_crtc;
5119 int i;
5120
5121 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5122 if (intel_crtc == NULL)
5123 return;
5124
5125 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5126
5127 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5128 intel_crtc->pipe = pipe;
5129 intel_crtc->plane = pipe;
5130 for (i = 0; i < 256; i++) {
5131 intel_crtc->lut_r[i] = i;
5132 intel_crtc->lut_g[i] = i;
5133 intel_crtc->lut_b[i] = i;
5134 }
5135
5136 /* Swap pipes & planes for FBC on pre-965 */
5137 intel_crtc->pipe = pipe;
5138 intel_crtc->plane = pipe;
5139 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5140 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5141 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5142 }
5143
5144 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5145 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5146 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5147 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5148
5149 intel_crtc->cursor_addr = 0;
5150 intel_crtc->dpms_mode = -1;
5151 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5152
5153 intel_crtc->busy = false;
5154
5155 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5156 (unsigned long)intel_crtc);
5157 }
5158
5159 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5160 struct drm_file *file_priv)
5161 {
5162 drm_i915_private_t *dev_priv = dev->dev_private;
5163 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5164 struct drm_mode_object *drmmode_obj;
5165 struct intel_crtc *crtc;
5166
5167 if (!dev_priv) {
5168 DRM_ERROR("called with no initialization\n");
5169 return -EINVAL;
5170 }
5171
5172 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5173 DRM_MODE_OBJECT_CRTC);
5174
5175 if (!drmmode_obj) {
5176 DRM_ERROR("no such CRTC id\n");
5177 return -EINVAL;
5178 }
5179
5180 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5181 pipe_from_crtc_id->pipe = crtc->pipe;
5182
5183 return 0;
5184 }
5185
5186 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5187 {
5188 struct drm_crtc *crtc = NULL;
5189
5190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 if (intel_crtc->pipe == pipe)
5193 break;
5194 }
5195 return crtc;
5196 }
5197
5198 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5199 {
5200 int index_mask = 0;
5201 struct drm_encoder *encoder;
5202 int entry = 0;
5203
5204 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5205 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5206 if (type_mask & intel_encoder->clone_mask)
5207 index_mask |= (1 << entry);
5208 entry++;
5209 }
5210 return index_mask;
5211 }
5212
5213
5214 static void intel_setup_outputs(struct drm_device *dev)
5215 {
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 struct drm_encoder *encoder;
5218 bool dpd_is_edp = false;
5219
5220 if (IS_MOBILE(dev) && !IS_I830(dev))
5221 intel_lvds_init(dev);
5222
5223 if (HAS_PCH_SPLIT(dev)) {
5224 dpd_is_edp = intel_dpd_is_edp(dev);
5225
5226 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5227 intel_dp_init(dev, DP_A);
5228
5229 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5230 intel_dp_init(dev, PCH_DP_D);
5231 }
5232
5233 intel_crt_init(dev);
5234
5235 if (HAS_PCH_SPLIT(dev)) {
5236 int found;
5237
5238 if (I915_READ(HDMIB) & PORT_DETECTED) {
5239 /* PCH SDVOB multiplex with HDMIB */
5240 found = intel_sdvo_init(dev, PCH_SDVOB);
5241 if (!found)
5242 intel_hdmi_init(dev, HDMIB);
5243 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5244 intel_dp_init(dev, PCH_DP_B);
5245 }
5246
5247 if (I915_READ(HDMIC) & PORT_DETECTED)
5248 intel_hdmi_init(dev, HDMIC);
5249
5250 if (I915_READ(HDMID) & PORT_DETECTED)
5251 intel_hdmi_init(dev, HDMID);
5252
5253 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5254 intel_dp_init(dev, PCH_DP_C);
5255
5256 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5257 intel_dp_init(dev, PCH_DP_D);
5258
5259 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5260 bool found = false;
5261
5262 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5263 DRM_DEBUG_KMS("probing SDVOB\n");
5264 found = intel_sdvo_init(dev, SDVOB);
5265 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5266 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5267 intel_hdmi_init(dev, SDVOB);
5268 }
5269
5270 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5271 DRM_DEBUG_KMS("probing DP_B\n");
5272 intel_dp_init(dev, DP_B);
5273 }
5274 }
5275
5276 /* Before G4X SDVOC doesn't have its own detect register */
5277
5278 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5279 DRM_DEBUG_KMS("probing SDVOC\n");
5280 found = intel_sdvo_init(dev, SDVOC);
5281 }
5282
5283 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5284
5285 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5286 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5287 intel_hdmi_init(dev, SDVOC);
5288 }
5289 if (SUPPORTS_INTEGRATED_DP(dev)) {
5290 DRM_DEBUG_KMS("probing DP_C\n");
5291 intel_dp_init(dev, DP_C);
5292 }
5293 }
5294
5295 if (SUPPORTS_INTEGRATED_DP(dev) &&
5296 (I915_READ(DP_D) & DP_DETECTED)) {
5297 DRM_DEBUG_KMS("probing DP_D\n");
5298 intel_dp_init(dev, DP_D);
5299 }
5300 } else if (IS_GEN2(dev))
5301 intel_dvo_init(dev);
5302
5303 if (SUPPORTS_TV(dev))
5304 intel_tv_init(dev);
5305
5306 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5307 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5308
5309 encoder->possible_crtcs = intel_encoder->crtc_mask;
5310 encoder->possible_clones = intel_encoder_clones(dev,
5311 intel_encoder->clone_mask);
5312 }
5313 }
5314
5315 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5316 {
5317 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5318
5319 drm_framebuffer_cleanup(fb);
5320 drm_gem_object_unreference_unlocked(intel_fb->obj);
5321
5322 kfree(intel_fb);
5323 }
5324
5325 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5326 struct drm_file *file_priv,
5327 unsigned int *handle)
5328 {
5329 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5330 struct drm_gem_object *object = intel_fb->obj;
5331
5332 return drm_gem_handle_create(file_priv, object, handle);
5333 }
5334
5335 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5336 .destroy = intel_user_framebuffer_destroy,
5337 .create_handle = intel_user_framebuffer_create_handle,
5338 };
5339
5340 int intel_framebuffer_init(struct drm_device *dev,
5341 struct intel_framebuffer *intel_fb,
5342 struct drm_mode_fb_cmd *mode_cmd,
5343 struct drm_gem_object *obj)
5344 {
5345 int ret;
5346
5347 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5348 if (ret) {
5349 DRM_ERROR("framebuffer init failed %d\n", ret);
5350 return ret;
5351 }
5352
5353 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5354 intel_fb->obj = obj;
5355 return 0;
5356 }
5357
5358 static struct drm_framebuffer *
5359 intel_user_framebuffer_create(struct drm_device *dev,
5360 struct drm_file *filp,
5361 struct drm_mode_fb_cmd *mode_cmd)
5362 {
5363 struct drm_gem_object *obj;
5364 struct intel_framebuffer *intel_fb;
5365 int ret;
5366
5367 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5368 if (!obj)
5369 return ERR_PTR(-ENOENT);
5370
5371 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5372 if (!intel_fb)
5373 return ERR_PTR(-ENOMEM);
5374
5375 ret = intel_framebuffer_init(dev, intel_fb,
5376 mode_cmd, obj);
5377 if (ret) {
5378 drm_gem_object_unreference_unlocked(obj);
5379 kfree(intel_fb);
5380 return ERR_PTR(ret);
5381 }
5382
5383 return &intel_fb->base;
5384 }
5385
5386 static const struct drm_mode_config_funcs intel_mode_funcs = {
5387 .fb_create = intel_user_framebuffer_create,
5388 .output_poll_changed = intel_fb_output_poll_changed,
5389 };
5390
5391 static struct drm_gem_object *
5392 intel_alloc_context_page(struct drm_device *dev)
5393 {
5394 struct drm_gem_object *ctx;
5395 int ret;
5396
5397 ctx = i915_gem_alloc_object(dev, 4096);
5398 if (!ctx) {
5399 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5400 return NULL;
5401 }
5402
5403 mutex_lock(&dev->struct_mutex);
5404 ret = i915_gem_object_pin(ctx, 4096);
5405 if (ret) {
5406 DRM_ERROR("failed to pin power context: %d\n", ret);
5407 goto err_unref;
5408 }
5409
5410 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5411 if (ret) {
5412 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5413 goto err_unpin;
5414 }
5415 mutex_unlock(&dev->struct_mutex);
5416
5417 return ctx;
5418
5419 err_unpin:
5420 i915_gem_object_unpin(ctx);
5421 err_unref:
5422 drm_gem_object_unreference(ctx);
5423 mutex_unlock(&dev->struct_mutex);
5424 return NULL;
5425 }
5426
5427 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5428 {
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 u16 rgvswctl;
5431
5432 rgvswctl = I915_READ16(MEMSWCTL);
5433 if (rgvswctl & MEMCTL_CMD_STS) {
5434 DRM_DEBUG("gpu busy, RCS change rejected\n");
5435 return false; /* still busy with another command */
5436 }
5437
5438 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5439 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5440 I915_WRITE16(MEMSWCTL, rgvswctl);
5441 POSTING_READ16(MEMSWCTL);
5442
5443 rgvswctl |= MEMCTL_CMD_STS;
5444 I915_WRITE16(MEMSWCTL, rgvswctl);
5445
5446 return true;
5447 }
5448
5449 void ironlake_enable_drps(struct drm_device *dev)
5450 {
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 u32 rgvmodectl = I915_READ(MEMMODECTL);
5453 u8 fmax, fmin, fstart, vstart;
5454
5455 /* 100ms RC evaluation intervals */
5456 I915_WRITE(RCUPEI, 100000);
5457 I915_WRITE(RCDNEI, 100000);
5458
5459 /* Set max/min thresholds to 90ms and 80ms respectively */
5460 I915_WRITE(RCBMAXAVG, 90000);
5461 I915_WRITE(RCBMINAVG, 80000);
5462
5463 I915_WRITE(MEMIHYST, 1);
5464
5465 /* Set up min, max, and cur for interrupt handling */
5466 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5467 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5468 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5469 MEMMODE_FSTART_SHIFT;
5470 fstart = fmax;
5471
5472 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5473 PXVFREQ_PX_SHIFT;
5474
5475 dev_priv->fmax = fstart; /* IPS callback will increase this */
5476 dev_priv->fstart = fstart;
5477
5478 dev_priv->max_delay = fmax;
5479 dev_priv->min_delay = fmin;
5480 dev_priv->cur_delay = fstart;
5481
5482 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5483 fstart);
5484
5485 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5486
5487 /*
5488 * Interrupts will be enabled in ironlake_irq_postinstall
5489 */
5490
5491 I915_WRITE(VIDSTART, vstart);
5492 POSTING_READ(VIDSTART);
5493
5494 rgvmodectl |= MEMMODE_SWMODE_EN;
5495 I915_WRITE(MEMMODECTL, rgvmodectl);
5496
5497 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5498 DRM_ERROR("stuck trying to change perf mode\n");
5499 msleep(1);
5500
5501 ironlake_set_drps(dev, fstart);
5502
5503 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5504 I915_READ(0x112e0);
5505 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5506 dev_priv->last_count2 = I915_READ(0x112f4);
5507 getrawmonotonic(&dev_priv->last_time2);
5508 }
5509
5510 void ironlake_disable_drps(struct drm_device *dev)
5511 {
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513 u16 rgvswctl = I915_READ16(MEMSWCTL);
5514
5515 /* Ack interrupts, disable EFC interrupt */
5516 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5517 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5518 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5519 I915_WRITE(DEIIR, DE_PCU_EVENT);
5520 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5521
5522 /* Go back to the starting frequency */
5523 ironlake_set_drps(dev, dev_priv->fstart);
5524 msleep(1);
5525 rgvswctl |= MEMCTL_CMD_STS;
5526 I915_WRITE(MEMSWCTL, rgvswctl);
5527 msleep(1);
5528
5529 }
5530
5531 static unsigned long intel_pxfreq(u32 vidfreq)
5532 {
5533 unsigned long freq;
5534 int div = (vidfreq & 0x3f0000) >> 16;
5535 int post = (vidfreq & 0x3000) >> 12;
5536 int pre = (vidfreq & 0x7);
5537
5538 if (!pre)
5539 return 0;
5540
5541 freq = ((div * 133333) / ((1<<post) * pre));
5542
5543 return freq;
5544 }
5545
5546 void intel_init_emon(struct drm_device *dev)
5547 {
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 u32 lcfuse;
5550 u8 pxw[16];
5551 int i;
5552
5553 /* Disable to program */
5554 I915_WRITE(ECR, 0);
5555 POSTING_READ(ECR);
5556
5557 /* Program energy weights for various events */
5558 I915_WRITE(SDEW, 0x15040d00);
5559 I915_WRITE(CSIEW0, 0x007f0000);
5560 I915_WRITE(CSIEW1, 0x1e220004);
5561 I915_WRITE(CSIEW2, 0x04000004);
5562
5563 for (i = 0; i < 5; i++)
5564 I915_WRITE(PEW + (i * 4), 0);
5565 for (i = 0; i < 3; i++)
5566 I915_WRITE(DEW + (i * 4), 0);
5567
5568 /* Program P-state weights to account for frequency power adjustment */
5569 for (i = 0; i < 16; i++) {
5570 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5571 unsigned long freq = intel_pxfreq(pxvidfreq);
5572 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5573 PXVFREQ_PX_SHIFT;
5574 unsigned long val;
5575
5576 val = vid * vid;
5577 val *= (freq / 1000);
5578 val *= 255;
5579 val /= (127*127*900);
5580 if (val > 0xff)
5581 DRM_ERROR("bad pxval: %ld\n", val);
5582 pxw[i] = val;
5583 }
5584 /* Render standby states get 0 weight */
5585 pxw[14] = 0;
5586 pxw[15] = 0;
5587
5588 for (i = 0; i < 4; i++) {
5589 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5590 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5591 I915_WRITE(PXW + (i * 4), val);
5592 }
5593
5594 /* Adjust magic regs to magic values (more experimental results) */
5595 I915_WRITE(OGW0, 0);
5596 I915_WRITE(OGW1, 0);
5597 I915_WRITE(EG0, 0x00007f00);
5598 I915_WRITE(EG1, 0x0000000e);
5599 I915_WRITE(EG2, 0x000e0000);
5600 I915_WRITE(EG3, 0x68000300);
5601 I915_WRITE(EG4, 0x42000000);
5602 I915_WRITE(EG5, 0x00140031);
5603 I915_WRITE(EG6, 0);
5604 I915_WRITE(EG7, 0);
5605
5606 for (i = 0; i < 8; i++)
5607 I915_WRITE(PXWL + (i * 4), 0);
5608
5609 /* Enable PMON + select events */
5610 I915_WRITE(ECR, 0x80000019);
5611
5612 lcfuse = I915_READ(LCFUSE02);
5613
5614 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5615 }
5616
5617 void intel_init_clock_gating(struct drm_device *dev)
5618 {
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5620
5621 /*
5622 * Disable clock gating reported to work incorrectly according to the
5623 * specs, but enable as much else as we can.
5624 */
5625 if (HAS_PCH_SPLIT(dev)) {
5626 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5627
5628 if (IS_IRONLAKE(dev)) {
5629 /* Required for FBC */
5630 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5631 /* Required for CxSR */
5632 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5633
5634 I915_WRITE(PCH_3DCGDIS0,
5635 MARIUNIT_CLOCK_GATE_DISABLE |
5636 SVSMUNIT_CLOCK_GATE_DISABLE);
5637 }
5638
5639 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5640
5641 /*
5642 * On Ibex Peak and Cougar Point, we need to disable clock
5643 * gating for the panel power sequencer or it will fail to
5644 * start up when no ports are active.
5645 */
5646 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5647
5648 /*
5649 * According to the spec the following bits should be set in
5650 * order to enable memory self-refresh
5651 * The bit 22/21 of 0x42004
5652 * The bit 5 of 0x42020
5653 * The bit 15 of 0x45000
5654 */
5655 if (IS_IRONLAKE(dev)) {
5656 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5657 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5658 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5659 I915_WRITE(ILK_DSPCLK_GATE,
5660 (I915_READ(ILK_DSPCLK_GATE) |
5661 ILK_DPARB_CLK_GATE));
5662 I915_WRITE(DISP_ARB_CTL,
5663 (I915_READ(DISP_ARB_CTL) |
5664 DISP_FBC_WM_DIS));
5665 I915_WRITE(WM3_LP_ILK, 0);
5666 I915_WRITE(WM2_LP_ILK, 0);
5667 I915_WRITE(WM1_LP_ILK, 0);
5668 }
5669 /*
5670 * Based on the document from hardware guys the following bits
5671 * should be set unconditionally in order to enable FBC.
5672 * The bit 22 of 0x42000
5673 * The bit 22 of 0x42004
5674 * The bit 7,8,9 of 0x42020.
5675 */
5676 if (IS_IRONLAKE_M(dev)) {
5677 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5678 I915_READ(ILK_DISPLAY_CHICKEN1) |
5679 ILK_FBCQ_DIS);
5680 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5681 I915_READ(ILK_DISPLAY_CHICKEN2) |
5682 ILK_DPARB_GATE);
5683 I915_WRITE(ILK_DSPCLK_GATE,
5684 I915_READ(ILK_DSPCLK_GATE) |
5685 ILK_DPFC_DIS1 |
5686 ILK_DPFC_DIS2 |
5687 ILK_CLK_FBC);
5688 }
5689 return;
5690 } else if (IS_G4X(dev)) {
5691 uint32_t dspclk_gate;
5692 I915_WRITE(RENCLK_GATE_D1, 0);
5693 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5694 GS_UNIT_CLOCK_GATE_DISABLE |
5695 CL_UNIT_CLOCK_GATE_DISABLE);
5696 I915_WRITE(RAMCLK_GATE_D, 0);
5697 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5698 OVRUNIT_CLOCK_GATE_DISABLE |
5699 OVCUNIT_CLOCK_GATE_DISABLE;
5700 if (IS_GM45(dev))
5701 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5702 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5703 } else if (IS_I965GM(dev)) {
5704 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5705 I915_WRITE(RENCLK_GATE_D2, 0);
5706 I915_WRITE(DSPCLK_GATE_D, 0);
5707 I915_WRITE(RAMCLK_GATE_D, 0);
5708 I915_WRITE16(DEUC, 0);
5709 } else if (IS_I965G(dev)) {
5710 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5711 I965_RCC_CLOCK_GATE_DISABLE |
5712 I965_RCPB_CLOCK_GATE_DISABLE |
5713 I965_ISC_CLOCK_GATE_DISABLE |
5714 I965_FBC_CLOCK_GATE_DISABLE);
5715 I915_WRITE(RENCLK_GATE_D2, 0);
5716 } else if (IS_I9XX(dev)) {
5717 u32 dstate = I915_READ(D_STATE);
5718
5719 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5720 DSTATE_DOT_CLOCK_GATING;
5721 I915_WRITE(D_STATE, dstate);
5722 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5723 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5724 } else if (IS_I830(dev)) {
5725 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5726 }
5727
5728 /*
5729 * GPU can automatically power down the render unit if given a page
5730 * to save state.
5731 */
5732 if (IS_IRONLAKE_M(dev)) {
5733 if (dev_priv->renderctx == NULL)
5734 dev_priv->renderctx = intel_alloc_context_page(dev);
5735 if (dev_priv->renderctx) {
5736 struct drm_i915_gem_object *obj_priv;
5737 obj_priv = to_intel_bo(dev_priv->renderctx);
5738 if (obj_priv) {
5739 BEGIN_LP_RING(4);
5740 OUT_RING(MI_SET_CONTEXT);
5741 OUT_RING(obj_priv->gtt_offset |
5742 MI_MM_SPACE_GTT |
5743 MI_SAVE_EXT_STATE_EN |
5744 MI_RESTORE_EXT_STATE_EN |
5745 MI_RESTORE_INHIBIT);
5746 OUT_RING(MI_NOOP);
5747 OUT_RING(MI_FLUSH);
5748 ADVANCE_LP_RING();
5749 }
5750 } else
5751 DRM_DEBUG_KMS("Failed to allocate render context."
5752 "Disable RC6\n");
5753 }
5754
5755 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5756 struct drm_i915_gem_object *obj_priv = NULL;
5757
5758 if (dev_priv->pwrctx) {
5759 obj_priv = to_intel_bo(dev_priv->pwrctx);
5760 } else {
5761 struct drm_gem_object *pwrctx;
5762
5763 pwrctx = intel_alloc_context_page(dev);
5764 if (pwrctx) {
5765 dev_priv->pwrctx = pwrctx;
5766 obj_priv = to_intel_bo(pwrctx);
5767 }
5768 }
5769
5770 if (obj_priv) {
5771 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5772 I915_WRITE(MCHBAR_RENDER_STANDBY,
5773 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5774 }
5775 }
5776 }
5777
5778 /* Set up chip specific display functions */
5779 static void intel_init_display(struct drm_device *dev)
5780 {
5781 struct drm_i915_private *dev_priv = dev->dev_private;
5782
5783 /* We always want a DPMS function */
5784 if (HAS_PCH_SPLIT(dev))
5785 dev_priv->display.dpms = ironlake_crtc_dpms;
5786 else
5787 dev_priv->display.dpms = i9xx_crtc_dpms;
5788
5789 if (I915_HAS_FBC(dev)) {
5790 if (IS_IRONLAKE_M(dev)) {
5791 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5792 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5793 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5794 } else if (IS_GM45(dev)) {
5795 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5796 dev_priv->display.enable_fbc = g4x_enable_fbc;
5797 dev_priv->display.disable_fbc = g4x_disable_fbc;
5798 } else if (IS_I965GM(dev)) {
5799 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5800 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5801 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5802 }
5803 /* 855GM needs testing */
5804 }
5805
5806 /* Returns the core display clock speed */
5807 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5808 dev_priv->display.get_display_clock_speed =
5809 i945_get_display_clock_speed;
5810 else if (IS_I915G(dev))
5811 dev_priv->display.get_display_clock_speed =
5812 i915_get_display_clock_speed;
5813 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5814 dev_priv->display.get_display_clock_speed =
5815 i9xx_misc_get_display_clock_speed;
5816 else if (IS_I915GM(dev))
5817 dev_priv->display.get_display_clock_speed =
5818 i915gm_get_display_clock_speed;
5819 else if (IS_I865G(dev))
5820 dev_priv->display.get_display_clock_speed =
5821 i865_get_display_clock_speed;
5822 else if (IS_I85X(dev))
5823 dev_priv->display.get_display_clock_speed =
5824 i855_get_display_clock_speed;
5825 else /* 852, 830 */
5826 dev_priv->display.get_display_clock_speed =
5827 i830_get_display_clock_speed;
5828
5829 /* For FIFO watermark updates */
5830 if (HAS_PCH_SPLIT(dev)) {
5831 if (IS_IRONLAKE(dev)) {
5832 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5833 dev_priv->display.update_wm = ironlake_update_wm;
5834 else {
5835 DRM_DEBUG_KMS("Failed to get proper latency. "
5836 "Disable CxSR\n");
5837 dev_priv->display.update_wm = NULL;
5838 }
5839 } else
5840 dev_priv->display.update_wm = NULL;
5841 } else if (IS_PINEVIEW(dev)) {
5842 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5843 dev_priv->is_ddr3,
5844 dev_priv->fsb_freq,
5845 dev_priv->mem_freq)) {
5846 DRM_INFO("failed to find known CxSR latency "
5847 "(found ddr%s fsb freq %d, mem freq %d), "
5848 "disabling CxSR\n",
5849 (dev_priv->is_ddr3 == 1) ? "3": "2",
5850 dev_priv->fsb_freq, dev_priv->mem_freq);
5851 /* Disable CxSR and never update its watermark again */
5852 pineview_disable_cxsr(dev);
5853 dev_priv->display.update_wm = NULL;
5854 } else
5855 dev_priv->display.update_wm = pineview_update_wm;
5856 } else if (IS_G4X(dev))
5857 dev_priv->display.update_wm = g4x_update_wm;
5858 else if (IS_I965G(dev))
5859 dev_priv->display.update_wm = i965_update_wm;
5860 else if (IS_I9XX(dev)) {
5861 dev_priv->display.update_wm = i9xx_update_wm;
5862 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5863 } else if (IS_I85X(dev)) {
5864 dev_priv->display.update_wm = i9xx_update_wm;
5865 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5866 } else {
5867 dev_priv->display.update_wm = i830_update_wm;
5868 if (IS_845G(dev))
5869 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5870 else
5871 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5872 }
5873 }
5874
5875 /*
5876 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5877 * resume, or other times. This quirk makes sure that's the case for
5878 * affected systems.
5879 */
5880 static void quirk_pipea_force (struct drm_device *dev)
5881 {
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883
5884 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5885 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5886 }
5887
5888 struct intel_quirk {
5889 int device;
5890 int subsystem_vendor;
5891 int subsystem_device;
5892 void (*hook)(struct drm_device *dev);
5893 };
5894
5895 struct intel_quirk intel_quirks[] = {
5896 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5897 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5898 /* HP Mini needs pipe A force quirk (LP: #322104) */
5899 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5900
5901 /* Thinkpad R31 needs pipe A force quirk */
5902 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5903 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5904 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5905
5906 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5907 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5908 /* ThinkPad X40 needs pipe A force quirk */
5909
5910 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5911 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5912
5913 /* 855 & before need to leave pipe A & dpll A up */
5914 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5915 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5916 };
5917
5918 static void intel_init_quirks(struct drm_device *dev)
5919 {
5920 struct pci_dev *d = dev->pdev;
5921 int i;
5922
5923 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5924 struct intel_quirk *q = &intel_quirks[i];
5925
5926 if (d->device == q->device &&
5927 (d->subsystem_vendor == q->subsystem_vendor ||
5928 q->subsystem_vendor == PCI_ANY_ID) &&
5929 (d->subsystem_device == q->subsystem_device ||
5930 q->subsystem_device == PCI_ANY_ID))
5931 q->hook(dev);
5932 }
5933 }
5934
5935 /* Disable the VGA plane that we never use */
5936 static void i915_disable_vga(struct drm_device *dev)
5937 {
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939 u8 sr1;
5940 u32 vga_reg;
5941
5942 if (HAS_PCH_SPLIT(dev))
5943 vga_reg = CPU_VGACNTRL;
5944 else
5945 vga_reg = VGACNTRL;
5946
5947 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5948 outb(1, VGA_SR_INDEX);
5949 sr1 = inb(VGA_SR_DATA);
5950 outb(sr1 | 1<<5, VGA_SR_DATA);
5951 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5952 udelay(300);
5953
5954 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5955 POSTING_READ(vga_reg);
5956 }
5957
5958 void intel_modeset_init(struct drm_device *dev)
5959 {
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961 int i;
5962
5963 drm_mode_config_init(dev);
5964
5965 dev->mode_config.min_width = 0;
5966 dev->mode_config.min_height = 0;
5967
5968 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5969
5970 intel_init_quirks(dev);
5971
5972 intel_init_display(dev);
5973
5974 if (IS_I965G(dev)) {
5975 dev->mode_config.max_width = 8192;
5976 dev->mode_config.max_height = 8192;
5977 } else if (IS_I9XX(dev)) {
5978 dev->mode_config.max_width = 4096;
5979 dev->mode_config.max_height = 4096;
5980 } else {
5981 dev->mode_config.max_width = 2048;
5982 dev->mode_config.max_height = 2048;
5983 }
5984
5985 /* set memory base */
5986 if (IS_I9XX(dev))
5987 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
5988 else
5989 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
5990
5991 if (IS_MOBILE(dev) || IS_I9XX(dev))
5992 dev_priv->num_pipe = 2;
5993 else
5994 dev_priv->num_pipe = 1;
5995 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5996 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
5997
5998 for (i = 0; i < dev_priv->num_pipe; i++) {
5999 intel_crtc_init(dev, i);
6000 }
6001
6002 intel_setup_outputs(dev);
6003
6004 intel_init_clock_gating(dev);
6005
6006 /* Just disable it once at startup */
6007 i915_disable_vga(dev);
6008
6009 if (IS_IRONLAKE_M(dev)) {
6010 ironlake_enable_drps(dev);
6011 intel_init_emon(dev);
6012 }
6013
6014 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6015 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6016 (unsigned long)dev);
6017
6018 intel_setup_overlay(dev);
6019 }
6020
6021 void intel_modeset_cleanup(struct drm_device *dev)
6022 {
6023 struct drm_i915_private *dev_priv = dev->dev_private;
6024 struct drm_crtc *crtc;
6025 struct intel_crtc *intel_crtc;
6026
6027 mutex_lock(&dev->struct_mutex);
6028
6029 drm_kms_helper_poll_fini(dev);
6030 intel_fbdev_fini(dev);
6031
6032 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6033 /* Skip inactive CRTCs */
6034 if (!crtc->fb)
6035 continue;
6036
6037 intel_crtc = to_intel_crtc(crtc);
6038 intel_increase_pllclock(crtc, false);
6039 del_timer_sync(&intel_crtc->idle_timer);
6040 }
6041
6042 del_timer_sync(&dev_priv->idle_timer);
6043
6044 if (dev_priv->display.disable_fbc)
6045 dev_priv->display.disable_fbc(dev);
6046
6047 if (dev_priv->renderctx) {
6048 struct drm_i915_gem_object *obj_priv;
6049
6050 obj_priv = to_intel_bo(dev_priv->renderctx);
6051 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6052 I915_READ(CCID);
6053 i915_gem_object_unpin(dev_priv->renderctx);
6054 drm_gem_object_unreference(dev_priv->renderctx);
6055 }
6056
6057 if (dev_priv->pwrctx) {
6058 struct drm_i915_gem_object *obj_priv;
6059
6060 obj_priv = to_intel_bo(dev_priv->pwrctx);
6061 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6062 I915_READ(PWRCTXA);
6063 i915_gem_object_unpin(dev_priv->pwrctx);
6064 drm_gem_object_unreference(dev_priv->pwrctx);
6065 }
6066
6067 if (IS_IRONLAKE_M(dev))
6068 ironlake_disable_drps(dev);
6069
6070 mutex_unlock(&dev->struct_mutex);
6071
6072 drm_mode_config_cleanup(dev);
6073 }
6074
6075
6076 /*
6077 * Return which encoder is currently attached for connector.
6078 */
6079 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6080 {
6081 struct drm_mode_object *obj;
6082 struct drm_encoder *encoder;
6083 int i;
6084
6085 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6086 if (connector->encoder_ids[i] == 0)
6087 break;
6088
6089 obj = drm_mode_object_find(connector->dev,
6090 connector->encoder_ids[i],
6091 DRM_MODE_OBJECT_ENCODER);
6092 if (!obj)
6093 continue;
6094
6095 encoder = obj_to_encoder(obj);
6096 return encoder;
6097 }
6098 return NULL;
6099 }
6100
6101 /*
6102 * set vga decode state - true == enable VGA decode
6103 */
6104 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6105 {
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107 u16 gmch_ctrl;
6108
6109 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6110 if (state)
6111 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6112 else
6113 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6114 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6115 return 0;
6116 }
Tomato firmware and modifications.