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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / char / agp / amd-k7-agp.c
blobb6b1568314c8a5f63a44de50d70ca176b57b8090
1 /*
2 * AMD K7 AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
9 #include <linux/page-flags.h>
10 #include <linux/mm.h>
11 #include <linux/slab.h>
12 #include "agp.h"
13
14 #define AMD_MMBASE 0x14
15 #define AMD_APSIZE 0xac
16 #define AMD_MODECNTL 0xb0
17 #define AMD_MODECNTL2 0xb2
18 #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
19 #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
20 #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
21 #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
22
23 static struct pci_device_id agp_amdk7_pci_table[];
24
25 struct amd_page_map {
26 unsigned long *real;
27 unsigned long __iomem *remapped;
28 };
29
30 static struct _amd_irongate_private {
31 volatile u8 __iomem *registers;
32 struct amd_page_map **gatt_pages;
33 int num_tables;
34 } amd_irongate_private;
35
36 static int amd_create_page_map(struct amd_page_map *page_map)
37 {
38 int i;
39
40 page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
41 if (page_map->real == NULL)
42 return -ENOMEM;
43
44 #ifndef CONFIG_X86
45 SetPageReserved(virt_to_page(page_map->real));
46 global_cache_flush();
47 page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
48 PAGE_SIZE);
49 if (page_map->remapped == NULL) {
50 ClearPageReserved(virt_to_page(page_map->real));
51 free_page((unsigned long) page_map->real);
52 page_map->real = NULL;
53 return -ENOMEM;
54 }
55 global_cache_flush();
56 #else
57 set_memory_uc((unsigned long)page_map->real, 1);
58 page_map->remapped = page_map->real;
59 #endif
60
61 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
62 writel(agp_bridge->scratch_page, page_map->remapped+i);
63 readl(page_map->remapped+i); /* PCI Posting. */
64 }
65
66 return 0;
67 }
68
69 static void amd_free_page_map(struct amd_page_map *page_map)
70 {
71 #ifndef CONFIG_X86
72 iounmap(page_map->remapped);
73 ClearPageReserved(virt_to_page(page_map->real));
74 #else
75 set_memory_wb((unsigned long)page_map->real, 1);
76 #endif
77 free_page((unsigned long) page_map->real);
78 }
79
80 static void amd_free_gatt_pages(void)
81 {
82 int i;
83 struct amd_page_map **tables;
84 struct amd_page_map *entry;
85
86 tables = amd_irongate_private.gatt_pages;
87 for (i = 0; i < amd_irongate_private.num_tables; i++) {
88 entry = tables[i];
89 if (entry != NULL) {
90 if (entry->real != NULL)
91 amd_free_page_map(entry);
92 kfree(entry);
93 }
94 }
95 kfree(tables);
96 amd_irongate_private.gatt_pages = NULL;
97 }
98
99 static int amd_create_gatt_pages(int nr_tables)
100 {
101 struct amd_page_map **tables;
102 struct amd_page_map *entry;
103 int retval = 0;
104 int i;
105
106 tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
107 if (tables == NULL)
108 return -ENOMEM;
109
110 for (i = 0; i < nr_tables; i++) {
111 entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
112 tables[i] = entry;
113 if (entry == NULL) {
114 retval = -ENOMEM;
115 break;
116 }
117 retval = amd_create_page_map(entry);
118 if (retval != 0)
119 break;
120 }
121 amd_irongate_private.num_tables = i;
122 amd_irongate_private.gatt_pages = tables;
123
124 if (retval != 0)
125 amd_free_gatt_pages();
126
127 return retval;
128 }
129
130 /* Since we don't need contiguous memory we just try
131 * to get the gatt table once
132 */
133
134 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
135 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
136 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
137 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
138 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
139 GET_PAGE_DIR_IDX(addr)]->remapped)
140
141 static int amd_create_gatt_table(struct agp_bridge_data *bridge)
142 {
143 struct aper_size_info_lvl2 *value;
144 struct amd_page_map page_dir;
145 unsigned long __iomem *cur_gatt;
146 unsigned long addr;
147 int retval;
148 u32 temp;
149 int i;
150
151 value = A_SIZE_LVL2(agp_bridge->current_size);
152 retval = amd_create_page_map(&page_dir);
153 if (retval != 0)
154 return retval;
155
156 retval = amd_create_gatt_pages(value->num_entries / 1024);
157 if (retval != 0) {
158 amd_free_page_map(&page_dir);
159 return retval;
160 }
161
162 agp_bridge->gatt_table_real = (u32 *)page_dir.real;
163 agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
164 agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
165
166 /* Get the address for the gart region.
167 * This is a bus address even on the alpha, b/c its
168 * used to program the agp master not the cpu
169 */
170
171 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
172 addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
173 agp_bridge->gart_bus_addr = addr;
174
175 /* Calculate the agp offset */
176 for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
177 writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
178 page_dir.remapped+GET_PAGE_DIR_OFF(addr));
179 readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
180 }
181
182 for (i = 0; i < value->num_entries; i++) {
183 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
184 cur_gatt = GET_GATT(addr);
185 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
186 readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
187 }
188
189 return 0;
190 }
191
192 static int amd_free_gatt_table(struct agp_bridge_data *bridge)
193 {
194 struct amd_page_map page_dir;
195
196 page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
197 page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
198
199 amd_free_gatt_pages();
200 amd_free_page_map(&page_dir);
201 return 0;
202 }
203
204 static int amd_irongate_fetch_size(void)
205 {
206 int i;
207 u32 temp;
208 struct aper_size_info_lvl2 *values;
209
210 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
211 temp = (temp & 0x0000000e);
212 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
213 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
214 if (temp == values[i].size_value) {
215 agp_bridge->previous_size =
216 agp_bridge->current_size = (void *) (values + i);
217
218 agp_bridge->aperture_size_idx = i;
219 return values[i].size;
220 }
221 }
222
223 return 0;
224 }
225
226 static int amd_irongate_configure(void)
227 {
228 struct aper_size_info_lvl2 *current_size;
229 u32 temp;
230 u16 enable_reg;
231
232 current_size = A_SIZE_LVL2(agp_bridge->current_size);
233
234 if (!amd_irongate_private.registers) {
235 /* Get the memory mapped registers */
236 pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
237 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
238 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
239 if (!amd_irongate_private.registers)
240 return -ENOMEM;
241 }
242
243 /* Write out the address of the gatt table */
244 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
245 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
246
247 /* Write the Sync register */
248 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
249
250 /* Set indexing mode */
251 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
252
253 /* Write the enable register */
254 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
255 enable_reg = (enable_reg | 0x0004);
256 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
257 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
258
259 /* Write out the size register */
260 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
261 temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
262 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
263
264 /* Flush the tlb */
265 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
266 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
267 return 0;
268 }
269
270 static void amd_irongate_cleanup(void)
271 {
272 struct aper_size_info_lvl2 *previous_size;
273 u32 temp;
274 u16 enable_reg;
275
276 previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
277
278 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
279 enable_reg = (enable_reg & ~(0x0004));
280 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
281 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
282
283 /* Write back the previous size and disable gart translation */
284 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
285 temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
286 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
287 iounmap((void __iomem *) amd_irongate_private.registers);
288 }
289
290 /*
291 * This routine could be implemented by taking the addresses
292 * written to the GATT, and flushing them individually. However
293 * currently it just flushes the whole table. Which is probably
294 * more efficent, since agp_memory blocks can be a large number of
295 * entries.
296 */
297
298 static void amd_irongate_tlbflush(struct agp_memory *temp)
299 {
300 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
301 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
302 }
303
304 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
305 {
306 int i, j, num_entries;
307 unsigned long __iomem *cur_gatt;
308 unsigned long addr;
309
310 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
311
312 if (type != 0 || mem->type != 0)
313 return -EINVAL;
314
315 if ((pg_start + mem->page_count) > num_entries)
316 return -EINVAL;
317
318 j = pg_start;
319 while (j < (pg_start + mem->page_count)) {
320 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
321 cur_gatt = GET_GATT(addr);
322 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
323 return -EBUSY;
324 j++;
325 }
326
327 if (!mem->is_flushed) {
328 global_cache_flush();
329 mem->is_flushed = true;
330 }
331
332 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
333 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
334 cur_gatt = GET_GATT(addr);
335 writel(agp_generic_mask_memory(agp_bridge,
336 page_to_phys(mem->pages[i]),
337 mem->type),
338 cur_gatt+GET_GATT_OFF(addr));
339 readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
340 }
341 amd_irongate_tlbflush(mem);
342 return 0;
343 }
344
345 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
346 {
347 int i;
348 unsigned long __iomem *cur_gatt;
349 unsigned long addr;
350
351 if (type != 0 || mem->type != 0)
352 return -EINVAL;
353
354 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
355 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
356 cur_gatt = GET_GATT(addr);
357 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
358 readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
359 }
360
361 amd_irongate_tlbflush(mem);
362 return 0;
363 }
364
365 static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
366 {
367 {2048, 524288, 0x0000000c},
368 {1024, 262144, 0x0000000a},
369 {512, 131072, 0x00000008},
370 {256, 65536, 0x00000006},
371 {128, 32768, 0x00000004},
372 {64, 16384, 0x00000002},
373 {32, 8192, 0x00000000}
374 };
375
376 static const struct gatt_mask amd_irongate_masks[] =
377 {
378 {.mask = 1, .type = 0}
379 };
380
381 static const struct agp_bridge_driver amd_irongate_driver = {
382 .owner = THIS_MODULE,
383 .aperture_sizes = amd_irongate_sizes,
384 .size_type = LVL2_APER_SIZE,
385 .num_aperture_sizes = 7,
386 .needs_scratch_page = true,
387 .configure = amd_irongate_configure,
388 .fetch_size = amd_irongate_fetch_size,
389 .cleanup = amd_irongate_cleanup,
390 .tlb_flush = amd_irongate_tlbflush,
391 .mask_memory = agp_generic_mask_memory,
392 .masks = amd_irongate_masks,
393 .agp_enable = agp_generic_enable,
394 .cache_flush = global_cache_flush,
395 .create_gatt_table = amd_create_gatt_table,
396 .free_gatt_table = amd_free_gatt_table,
397 .insert_memory = amd_insert_memory,
398 .remove_memory = amd_remove_memory,
399 .alloc_by_type = agp_generic_alloc_by_type,
400 .free_by_type = agp_generic_free_by_type,
401 .agp_alloc_page = agp_generic_alloc_page,
402 .agp_alloc_pages = agp_generic_alloc_pages,
403 .agp_destroy_page = agp_generic_destroy_page,
404 .agp_destroy_pages = agp_generic_destroy_pages,
405 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
406 };
407
408 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
409 {
410 {
411 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
412 .chipset_name = "Irongate",
413 },
414 {
415 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
416 .chipset_name = "761",
417 },
418 {
419 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
420 .chipset_name = "760MP",
421 },
422 { }, /* dummy final entry, always present */
423 };
424
425 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
426 const struct pci_device_id *ent)
427 {
428 struct agp_bridge_data *bridge;
429 u8 cap_ptr;
430 int j;
431
432 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
433 if (!cap_ptr)
434 return -ENODEV;
435
436 j = ent - agp_amdk7_pci_table;
437 dev_info(&pdev->dev, "AMD %s chipset\n",
438 amd_agp_device_ids[j].chipset_name);
439
440 bridge = agp_alloc_bridge();
441 if (!bridge)
442 return -ENOMEM;
443
444 bridge->driver = &amd_irongate_driver;
445 bridge->dev_private_data = &amd_irongate_private,
446 bridge->dev = pdev;
447 bridge->capndx = cap_ptr;
448
449 /* 751 Errata (22564_B-1.PDF)
450 erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
451 system controller may experience noise due to strong drive strengths
452 */
453 if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
454 struct pci_dev *gfxcard=NULL;
455
456 cap_ptr = 0;
457 while (!cap_ptr) {
458 gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
459 if (!gfxcard) {
460 dev_info(&pdev->dev, "no AGP VGA controller\n");
461 return -ENODEV;
462 }
463 cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
464 }
465
466 /* With so many variants of NVidia cards, it's simpler just
467 to blacklist them all, and then whitelist them as needed
468 (if necessary at all). */
469 if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
470 agp_bridge->flags |= AGP_ERRATA_1X;
471 dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
472 }
473 pci_dev_put(gfxcard);
474 }
475
476 /* 761 Errata (23613_F.pdf)
477 * Revisions B0/B1 were a disaster.
478 * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
479 * erratum 45: Timing problem prevents fast writes -- Disable fast write.
480 * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
481 * With this lot disabled, we should prevent lockups. */
482 if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
483 if (pdev->revision == 0x10 || pdev->revision == 0x11) {
484 agp_bridge->flags = AGP_ERRATA_FASTWRITES;
485 agp_bridge->flags |= AGP_ERRATA_SBA;
486 agp_bridge->flags |= AGP_ERRATA_1X;
487 dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
488 }
489 }
490
491 /* Fill in the mode register */
492 pci_read_config_dword(pdev,
493 bridge->capndx+PCI_AGP_STATUS,
494 &bridge->mode);
495
496 pci_set_drvdata(pdev, bridge);
497 return agp_add_bridge(bridge);
498 }
499
500 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
501 {
502 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
503
504 agp_remove_bridge(bridge);
505 agp_put_bridge(bridge);
506 }
507
508 #ifdef CONFIG_PM
509
510 static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
511 {
512 pci_save_state(pdev);
513 pci_set_power_state(pdev, pci_choose_state(pdev, state));
514
515 return 0;
516 }
517
518 static int agp_amdk7_resume(struct pci_dev *pdev)
519 {
520 pci_set_power_state(pdev, PCI_D0);
521 pci_restore_state(pdev);
522
523 return amd_irongate_driver.configure();
524 }
525
526 #endif /* CONFIG_PM */
527
528 /* must be the same order as name table above */
529 static struct pci_device_id agp_amdk7_pci_table[] = {
530 {
531 .class = (PCI_CLASS_BRIDGE_HOST << 8),
532 .class_mask = ~0,
533 .vendor = PCI_VENDOR_ID_AMD,
534 .device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
535 .subvendor = PCI_ANY_ID,
536 .subdevice = PCI_ANY_ID,
537 },
538 {
539 .class = (PCI_CLASS_BRIDGE_HOST << 8),
540 .class_mask = ~0,
541 .vendor = PCI_VENDOR_ID_AMD,
542 .device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
543 .subvendor = PCI_ANY_ID,
544 .subdevice = PCI_ANY_ID,
545 },
546 {
547 .class = (PCI_CLASS_BRIDGE_HOST << 8),
548 .class_mask = ~0,
549 .vendor = PCI_VENDOR_ID_AMD,
550 .device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
551 .subvendor = PCI_ANY_ID,
552 .subdevice = PCI_ANY_ID,
553 },
554 { }
555 };
556
557 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
558
559 static struct pci_driver agp_amdk7_pci_driver = {
560 .name = "agpgart-amdk7",
561 .id_table = agp_amdk7_pci_table,
562 .probe = agp_amdk7_probe,
563 .remove = agp_amdk7_remove,
564 #ifdef CONFIG_PM
565 .suspend = agp_amdk7_suspend,
566 .resume = agp_amdk7_resume,
567 #endif
568 };
569
570 static int __init agp_amdk7_init(void)
571 {
572 if (agp_off)
573 return -EINVAL;
574 return pci_register_driver(&agp_amdk7_pci_driver);
575 }
576
577 static void __exit agp_amdk7_cleanup(void)
578 {
579 pci_unregister_driver(&agp_amdk7_pci_driver);
580 }
581
582 module_init(agp_amdk7_init);
583 module_exit(agp_amdk7_cleanup);
584
585 MODULE_LICENSE("GPL and additional rights");
Tomato firmware and modifications.