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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / drivers / atm / idt77252.c
blobd87709c14f49da87a678fd572dd24077642fdeec
1 /*******************************************************************
2 *
3 * Copyright (c) 2000 ATecoM GmbH
4 *
5 * The author may be reached at ecd@atecom.com.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *******************************************************************/
28
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/poison.h>
32 #include <linux/skbuff.h>
33 #include <linux/kernel.h>
34 #include <linux/vmalloc.h>
35 #include <linux/netdevice.h>
36 #include <linux/atmdev.h>
37 #include <linux/atm.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/bitops.h>
41 #include <linux/wait.h>
42 #include <linux/jiffies.h>
43 #include <linux/mutex.h>
44 #include <linux/slab.h>
45
46 #include <asm/io.h>
47 #include <asm/uaccess.h>
48 #include <asm/atomic.h>
49 #include <asm/byteorder.h>
50
51 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
52 #include "suni.h"
53 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
54
55
56 #include "idt77252.h"
57 #include "idt77252_tables.h"
58
59 static unsigned int vpibits = 1;
60
61
62 #define ATM_IDT77252_SEND_IDLE 1
63
64
65 /*
66 * Debug HACKs.
67 */
68 #define DEBUG_MODULE 1
69 #undef HAVE_EEPROM /* does not work, yet. */
70
71 #ifdef CONFIG_ATM_IDT77252_DEBUG
72 static unsigned long debug = DBG_GENERAL;
73 #endif
74
75
76 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
77
78
79 /*
80 * SCQ Handling.
81 */
82 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
83 static void free_scq(struct idt77252_dev *, struct scq_info *);
84 static int queue_skb(struct idt77252_dev *, struct vc_map *,
85 struct sk_buff *, int oam);
86 static void drain_scq(struct idt77252_dev *, struct vc_map *);
87 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
88 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
89
90 /*
91 * FBQ Handling.
92 */
93 static int push_rx_skb(struct idt77252_dev *,
94 struct sk_buff *, int queue);
95 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
96 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
97 static void recycle_rx_pool_skb(struct idt77252_dev *,
98 struct rx_pool *);
99 static void add_rx_skb(struct idt77252_dev *, int queue,
100 unsigned int size, unsigned int count);
101
102 /*
103 * RSQ Handling.
104 */
105 static int init_rsq(struct idt77252_dev *);
106 static void deinit_rsq(struct idt77252_dev *);
107 static void idt77252_rx(struct idt77252_dev *);
108
109 /*
110 * TSQ handling.
111 */
112 static int init_tsq(struct idt77252_dev *);
113 static void deinit_tsq(struct idt77252_dev *);
114 static void idt77252_tx(struct idt77252_dev *);
115
116
117 /*
118 * ATM Interface.
119 */
120 static void idt77252_dev_close(struct atm_dev *dev);
121 static int idt77252_open(struct atm_vcc *vcc);
122 static void idt77252_close(struct atm_vcc *vcc);
123 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
124 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
125 int flags);
126 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
127 unsigned long addr);
128 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
129 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
130 int flags);
131 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
132 char *page);
133 static void idt77252_softint(struct work_struct *work);
134
135
136 static struct atmdev_ops idt77252_ops =
137 {
138 .dev_close = idt77252_dev_close,
139 .open = idt77252_open,
140 .close = idt77252_close,
141 .send = idt77252_send,
142 .send_oam = idt77252_send_oam,
143 .phy_put = idt77252_phy_put,
144 .phy_get = idt77252_phy_get,
145 .change_qos = idt77252_change_qos,
146 .proc_read = idt77252_proc_read,
147 .owner = THIS_MODULE
148 };
149
150 static struct idt77252_dev *idt77252_chain = NULL;
151 static unsigned int idt77252_sram_write_errors = 0;
152
153 /*****************************************************************************/
154 /* */
155 /* I/O and Utility Bus */
156 /* */
157 /*****************************************************************************/
158
159 static void
160 waitfor_idle(struct idt77252_dev *card)
161 {
162 u32 stat;
163
164 stat = readl(SAR_REG_STAT);
165 while (stat & SAR_STAT_CMDBZ)
166 stat = readl(SAR_REG_STAT);
167 }
168
169 static u32
170 read_sram(struct idt77252_dev *card, unsigned long addr)
171 {
172 unsigned long flags;
173 u32 value;
174
175 spin_lock_irqsave(&card->cmd_lock, flags);
176 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
177 waitfor_idle(card);
178 value = readl(SAR_REG_DR0);
179 spin_unlock_irqrestore(&card->cmd_lock, flags);
180 return value;
181 }
182
183 static void
184 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
185 {
186 unsigned long flags;
187
188 if ((idt77252_sram_write_errors == 0) &&
189 (((addr > card->tst[0] + card->tst_size - 2) &&
190 (addr < card->tst[0] + card->tst_size)) ||
191 ((addr > card->tst[1] + card->tst_size - 2) &&
192 (addr < card->tst[1] + card->tst_size)))) {
193 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
194 card->name, addr, value);
195 }
196
197 spin_lock_irqsave(&card->cmd_lock, flags);
198 writel(value, SAR_REG_DR0);
199 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
200 waitfor_idle(card);
201 spin_unlock_irqrestore(&card->cmd_lock, flags);
202 }
203
204 static u8
205 read_utility(void *dev, unsigned long ubus_addr)
206 {
207 struct idt77252_dev *card = dev;
208 unsigned long flags;
209 u8 value;
210
211 if (!card) {
212 printk("Error: No such device.\n");
213 return -1;
214 }
215
216 spin_lock_irqsave(&card->cmd_lock, flags);
217 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
218 waitfor_idle(card);
219 value = readl(SAR_REG_DR0);
220 spin_unlock_irqrestore(&card->cmd_lock, flags);
221 return value;
222 }
223
224 static void
225 write_utility(void *dev, unsigned long ubus_addr, u8 value)
226 {
227 struct idt77252_dev *card = dev;
228 unsigned long flags;
229
230 if (!card) {
231 printk("Error: No such device.\n");
232 return;
233 }
234
235 spin_lock_irqsave(&card->cmd_lock, flags);
236 writel((u32) value, SAR_REG_DR0);
237 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
238 waitfor_idle(card);
239 spin_unlock_irqrestore(&card->cmd_lock, flags);
240 }
241
242 #ifdef HAVE_EEPROM
243 static u32 rdsrtab[] =
244 {
245 SAR_GP_EECS | SAR_GP_EESCLK,
246 0,
247 SAR_GP_EESCLK, /* 0 */
248 0,
249 SAR_GP_EESCLK, /* 0 */
250 0,
251 SAR_GP_EESCLK, /* 0 */
252 0,
253 SAR_GP_EESCLK, /* 0 */
254 0,
255 SAR_GP_EESCLK, /* 0 */
256 SAR_GP_EEDO,
257 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
258 0,
259 SAR_GP_EESCLK, /* 0 */
260 SAR_GP_EEDO,
261 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
262 };
263
264 static u32 wrentab[] =
265 {
266 SAR_GP_EECS | SAR_GP_EESCLK,
267 0,
268 SAR_GP_EESCLK, /* 0 */
269 0,
270 SAR_GP_EESCLK, /* 0 */
271 0,
272 SAR_GP_EESCLK, /* 0 */
273 0,
274 SAR_GP_EESCLK, /* 0 */
275 SAR_GP_EEDO,
276 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
277 SAR_GP_EEDO,
278 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
279 0,
280 SAR_GP_EESCLK, /* 0 */
281 0,
282 SAR_GP_EESCLK /* 0 */
283 };
284
285 static u32 rdtab[] =
286 {
287 SAR_GP_EECS | SAR_GP_EESCLK,
288 0,
289 SAR_GP_EESCLK, /* 0 */
290 0,
291 SAR_GP_EESCLK, /* 0 */
292 0,
293 SAR_GP_EESCLK, /* 0 */
294 0,
295 SAR_GP_EESCLK, /* 0 */
296 0,
297 SAR_GP_EESCLK, /* 0 */
298 0,
299 SAR_GP_EESCLK, /* 0 */
300 SAR_GP_EEDO,
301 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
302 SAR_GP_EEDO,
303 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
304 };
305
306 static u32 wrtab[] =
307 {
308 SAR_GP_EECS | SAR_GP_EESCLK,
309 0,
310 SAR_GP_EESCLK, /* 0 */
311 0,
312 SAR_GP_EESCLK, /* 0 */
313 0,
314 SAR_GP_EESCLK, /* 0 */
315 0,
316 SAR_GP_EESCLK, /* 0 */
317 0,
318 SAR_GP_EESCLK, /* 0 */
319 0,
320 SAR_GP_EESCLK, /* 0 */
321 SAR_GP_EEDO,
322 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
323 0,
324 SAR_GP_EESCLK /* 0 */
325 };
326
327 static u32 clktab[] =
328 {
329 0,
330 SAR_GP_EESCLK,
331 0,
332 SAR_GP_EESCLK,
333 0,
334 SAR_GP_EESCLK,
335 0,
336 SAR_GP_EESCLK,
337 0,
338 SAR_GP_EESCLK,
339 0,
340 SAR_GP_EESCLK,
341 0,
342 SAR_GP_EESCLK,
343 0,
344 SAR_GP_EESCLK,
345 0
346 };
347
348 static u32
349 idt77252_read_gp(struct idt77252_dev *card)
350 {
351 u32 gp;
352
353 gp = readl(SAR_REG_GP);
354 return gp;
355 }
356
357 static void
358 idt77252_write_gp(struct idt77252_dev *card, u32 value)
359 {
360 unsigned long flags;
361
362
363 spin_lock_irqsave(&card->cmd_lock, flags);
364 waitfor_idle(card);
365 writel(value, SAR_REG_GP);
366 spin_unlock_irqrestore(&card->cmd_lock, flags);
367 }
368
369 static u8
370 idt77252_eeprom_read_status(struct idt77252_dev *card)
371 {
372 u8 byte;
373 u32 gp;
374 int i, j;
375
376 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
377
378 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
379 idt77252_write_gp(card, gp | rdsrtab[i]);
380 udelay(5);
381 }
382 idt77252_write_gp(card, gp | SAR_GP_EECS);
383 udelay(5);
384
385 byte = 0;
386 for (i = 0, j = 0; i < 8; i++) {
387 byte <<= 1;
388
389 idt77252_write_gp(card, gp | clktab[j++]);
390 udelay(5);
391
392 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
393
394 idt77252_write_gp(card, gp | clktab[j++]);
395 udelay(5);
396 }
397 idt77252_write_gp(card, gp | SAR_GP_EECS);
398 udelay(5);
399
400 return byte;
401 }
402
403 static u8
404 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
405 {
406 u8 byte;
407 u32 gp;
408 int i, j;
409
410 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
411
412 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
413 idt77252_write_gp(card, gp | rdtab[i]);
414 udelay(5);
415 }
416 idt77252_write_gp(card, gp | SAR_GP_EECS);
417 udelay(5);
418
419 for (i = 0, j = 0; i < 8; i++) {
420 idt77252_write_gp(card, gp | clktab[j++] |
421 (offset & 1 ? SAR_GP_EEDO : 0));
422 udelay(5);
423
424 idt77252_write_gp(card, gp | clktab[j++] |
425 (offset & 1 ? SAR_GP_EEDO : 0));
426 udelay(5);
427
428 offset >>= 1;
429 }
430 idt77252_write_gp(card, gp | SAR_GP_EECS);
431 udelay(5);
432
433 byte = 0;
434 for (i = 0, j = 0; i < 8; i++) {
435 byte <<= 1;
436
437 idt77252_write_gp(card, gp | clktab[j++]);
438 udelay(5);
439
440 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
441
442 idt77252_write_gp(card, gp | clktab[j++]);
443 udelay(5);
444 }
445 idt77252_write_gp(card, gp | SAR_GP_EECS);
446 udelay(5);
447
448 return byte;
449 }
450
451 static void
452 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
453 {
454 u32 gp;
455 int i, j;
456
457 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
458
459 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
460 idt77252_write_gp(card, gp | wrentab[i]);
461 udelay(5);
462 }
463 idt77252_write_gp(card, gp | SAR_GP_EECS);
464 udelay(5);
465
466 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
467 idt77252_write_gp(card, gp | wrtab[i]);
468 udelay(5);
469 }
470 idt77252_write_gp(card, gp | SAR_GP_EECS);
471 udelay(5);
472
473 for (i = 0, j = 0; i < 8; i++) {
474 idt77252_write_gp(card, gp | clktab[j++] |
475 (offset & 1 ? SAR_GP_EEDO : 0));
476 udelay(5);
477
478 idt77252_write_gp(card, gp | clktab[j++] |
479 (offset & 1 ? SAR_GP_EEDO : 0));
480 udelay(5);
481
482 offset >>= 1;
483 }
484 idt77252_write_gp(card, gp | SAR_GP_EECS);
485 udelay(5);
486
487 for (i = 0, j = 0; i < 8; i++) {
488 idt77252_write_gp(card, gp | clktab[j++] |
489 (data & 1 ? SAR_GP_EEDO : 0));
490 udelay(5);
491
492 idt77252_write_gp(card, gp | clktab[j++] |
493 (data & 1 ? SAR_GP_EEDO : 0));
494 udelay(5);
495
496 data >>= 1;
497 }
498 idt77252_write_gp(card, gp | SAR_GP_EECS);
499 udelay(5);
500 }
501
502 static void
503 idt77252_eeprom_init(struct idt77252_dev *card)
504 {
505 u32 gp;
506
507 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
508
509 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
510 udelay(5);
511 idt77252_write_gp(card, gp | SAR_GP_EECS);
512 udelay(5);
513 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
514 udelay(5);
515 idt77252_write_gp(card, gp | SAR_GP_EECS);
516 udelay(5);
517 }
518 #endif /* HAVE_EEPROM */
519
520
521 #ifdef CONFIG_ATM_IDT77252_DEBUG
522 static void
523 dump_tct(struct idt77252_dev *card, int index)
524 {
525 unsigned long tct;
526 int i;
527
528 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
529
530 printk("%s: TCT %x:", card->name, index);
531 for (i = 0; i < 8; i++) {
532 printk(" %08x", read_sram(card, tct + i));
533 }
534 printk("\n");
535 }
536
537 static void
538 idt77252_tx_dump(struct idt77252_dev *card)
539 {
540 struct atm_vcc *vcc;
541 struct vc_map *vc;
542 int i;
543
544 printk("%s\n", __func__);
545 for (i = 0; i < card->tct_size; i++) {
546 vc = card->vcs[i];
547 if (!vc)
548 continue;
549
550 vcc = NULL;
551 if (vc->rx_vcc)
552 vcc = vc->rx_vcc;
553 else if (vc->tx_vcc)
554 vcc = vc->tx_vcc;
555
556 if (!vcc)
557 continue;
558
559 printk("%s: Connection %d:\n", card->name, vc->index);
560 dump_tct(card, vc->index);
561 }
562 }
563 #endif
564
565
566 /*****************************************************************************/
567 /* */
568 /* SCQ Handling */
569 /* */
570 /*****************************************************************************/
571
572 static int
573 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
574 {
575 struct sb_pool *pool = &card->sbpool[queue];
576 int index;
577
578 index = pool->index;
579 while (pool->skb[index]) {
580 index = (index + 1) & FBQ_MASK;
581 if (index == pool->index)
582 return -ENOBUFS;
583 }
584
585 pool->skb[index] = skb;
586 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
587
588 pool->index = (index + 1) & FBQ_MASK;
589 return 0;
590 }
591
592 static void
593 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
594 {
595 unsigned int queue, index;
596 u32 handle;
597
598 handle = IDT77252_PRV_POOL(skb);
599
600 queue = POOL_QUEUE(handle);
601 if (queue > 3)
602 return;
603
604 index = POOL_INDEX(handle);
605 if (index > FBQ_SIZE - 1)
606 return;
607
608 card->sbpool[queue].skb[index] = NULL;
609 }
610
611 static struct sk_buff *
612 sb_pool_skb(struct idt77252_dev *card, u32 handle)
613 {
614 unsigned int queue, index;
615
616 queue = POOL_QUEUE(handle);
617 if (queue > 3)
618 return NULL;
619
620 index = POOL_INDEX(handle);
621 if (index > FBQ_SIZE - 1)
622 return NULL;
623
624 return card->sbpool[queue].skb[index];
625 }
626
627 static struct scq_info *
628 alloc_scq(struct idt77252_dev *card, int class)
629 {
630 struct scq_info *scq;
631
632 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
633 if (!scq)
634 return NULL;
635 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
636 &scq->paddr);
637 if (scq->base == NULL) {
638 kfree(scq);
639 return NULL;
640 }
641 memset(scq->base, 0, SCQ_SIZE);
642
643 scq->next = scq->base;
644 scq->last = scq->base + (SCQ_ENTRIES - 1);
645 atomic_set(&scq->used, 0);
646
647 spin_lock_init(&scq->lock);
648 spin_lock_init(&scq->skblock);
649
650 skb_queue_head_init(&scq->transmit);
651 skb_queue_head_init(&scq->pending);
652
653 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
654 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
655
656 return scq;
657 }
658
659 static void
660 free_scq(struct idt77252_dev *card, struct scq_info *scq)
661 {
662 struct sk_buff *skb;
663 struct atm_vcc *vcc;
664
665 pci_free_consistent(card->pcidev, SCQ_SIZE,
666 scq->base, scq->paddr);
667
668 while ((skb = skb_dequeue(&scq->transmit))) {
669 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
670 skb->len, PCI_DMA_TODEVICE);
671
672 vcc = ATM_SKB(skb)->vcc;
673 if (vcc->pop)
674 vcc->pop(vcc, skb);
675 else
676 dev_kfree_skb(skb);
677 }
678
679 while ((skb = skb_dequeue(&scq->pending))) {
680 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
681 skb->len, PCI_DMA_TODEVICE);
682
683 vcc = ATM_SKB(skb)->vcc;
684 if (vcc->pop)
685 vcc->pop(vcc, skb);
686 else
687 dev_kfree_skb(skb);
688 }
689
690 kfree(scq);
691 }
692
693
694 static int
695 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
696 {
697 struct scq_info *scq = vc->scq;
698 unsigned long flags;
699 struct scqe *tbd;
700 int entries;
701
702 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
703
704 atomic_inc(&scq->used);
705 entries = atomic_read(&scq->used);
706 if (entries > (SCQ_ENTRIES - 1)) {
707 atomic_dec(&scq->used);
708 goto out;
709 }
710
711 skb_queue_tail(&scq->transmit, skb);
712
713 spin_lock_irqsave(&vc->lock, flags);
714 if (vc->estimator) {
715 struct atm_vcc *vcc = vc->tx_vcc;
716 struct sock *sk = sk_atm(vcc);
717
718 vc->estimator->cells += (skb->len + 47) / 48;
719 if (atomic_read(&sk->sk_wmem_alloc) >
720 (sk->sk_sndbuf >> 1)) {
721 u32 cps = vc->estimator->maxcps;
722
723 vc->estimator->cps = cps;
724 vc->estimator->avcps = cps << 5;
725 if (vc->lacr < vc->init_er) {
726 vc->lacr = vc->init_er;
727 writel(TCMDQ_LACR | (vc->lacr << 16) |
728 vc->index, SAR_REG_TCMDQ);
729 }
730 }
731 }
732 spin_unlock_irqrestore(&vc->lock, flags);
733
734 tbd = &IDT77252_PRV_TBD(skb);
735
736 spin_lock_irqsave(&scq->lock, flags);
737 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
738 SAR_TBD_TSIF | SAR_TBD_GTSI);
739 scq->next->word_2 = cpu_to_le32(tbd->word_2);
740 scq->next->word_3 = cpu_to_le32(tbd->word_3);
741 scq->next->word_4 = cpu_to_le32(tbd->word_4);
742
743 if (scq->next == scq->last)
744 scq->next = scq->base;
745 else
746 scq->next++;
747
748 write_sram(card, scq->scd,
749 scq->paddr +
750 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
751 spin_unlock_irqrestore(&scq->lock, flags);
752
753 scq->trans_start = jiffies;
754
755 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
756 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
757 SAR_REG_TCMDQ);
758 }
759
760 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
761
762 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
763 card->name, atomic_read(&scq->used),
764 read_sram(card, scq->scd + 1), scq->next);
765
766 return 0;
767
768 out:
769 if (time_after(jiffies, scq->trans_start + HZ)) {
770 printk("%s: Error pushing TBD for %d.%d\n",
771 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
772 #ifdef CONFIG_ATM_IDT77252_DEBUG
773 idt77252_tx_dump(card);
774 #endif
775 scq->trans_start = jiffies;
776 }
777
778 return -ENOBUFS;
779 }
780
781
782 static void
783 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
784 {
785 struct scq_info *scq = vc->scq;
786 struct sk_buff *skb;
787 struct atm_vcc *vcc;
788
789 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
790 card->name, atomic_read(&scq->used), scq->next);
791
792 skb = skb_dequeue(&scq->transmit);
793 if (skb) {
794 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
795
796 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
797 skb->len, PCI_DMA_TODEVICE);
798
799 vcc = ATM_SKB(skb)->vcc;
800
801 if (vcc->pop)
802 vcc->pop(vcc, skb);
803 else
804 dev_kfree_skb(skb);
805
806 atomic_inc(&vcc->stats->tx);
807 }
808
809 atomic_dec(&scq->used);
810
811 spin_lock(&scq->skblock);
812 while ((skb = skb_dequeue(&scq->pending))) {
813 if (push_on_scq(card, vc, skb)) {
814 skb_queue_head(&vc->scq->pending, skb);
815 break;
816 }
817 }
818 spin_unlock(&scq->skblock);
819 }
820
821 static int
822 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
823 struct sk_buff *skb, int oam)
824 {
825 struct atm_vcc *vcc;
826 struct scqe *tbd;
827 unsigned long flags;
828 int error;
829 int aal;
830
831 if (skb->len == 0) {
832 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
833 return -EINVAL;
834 }
835
836 TXPRINTK("%s: Sending %d bytes of data.\n",
837 card->name, skb->len);
838
839 tbd = &IDT77252_PRV_TBD(skb);
840 vcc = ATM_SKB(skb)->vcc;
841
842 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
843 skb->len, PCI_DMA_TODEVICE);
844
845 error = -EINVAL;
846
847 if (oam) {
848 if (skb->len != 52)
849 goto errout;
850
851 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
852 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
853 tbd->word_3 = 0x00000000;
854 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
855 (skb->data[2] << 8) | (skb->data[3] << 0);
856
857 if (test_bit(VCF_RSV, &vc->flags))
858 vc = card->vcs[0];
859
860 goto done;
861 }
862
863 if (test_bit(VCF_RSV, &vc->flags)) {
864 printk("%s: Trying to transmit on reserved VC\n", card->name);
865 goto errout;
866 }
867
868 aal = vcc->qos.aal;
869
870 switch (aal) {
871 case ATM_AAL0:
872 case ATM_AAL34:
873 if (skb->len > 52)
874 goto errout;
875
876 if (aal == ATM_AAL0)
877 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
878 ATM_CELL_PAYLOAD;
879 else
880 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
881 ATM_CELL_PAYLOAD;
882
883 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
884 tbd->word_3 = 0x00000000;
885 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
886 (skb->data[2] << 8) | (skb->data[3] << 0);
887 break;
888
889 case ATM_AAL5:
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
891 tbd->word_2 = IDT77252_PRV_PADDR(skb);
892 tbd->word_3 = skb->len;
893 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
894 (vcc->vci << SAR_TBD_VCI_SHIFT);
895 break;
896
897 case ATM_AAL1:
898 case ATM_AAL2:
899 default:
900 printk("%s: Traffic type not supported.\n", card->name);
901 error = -EPROTONOSUPPORT;
902 goto errout;
903 }
904
905 done:
906 spin_lock_irqsave(&vc->scq->skblock, flags);
907 skb_queue_tail(&vc->scq->pending, skb);
908
909 while ((skb = skb_dequeue(&vc->scq->pending))) {
910 if (push_on_scq(card, vc, skb)) {
911 skb_queue_head(&vc->scq->pending, skb);
912 break;
913 }
914 }
915 spin_unlock_irqrestore(&vc->scq->skblock, flags);
916
917 return 0;
918
919 errout:
920 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
921 skb->len, PCI_DMA_TODEVICE);
922 return error;
923 }
924
925 static unsigned long
926 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
927 {
928 int i;
929
930 for (i = 0; i < card->scd_size; i++) {
931 if (!card->scd2vc[i]) {
932 card->scd2vc[i] = vc;
933 vc->scd_index = i;
934 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
935 }
936 }
937 return 0;
938 }
939
940 static void
941 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
942 {
943 write_sram(card, scq->scd, scq->paddr);
944 write_sram(card, scq->scd + 1, 0x00000000);
945 write_sram(card, scq->scd + 2, 0xffffffff);
946 write_sram(card, scq->scd + 3, 0x00000000);
947 }
948
949 static void
950 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
951 {
952 return;
953 }
954
955 /*****************************************************************************/
956 /* */
957 /* RSQ Handling */
958 /* */
959 /*****************************************************************************/
960
961 static int
962 init_rsq(struct idt77252_dev *card)
963 {
964 struct rsq_entry *rsqe;
965
966 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
967 &card->rsq.paddr);
968 if (card->rsq.base == NULL) {
969 printk("%s: can't allocate RSQ.\n", card->name);
970 return -1;
971 }
972 memset(card->rsq.base, 0, RSQSIZE);
973
974 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
975 card->rsq.next = card->rsq.last;
976 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
977 rsqe->word_4 = 0;
978
979 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
980 SAR_REG_RSQH);
981 writel(card->rsq.paddr, SAR_REG_RSQB);
982
983 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
984 (unsigned long) card->rsq.base,
985 readl(SAR_REG_RSQB));
986 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
987 card->name,
988 readl(SAR_REG_RSQH),
989 readl(SAR_REG_RSQB),
990 readl(SAR_REG_RSQT));
991
992 return 0;
993 }
994
995 static void
996 deinit_rsq(struct idt77252_dev *card)
997 {
998 pci_free_consistent(card->pcidev, RSQSIZE,
999 card->rsq.base, card->rsq.paddr);
1000 }
1001
1002 static void
1003 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1004 {
1005 struct atm_vcc *vcc;
1006 struct sk_buff *skb;
1007 struct rx_pool *rpp;
1008 struct vc_map *vc;
1009 u32 header, vpi, vci;
1010 u32 stat;
1011 int i;
1012
1013 stat = le32_to_cpu(rsqe->word_4);
1014
1015 if (stat & SAR_RSQE_IDLE) {
1016 RXPRINTK("%s: message about inactive connection.\n",
1017 card->name);
1018 return;
1019 }
1020
1021 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1022 if (skb == NULL) {
1023 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1024 card->name, __func__,
1025 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1026 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1027 return;
1028 }
1029
1030 header = le32_to_cpu(rsqe->word_1);
1031 vpi = (header >> 16) & 0x00ff;
1032 vci = (header >> 0) & 0xffff;
1033
1034 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1035 card->name, vpi, vci, skb, skb->data);
1036
1037 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1038 printk("%s: SDU received for out-of-range vc %u.%u\n",
1039 card->name, vpi, vci);
1040 recycle_rx_skb(card, skb);
1041 return;
1042 }
1043
1044 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1045 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1046 printk("%s: SDU received on non RX vc %u.%u\n",
1047 card->name, vpi, vci);
1048 recycle_rx_skb(card, skb);
1049 return;
1050 }
1051
1052 vcc = vc->rx_vcc;
1053
1054 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1055 skb_end_pointer(skb) - skb->data,
1056 PCI_DMA_FROMDEVICE);
1057
1058 if ((vcc->qos.aal == ATM_AAL0) ||
1059 (vcc->qos.aal == ATM_AAL34)) {
1060 struct sk_buff *sb;
1061 unsigned char *cell;
1062 u32 aal0;
1063
1064 cell = skb->data;
1065 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1066 if ((sb = dev_alloc_skb(64)) == NULL) {
1067 printk("%s: Can't allocate buffers for aal0.\n",
1068 card->name);
1069 atomic_add(i, &vcc->stats->rx_drop);
1070 break;
1071 }
1072 if (!atm_charge(vcc, sb->truesize)) {
1073 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1074 card->name);
1075 atomic_add(i - 1, &vcc->stats->rx_drop);
1076 dev_kfree_skb(sb);
1077 break;
1078 }
1079 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1080 (vci << ATM_HDR_VCI_SHIFT);
1081 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1082 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1083
1084 *((u32 *) sb->data) = aal0;
1085 skb_put(sb, sizeof(u32));
1086 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1087 cell, ATM_CELL_PAYLOAD);
1088
1089 ATM_SKB(sb)->vcc = vcc;
1090 __net_timestamp(sb);
1091 vcc->push(vcc, sb);
1092 atomic_inc(&vcc->stats->rx);
1093
1094 cell += ATM_CELL_PAYLOAD;
1095 }
1096
1097 recycle_rx_skb(card, skb);
1098 return;
1099 }
1100 if (vcc->qos.aal != ATM_AAL5) {
1101 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1102 card->name, vcc->qos.aal);
1103 recycle_rx_skb(card, skb);
1104 return;
1105 }
1106 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1107
1108 rpp = &vc->rcv.rx_pool;
1109
1110 __skb_queue_tail(&rpp->queue, skb);
1111 rpp->len += skb->len;
1112
1113 if (stat & SAR_RSQE_EPDU) {
1114 unsigned char *l1l2;
1115 unsigned int len;
1116
1117 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1118
1119 len = (l1l2[0] << 8) | l1l2[1];
1120 len = len ? len : 0x10000;
1121
1122 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1123
1124 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1125 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1126 "(CDC: %08x)\n",
1127 card->name, len, rpp->len, readl(SAR_REG_CDC));
1128 recycle_rx_pool_skb(card, rpp);
1129 atomic_inc(&vcc->stats->rx_err);
1130 return;
1131 }
1132 if (stat & SAR_RSQE_CRC) {
1133 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1134 recycle_rx_pool_skb(card, rpp);
1135 atomic_inc(&vcc->stats->rx_err);
1136 return;
1137 }
1138 if (skb_queue_len(&rpp->queue) > 1) {
1139 struct sk_buff *sb;
1140
1141 skb = dev_alloc_skb(rpp->len);
1142 if (!skb) {
1143 RXPRINTK("%s: Can't alloc RX skb.\n",
1144 card->name);
1145 recycle_rx_pool_skb(card, rpp);
1146 atomic_inc(&vcc->stats->rx_err);
1147 return;
1148 }
1149 if (!atm_charge(vcc, skb->truesize)) {
1150 recycle_rx_pool_skb(card, rpp);
1151 dev_kfree_skb(skb);
1152 return;
1153 }
1154 skb_queue_walk(&rpp->queue, sb)
1155 memcpy(skb_put(skb, sb->len),
1156 sb->data, sb->len);
1157
1158 recycle_rx_pool_skb(card, rpp);
1159
1160 skb_trim(skb, len);
1161 ATM_SKB(skb)->vcc = vcc;
1162 __net_timestamp(skb);
1163
1164 vcc->push(vcc, skb);
1165 atomic_inc(&vcc->stats->rx);
1166
1167 return;
1168 }
1169
1170 flush_rx_pool(card, rpp);
1171
1172 if (!atm_charge(vcc, skb->truesize)) {
1173 recycle_rx_skb(card, skb);
1174 return;
1175 }
1176
1177 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1178 skb_end_pointer(skb) - skb->data,
1179 PCI_DMA_FROMDEVICE);
1180 sb_pool_remove(card, skb);
1181
1182 skb_trim(skb, len);
1183 ATM_SKB(skb)->vcc = vcc;
1184 __net_timestamp(skb);
1185
1186 vcc->push(vcc, skb);
1187 atomic_inc(&vcc->stats->rx);
1188
1189 if (skb->truesize > SAR_FB_SIZE_3)
1190 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1191 else if (skb->truesize > SAR_FB_SIZE_2)
1192 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1193 else if (skb->truesize > SAR_FB_SIZE_1)
1194 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1195 else
1196 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1197 return;
1198 }
1199 }
1200
1201 static void
1202 idt77252_rx(struct idt77252_dev *card)
1203 {
1204 struct rsq_entry *rsqe;
1205
1206 if (card->rsq.next == card->rsq.last)
1207 rsqe = card->rsq.base;
1208 else
1209 rsqe = card->rsq.next + 1;
1210
1211 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1212 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1213 return;
1214 }
1215
1216 do {
1217 dequeue_rx(card, rsqe);
1218 rsqe->word_4 = 0;
1219 card->rsq.next = rsqe;
1220 if (card->rsq.next == card->rsq.last)
1221 rsqe = card->rsq.base;
1222 else
1223 rsqe = card->rsq.next + 1;
1224 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1225
1226 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1227 SAR_REG_RSQH);
1228 }
1229
1230 static void
1231 idt77252_rx_raw(struct idt77252_dev *card)
1232 {
1233 struct sk_buff *queue;
1234 u32 head, tail;
1235 struct atm_vcc *vcc;
1236 struct vc_map *vc;
1237 struct sk_buff *sb;
1238
1239 if (card->raw_cell_head == NULL) {
1240 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1241 card->raw_cell_head = sb_pool_skb(card, handle);
1242 }
1243
1244 queue = card->raw_cell_head;
1245 if (!queue)
1246 return;
1247
1248 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1249 tail = readl(SAR_REG_RAWCT);
1250
1251 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1252 skb_end_pointer(queue) - queue->head - 16,
1253 PCI_DMA_FROMDEVICE);
1254
1255 while (head != tail) {
1256 unsigned int vpi, vci, pti;
1257 u32 header;
1258
1259 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1260
1261 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1262 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1263 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1264
1265 #ifdef CONFIG_ATM_IDT77252_DEBUG
1266 if (debug & DBG_RAW_CELL) {
1267 int i;
1268
1269 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1270 card->name, (header >> 28) & 0x000f,
1271 (header >> 20) & 0x00ff,
1272 (header >> 4) & 0xffff,
1273 (header >> 1) & 0x0007,
1274 (header >> 0) & 0x0001);
1275 for (i = 16; i < 64; i++)
1276 printk(" %02x", queue->data[i]);
1277 printk("\n");
1278 }
1279 #endif
1280
1281 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1282 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1283 card->name, vpi, vci);
1284 goto drop;
1285 }
1286
1287 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1288 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1289 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1290 card->name, vpi, vci);
1291 goto drop;
1292 }
1293
1294 vcc = vc->rx_vcc;
1295
1296 if (vcc->qos.aal != ATM_AAL0) {
1297 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1298 card->name, vpi, vci);
1299 atomic_inc(&vcc->stats->rx_drop);
1300 goto drop;
1301 }
1302
1303 if ((sb = dev_alloc_skb(64)) == NULL) {
1304 printk("%s: Can't allocate buffers for AAL0.\n",
1305 card->name);
1306 atomic_inc(&vcc->stats->rx_err);
1307 goto drop;
1308 }
1309
1310 if (!atm_charge(vcc, sb->truesize)) {
1311 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1312 card->name);
1313 dev_kfree_skb(sb);
1314 goto drop;
1315 }
1316
1317 *((u32 *) sb->data) = header;
1318 skb_put(sb, sizeof(u32));
1319 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1320 ATM_CELL_PAYLOAD);
1321
1322 ATM_SKB(sb)->vcc = vcc;
1323 __net_timestamp(sb);
1324 vcc->push(vcc, sb);
1325 atomic_inc(&vcc->stats->rx);
1326
1327 drop:
1328 skb_pull(queue, 64);
1329
1330 head = IDT77252_PRV_PADDR(queue)
1331 + (queue->data - queue->head - 16);
1332
1333 if (queue->len < 128) {
1334 struct sk_buff *next;
1335 u32 handle;
1336
1337 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1338 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1339
1340 next = sb_pool_skb(card, handle);
1341 recycle_rx_skb(card, queue);
1342
1343 if (next) {
1344 card->raw_cell_head = next;
1345 queue = card->raw_cell_head;
1346 pci_dma_sync_single_for_cpu(card->pcidev,
1347 IDT77252_PRV_PADDR(queue),
1348 (skb_end_pointer(queue) -
1349 queue->data),
1350 PCI_DMA_FROMDEVICE);
1351 } else {
1352 card->raw_cell_head = NULL;
1353 printk("%s: raw cell queue overrun\n",
1354 card->name);
1355 break;
1356 }
1357 }
1358 }
1359 }
1360
1361
1362 /*****************************************************************************/
1363 /* */
1364 /* TSQ Handling */
1365 /* */
1366 /*****************************************************************************/
1367
1368 static int
1369 init_tsq(struct idt77252_dev *card)
1370 {
1371 struct tsq_entry *tsqe;
1372
1373 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1374 &card->tsq.paddr);
1375 if (card->tsq.base == NULL) {
1376 printk("%s: can't allocate TSQ.\n", card->name);
1377 return -1;
1378 }
1379 memset(card->tsq.base, 0, TSQSIZE);
1380
1381 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1382 card->tsq.next = card->tsq.last;
1383 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1384 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1385
1386 writel(card->tsq.paddr, SAR_REG_TSQB);
1387 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1388 SAR_REG_TSQH);
1389
1390 return 0;
1391 }
1392
1393 static void
1394 deinit_tsq(struct idt77252_dev *card)
1395 {
1396 pci_free_consistent(card->pcidev, TSQSIZE,
1397 card->tsq.base, card->tsq.paddr);
1398 }
1399
1400 static void
1401 idt77252_tx(struct idt77252_dev *card)
1402 {
1403 struct tsq_entry *tsqe;
1404 unsigned int vpi, vci;
1405 struct vc_map *vc;
1406 u32 conn, stat;
1407
1408 if (card->tsq.next == card->tsq.last)
1409 tsqe = card->tsq.base;
1410 else
1411 tsqe = card->tsq.next + 1;
1412
1413 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1414 card->tsq.base, card->tsq.next, card->tsq.last);
1415 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1416 readl(SAR_REG_TSQB),
1417 readl(SAR_REG_TSQT),
1418 readl(SAR_REG_TSQH));
1419
1420 stat = le32_to_cpu(tsqe->word_2);
1421
1422 if (stat & SAR_TSQE_INVALID)
1423 return;
1424
1425 do {
1426 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1427 le32_to_cpu(tsqe->word_1),
1428 le32_to_cpu(tsqe->word_2));
1429
1430 switch (stat & SAR_TSQE_TYPE) {
1431 case SAR_TSQE_TYPE_TIMER:
1432 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1433 break;
1434
1435 case SAR_TSQE_TYPE_IDLE:
1436
1437 conn = le32_to_cpu(tsqe->word_1);
1438
1439 if (SAR_TSQE_TAG(stat) == 0x10) {
1440 #ifdef NOTDEF
1441 printk("%s: Connection %d halted.\n",
1442 card->name,
1443 le32_to_cpu(tsqe->word_1) & 0x1fff);
1444 #endif
1445 break;
1446 }
1447
1448 vc = card->vcs[conn & 0x1fff];
1449 if (!vc) {
1450 printk("%s: could not find VC from conn %d\n",
1451 card->name, conn & 0x1fff);
1452 break;
1453 }
1454
1455 printk("%s: Connection %d IDLE.\n",
1456 card->name, vc->index);
1457
1458 set_bit(VCF_IDLE, &vc->flags);
1459 break;
1460
1461 case SAR_TSQE_TYPE_TSR:
1462
1463 conn = le32_to_cpu(tsqe->word_1);
1464
1465 vc = card->vcs[conn & 0x1fff];
1466 if (!vc) {
1467 printk("%s: no VC at index %d\n",
1468 card->name,
1469 le32_to_cpu(tsqe->word_1) & 0x1fff);
1470 break;
1471 }
1472
1473 drain_scq(card, vc);
1474 break;
1475
1476 case SAR_TSQE_TYPE_TBD_COMP:
1477
1478 conn = le32_to_cpu(tsqe->word_1);
1479
1480 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1481 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1482
1483 if (vpi >= (1 << card->vpibits) ||
1484 vci >= (1 << card->vcibits)) {
1485 printk("%s: TBD complete: "
1486 "out of range VPI.VCI %u.%u\n",
1487 card->name, vpi, vci);
1488 break;
1489 }
1490
1491 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1492 if (!vc) {
1493 printk("%s: TBD complete: "
1494 "no VC at VPI.VCI %u.%u\n",
1495 card->name, vpi, vci);
1496 break;
1497 }
1498
1499 drain_scq(card, vc);
1500 break;
1501 }
1502
1503 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1504
1505 card->tsq.next = tsqe;
1506 if (card->tsq.next == card->tsq.last)
1507 tsqe = card->tsq.base;
1508 else
1509 tsqe = card->tsq.next + 1;
1510
1511 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1512 card->tsq.base, card->tsq.next, card->tsq.last);
1513
1514 stat = le32_to_cpu(tsqe->word_2);
1515
1516 } while (!(stat & SAR_TSQE_INVALID));
1517
1518 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1519 SAR_REG_TSQH);
1520
1521 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1522 card->index, readl(SAR_REG_TSQH),
1523 readl(SAR_REG_TSQT), card->tsq.next);
1524 }
1525
1526
1527 static void
1528 tst_timer(unsigned long data)
1529 {
1530 struct idt77252_dev *card = (struct idt77252_dev *)data;
1531 unsigned long base, idle, jump;
1532 unsigned long flags;
1533 u32 pc;
1534 int e;
1535
1536 spin_lock_irqsave(&card->tst_lock, flags);
1537
1538 base = card->tst[card->tst_index];
1539 idle = card->tst[card->tst_index ^ 1];
1540
1541 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1542 jump = base + card->tst_size - 2;
1543
1544 pc = readl(SAR_REG_NOW) >> 2;
1545 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1546 mod_timer(&card->tst_timer, jiffies + 1);
1547 goto out;
1548 }
1549
1550 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1551
1552 card->tst_index ^= 1;
1553 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1554
1555 base = card->tst[card->tst_index];
1556 idle = card->tst[card->tst_index ^ 1];
1557
1558 for (e = 0; e < card->tst_size - 2; e++) {
1559 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1560 write_sram(card, idle + e,
1561 card->soft_tst[e].tste & TSTE_MASK);
1562 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1563 }
1564 }
1565 }
1566
1567 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1568
1569 for (e = 0; e < card->tst_size - 2; e++) {
1570 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1571 write_sram(card, idle + e,
1572 card->soft_tst[e].tste & TSTE_MASK);
1573 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1574 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1575 }
1576 }
1577
1578 jump = base + card->tst_size - 2;
1579
1580 write_sram(card, jump, TSTE_OPC_NULL);
1581 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1582
1583 mod_timer(&card->tst_timer, jiffies + 1);
1584 }
1585
1586 out:
1587 spin_unlock_irqrestore(&card->tst_lock, flags);
1588 }
1589
1590 static int
1591 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1592 int n, unsigned int opc)
1593 {
1594 unsigned long cl, avail;
1595 unsigned long idle;
1596 int e, r;
1597 u32 data;
1598
1599 avail = card->tst_size - 2;
1600 for (e = 0; e < avail; e++) {
1601 if (card->soft_tst[e].vc == NULL)
1602 break;
1603 }
1604 if (e >= avail) {
1605 printk("%s: No free TST entries found\n", card->name);
1606 return -1;
1607 }
1608
1609 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1610 card->name, vc ? vc->index : -1, e);
1611
1612 r = n;
1613 cl = avail;
1614 data = opc & TSTE_OPC_MASK;
1615 if (vc && (opc != TSTE_OPC_NULL))
1616 data = opc | vc->index;
1617
1618 idle = card->tst[card->tst_index ^ 1];
1619
1620 /*
1621 * Fill Soft TST.
1622 */
1623 while (r > 0) {
1624 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1625 if (vc)
1626 card->soft_tst[e].vc = vc;
1627 else
1628 card->soft_tst[e].vc = (void *)-1;
1629
1630 card->soft_tst[e].tste = data;
1631 if (timer_pending(&card->tst_timer))
1632 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1633 else {
1634 write_sram(card, idle + e, data);
1635 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1636 }
1637
1638 cl -= card->tst_size;
1639 r--;
1640 }
1641
1642 if (++e == avail)
1643 e = 0;
1644 cl += n;
1645 }
1646
1647 return 0;
1648 }
1649
1650 static int
1651 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1652 {
1653 unsigned long flags;
1654 int res;
1655
1656 spin_lock_irqsave(&card->tst_lock, flags);
1657
1658 res = __fill_tst(card, vc, n, opc);
1659
1660 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1661 if (!timer_pending(&card->tst_timer))
1662 mod_timer(&card->tst_timer, jiffies + 1);
1663
1664 spin_unlock_irqrestore(&card->tst_lock, flags);
1665 return res;
1666 }
1667
1668 static int
1669 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1670 {
1671 unsigned long idle;
1672 int e;
1673
1674 idle = card->tst[card->tst_index ^ 1];
1675
1676 for (e = 0; e < card->tst_size - 2; e++) {
1677 if (card->soft_tst[e].vc == vc) {
1678 card->soft_tst[e].vc = NULL;
1679
1680 card->soft_tst[e].tste = TSTE_OPC_VAR;
1681 if (timer_pending(&card->tst_timer))
1682 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1683 else {
1684 write_sram(card, idle + e, TSTE_OPC_VAR);
1685 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1686 }
1687 }
1688 }
1689
1690 return 0;
1691 }
1692
1693 static int
1694 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1695 {
1696 unsigned long flags;
1697 int res;
1698
1699 spin_lock_irqsave(&card->tst_lock, flags);
1700
1701 res = __clear_tst(card, vc);
1702
1703 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1704 if (!timer_pending(&card->tst_timer))
1705 mod_timer(&card->tst_timer, jiffies + 1);
1706
1707 spin_unlock_irqrestore(&card->tst_lock, flags);
1708 return res;
1709 }
1710
1711 static int
1712 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1713 int n, unsigned int opc)
1714 {
1715 unsigned long flags;
1716 int res;
1717
1718 spin_lock_irqsave(&card->tst_lock, flags);
1719
1720 __clear_tst(card, vc);
1721 res = __fill_tst(card, vc, n, opc);
1722
1723 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1724 if (!timer_pending(&card->tst_timer))
1725 mod_timer(&card->tst_timer, jiffies + 1);
1726
1727 spin_unlock_irqrestore(&card->tst_lock, flags);
1728 return res;
1729 }
1730
1731
1732 static int
1733 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1734 {
1735 unsigned long tct;
1736
1737 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1738
1739 switch (vc->class) {
1740 case SCHED_CBR:
1741 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1742 card->name, tct, vc->scq->scd);
1743
1744 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1745 write_sram(card, tct + 1, 0);
1746 write_sram(card, tct + 2, 0);
1747 write_sram(card, tct + 3, 0);
1748 write_sram(card, tct + 4, 0);
1749 write_sram(card, tct + 5, 0);
1750 write_sram(card, tct + 6, 0);
1751 write_sram(card, tct + 7, 0);
1752 break;
1753
1754 case SCHED_UBR:
1755 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1756 card->name, tct, vc->scq->scd);
1757
1758 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1759 write_sram(card, tct + 1, 0);
1760 write_sram(card, tct + 2, TCT_TSIF);
1761 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1762 write_sram(card, tct + 4, 0);
1763 write_sram(card, tct + 5, vc->init_er);
1764 write_sram(card, tct + 6, 0);
1765 write_sram(card, tct + 7, TCT_FLAG_UBR);
1766 break;
1767
1768 case SCHED_VBR:
1769 case SCHED_ABR:
1770 default:
1771 return -ENOSYS;
1772 }
1773
1774 return 0;
1775 }
1776
1777 /*****************************************************************************/
1778 /* */
1779 /* FBQ Handling */
1780 /* */
1781 /*****************************************************************************/
1782
1783 static __inline__ int
1784 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1785 {
1786 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1787 }
1788
1789 static __inline__ int
1790 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1791 {
1792 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1793 }
1794
1795 static int
1796 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1797 {
1798 unsigned long flags;
1799 u32 handle;
1800 u32 addr;
1801
1802 skb->data = skb->head;
1803 skb_reset_tail_pointer(skb);
1804 skb->len = 0;
1805
1806 skb_reserve(skb, 16);
1807
1808 switch (queue) {
1809 case 0:
1810 skb_put(skb, SAR_FB_SIZE_0);
1811 break;
1812 case 1:
1813 skb_put(skb, SAR_FB_SIZE_1);
1814 break;
1815 case 2:
1816 skb_put(skb, SAR_FB_SIZE_2);
1817 break;
1818 case 3:
1819 skb_put(skb, SAR_FB_SIZE_3);
1820 break;
1821 default:
1822 return -1;
1823 }
1824
1825 if (idt77252_fbq_full(card, queue))
1826 return -1;
1827
1828 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1829
1830 handle = IDT77252_PRV_POOL(skb);
1831 addr = IDT77252_PRV_PADDR(skb);
1832
1833 spin_lock_irqsave(&card->cmd_lock, flags);
1834 writel(handle, card->fbq[queue]);
1835 writel(addr, card->fbq[queue]);
1836 spin_unlock_irqrestore(&card->cmd_lock, flags);
1837
1838 return 0;
1839 }
1840
1841 static void
1842 add_rx_skb(struct idt77252_dev *card, int queue,
1843 unsigned int size, unsigned int count)
1844 {
1845 struct sk_buff *skb;
1846 dma_addr_t paddr;
1847 u32 handle;
1848
1849 while (count--) {
1850 skb = dev_alloc_skb(size);
1851 if (!skb)
1852 return;
1853
1854 if (sb_pool_add(card, skb, queue)) {
1855 printk("%s: SB POOL full\n", __func__);
1856 goto outfree;
1857 }
1858
1859 paddr = pci_map_single(card->pcidev, skb->data,
1860 skb_end_pointer(skb) - skb->data,
1861 PCI_DMA_FROMDEVICE);
1862 IDT77252_PRV_PADDR(skb) = paddr;
1863
1864 if (push_rx_skb(card, skb, queue)) {
1865 printk("%s: FB QUEUE full\n", __func__);
1866 goto outunmap;
1867 }
1868 }
1869
1870 return;
1871
1872 outunmap:
1873 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1874 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE);
1875
1876 handle = IDT77252_PRV_POOL(skb);
1877 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1878
1879 outfree:
1880 dev_kfree_skb(skb);
1881 }
1882
1883
1884 static void
1885 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1886 {
1887 u32 handle = IDT77252_PRV_POOL(skb);
1888 int err;
1889
1890 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1891 skb_end_pointer(skb) - skb->data,
1892 PCI_DMA_FROMDEVICE);
1893
1894 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1895 if (err) {
1896 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1897 skb_end_pointer(skb) - skb->data,
1898 PCI_DMA_FROMDEVICE);
1899 sb_pool_remove(card, skb);
1900 dev_kfree_skb(skb);
1901 }
1902 }
1903
1904 static void
1905 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1906 {
1907 skb_queue_head_init(&rpp->queue);
1908 rpp->len = 0;
1909 }
1910
1911 static void
1912 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1913 {
1914 struct sk_buff *skb, *tmp;
1915
1916 skb_queue_walk_safe(&rpp->queue, skb, tmp)
1917 recycle_rx_skb(card, skb);
1918
1919 flush_rx_pool(card, rpp);
1920 }
1921
1922 /*****************************************************************************/
1923 /* */
1924 /* ATM Interface */
1925 /* */
1926 /*****************************************************************************/
1927
1928 static void
1929 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1930 {
1931 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1932 }
1933
1934 static unsigned char
1935 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1936 {
1937 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1938 }
1939
1940 static inline int
1941 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1942 {
1943 struct atm_dev *dev = vcc->dev;
1944 struct idt77252_dev *card = dev->dev_data;
1945 struct vc_map *vc = vcc->dev_data;
1946 int err;
1947
1948 if (vc == NULL) {
1949 printk("%s: NULL connection in send().\n", card->name);
1950 atomic_inc(&vcc->stats->tx_err);
1951 dev_kfree_skb(skb);
1952 return -EINVAL;
1953 }
1954 if (!test_bit(VCF_TX, &vc->flags)) {
1955 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1956 atomic_inc(&vcc->stats->tx_err);
1957 dev_kfree_skb(skb);
1958 return -EINVAL;
1959 }
1960
1961 switch (vcc->qos.aal) {
1962 case ATM_AAL0:
1963 case ATM_AAL1:
1964 case ATM_AAL5:
1965 break;
1966 default:
1967 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1968 atomic_inc(&vcc->stats->tx_err);
1969 dev_kfree_skb(skb);
1970 return -EINVAL;
1971 }
1972
1973 if (skb_shinfo(skb)->nr_frags != 0) {
1974 printk("%s: No scatter-gather yet.\n", card->name);
1975 atomic_inc(&vcc->stats->tx_err);
1976 dev_kfree_skb(skb);
1977 return -EINVAL;
1978 }
1979 ATM_SKB(skb)->vcc = vcc;
1980
1981 err = queue_skb(card, vc, skb, oam);
1982 if (err) {
1983 atomic_inc(&vcc->stats->tx_err);
1984 dev_kfree_skb(skb);
1985 return err;
1986 }
1987
1988 return 0;
1989 }
1990
1991 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
1992 {
1993 return idt77252_send_skb(vcc, skb, 0);
1994 }
1995
1996 static int
1997 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
1998 {
1999 struct atm_dev *dev = vcc->dev;
2000 struct idt77252_dev *card = dev->dev_data;
2001 struct sk_buff *skb;
2002
2003 skb = dev_alloc_skb(64);
2004 if (!skb) {
2005 printk("%s: Out of memory in send_oam().\n", card->name);
2006 atomic_inc(&vcc->stats->tx_err);
2007 return -ENOMEM;
2008 }
2009 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2010
2011 memcpy(skb_put(skb, 52), cell, 52);
2012
2013 return idt77252_send_skb(vcc, skb, 1);
2014 }
2015
2016 static __inline__ unsigned int
2017 idt77252_fls(unsigned int x)
2018 {
2019 int r = 1;
2020
2021 if (x == 0)
2022 return 0;
2023 if (x & 0xffff0000) {
2024 x >>= 16;
2025 r += 16;
2026 }
2027 if (x & 0xff00) {
2028 x >>= 8;
2029 r += 8;
2030 }
2031 if (x & 0xf0) {
2032 x >>= 4;
2033 r += 4;
2034 }
2035 if (x & 0xc) {
2036 x >>= 2;
2037 r += 2;
2038 }
2039 if (x & 0x2)
2040 r += 1;
2041 return r;
2042 }
2043
2044 static u16
2045 idt77252_int_to_atmfp(unsigned int rate)
2046 {
2047 u16 m, e;
2048
2049 if (rate == 0)
2050 return 0;
2051 e = idt77252_fls(rate) - 1;
2052 if (e < 9)
2053 m = (rate - (1 << e)) << (9 - e);
2054 else if (e == 9)
2055 m = (rate - (1 << e));
2056 else /* e > 9 */
2057 m = (rate - (1 << e)) >> (e - 9);
2058 return 0x4000 | (e << 9) | m;
2059 }
2060
2061 static u8
2062 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2063 {
2064 u16 afp;
2065
2066 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2067 if (pcr < 0)
2068 return rate_to_log[(afp >> 5) & 0x1ff];
2069 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2070 }
2071
2072 static void
2073 idt77252_est_timer(unsigned long data)
2074 {
2075 struct vc_map *vc = (struct vc_map *)data;
2076 struct idt77252_dev *card = vc->card;
2077 struct rate_estimator *est;
2078 unsigned long flags;
2079 u32 rate, cps;
2080 u64 ncells;
2081 u8 lacr;
2082
2083 spin_lock_irqsave(&vc->lock, flags);
2084 est = vc->estimator;
2085 if (!est)
2086 goto out;
2087
2088 ncells = est->cells;
2089
2090 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2091 est->last_cells = ncells;
2092 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2093 est->cps = (est->avcps + 0x1f) >> 5;
2094
2095 cps = est->cps;
2096 if (cps < (est->maxcps >> 4))
2097 cps = est->maxcps >> 4;
2098
2099 lacr = idt77252_rate_logindex(card, cps);
2100 if (lacr > vc->max_er)
2101 lacr = vc->max_er;
2102
2103 if (lacr != vc->lacr) {
2104 vc->lacr = lacr;
2105 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2106 }
2107
2108 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2109 add_timer(&est->timer);
2110
2111 out:
2112 spin_unlock_irqrestore(&vc->lock, flags);
2113 }
2114
2115 static struct rate_estimator *
2116 idt77252_init_est(struct vc_map *vc, int pcr)
2117 {
2118 struct rate_estimator *est;
2119
2120 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2121 if (!est)
2122 return NULL;
2123 est->maxcps = pcr < 0 ? -pcr : pcr;
2124 est->cps = est->maxcps;
2125 est->avcps = est->cps << 5;
2126
2127 est->interval = 2;
2128 est->ewma_log = 2;
2129 init_timer(&est->timer);
2130 est->timer.data = (unsigned long)vc;
2131 est->timer.function = idt77252_est_timer;
2132
2133 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2134 add_timer(&est->timer);
2135
2136 return est;
2137 }
2138
2139 static int
2140 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2141 struct atm_vcc *vcc, struct atm_qos *qos)
2142 {
2143 int tst_free, tst_used, tst_entries;
2144 unsigned long tmpl, modl;
2145 int tcr, tcra;
2146
2147 if ((qos->txtp.max_pcr == 0) &&
2148 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2149 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2150 card->name);
2151 return -EINVAL;
2152 }
2153
2154 tst_used = 0;
2155 tst_free = card->tst_free;
2156 if (test_bit(VCF_TX, &vc->flags))
2157 tst_used = vc->ntste;
2158 tst_free += tst_used;
2159
2160 tcr = atm_pcr_goal(&qos->txtp);
2161 tcra = tcr >= 0 ? tcr : -tcr;
2162
2163 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2164
2165 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2166 modl = tmpl % (unsigned long)card->utopia_pcr;
2167
2168 tst_entries = (int) (tmpl / card->utopia_pcr);
2169 if (tcr > 0) {
2170 if (modl > 0)
2171 tst_entries++;
2172 } else if (tcr == 0) {
2173 tst_entries = tst_free - SAR_TST_RESERVED;
2174 if (tst_entries <= 0) {
2175 printk("%s: no CBR bandwidth free.\n", card->name);
2176 return -ENOSR;
2177 }
2178 }
2179
2180 if (tst_entries == 0) {
2181 printk("%s: selected CBR bandwidth < granularity.\n",
2182 card->name);
2183 return -EINVAL;
2184 }
2185
2186 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2187 printk("%s: not enough CBR bandwidth free.\n", card->name);
2188 return -ENOSR;
2189 }
2190
2191 vc->ntste = tst_entries;
2192
2193 card->tst_free = tst_free - tst_entries;
2194 if (test_bit(VCF_TX, &vc->flags)) {
2195 if (tst_used == tst_entries)
2196 return 0;
2197
2198 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2199 card->name, tst_used, tst_entries);
2200 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2201 return 0;
2202 }
2203
2204 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2205 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2206 return 0;
2207 }
2208
2209 static int
2210 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2211 struct atm_vcc *vcc, struct atm_qos *qos)
2212 {
2213 unsigned long flags;
2214 int tcr;
2215
2216 spin_lock_irqsave(&vc->lock, flags);
2217 if (vc->estimator) {
2218 del_timer(&vc->estimator->timer);
2219 kfree(vc->estimator);
2220 vc->estimator = NULL;
2221 }
2222 spin_unlock_irqrestore(&vc->lock, flags);
2223
2224 tcr = atm_pcr_goal(&qos->txtp);
2225 if (tcr == 0)
2226 tcr = card->link_pcr;
2227
2228 vc->estimator = idt77252_init_est(vc, tcr);
2229
2230 vc->class = SCHED_UBR;
2231 vc->init_er = idt77252_rate_logindex(card, tcr);
2232 vc->lacr = vc->init_er;
2233 if (tcr < 0)
2234 vc->max_er = vc->init_er;
2235 else
2236 vc->max_er = 0xff;
2237
2238 return 0;
2239 }
2240
2241 static int
2242 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2243 struct atm_vcc *vcc, struct atm_qos *qos)
2244 {
2245 int error;
2246
2247 if (test_bit(VCF_TX, &vc->flags))
2248 return -EBUSY;
2249
2250 switch (qos->txtp.traffic_class) {
2251 case ATM_CBR:
2252 vc->class = SCHED_CBR;
2253 break;
2254
2255 case ATM_UBR:
2256 vc->class = SCHED_UBR;
2257 break;
2258
2259 case ATM_VBR:
2260 case ATM_ABR:
2261 default:
2262 return -EPROTONOSUPPORT;
2263 }
2264
2265 vc->scq = alloc_scq(card, vc->class);
2266 if (!vc->scq) {
2267 printk("%s: can't get SCQ.\n", card->name);
2268 return -ENOMEM;
2269 }
2270
2271 vc->scq->scd = get_free_scd(card, vc);
2272 if (vc->scq->scd == 0) {
2273 printk("%s: no SCD available.\n", card->name);
2274 free_scq(card, vc->scq);
2275 return -ENOMEM;
2276 }
2277
2278 fill_scd(card, vc->scq, vc->class);
2279
2280 if (set_tct(card, vc)) {
2281 printk("%s: class %d not supported.\n",
2282 card->name, qos->txtp.traffic_class);
2283
2284 card->scd2vc[vc->scd_index] = NULL;
2285 free_scq(card, vc->scq);
2286 return -EPROTONOSUPPORT;
2287 }
2288
2289 switch (vc->class) {
2290 case SCHED_CBR:
2291 error = idt77252_init_cbr(card, vc, vcc, qos);
2292 if (error) {
2293 card->scd2vc[vc->scd_index] = NULL;
2294 free_scq(card, vc->scq);
2295 return error;
2296 }
2297
2298 clear_bit(VCF_IDLE, &vc->flags);
2299 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2300 break;
2301
2302 case SCHED_UBR:
2303 error = idt77252_init_ubr(card, vc, vcc, qos);
2304 if (error) {
2305 card->scd2vc[vc->scd_index] = NULL;
2306 free_scq(card, vc->scq);
2307 return error;
2308 }
2309
2310 set_bit(VCF_IDLE, &vc->flags);
2311 break;
2312 }
2313
2314 vc->tx_vcc = vcc;
2315 set_bit(VCF_TX, &vc->flags);
2316 return 0;
2317 }
2318
2319 static int
2320 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2321 struct atm_vcc *vcc, struct atm_qos *qos)
2322 {
2323 unsigned long flags;
2324 unsigned long addr;
2325 u32 rcte = 0;
2326
2327 if (test_bit(VCF_RX, &vc->flags))
2328 return -EBUSY;
2329
2330 vc->rx_vcc = vcc;
2331 set_bit(VCF_RX, &vc->flags);
2332
2333 if ((vcc->vci == 3) || (vcc->vci == 4))
2334 return 0;
2335
2336 flush_rx_pool(card, &vc->rcv.rx_pool);
2337
2338 rcte |= SAR_RCTE_CONNECTOPEN;
2339 rcte |= SAR_RCTE_RAWCELLINTEN;
2340
2341 switch (qos->aal) {
2342 case ATM_AAL0:
2343 rcte |= SAR_RCTE_RCQ;
2344 break;
2345 case ATM_AAL1:
2346 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2347 break;
2348 case ATM_AAL34:
2349 rcte |= SAR_RCTE_AAL34;
2350 break;
2351 case ATM_AAL5:
2352 rcte |= SAR_RCTE_AAL5;
2353 break;
2354 default:
2355 rcte |= SAR_RCTE_RCQ;
2356 break;
2357 }
2358
2359 if (qos->aal != ATM_AAL5)
2360 rcte |= SAR_RCTE_FBP_1;
2361 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2362 rcte |= SAR_RCTE_FBP_3;
2363 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2364 rcte |= SAR_RCTE_FBP_2;
2365 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2366 rcte |= SAR_RCTE_FBP_1;
2367 else
2368 rcte |= SAR_RCTE_FBP_01;
2369
2370 addr = card->rct_base + (vc->index << 2);
2371
2372 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2373 write_sram(card, addr, rcte);
2374
2375 spin_lock_irqsave(&card->cmd_lock, flags);
2376 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2377 waitfor_idle(card);
2378 spin_unlock_irqrestore(&card->cmd_lock, flags);
2379
2380 return 0;
2381 }
2382
2383 static int
2384 idt77252_open(struct atm_vcc *vcc)
2385 {
2386 struct atm_dev *dev = vcc->dev;
2387 struct idt77252_dev *card = dev->dev_data;
2388 struct vc_map *vc;
2389 unsigned int index;
2390 unsigned int inuse;
2391 int error;
2392 int vci = vcc->vci;
2393 short vpi = vcc->vpi;
2394
2395 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2396 return 0;
2397
2398 if (vpi >= (1 << card->vpibits)) {
2399 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2400 return -EINVAL;
2401 }
2402
2403 if (vci >= (1 << card->vcibits)) {
2404 printk("%s: unsupported VCI: %d\n", card->name, vci);
2405 return -EINVAL;
2406 }
2407
2408 set_bit(ATM_VF_ADDR, &vcc->flags);
2409
2410 mutex_lock(&card->mutex);
2411
2412 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2413
2414 switch (vcc->qos.aal) {
2415 case ATM_AAL0:
2416 case ATM_AAL1:
2417 case ATM_AAL5:
2418 break;
2419 default:
2420 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2421 mutex_unlock(&card->mutex);
2422 return -EPROTONOSUPPORT;
2423 }
2424
2425 index = VPCI2VC(card, vpi, vci);
2426 if (!card->vcs[index]) {
2427 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2428 if (!card->vcs[index]) {
2429 printk("%s: can't alloc vc in open()\n", card->name);
2430 mutex_unlock(&card->mutex);
2431 return -ENOMEM;
2432 }
2433 card->vcs[index]->card = card;
2434 card->vcs[index]->index = index;
2435
2436 spin_lock_init(&card->vcs[index]->lock);
2437 }
2438 vc = card->vcs[index];
2439
2440 vcc->dev_data = vc;
2441
2442 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2443 card->name, vc->index, vcc->vpi, vcc->vci,
2444 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2445 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2446 vcc->qos.rxtp.max_sdu);
2447
2448 inuse = 0;
2449 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2450 test_bit(VCF_TX, &vc->flags))
2451 inuse = 1;
2452 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2453 test_bit(VCF_RX, &vc->flags))
2454 inuse += 2;
2455
2456 if (inuse) {
2457 printk("%s: %s vci already in use.\n", card->name,
2458 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2459 mutex_unlock(&card->mutex);
2460 return -EADDRINUSE;
2461 }
2462
2463 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2464 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2465 if (error) {
2466 mutex_unlock(&card->mutex);
2467 return error;
2468 }
2469 }
2470
2471 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2472 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2473 if (error) {
2474 mutex_unlock(&card->mutex);
2475 return error;
2476 }
2477 }
2478
2479 set_bit(ATM_VF_READY, &vcc->flags);
2480
2481 mutex_unlock(&card->mutex);
2482 return 0;
2483 }
2484
2485 static void
2486 idt77252_close(struct atm_vcc *vcc)
2487 {
2488 struct atm_dev *dev = vcc->dev;
2489 struct idt77252_dev *card = dev->dev_data;
2490 struct vc_map *vc = vcc->dev_data;
2491 unsigned long flags;
2492 unsigned long addr;
2493 unsigned long timeout;
2494
2495 mutex_lock(&card->mutex);
2496
2497 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2498 card->name, vc->index, vcc->vpi, vcc->vci);
2499
2500 clear_bit(ATM_VF_READY, &vcc->flags);
2501
2502 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2503
2504 spin_lock_irqsave(&vc->lock, flags);
2505 clear_bit(VCF_RX, &vc->flags);
2506 vc->rx_vcc = NULL;
2507 spin_unlock_irqrestore(&vc->lock, flags);
2508
2509 if ((vcc->vci == 3) || (vcc->vci == 4))
2510 goto done;
2511
2512 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2513
2514 spin_lock_irqsave(&card->cmd_lock, flags);
2515 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2516 waitfor_idle(card);
2517 spin_unlock_irqrestore(&card->cmd_lock, flags);
2518
2519 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2520 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2521 card->name);
2522
2523 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2524 }
2525 }
2526
2527 done:
2528 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2529
2530 spin_lock_irqsave(&vc->lock, flags);
2531 clear_bit(VCF_TX, &vc->flags);
2532 clear_bit(VCF_IDLE, &vc->flags);
2533 clear_bit(VCF_RSV, &vc->flags);
2534 vc->tx_vcc = NULL;
2535
2536 if (vc->estimator) {
2537 del_timer(&vc->estimator->timer);
2538 kfree(vc->estimator);
2539 vc->estimator = NULL;
2540 }
2541 spin_unlock_irqrestore(&vc->lock, flags);
2542
2543 timeout = 5 * 1000;
2544 while (atomic_read(&vc->scq->used) > 0) {
2545 timeout = msleep_interruptible(timeout);
2546 if (!timeout)
2547 break;
2548 }
2549 if (!timeout)
2550 printk("%s: SCQ drain timeout: %u used\n",
2551 card->name, atomic_read(&vc->scq->used));
2552
2553 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2554 clear_scd(card, vc->scq, vc->class);
2555
2556 if (vc->class == SCHED_CBR) {
2557 clear_tst(card, vc);
2558 card->tst_free += vc->ntste;
2559 vc->ntste = 0;
2560 }
2561
2562 card->scd2vc[vc->scd_index] = NULL;
2563 free_scq(card, vc->scq);
2564 }
2565
2566 mutex_unlock(&card->mutex);
2567 }
2568
2569 static int
2570 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2571 {
2572 struct atm_dev *dev = vcc->dev;
2573 struct idt77252_dev *card = dev->dev_data;
2574 struct vc_map *vc = vcc->dev_data;
2575 int error = 0;
2576
2577 mutex_lock(&card->mutex);
2578
2579 if (qos->txtp.traffic_class != ATM_NONE) {
2580 if (!test_bit(VCF_TX, &vc->flags)) {
2581 error = idt77252_init_tx(card, vc, vcc, qos);
2582 if (error)
2583 goto out;
2584 } else {
2585 switch (qos->txtp.traffic_class) {
2586 case ATM_CBR:
2587 error = idt77252_init_cbr(card, vc, vcc, qos);
2588 if (error)
2589 goto out;
2590 break;
2591
2592 case ATM_UBR:
2593 error = idt77252_init_ubr(card, vc, vcc, qos);
2594 if (error)
2595 goto out;
2596
2597 if (!test_bit(VCF_IDLE, &vc->flags)) {
2598 writel(TCMDQ_LACR | (vc->lacr << 16) |
2599 vc->index, SAR_REG_TCMDQ);
2600 }
2601 break;
2602
2603 case ATM_VBR:
2604 case ATM_ABR:
2605 error = -EOPNOTSUPP;
2606 goto out;
2607 }
2608 }
2609 }
2610
2611 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2612 !test_bit(VCF_RX, &vc->flags)) {
2613 error = idt77252_init_rx(card, vc, vcc, qos);
2614 if (error)
2615 goto out;
2616 }
2617
2618 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2619
2620 set_bit(ATM_VF_HASQOS, &vcc->flags);
2621
2622 out:
2623 mutex_unlock(&card->mutex);
2624 return error;
2625 }
2626
2627 static int
2628 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2629 {
2630 struct idt77252_dev *card = dev->dev_data;
2631 int i, left;
2632
2633 left = (int) *pos;
2634 if (!left--)
2635 return sprintf(page, "IDT77252 Interrupts:\n");
2636 if (!left--)
2637 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2638 if (!left--)
2639 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2640 if (!left--)
2641 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2642 if (!left--)
2643 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2644 if (!left--)
2645 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2646 if (!left--)
2647 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2648 if (!left--)
2649 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2650 if (!left--)
2651 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2652 if (!left--)
2653 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2654 if (!left--)
2655 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2656 if (!left--)
2657 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2658 if (!left--)
2659 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2660 if (!left--)
2661 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2662 if (!left--)
2663 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2664
2665 for (i = 0; i < card->tct_size; i++) {
2666 unsigned long tct;
2667 struct atm_vcc *vcc;
2668 struct vc_map *vc;
2669 char *p;
2670
2671 vc = card->vcs[i];
2672 if (!vc)
2673 continue;
2674
2675 vcc = NULL;
2676 if (vc->tx_vcc)
2677 vcc = vc->tx_vcc;
2678 if (!vcc)
2679 continue;
2680 if (left--)
2681 continue;
2682
2683 p = page;
2684 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2685 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2686
2687 for (i = 0; i < 8; i++)
2688 p += sprintf(p, " %08x", read_sram(card, tct + i));
2689 p += sprintf(p, "\n");
2690 return p - page;
2691 }
2692 return 0;
2693 }
2694
2695 /*****************************************************************************/
2696 /* */
2697 /* Interrupt handler */
2698 /* */
2699 /*****************************************************************************/
2700
2701 static void
2702 idt77252_collect_stat(struct idt77252_dev *card)
2703 {
2704 u32 cdc, vpec, icc;
2705
2706 cdc = readl(SAR_REG_CDC);
2707 vpec = readl(SAR_REG_VPEC);
2708 icc = readl(SAR_REG_ICC);
2709
2710 #ifdef NOTDEF
2711 printk("%s:", card->name);
2712
2713 if (cdc & 0x7f0000) {
2714 char *s = "";
2715
2716 printk(" [");
2717 if (cdc & (1 << 22)) {
2718 printk("%sRM ID", s);
2719 s = " | ";
2720 }
2721 if (cdc & (1 << 21)) {
2722 printk("%sCON TAB", s);
2723 s = " | ";
2724 }
2725 if (cdc & (1 << 20)) {
2726 printk("%sNO FB", s);
2727 s = " | ";
2728 }
2729 if (cdc & (1 << 19)) {
2730 printk("%sOAM CRC", s);
2731 s = " | ";
2732 }
2733 if (cdc & (1 << 18)) {
2734 printk("%sRM CRC", s);
2735 s = " | ";
2736 }
2737 if (cdc & (1 << 17)) {
2738 printk("%sRM FIFO", s);
2739 s = " | ";
2740 }
2741 if (cdc & (1 << 16)) {
2742 printk("%sRX FIFO", s);
2743 s = " | ";
2744 }
2745 printk("]");
2746 }
2747
2748 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2749 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2750 #endif
2751 }
2752
2753 static irqreturn_t
2754 idt77252_interrupt(int irq, void *dev_id)
2755 {
2756 struct idt77252_dev *card = dev_id;
2757 u32 stat;
2758
2759 stat = readl(SAR_REG_STAT) & 0xffff;
2760 if (!stat) /* no interrupt for us */
2761 return IRQ_NONE;
2762
2763 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2764 printk("%s: Re-entering irq_handler()\n", card->name);
2765 goto out;
2766 }
2767
2768 writel(stat, SAR_REG_STAT); /* reset interrupt */
2769
2770 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2771 INTPRINTK("%s: TSIF\n", card->name);
2772 card->irqstat[15]++;
2773 idt77252_tx(card);
2774 }
2775 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2776 INTPRINTK("%s: TXICP\n", card->name);
2777 card->irqstat[14]++;
2778 #ifdef CONFIG_ATM_IDT77252_DEBUG
2779 idt77252_tx_dump(card);
2780 #endif
2781 }
2782 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2783 INTPRINTK("%s: TSQF\n", card->name);
2784 card->irqstat[12]++;
2785 idt77252_tx(card);
2786 }
2787 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2788 INTPRINTK("%s: TMROF\n", card->name);
2789 card->irqstat[11]++;
2790 idt77252_collect_stat(card);
2791 }
2792
2793 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2794 INTPRINTK("%s: EPDU\n", card->name);
2795 card->irqstat[5]++;
2796 idt77252_rx(card);
2797 }
2798 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2799 INTPRINTK("%s: RSQAF\n", card->name);
2800 card->irqstat[1]++;
2801 idt77252_rx(card);
2802 }
2803 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2804 INTPRINTK("%s: RSQF\n", card->name);
2805 card->irqstat[6]++;
2806 idt77252_rx(card);
2807 }
2808 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2809 INTPRINTK("%s: RAWCF\n", card->name);
2810 card->irqstat[4]++;
2811 idt77252_rx_raw(card);
2812 }
2813
2814 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2815 INTPRINTK("%s: PHYI", card->name);
2816 card->irqstat[10]++;
2817 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2818 card->atmdev->phy->interrupt(card->atmdev);
2819 }
2820
2821 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2822 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2823
2824 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2825
2826 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2827
2828 if (stat & SAR_STAT_FBQ0A)
2829 card->irqstat[2]++;
2830 if (stat & SAR_STAT_FBQ1A)
2831 card->irqstat[3]++;
2832 if (stat & SAR_STAT_FBQ2A)
2833 card->irqstat[7]++;
2834 if (stat & SAR_STAT_FBQ3A)
2835 card->irqstat[8]++;
2836
2837 schedule_work(&card->tqueue);
2838 }
2839
2840 out:
2841 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2842 return IRQ_HANDLED;
2843 }
2844
2845 static void
2846 idt77252_softint(struct work_struct *work)
2847 {
2848 struct idt77252_dev *card =
2849 container_of(work, struct idt77252_dev, tqueue);
2850 u32 stat;
2851 int done;
2852
2853 for (done = 1; ; done = 1) {
2854 stat = readl(SAR_REG_STAT) >> 16;
2855
2856 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2857 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2858 done = 0;
2859 }
2860
2861 stat >>= 4;
2862 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2863 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2864 done = 0;
2865 }
2866
2867 stat >>= 4;
2868 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2869 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2870 done = 0;
2871 }
2872
2873 stat >>= 4;
2874 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2875 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2876 done = 0;
2877 }
2878
2879 if (done)
2880 break;
2881 }
2882
2883 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2884 }
2885
2886
2887 static int
2888 open_card_oam(struct idt77252_dev *card)
2889 {
2890 unsigned long flags;
2891 unsigned long addr;
2892 struct vc_map *vc;
2893 int vpi, vci;
2894 int index;
2895 u32 rcte;
2896
2897 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2898 for (vci = 3; vci < 5; vci++) {
2899 index = VPCI2VC(card, vpi, vci);
2900
2901 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2902 if (!vc) {
2903 printk("%s: can't alloc vc\n", card->name);
2904 return -ENOMEM;
2905 }
2906 vc->index = index;
2907 card->vcs[index] = vc;
2908
2909 flush_rx_pool(card, &vc->rcv.rx_pool);
2910
2911 rcte = SAR_RCTE_CONNECTOPEN |
2912 SAR_RCTE_RAWCELLINTEN |
2913 SAR_RCTE_RCQ |
2914 SAR_RCTE_FBP_1;
2915
2916 addr = card->rct_base + (vc->index << 2);
2917 write_sram(card, addr, rcte);
2918
2919 spin_lock_irqsave(&card->cmd_lock, flags);
2920 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2921 SAR_REG_CMD);
2922 waitfor_idle(card);
2923 spin_unlock_irqrestore(&card->cmd_lock, flags);
2924 }
2925 }
2926
2927 return 0;
2928 }
2929
2930 static void
2931 close_card_oam(struct idt77252_dev *card)
2932 {
2933 unsigned long flags;
2934 unsigned long addr;
2935 struct vc_map *vc;
2936 int vpi, vci;
2937 int index;
2938
2939 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2940 for (vci = 3; vci < 5; vci++) {
2941 index = VPCI2VC(card, vpi, vci);
2942 vc = card->vcs[index];
2943
2944 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2945
2946 spin_lock_irqsave(&card->cmd_lock, flags);
2947 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2948 SAR_REG_CMD);
2949 waitfor_idle(card);
2950 spin_unlock_irqrestore(&card->cmd_lock, flags);
2951
2952 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) {
2953 DPRINTK("%s: closing a VC "
2954 "with pending rx buffers.\n",
2955 card->name);
2956
2957 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2958 }
2959 }
2960 }
2961 }
2962
2963 static int
2964 open_card_ubr0(struct idt77252_dev *card)
2965 {
2966 struct vc_map *vc;
2967
2968 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2969 if (!vc) {
2970 printk("%s: can't alloc vc\n", card->name);
2971 return -ENOMEM;
2972 }
2973 card->vcs[0] = vc;
2974 vc->class = SCHED_UBR0;
2975
2976 vc->scq = alloc_scq(card, vc->class);
2977 if (!vc->scq) {
2978 printk("%s: can't get SCQ.\n", card->name);
2979 return -ENOMEM;
2980 }
2981
2982 card->scd2vc[0] = vc;
2983 vc->scd_index = 0;
2984 vc->scq->scd = card->scd_base;
2985
2986 fill_scd(card, vc->scq, vc->class);
2987
2988 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
2989 write_sram(card, card->tct_base + 1, 0);
2990 write_sram(card, card->tct_base + 2, 0);
2991 write_sram(card, card->tct_base + 3, 0);
2992 write_sram(card, card->tct_base + 4, 0);
2993 write_sram(card, card->tct_base + 5, 0);
2994 write_sram(card, card->tct_base + 6, 0);
2995 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
2996
2997 clear_bit(VCF_IDLE, &vc->flags);
2998 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
2999 return 0;
3000 }
3001
3002 static int
3003 idt77252_dev_open(struct idt77252_dev *card)
3004 {
3005 u32 conf;
3006
3007 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3008 printk("%s: SAR not yet initialized.\n", card->name);
3009 return -1;
3010 }
3011
3012 conf = SAR_CFG_RXPTH| /* enable receive path */
3013 SAR_RX_DELAY | /* interrupt on complete PDU */
3014 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3015 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3016 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3017 SAR_CFG_FBIE | /* interrupt on low free buffers */
3018 SAR_CFG_TXEN | /* transmit operation enable */
3019 SAR_CFG_TXINT | /* interrupt on transmit status */
3020 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3021 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3022 SAR_CFG_PHYIE /* enable PHY interrupts */
3023 ;
3024
3025 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3026 /* Test RAW cell receive. */
3027 conf |= SAR_CFG_VPECA;
3028 #endif
3029
3030 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3031
3032 if (open_card_oam(card)) {
3033 printk("%s: Error initializing OAM.\n", card->name);
3034 return -1;
3035 }
3036
3037 if (open_card_ubr0(card)) {
3038 printk("%s: Error initializing UBR0.\n", card->name);
3039 return -1;
3040 }
3041
3042 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3043 return 0;
3044 }
3045
3046 static void idt77252_dev_close(struct atm_dev *dev)
3047 {
3048 struct idt77252_dev *card = dev->dev_data;
3049 u32 conf;
3050
3051 close_card_oam(card);
3052
3053 conf = SAR_CFG_RXPTH | /* enable receive path */
3054 SAR_RX_DELAY | /* interrupt on complete PDU */
3055 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3056 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3057 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3058 SAR_CFG_FBIE | /* interrupt on low free buffers */
3059 SAR_CFG_TXEN | /* transmit operation enable */
3060 SAR_CFG_TXINT | /* interrupt on transmit status */
3061 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3062 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3063 ;
3064
3065 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3066
3067 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3068 }
3069
3070
3071 /*****************************************************************************/
3072 /* */
3073 /* Initialisation and Deinitialization of IDT77252 */
3074 /* */
3075 /*****************************************************************************/
3076
3077
3078 static void
3079 deinit_card(struct idt77252_dev *card)
3080 {
3081 struct sk_buff *skb;
3082 int i, j;
3083
3084 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3085 printk("%s: SAR not yet initialized.\n", card->name);
3086 return;
3087 }
3088 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3089
3090 writel(0, SAR_REG_CFG);
3091
3092 if (card->atmdev)
3093 atm_dev_deregister(card->atmdev);
3094
3095 for (i = 0; i < 4; i++) {
3096 for (j = 0; j < FBQ_SIZE; j++) {
3097 skb = card->sbpool[i].skb[j];
3098 if (skb) {
3099 pci_unmap_single(card->pcidev,
3100 IDT77252_PRV_PADDR(skb),
3101 (skb_end_pointer(skb) -
3102 skb->data),
3103 PCI_DMA_FROMDEVICE);
3104 card->sbpool[i].skb[j] = NULL;
3105 dev_kfree_skb(skb);
3106 }
3107 }
3108 }
3109
3110 vfree(card->soft_tst);
3111
3112 vfree(card->scd2vc);
3113
3114 vfree(card->vcs);
3115
3116 if (card->raw_cell_hnd) {
3117 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3118 card->raw_cell_hnd, card->raw_cell_paddr);
3119 }
3120
3121 if (card->rsq.base) {
3122 DIPRINTK("%s: Release RSQ ...\n", card->name);
3123 deinit_rsq(card);
3124 }
3125
3126 if (card->tsq.base) {
3127 DIPRINTK("%s: Release TSQ ...\n", card->name);
3128 deinit_tsq(card);
3129 }
3130
3131 DIPRINTK("idt77252: Release IRQ.\n");
3132 free_irq(card->pcidev->irq, card);
3133
3134 for (i = 0; i < 4; i++) {
3135 if (card->fbq[i])
3136 iounmap(card->fbq[i]);
3137 }
3138
3139 if (card->membase)
3140 iounmap(card->membase);
3141
3142 clear_bit(IDT77252_BIT_INIT, &card->flags);
3143 DIPRINTK("%s: Card deinitialized.\n", card->name);
3144 }
3145
3146
3147 static int __devinit
3148 init_sram(struct idt77252_dev *card)
3149 {
3150 int i;
3151
3152 for (i = 0; i < card->sramsize; i += 4)
3153 write_sram(card, (i >> 2), 0);
3154
3155 /* set SRAM layout for THIS card */
3156 if (card->sramsize == (512 * 1024)) {
3157 card->tct_base = SAR_SRAM_TCT_128_BASE;
3158 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3159 / SAR_SRAM_TCT_SIZE;
3160 card->rct_base = SAR_SRAM_RCT_128_BASE;
3161 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3162 / SAR_SRAM_RCT_SIZE;
3163 card->rt_base = SAR_SRAM_RT_128_BASE;
3164 card->scd_base = SAR_SRAM_SCD_128_BASE;
3165 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3166 / SAR_SRAM_SCD_SIZE;
3167 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3168 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3169 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3170 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3171 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3172 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3173 card->fifo_size = SAR_RXFD_SIZE_32K;
3174 } else {
3175 card->tct_base = SAR_SRAM_TCT_32_BASE;
3176 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3177 / SAR_SRAM_TCT_SIZE;
3178 card->rct_base = SAR_SRAM_RCT_32_BASE;
3179 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3180 / SAR_SRAM_RCT_SIZE;
3181 card->rt_base = SAR_SRAM_RT_32_BASE;
3182 card->scd_base = SAR_SRAM_SCD_32_BASE;
3183 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3184 / SAR_SRAM_SCD_SIZE;
3185 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3186 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3187 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3188 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3189 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3190 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3191 card->fifo_size = SAR_RXFD_SIZE_4K;
3192 }
3193
3194 /* Initialize TCT */
3195 for (i = 0; i < card->tct_size; i++) {
3196 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3197 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3198 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3199 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3200 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3201 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3202 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3203 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3204 }
3205
3206 /* Initialize RCT */
3207 for (i = 0; i < card->rct_size; i++) {
3208 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3209 (u32) SAR_RCTE_RAWCELLINTEN);
3210 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3211 (u32) 0);
3212 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3213 (u32) 0);
3214 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3215 (u32) 0xffffffff);
3216 }
3217
3218 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3219 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3220 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3221 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3222 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3223 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3224 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3225 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3226
3227 /* Initialize rate table */
3228 for (i = 0; i < 256; i++) {
3229 write_sram(card, card->rt_base + i, log_to_rate[i]);
3230 }
3231
3232 for (i = 0; i < 128; i++) {
3233 unsigned int tmp;
3234
3235 tmp = rate_to_log[(i << 2) + 0] << 0;
3236 tmp |= rate_to_log[(i << 2) + 1] << 8;
3237 tmp |= rate_to_log[(i << 2) + 2] << 16;
3238 tmp |= rate_to_log[(i << 2) + 3] << 24;
3239 write_sram(card, card->rt_base + 256 + i, tmp);
3240 }
3241
3242
3243 IPRINTK("%s: initialize rate table ...\n", card->name);
3244 writel(card->rt_base << 2, SAR_REG_RTBL);
3245
3246 /* Initialize TSTs */
3247 IPRINTK("%s: initialize TST ...\n", card->name);
3248 card->tst_free = card->tst_size - 2; /* last two are jumps */
3249
3250 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3251 write_sram(card, i, TSTE_OPC_VAR);
3252 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3253 idt77252_sram_write_errors = 1;
3254 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3255 idt77252_sram_write_errors = 0;
3256 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3257 write_sram(card, i, TSTE_OPC_VAR);
3258 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3259 idt77252_sram_write_errors = 1;
3260 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3261 idt77252_sram_write_errors = 0;
3262
3263 card->tst_index = 0;
3264 writel(card->tst[0] << 2, SAR_REG_TSTB);
3265
3266 /* Initialize ABRSTD and Receive FIFO */
3267 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3268 writel(card->abrst_size | (card->abrst_base << 2),
3269 SAR_REG_ABRSTD);
3270
3271 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3272 writel(card->fifo_size | (card->fifo_base << 2),
3273 SAR_REG_RXFD);
3274
3275 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3276 return 0;
3277 }
3278
3279 static int __devinit
3280 init_card(struct atm_dev *dev)
3281 {
3282 struct idt77252_dev *card = dev->dev_data;
3283 struct pci_dev *pcidev = card->pcidev;
3284 unsigned long tmpl, modl;
3285 unsigned int linkrate, rsvdcr;
3286 unsigned int tst_entries;
3287 struct net_device *tmp;
3288 char tname[10];
3289
3290 u32 size;
3291 u_char pci_byte;
3292 u32 conf;
3293 int i, k;
3294
3295 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3296 printk("Error: SAR already initialized.\n");
3297 return -1;
3298 }
3299
3300 /*****************************************************************/
3301 /* P C I C O N F I G U R A T I O N */
3302 /*****************************************************************/
3303
3304 /* Set PCI Retry-Timeout and TRDY timeout */
3305 IPRINTK("%s: Checking PCI retries.\n", card->name);
3306 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3307 printk("%s: can't read PCI retry timeout.\n", card->name);
3308 deinit_card(card);
3309 return -1;
3310 }
3311 if (pci_byte != 0) {
3312 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3313 card->name, pci_byte);
3314 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3315 printk("%s: can't set PCI retry timeout.\n",
3316 card->name);
3317 deinit_card(card);
3318 return -1;
3319 }
3320 }
3321 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3322 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3323 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3324 deinit_card(card);
3325 return -1;
3326 }
3327 if (pci_byte != 0) {
3328 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3329 card->name, pci_byte);
3330 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3331 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3332 deinit_card(card);
3333 return -1;
3334 }
3335 }
3336 /* Reset Timer register */
3337 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3338 printk("%s: resetting timer overflow.\n", card->name);
3339 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3340 }
3341 IPRINTK("%s: Request IRQ ... ", card->name);
3342 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED,
3343 card->name, card) != 0) {
3344 printk("%s: can't allocate IRQ.\n", card->name);
3345 deinit_card(card);
3346 return -1;
3347 }
3348 IPRINTK("got %d.\n", pcidev->irq);
3349
3350 /*****************************************************************/
3351 /* C H E C K A N D I N I T S R A M */
3352 /*****************************************************************/
3353
3354 IPRINTK("%s: Initializing SRAM\n", card->name);
3355
3356 /* preset size of connecton table, so that init_sram() knows about it */
3357 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3358 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3359 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3360 #ifndef ATM_IDT77252_SEND_IDLE
3361 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3362 #endif
3363 0;
3364
3365 if (card->sramsize == (512 * 1024))
3366 conf |= SAR_CFG_CNTBL_1k;
3367 else
3368 conf |= SAR_CFG_CNTBL_512;
3369
3370 switch (vpibits) {
3371 case 0:
3372 conf |= SAR_CFG_VPVCS_0;
3373 break;
3374 default:
3375 case 1:
3376 conf |= SAR_CFG_VPVCS_1;
3377 break;
3378 case 2:
3379 conf |= SAR_CFG_VPVCS_2;
3380 break;
3381 case 8:
3382 conf |= SAR_CFG_VPVCS_8;
3383 break;
3384 }
3385
3386 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3387
3388 if (init_sram(card) < 0)
3389 return -1;
3390
3391 /********************************************************************/
3392 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3393 /********************************************************************/
3394 /* Initialize TSQ */
3395 if (0 != init_tsq(card)) {
3396 deinit_card(card);
3397 return -1;
3398 }
3399 /* Initialize RSQ */
3400 if (0 != init_rsq(card)) {
3401 deinit_card(card);
3402 return -1;
3403 }
3404
3405 card->vpibits = vpibits;
3406 if (card->sramsize == (512 * 1024)) {
3407 card->vcibits = 10 - card->vpibits;
3408 } else {
3409 card->vcibits = 9 - card->vpibits;
3410 }
3411
3412 card->vcimask = 0;
3413 for (k = 0, i = 1; k < card->vcibits; k++) {
3414 card->vcimask |= i;
3415 i <<= 1;
3416 }
3417
3418 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3419 writel(0, SAR_REG_VPM);
3420
3421 /* Little Endian Order */
3422 writel(0, SAR_REG_GP);
3423
3424 /* Initialize RAW Cell Handle Register */
3425 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3426 &card->raw_cell_paddr);
3427 if (!card->raw_cell_hnd) {
3428 printk("%s: memory allocation failure.\n", card->name);
3429 deinit_card(card);
3430 return -1;
3431 }
3432 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3433 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3434 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3435 card->raw_cell_hnd);
3436
3437 size = sizeof(struct vc_map *) * card->tct_size;
3438 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3439 if (NULL == (card->vcs = vmalloc(size))) {
3440 printk("%s: memory allocation failure.\n", card->name);
3441 deinit_card(card);
3442 return -1;
3443 }
3444 memset(card->vcs, 0, size);
3445
3446 size = sizeof(struct vc_map *) * card->scd_size;
3447 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3448 card->name, size);
3449 if (NULL == (card->scd2vc = vmalloc(size))) {
3450 printk("%s: memory allocation failure.\n", card->name);
3451 deinit_card(card);
3452 return -1;
3453 }
3454 memset(card->scd2vc, 0, size);
3455
3456 size = sizeof(struct tst_info) * (card->tst_size - 2);
3457 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3458 card->name, size);
3459 if (NULL == (card->soft_tst = vmalloc(size))) {
3460 printk("%s: memory allocation failure.\n", card->name);
3461 deinit_card(card);
3462 return -1;
3463 }
3464 for (i = 0; i < card->tst_size - 2; i++) {
3465 card->soft_tst[i].tste = TSTE_OPC_VAR;
3466 card->soft_tst[i].vc = NULL;
3467 }
3468
3469 if (dev->phy == NULL) {
3470 printk("%s: No LT device defined.\n", card->name);
3471 deinit_card(card);
3472 return -1;
3473 }
3474 if (dev->phy->ioctl == NULL) {
3475 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3476 deinit_card(card);
3477 return -1;
3478 }
3479
3480 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3481 /*
3482 * this is a jhs hack to get around special functionality in the
3483 * phy driver for the atecom hardware; the functionality doesn't
3484 * exist in the linux atm suni driver
3485 *
3486 * it isn't the right way to do things, but as the guy from NIST
3487 * said, talking about their measurement of the fine structure
3488 * constant, "it's good enough for government work."
3489 */
3490 linkrate = 149760000;
3491 #endif
3492
3493 card->link_pcr = (linkrate / 8 / 53);
3494 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3495 card->name, linkrate, card->link_pcr);
3496
3497 #ifdef ATM_IDT77252_SEND_IDLE
3498 card->utopia_pcr = card->link_pcr;
3499 #else
3500 card->utopia_pcr = (160000000 / 8 / 54);
3501 #endif
3502
3503 rsvdcr = 0;
3504 if (card->utopia_pcr > card->link_pcr)
3505 rsvdcr = card->utopia_pcr - card->link_pcr;
3506
3507 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3508 modl = tmpl % (unsigned long)card->utopia_pcr;
3509 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3510 if (modl)
3511 tst_entries++;
3512 card->tst_free -= tst_entries;
3513 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3514
3515 #ifdef HAVE_EEPROM
3516 idt77252_eeprom_init(card);
3517 printk("%s: EEPROM: %02x:", card->name,
3518 idt77252_eeprom_read_status(card));
3519
3520 for (i = 0; i < 0x80; i++) {
3521 printk(" %02x",
3522 idt77252_eeprom_read_byte(card, i)
3523 );
3524 }
3525 printk("\n");
3526 #endif /* HAVE_EEPROM */
3527
3528 sprintf(tname, "eth%d", card->index);
3529 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
3530 if (tmp) {
3531 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3532
3533 printk("%s: ESI %pM\n", card->name, card->atmdev->esi);
3534 }
3535
3536 /* Set Maximum Deficit Count for now. */
3537 writel(0xffff, SAR_REG_MDFCT);
3538
3539 set_bit(IDT77252_BIT_INIT, &card->flags);
3540
3541 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3542 return 0;
3543 }
3544
3545
3546 /*****************************************************************************/
3547 /* */
3548 /* Probing of IDT77252 ABR SAR */
3549 /* */
3550 /*****************************************************************************/
3551
3552
3553 static int __devinit
3554 idt77252_preset(struct idt77252_dev *card)
3555 {
3556 u16 pci_command;
3557
3558 /*****************************************************************/
3559 /* P C I C O N F I G U R A T I O N */
3560 /*****************************************************************/
3561
3562 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3563 card->name);
3564 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3565 printk("%s: can't read PCI_COMMAND.\n", card->name);
3566 deinit_card(card);
3567 return -1;
3568 }
3569 if (!(pci_command & PCI_COMMAND_IO)) {
3570 printk("%s: PCI_COMMAND: %04x (???)\n",
3571 card->name, pci_command);
3572 deinit_card(card);
3573 return (-1);
3574 }
3575 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3576 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3577 printk("%s: can't write PCI_COMMAND.\n", card->name);
3578 deinit_card(card);
3579 return -1;
3580 }
3581 /*****************************************************************/
3582 /* G E N E R I C R E S E T */
3583 /*****************************************************************/
3584
3585 /* Software reset */
3586 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3587 mdelay(1);
3588 writel(0, SAR_REG_CFG);
3589
3590 IPRINTK("%s: Software resetted.\n", card->name);
3591 return 0;
3592 }
3593
3594
3595 static unsigned long __devinit
3596 probe_sram(struct idt77252_dev *card)
3597 {
3598 u32 data, addr;
3599
3600 writel(0, SAR_REG_DR0);
3601 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3602
3603 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3604 writel(ATM_POISON, SAR_REG_DR0);
3605 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3606
3607 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3608 data = readl(SAR_REG_DR0);
3609
3610 if (data != 0)
3611 break;
3612 }
3613
3614 return addr * sizeof(u32);
3615 }
3616
3617 static int __devinit
3618 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3619 {
3620 static struct idt77252_dev **last = &idt77252_chain;
3621 static int index = 0;
3622
3623 unsigned long membase, srambase;
3624 struct idt77252_dev *card;
3625 struct atm_dev *dev;
3626 int i, err;
3627
3628
3629 if ((err = pci_enable_device(pcidev))) {
3630 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3631 return err;
3632 }
3633
3634 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3635 if (!card) {
3636 printk("idt77252-%d: can't allocate private data\n", index);
3637 err = -ENOMEM;
3638 goto err_out_disable_pdev;
3639 }
3640 card->revision = pcidev->revision;
3641 card->index = index;
3642 card->pcidev = pcidev;
3643 sprintf(card->name, "idt77252-%d", card->index);
3644
3645 INIT_WORK(&card->tqueue, idt77252_softint);
3646
3647 membase = pci_resource_start(pcidev, 1);
3648 srambase = pci_resource_start(pcidev, 2);
3649
3650 mutex_init(&card->mutex);
3651 spin_lock_init(&card->cmd_lock);
3652 spin_lock_init(&card->tst_lock);
3653
3654 init_timer(&card->tst_timer);
3655 card->tst_timer.data = (unsigned long)card;
3656 card->tst_timer.function = tst_timer;
3657
3658 /* Do the I/O remapping... */
3659 card->membase = ioremap(membase, 1024);
3660 if (!card->membase) {
3661 printk("%s: can't ioremap() membase\n", card->name);
3662 err = -EIO;
3663 goto err_out_free_card;
3664 }
3665
3666 if (idt77252_preset(card)) {
3667 printk("%s: preset failed\n", card->name);
3668 err = -EIO;
3669 goto err_out_iounmap;
3670 }
3671
3672 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3673 if (!dev) {
3674 printk("%s: can't register atm device\n", card->name);
3675 err = -EIO;
3676 goto err_out_iounmap;
3677 }
3678 dev->dev_data = card;
3679 card->atmdev = dev;
3680
3681 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3682 suni_init(dev);
3683 if (!dev->phy) {
3684 printk("%s: can't init SUNI\n", card->name);
3685 err = -EIO;
3686 goto err_out_deinit_card;
3687 }
3688 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3689
3690 card->sramsize = probe_sram(card);
3691
3692 for (i = 0; i < 4; i++) {
3693 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3694 if (!card->fbq[i]) {
3695 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3696 err = -EIO;
3697 goto err_out_deinit_card;
3698 }
3699 }
3700
3701 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3702 card->name, ((card->revision > 1) && (card->revision < 25)) ?
3703 'A' + card->revision - 1 : '?', membase, srambase,
3704 card->sramsize / 1024);
3705
3706 if (init_card(dev)) {
3707 printk("%s: init_card failed\n", card->name);
3708 err = -EIO;
3709 goto err_out_deinit_card;
3710 }
3711
3712 dev->ci_range.vpi_bits = card->vpibits;
3713 dev->ci_range.vci_bits = card->vcibits;
3714 dev->link_rate = card->link_pcr;
3715
3716 if (dev->phy->start)
3717 dev->phy->start(dev);
3718
3719 if (idt77252_dev_open(card)) {
3720 printk("%s: dev_open failed\n", card->name);
3721 err = -EIO;
3722 goto err_out_stop;
3723 }
3724
3725 *last = card;
3726 last = &card->next;
3727 index++;
3728
3729 return 0;
3730
3731 err_out_stop:
3732 if (dev->phy->stop)
3733 dev->phy->stop(dev);
3734
3735 err_out_deinit_card:
3736 deinit_card(card);
3737
3738 err_out_iounmap:
3739 iounmap(card->membase);
3740
3741 err_out_free_card:
3742 kfree(card);
3743
3744 err_out_disable_pdev:
3745 pci_disable_device(pcidev);
3746 return err;
3747 }
3748
3749 static struct pci_device_id idt77252_pci_tbl[] =
3750 {
3751 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 },
3752 { 0, }
3753 };
3754
3755 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3756
3757 static struct pci_driver idt77252_driver = {
3758 .name = "idt77252",
3759 .id_table = idt77252_pci_tbl,
3760 .probe = idt77252_init_one,
3761 };
3762
3763 static int __init idt77252_init(void)
3764 {
3765 struct sk_buff *skb;
3766
3767 printk("%s: at %p\n", __func__, idt77252_init);
3768
3769 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3770 sizeof(struct idt77252_skb_prv)) {
3771 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3772 __func__, (unsigned long) sizeof(skb->cb),
3773 (unsigned long) sizeof(struct atm_skb_data) +
3774 sizeof(struct idt77252_skb_prv));
3775 return -EIO;
3776 }
3777
3778 return pci_register_driver(&idt77252_driver);
3779 }
3780
3781 static void __exit idt77252_exit(void)
3782 {
3783 struct idt77252_dev *card;
3784 struct atm_dev *dev;
3785
3786 pci_unregister_driver(&idt77252_driver);
3787
3788 while (idt77252_chain) {
3789 card = idt77252_chain;
3790 dev = card->atmdev;
3791 idt77252_chain = card->next;
3792
3793 if (dev->phy->stop)
3794 dev->phy->stop(dev);
3795 deinit_card(card);
3796 pci_disable_device(card->pcidev);
3797 kfree(card);
3798 }
3799
3800 DIPRINTK("idt77252: finished cleanup-module().\n");
3801 }
3802
3803 module_init(idt77252_init);
3804 module_exit(idt77252_exit);
3805
3806 MODULE_LICENSE("GPL");
3807
3808 module_param(vpibits, uint, 0);
3809 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3810 #ifdef CONFIG_ATM_IDT77252_DEBUG
3811 module_param(debug, ulong, 0644);
3812 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3813 #endif
3814
3815 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3816 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
Tomato firmware and modifications.