release/src-rt-6.x.4708/linux/linux-2.6.36/arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/sched.h>
   8 #include <linux/thread_info.h>
   9 #include <linux/module.h>
  10 #include <linux/uaccess.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/msr.h>
  15 #include <asm/bugs.h>
  16 #include <asm/cpu.h>
  17
  18 #ifdef CONFIG_X86_64
  19 #include <linux/topology.h>
  20 #include <asm/numa_64.h>
  21 #endif
  22
  23 #include "cpu.h"
  24
  25 #ifdef CONFIG_X86_LOCAL_APIC
  26 #include <asm/mpspec.h>
  27 #include <asm/apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         /* Unmask CPUID levels if masked: */
  33         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  34                 u64 misc_enable;
  35
  36                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  37
  38                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  39                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  40                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  41                         c->cpuid_level = cpuid_eax(0);
  42                         get_cpu_cap(c);
  43                 }
  44         }
  45
  46         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  47                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  48                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  49
  50         /*
  51          * Atom erratum AAE44/AAF40/AAG38/AAH41:
  52          *
  53          * A race condition between speculative fetches and invalidating
  54          * a large page.  This is worked around in microcode, but we
  55          * need the microcode to have already been loaded... so if it is
  56          * not, recommend a BIOS update and disable large pages.
  57          */
  58         if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
  59                 u32 ucode, junk;
  60
  61                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  62                 sync_core();
  63                 rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
  64
  65                 if (ucode < 0x20e) {
  66                         printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
  67                         clear_cpu_cap(c, X86_FEATURE_PSE);
  68                 }
  69         }
  70
  71 #ifdef CONFIG_X86_64
  72         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  73 #else
  74         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  75         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  76                 c->x86_cache_alignment = 128;
  77 #endif
  78
  79         if (c->x86 == 0xF && c->x86_model == 0x3
  80             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
  81                 c->x86_phys_bits = 36;
  82
  83         /*
  84          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  85          * with P/T states and does not stop in deep C-states.
  86          *
  87          * It is also reliable across cores and sockets. (but not across
  88          * cabinets - we turn it off in that case explicitly.)
  89          */
  90         if (c->x86_power & (1 << 8)) {
  91                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  92                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  93                 if (!check_tsc_unstable())
  94                         sched_clock_stable = 1;
  95         }
  96
  97         /*
  98          * There is a known erratum on Pentium III and Core Solo
  99          * and Core Duo CPUs.
 100          * " Page with PAT set to WC while associated MTRR is UC
 101          *   may consolidate to UC "
 102          * Because of this erratum, it is better to stick with
 103          * setting WC in MTRR rather than using PAT on these CPUs.
 104          *
 105          * Enable PAT WC only on P4, Core 2 or later CPUs.
 106          */
 107         if (c->x86 == 6 && c->x86_model < 15)
 108                 clear_cpu_cap(c, X86_FEATURE_PAT);
 109
 110 #ifdef CONFIG_KMEMCHECK
 111         /*
 112          * P4s have a "fast strings" feature which causes single-
 113          * stepping REP instructions to only generate a #DB on
 114          * cache-line boundaries.
 115          *
 116          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
 117          * (model 2) with the same problem.
 118          */
 119         if (c->x86 == 15) {
 120                 u64 misc_enable;
 121
 122                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 123
 124                 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
 125                         printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
 126
 127                         misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
 128                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 129                 }
 130         }
 131 #endif
 132 }
 133
 134 #ifdef CONFIG_X86_32
 135 /*
 136  *      Early probe support logic for ppro memory erratum #50
 137  *
 138  *      This is called before we do cpu ident work
 139  */
 140
 141 int __cpuinit ppro_with_ram_bug(void)
 142 {
 143         /* Uses data from early_cpu_detect now */
 144         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 145             boot_cpu_data.x86 == 6 &&
 146             boot_cpu_data.x86_model == 1 &&
 147             boot_cpu_data.x86_mask < 8) {
 148                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 149                 return 1;
 150         }
 151         return 0;
 152 }
 153
 154 #ifdef CONFIG_X86_F00F_BUG
 155 static void __cpuinit trap_init_f00f_bug(void)
 156 {
 157         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 158
 159         /*
 160          * Update the IDT descriptor and reload the IDT so that
 161          * it uses the read-only mapped virtual address.
 162          */
 163         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 164         load_idt(&idt_descr);
 165 }
 166 #endif
 167
 168 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 169 {
 170 #ifdef CONFIG_SMP
 171         /* calling is from identify_secondary_cpu() ? */
 172         if (c->cpu_index == boot_cpu_id)
 173                 return;
 174
 175         /*
 176          * Mask B, Pentium, but not Pentium MMX
 177          */
 178         if (c->x86 == 5 &&
 179             c->x86_mask >= 1 && c->x86_mask <= 4 &&
 180             c->x86_model <= 3) {
 181                 /*
 182                  * Remember we have B step Pentia with bugs
 183                  */
 184                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
 185                                     "with B stepping processors.\n");
 186         }
 187 #endif
 188 }
 189
 190 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 191 {
 192         unsigned long lo, hi;
 193
 194 #ifdef CONFIG_X86_F00F_BUG
 195         c->f00f_bug = 0;
 196         if (!paravirt_enabled() && c->x86 == 5) {
 197                 static int f00f_workaround_enabled;
 198
 199                 c->f00f_bug = 1;
 200                 if (!f00f_workaround_enabled) {
 201                         trap_init_f00f_bug();
 202                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 203                         f00f_workaround_enabled = 1;
 204                 }
 205         }
 206 #endif
 207
 208         /*
 209          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 210          * model 3 mask 3
 211          */
 212         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 213                 clear_cpu_cap(c, X86_FEATURE_SEP);
 214
 215         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 216                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 217                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
 218                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 219                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 220                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
 221                         wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 222                 }
 223         }
 224
 225         /*
 226          * See if we have a good local APIC by checking for buggy Pentia,
 227          * i.e. all B steppings and the C2 stepping of P54C when using their
 228          * integrated APIC (see 11AP erratum in "Pentium Processor
 229          * Specification Update").
 230          */
 231         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 232             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 233                 set_cpu_cap(c, X86_FEATURE_11AP);
 234
 235
 236 #ifdef CONFIG_X86_INTEL_USERCOPY
 237         /*
 238          * Set up the preferred alignment for movsl bulk memory moves
 239          */
 240         switch (c->x86) {
 241         case 4:         /* 486: untested */
 242                 break;
 243         case 5:         /* Old Pentia: untested */
 244                 break;
 245         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 246                 movsl_mask.mask = 7;
 247                 break;
 248         case 15:        /* P4 is OK down to 8-byte alignment */
 249                 movsl_mask.mask = 7;
 250                 break;
 251         }
 252 #endif
 253
 254 #ifdef CONFIG_X86_NUMAQ
 255         numaq_tsc_disable();
 256 #endif
 257
 258         intel_smp_check(c);
 259 }
 260 #else
 261 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 262 {
 263 }
 264 #endif
 265
 266 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 267 {
 268 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 269         unsigned node;
 270         int cpu = smp_processor_id();
 271         int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
 272
 273         /* Don't do the funky fallback heuristics the AMD version employs
 274            for now. */
 275         node = apicid_to_node[apicid];
 276         if (node == NUMA_NO_NODE)
 277                 node = first_node(node_online_map);
 278         else if (!node_online(node)) {
 279                 /* reuse the value from init_cpu_to_node() */
 280                 node = cpu_to_node(cpu);
 281         }
 282         numa_set_node(cpu, node);
 283 #endif
 284 }
 285
 286 /*
 287  * find out the number of processor cores on the die
 288  */
 289 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 290 {
 291         unsigned int eax, ebx, ecx, edx;
 292
 293         if (c->cpuid_level < 4)
 294                 return 1;
 295
 296         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 297         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 298         if (eax & 0x1f)
 299                 return (eax >> 26) + 1;
 300         else
 301                 return 1;
 302 }
 303
 304 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 305 {
 306         /* Intel VMX MSR indicated features */
 307 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 308 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 309 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 310 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 311 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 312 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 313
 314         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 315
 316         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 317         clear_cpu_cap(c, X86_FEATURE_VNMI);
 318         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 319         clear_cpu_cap(c, X86_FEATURE_EPT);
 320         clear_cpu_cap(c, X86_FEATURE_VPID);
 321
 322         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 323         msr_ctl = vmx_msr_high | vmx_msr_low;
 324         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 325                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 326         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 327                 set_cpu_cap(c, X86_FEATURE_VNMI);
 328         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 329                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 330                       vmx_msr_low, vmx_msr_high);
 331                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 332                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 333                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 334                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 335                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 336                         set_cpu_cap(c, X86_FEATURE_EPT);
 337                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 338                         set_cpu_cap(c, X86_FEATURE_VPID);
 339         }
 340 }
 341
 342 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 343 {
 344         unsigned int l2 = 0;
 345
 346         early_init_intel(c);
 347
 348         intel_workarounds(c);
 349
 350         /*
 351          * Detect the extended topology information if available. This
 352          * will reinitialise the initial_apicid which will be used
 353          * in init_intel_cacheinfo()
 354          */
 355         detect_extended_topology(c);
 356
 357         l2 = init_intel_cacheinfo(c);
 358         if (c->cpuid_level > 9) {
 359                 unsigned eax = cpuid_eax(10);
 360                 /* Check for version and the number of counters */
 361                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 362                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 363         }
 364
 365         if (cpu_has_xmm2)
 366                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 367         if (cpu_has_ds) {
 368                 unsigned int l1;
 369                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 370                 if (!(l1 & (1<<11)))
 371                         set_cpu_cap(c, X86_FEATURE_BTS);
 372                 if (!(l1 & (1<<12)))
 373                         set_cpu_cap(c, X86_FEATURE_PEBS);
 374         }
 375
 376         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
 377                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
 378
 379 #ifdef CONFIG_X86_64
 380         if (c->x86 == 15)
 381                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 382         if (c->x86 == 6)
 383                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 384 #else
 385         /*
 386          * Names for the Pentium II/Celeron processors
 387          * detectable only by also checking the cache size.
 388          * Dixon is NOT a Celeron.
 389          */
 390         if (c->x86 == 6) {
 391                 char *p = NULL;
 392
 393                 switch (c->x86_model) {
 394                 case 5:
 395                         if (c->x86_mask == 0) {
 396                                 if (l2 == 0)
 397                                         p = "Celeron (Covington)";
 398                                 else if (l2 == 256)
 399                                         p = "Mobile Pentium II (Dixon)";
 400                         }
 401                         break;
 402
 403                 case 6:
 404                         if (l2 == 128)
 405                                 p = "Celeron (Mendocino)";
 406                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 407                                 p = "Celeron-A";
 408                         break;
 409
 410                 case 8:
 411                         if (l2 == 128)
 412                                 p = "Celeron (Coppermine)";
 413                         break;
 414                 }
 415
 416                 if (p)
 417                         strcpy(c->x86_model_id, p);
 418         }
 419
 420         if (c->x86 == 15)
 421                 set_cpu_cap(c, X86_FEATURE_P4);
 422         if (c->x86 == 6)
 423                 set_cpu_cap(c, X86_FEATURE_P3);
 424 #endif
 425
 426         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 427                 /*
 428                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 429                  * detection.
 430                  */
 431                 c->x86_max_cores = intel_num_cpu_cores(c);
 432 #ifdef CONFIG_X86_32
 433                 detect_ht(c);
 434 #endif
 435         }
 436
 437         srat_detect_node(c);
 438
 439         if (cpu_has(c, X86_FEATURE_VMX))
 440                 detect_vmx_virtcap(c);
 441 }
 442
 443 #ifdef CONFIG_X86_32
 444 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 445 {
 446         /*
 447          * Intel PIII Tualatin. This comes in two flavours.
 448          * One has 256kb of cache, the other 512. We have no way
 449          * to determine which, so we use a boottime override
 450          * for the 512kb model, and assume 256 otherwise.
 451          */
 452         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 453                 size = 256;
 454         return size;
 455 }
 456 #endif
 457
 458 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
 459         .c_vendor       = "Intel",
 460         .c_ident        = { "GenuineIntel" },
 461 #ifdef CONFIG_X86_32
 462         .c_models = {
 463                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 464                   {
 465                           [0] = "486 DX-25/33",
 466                           [1] = "486 DX-50",
 467                           [2] = "486 SX",
 468                           [3] = "486 DX/2",
 469                           [4] = "486 SL",
 470                           [5] = "486 SX/2",
 471                           [7] = "486 DX/2-WB",
 472                           [8] = "486 DX/4",
 473                           [9] = "486 DX/4-WB"
 474                   }
 475                 },
 476                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 477                   {
 478                           [0] = "Pentium 60/66 A-step",
 479                           [1] = "Pentium 60/66",
 480                           [2] = "Pentium 75 - 200",
 481                           [3] = "OverDrive PODP5V83",
 482                           [4] = "Pentium MMX",
 483                           [7] = "Mobile Pentium 75 - 200",
 484                           [8] = "Mobile Pentium MMX"
 485                   }
 486                 },
 487                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 488                   {
 489                           [0] = "Pentium Pro A-step",
 490                           [1] = "Pentium Pro",
 491                           [3] = "Pentium II (Klamath)",
 492                           [4] = "Pentium II (Deschutes)",
 493                           [5] = "Pentium II (Deschutes)",
 494                           [6] = "Mobile Pentium II",
 495                           [7] = "Pentium III (Katmai)",
 496                           [8] = "Pentium III (Coppermine)",
 497                           [10] = "Pentium III (Cascades)",
 498                           [11] = "Pentium III (Tualatin)",
 499                   }
 500                 },
 501                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 502                   {
 503                           [0] = "Pentium 4 (Unknown)",
 504                           [1] = "Pentium 4 (Willamette)",
 505                           [2] = "Pentium 4 (Northwood)",
 506                           [4] = "Pentium 4 (Foster)",
 507                           [5] = "Pentium 4 (Foster)",
 508                   }
 509                 },
 510         },
 511         .c_size_cache   = intel_size_cache,
 512 #endif
 513         .c_early_init   = early_init_intel,
 514         .c_init         = init_intel,
 515         .c_x86_vendor   = X86_VENDOR_INTEL,
 516 };
 517
 518 cpu_dev_register(intel_cpu_dev);