RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / sparc / kernel / time_64.c
blob645138c4d98d47952580d5fc187adf001a55303c
1 /* time.c: UltraSparc timer and TOD clock support.
3 * Copyright (C) 1997, 2008 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Based largely on code which is:
8 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
9 */
11 #include <linux/errno.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/param.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/interrupt.h>
19 #include <linux/time.h>
20 #include <linux/timex.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/delay.h>
25 #include <linux/profile.h>
26 #include <linux/bcd.h>
27 #include <linux/jiffies.h>
28 #include <linux/cpufreq.h>
29 #include <linux/percpu.h>
30 #include <linux/miscdevice.h>
31 #include <linux/rtc.h>
32 #include <linux/rtc/m48t59.h>
33 #include <linux/kernel_stat.h>
34 #include <linux/clockchips.h>
35 #include <linux/clocksource.h>
36 #include <linux/of_device.h>
37 #include <linux/platform_device.h>
38 #include <linux/ftrace.h>
40 #include <asm/oplib.h>
41 #include <asm/timer.h>
42 #include <asm/irq.h>
43 #include <asm/io.h>
44 #include <asm/prom.h>
45 #include <asm/starfire.h>
46 #include <asm/smp.h>
47 #include <asm/sections.h>
48 #include <asm/cpudata.h>
49 #include <asm/uaccess.h>
50 #include <asm/irq_regs.h>
52 #include "entry.h"
54 DEFINE_SPINLOCK(rtc_lock);
56 #define TICK_PRIV_BIT (1UL << 63)
57 #define TICKCMP_IRQ_BIT (1UL << 63)
59 #ifdef CONFIG_SMP
60 unsigned long profile_pc(struct pt_regs *regs)
62 unsigned long pc = instruction_pointer(regs);
64 if (in_lock_functions(pc))
65 return regs->u_regs[UREG_RETPC];
66 return pc;
68 EXPORT_SYMBOL(profile_pc);
69 #endif
71 static void tick_disable_protection(void)
73 __asm__ __volatile__(
74 " ba,pt %%xcc, 1f\n"
75 " nop\n"
76 " .align 64\n"
77 "1: rd %%tick, %%g2\n"
78 " add %%g2, 6, %%g2\n"
79 " andn %%g2, %0, %%g2\n"
80 " wrpr %%g2, 0, %%tick\n"
81 " rdpr %%tick, %%g0"
82 : /* no outputs */
83 : "r" (TICK_PRIV_BIT)
84 : "g2");
87 static void tick_disable_irq(void)
89 __asm__ __volatile__(
90 " ba,pt %%xcc, 1f\n"
91 " nop\n"
92 " .align 64\n"
93 "1: wr %0, 0x0, %%tick_cmpr\n"
94 " rd %%tick_cmpr, %%g0"
95 : /* no outputs */
96 : "r" (TICKCMP_IRQ_BIT));
99 static void tick_init_tick(void)
101 tick_disable_protection();
102 tick_disable_irq();
105 static unsigned long long tick_get_tick(void)
107 unsigned long ret;
109 __asm__ __volatile__("rd %%tick, %0\n\t"
110 "mov %0, %0"
111 : "=r" (ret));
113 return ret & ~TICK_PRIV_BIT;
116 static int tick_add_compare(unsigned long adj)
118 unsigned long orig_tick, new_tick, new_compare;
120 __asm__ __volatile__("rd %%tick, %0"
121 : "=r" (orig_tick));
123 orig_tick &= ~TICKCMP_IRQ_BIT;
125 __asm__ __volatile__("ba,pt %%xcc, 1f\n\t"
126 " add %1, %2, %0\n\t"
127 ".align 64\n"
128 "1:\n\t"
129 "wr %0, 0, %%tick_cmpr\n\t"
130 "rd %%tick_cmpr, %%g0\n\t"
131 : "=r" (new_compare)
132 : "r" (orig_tick), "r" (adj));
134 __asm__ __volatile__("rd %%tick, %0"
135 : "=r" (new_tick));
136 new_tick &= ~TICKCMP_IRQ_BIT;
138 return ((long)(new_tick - (orig_tick+adj))) > 0L;
141 static unsigned long tick_add_tick(unsigned long adj)
143 unsigned long new_tick;
145 /* Also need to handle Blackbird bug here too. */
146 __asm__ __volatile__("rd %%tick, %0\n\t"
147 "add %0, %1, %0\n\t"
148 "wrpr %0, 0, %%tick\n\t"
149 : "=&r" (new_tick)
150 : "r" (adj));
152 return new_tick;
155 static struct sparc64_tick_ops tick_operations __read_mostly = {
156 .name = "tick",
157 .init_tick = tick_init_tick,
158 .disable_irq = tick_disable_irq,
159 .get_tick = tick_get_tick,
160 .add_tick = tick_add_tick,
161 .add_compare = tick_add_compare,
162 .softint_mask = 1UL << 0,
165 struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
166 EXPORT_SYMBOL(tick_ops);
168 static void stick_disable_irq(void)
170 __asm__ __volatile__(
171 "wr %0, 0x0, %%asr25"
172 : /* no outputs */
173 : "r" (TICKCMP_IRQ_BIT));
176 static void stick_init_tick(void)
178 /* Writes to the %tick and %stick register are not
179 * allowed on sun4v. The Hypervisor controls that
180 * bit, per-strand.
182 if (tlb_type != hypervisor) {
183 tick_disable_protection();
184 tick_disable_irq();
186 /* Let the user get at STICK too. */
187 __asm__ __volatile__(
188 " rd %%asr24, %%g2\n"
189 " andn %%g2, %0, %%g2\n"
190 " wr %%g2, 0, %%asr24"
191 : /* no outputs */
192 : "r" (TICK_PRIV_BIT)
193 : "g1", "g2");
196 stick_disable_irq();
199 static unsigned long long stick_get_tick(void)
201 unsigned long ret;
203 __asm__ __volatile__("rd %%asr24, %0"
204 : "=r" (ret));
206 return ret & ~TICK_PRIV_BIT;
209 static unsigned long stick_add_tick(unsigned long adj)
211 unsigned long new_tick;
213 __asm__ __volatile__("rd %%asr24, %0\n\t"
214 "add %0, %1, %0\n\t"
215 "wr %0, 0, %%asr24\n\t"
216 : "=&r" (new_tick)
217 : "r" (adj));
219 return new_tick;
222 static int stick_add_compare(unsigned long adj)
224 unsigned long orig_tick, new_tick;
226 __asm__ __volatile__("rd %%asr24, %0"
227 : "=r" (orig_tick));
228 orig_tick &= ~TICKCMP_IRQ_BIT;
230 __asm__ __volatile__("wr %0, 0, %%asr25"
231 : /* no outputs */
232 : "r" (orig_tick + adj));
234 __asm__ __volatile__("rd %%asr24, %0"
235 : "=r" (new_tick));
236 new_tick &= ~TICKCMP_IRQ_BIT;
238 return ((long)(new_tick - (orig_tick+adj))) > 0L;
241 static struct sparc64_tick_ops stick_operations __read_mostly = {
242 .name = "stick",
243 .init_tick = stick_init_tick,
244 .disable_irq = stick_disable_irq,
245 .get_tick = stick_get_tick,
246 .add_tick = stick_add_tick,
247 .add_compare = stick_add_compare,
248 .softint_mask = 1UL << 16,
251 /* On Hummingbird the STICK/STICK_CMPR register is implemented
252 * in I/O space. There are two 64-bit registers each, the
253 * first holds the low 32-bits of the value and the second holds
254 * the high 32-bits.
256 * Since STICK is constantly updating, we have to access it carefully.
258 * The sequence we use to read is:
259 * 1) read high
260 * 2) read low
261 * 3) read high again, if it rolled re-read both low and high again.
263 * Writing STICK safely is also tricky:
264 * 1) write low to zero
265 * 2) write high
266 * 3) write low
268 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
269 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
271 static unsigned long __hbird_read_stick(void)
273 unsigned long ret, tmp1, tmp2, tmp3;
274 unsigned long addr = HBIRD_STICK_ADDR+8;
276 __asm__ __volatile__("ldxa [%1] %5, %2\n"
277 "1:\n\t"
278 "sub %1, 0x8, %1\n\t"
279 "ldxa [%1] %5, %3\n\t"
280 "add %1, 0x8, %1\n\t"
281 "ldxa [%1] %5, %4\n\t"
282 "cmp %4, %2\n\t"
283 "bne,a,pn %%xcc, 1b\n\t"
284 " mov %4, %2\n\t"
285 "sllx %4, 32, %4\n\t"
286 "or %3, %4, %0\n\t"
287 : "=&r" (ret), "=&r" (addr),
288 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
289 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
291 return ret;
294 static void __hbird_write_stick(unsigned long val)
296 unsigned long low = (val & 0xffffffffUL);
297 unsigned long high = (val >> 32UL);
298 unsigned long addr = HBIRD_STICK_ADDR;
300 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
301 "add %0, 0x8, %0\n\t"
302 "stxa %3, [%0] %4\n\t"
303 "sub %0, 0x8, %0\n\t"
304 "stxa %2, [%0] %4"
305 : "=&r" (addr)
306 : "0" (addr), "r" (low), "r" (high),
307 "i" (ASI_PHYS_BYPASS_EC_E));
310 static void __hbird_write_compare(unsigned long val)
312 unsigned long low = (val & 0xffffffffUL);
313 unsigned long high = (val >> 32UL);
314 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
316 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
317 "sub %0, 0x8, %0\n\t"
318 "stxa %2, [%0] %4"
319 : "=&r" (addr)
320 : "0" (addr), "r" (low), "r" (high),
321 "i" (ASI_PHYS_BYPASS_EC_E));
324 static void hbtick_disable_irq(void)
326 __hbird_write_compare(TICKCMP_IRQ_BIT);
329 static void hbtick_init_tick(void)
331 tick_disable_protection();
333 __hbird_write_stick(__hbird_read_stick());
335 hbtick_disable_irq();
338 static unsigned long long hbtick_get_tick(void)
340 return __hbird_read_stick() & ~TICK_PRIV_BIT;
343 static unsigned long hbtick_add_tick(unsigned long adj)
345 unsigned long val;
347 val = __hbird_read_stick() + adj;
348 __hbird_write_stick(val);
350 return val;
353 static int hbtick_add_compare(unsigned long adj)
355 unsigned long val = __hbird_read_stick();
356 unsigned long val2;
358 val &= ~TICKCMP_IRQ_BIT;
359 val += adj;
360 __hbird_write_compare(val);
362 val2 = __hbird_read_stick() & ~TICKCMP_IRQ_BIT;
364 return ((long)(val2 - val)) > 0L;
367 static struct sparc64_tick_ops hbtick_operations __read_mostly = {
368 .name = "hbtick",
369 .init_tick = hbtick_init_tick,
370 .disable_irq = hbtick_disable_irq,
371 .get_tick = hbtick_get_tick,
372 .add_tick = hbtick_add_tick,
373 .add_compare = hbtick_add_compare,
374 .softint_mask = 1UL << 0,
377 static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
379 int update_persistent_clock(struct timespec now)
381 struct rtc_device *rtc = rtc_class_open("rtc0");
382 int err = -1;
384 if (rtc) {
385 err = rtc_set_mmss(rtc, now.tv_sec);
386 rtc_class_close(rtc);
389 return err;
392 unsigned long cmos_regs;
393 EXPORT_SYMBOL(cmos_regs);
395 static struct resource rtc_cmos_resource;
397 static struct platform_device rtc_cmos_device = {
398 .name = "rtc_cmos",
399 .id = -1,
400 .resource = &rtc_cmos_resource,
401 .num_resources = 1,
404 static int __devinit rtc_probe(struct platform_device *op, const struct of_device_id *match)
406 struct resource *r;
408 printk(KERN_INFO "%s: RTC regs at 0x%llx\n",
409 op->dev.of_node->full_name, op->resource[0].start);
411 /* The CMOS RTC driver only accepts IORESOURCE_IO, so cons
412 * up a fake resource so that the probe works for all cases.
413 * When the RTC is behind an ISA bus it will have IORESOURCE_IO
414 * already, whereas when it's behind EBUS is will be IORESOURCE_MEM.
417 r = &rtc_cmos_resource;
418 r->flags = IORESOURCE_IO;
419 r->name = op->resource[0].name;
420 r->start = op->resource[0].start;
421 r->end = op->resource[0].end;
423 cmos_regs = op->resource[0].start;
424 return platform_device_register(&rtc_cmos_device);
427 static struct of_device_id __initdata rtc_match[] = {
429 .name = "rtc",
430 .compatible = "m5819",
433 .name = "rtc",
434 .compatible = "isa-m5819p",
437 .name = "rtc",
438 .compatible = "isa-m5823p",
441 .name = "rtc",
442 .compatible = "ds1287",
447 static struct of_platform_driver rtc_driver = {
448 .probe = rtc_probe,
449 .driver = {
450 .name = "rtc",
451 .owner = THIS_MODULE,
452 .of_match_table = rtc_match,
456 static struct platform_device rtc_bq4802_device = {
457 .name = "rtc-bq4802",
458 .id = -1,
459 .num_resources = 1,
462 static int __devinit bq4802_probe(struct platform_device *op, const struct of_device_id *match)
465 printk(KERN_INFO "%s: BQ4802 regs at 0x%llx\n",
466 op->dev.of_node->full_name, op->resource[0].start);
468 rtc_bq4802_device.resource = &op->resource[0];
469 return platform_device_register(&rtc_bq4802_device);
472 static struct of_device_id __initdata bq4802_match[] = {
474 .name = "rtc",
475 .compatible = "bq4802",
480 static struct of_platform_driver bq4802_driver = {
481 .probe = bq4802_probe,
482 .driver = {
483 .name = "bq4802",
484 .owner = THIS_MODULE,
485 .of_match_table = bq4802_match,
489 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
491 struct platform_device *pdev = to_platform_device(dev);
492 void __iomem *regs = (void __iomem *) pdev->resource[0].start;
494 return readb(regs + ofs);
497 static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
499 struct platform_device *pdev = to_platform_device(dev);
500 void __iomem *regs = (void __iomem *) pdev->resource[0].start;
502 writeb(val, regs + ofs);
505 static struct m48t59_plat_data m48t59_data = {
506 .read_byte = mostek_read_byte,
507 .write_byte = mostek_write_byte,
510 static struct platform_device m48t59_rtc = {
511 .name = "rtc-m48t59",
512 .id = 0,
513 .num_resources = 1,
514 .dev = {
515 .platform_data = &m48t59_data,
519 static int __devinit mostek_probe(struct platform_device *op, const struct of_device_id *match)
521 struct device_node *dp = op->dev.of_node;
523 /* On an Enterprise system there can be multiple mostek clocks.
524 * We should only match the one that is on the central FHC bus.
526 if (!strcmp(dp->parent->name, "fhc") &&
527 strcmp(dp->parent->parent->name, "central") != 0)
528 return -ENODEV;
530 printk(KERN_INFO "%s: Mostek regs at 0x%llx\n",
531 dp->full_name, op->resource[0].start);
533 m48t59_rtc.resource = &op->resource[0];
534 return platform_device_register(&m48t59_rtc);
537 static struct of_device_id __initdata mostek_match[] = {
539 .name = "eeprom",
544 static struct of_platform_driver mostek_driver = {
545 .probe = mostek_probe,
546 .driver = {
547 .name = "mostek",
548 .owner = THIS_MODULE,
549 .of_match_table = mostek_match,
553 static struct platform_device rtc_sun4v_device = {
554 .name = "rtc-sun4v",
555 .id = -1,
558 static struct platform_device rtc_starfire_device = {
559 .name = "rtc-starfire",
560 .id = -1,
563 static int __init clock_init(void)
565 if (this_is_starfire)
566 return platform_device_register(&rtc_starfire_device);
568 if (tlb_type == hypervisor)
569 return platform_device_register(&rtc_sun4v_device);
571 (void) of_register_platform_driver(&rtc_driver);
572 (void) of_register_platform_driver(&mostek_driver);
573 (void) of_register_platform_driver(&bq4802_driver);
575 return 0;
578 /* Must be after subsys_initcall() so that busses are probed. Must
579 * be before device_initcall() because things like the RTC driver
580 * need to see the clock registers.
582 fs_initcall(clock_init);
584 /* This is gets the master TICK_INT timer going. */
585 static unsigned long sparc64_init_timers(void)
587 struct device_node *dp;
588 unsigned long freq;
590 dp = of_find_node_by_path("/");
591 if (tlb_type == spitfire) {
592 unsigned long ver, manuf, impl;
594 __asm__ __volatile__ ("rdpr %%ver, %0"
595 : "=&r" (ver));
596 manuf = ((ver >> 48) & 0xffff);
597 impl = ((ver >> 32) & 0xffff);
598 if (manuf == 0x17 && impl == 0x13) {
599 /* Hummingbird, aka Ultra-IIe */
600 tick_ops = &hbtick_operations;
601 freq = of_getintprop_default(dp, "stick-frequency", 0);
602 } else {
603 tick_ops = &tick_operations;
604 freq = local_cpu_data().clock_tick;
606 } else {
607 tick_ops = &stick_operations;
608 freq = of_getintprop_default(dp, "stick-frequency", 0);
611 return freq;
614 struct freq_table {
615 unsigned long clock_tick_ref;
616 unsigned int ref_freq;
618 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0 };
620 unsigned long sparc64_get_clock_tick(unsigned int cpu)
622 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
624 if (ft->clock_tick_ref)
625 return ft->clock_tick_ref;
626 return cpu_data(cpu).clock_tick;
628 EXPORT_SYMBOL(sparc64_get_clock_tick);
630 #ifdef CONFIG_CPU_FREQ
632 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
633 void *data)
635 struct cpufreq_freqs *freq = data;
636 unsigned int cpu = freq->cpu;
637 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
639 if (!ft->ref_freq) {
640 ft->ref_freq = freq->old;
641 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
643 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
644 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
645 (val == CPUFREQ_RESUMECHANGE)) {
646 cpu_data(cpu).clock_tick =
647 cpufreq_scale(ft->clock_tick_ref,
648 ft->ref_freq,
649 freq->new);
652 return 0;
655 static struct notifier_block sparc64_cpufreq_notifier_block = {
656 .notifier_call = sparc64_cpufreq_notifier
659 static int __init register_sparc64_cpufreq_notifier(void)
662 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
663 CPUFREQ_TRANSITION_NOTIFIER);
664 return 0;
667 core_initcall(register_sparc64_cpufreq_notifier);
669 #endif /* CONFIG_CPU_FREQ */
671 static int sparc64_next_event(unsigned long delta,
672 struct clock_event_device *evt)
674 return tick_ops->add_compare(delta) ? -ETIME : 0;
677 static void sparc64_timer_setup(enum clock_event_mode mode,
678 struct clock_event_device *evt)
680 switch (mode) {
681 case CLOCK_EVT_MODE_ONESHOT:
682 case CLOCK_EVT_MODE_RESUME:
683 break;
685 case CLOCK_EVT_MODE_SHUTDOWN:
686 tick_ops->disable_irq();
687 break;
689 case CLOCK_EVT_MODE_PERIODIC:
690 case CLOCK_EVT_MODE_UNUSED:
691 WARN_ON(1);
692 break;
696 static struct clock_event_device sparc64_clockevent = {
697 .features = CLOCK_EVT_FEAT_ONESHOT,
698 .set_mode = sparc64_timer_setup,
699 .set_next_event = sparc64_next_event,
700 .rating = 100,
701 .shift = 30,
702 .irq = -1,
704 static DEFINE_PER_CPU(struct clock_event_device, sparc64_events);
706 void __irq_entry timer_interrupt(int irq, struct pt_regs *regs)
708 struct pt_regs *old_regs = set_irq_regs(regs);
709 unsigned long tick_mask = tick_ops->softint_mask;
710 int cpu = smp_processor_id();
711 struct clock_event_device *evt = &per_cpu(sparc64_events, cpu);
713 clear_softint(tick_mask);
715 irq_enter();
717 local_cpu_data().irq0_irqs++;
718 kstat_incr_irqs_this_cpu(0, irq_to_desc(0));
720 if (unlikely(!evt->event_handler)) {
721 printk(KERN_WARNING
722 "Spurious SPARC64 timer interrupt on cpu %d\n", cpu);
723 } else
724 evt->event_handler(evt);
726 irq_exit();
728 set_irq_regs(old_regs);
731 void __devinit setup_sparc64_timer(void)
733 struct clock_event_device *sevt;
734 unsigned long pstate;
736 /* Guarantee that the following sequences execute
737 * uninterrupted.
739 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
740 "wrpr %0, %1, %%pstate"
741 : "=r" (pstate)
742 : "i" (PSTATE_IE));
744 tick_ops->init_tick();
746 /* Restore PSTATE_IE. */
747 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
748 : /* no outputs */
749 : "r" (pstate));
751 sevt = &__get_cpu_var(sparc64_events);
753 memcpy(sevt, &sparc64_clockevent, sizeof(*sevt));
754 sevt->cpumask = cpumask_of(smp_processor_id());
756 clockevents_register_device(sevt);
759 #define SPARC64_NSEC_PER_CYC_SHIFT 10UL
761 static struct clocksource clocksource_tick = {
762 .rating = 100,
763 .mask = CLOCKSOURCE_MASK(64),
764 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
767 static unsigned long tb_ticks_per_usec __read_mostly;
769 void __delay(unsigned long loops)
771 unsigned long bclock, now;
773 bclock = tick_ops->get_tick();
774 do {
775 now = tick_ops->get_tick();
776 } while ((now-bclock) < loops);
778 EXPORT_SYMBOL(__delay);
780 void udelay(unsigned long usecs)
782 __delay(tb_ticks_per_usec * usecs);
784 EXPORT_SYMBOL(udelay);
786 static cycle_t clocksource_tick_read(struct clocksource *cs)
788 return tick_ops->get_tick();
791 void __init time_init(void)
793 unsigned long freq = sparc64_init_timers();
795 tb_ticks_per_usec = freq / USEC_PER_SEC;
797 timer_ticks_per_nsec_quotient =
798 clocksource_hz2mult(freq, SPARC64_NSEC_PER_CYC_SHIFT);
800 clocksource_tick.name = tick_ops->name;
801 clocksource_calc_mult_shift(&clocksource_tick, freq, 4);
802 clocksource_tick.read = clocksource_tick_read;
804 printk("clocksource: mult[%x] shift[%d]\n",
805 clocksource_tick.mult, clocksource_tick.shift);
807 clocksource_register(&clocksource_tick);
809 sparc64_clockevent.name = tick_ops->name;
810 clockevents_calc_mult_shift(&sparc64_clockevent, freq, 4);
812 sparc64_clockevent.max_delta_ns =
813 clockevent_delta2ns(0x7fffffffffffffffUL, &sparc64_clockevent);
814 sparc64_clockevent.min_delta_ns =
815 clockevent_delta2ns(0xF, &sparc64_clockevent);
817 printk("clockevent: mult[%x] shift[%d]\n",
818 sparc64_clockevent.mult, sparc64_clockevent.shift);
820 setup_sparc64_timer();
823 unsigned long long sched_clock(void)
825 unsigned long ticks = tick_ops->get_tick();
827 return (ticks * timer_ticks_per_nsec_quotient)
828 >> SPARC64_NSEC_PER_CYC_SHIFT;
831 int __devinit read_current_timer(unsigned long *timer_val)
833 *timer_val = tick_ops->get_tick();
834 return 0;