release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sparc/include/asm/pgtsrmmu.h

   1 /*
   2  * pgtsrmmu.h:  SRMMU page table defines and code.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_PGTSRMMU_H
   8 #define _SPARC_PGTSRMMU_H
   9
  10 #include <asm/page.h>
  11
  12 #ifdef __ASSEMBLY__
  13 #include <asm/thread_info.h>    /* TI_UWINMASK for WINDOW_FLUSH */
  14 #endif
  15
  16 /* Number of contexts is implementation-dependent; 64k is the most we support */
  17 #define SRMMU_MAX_CONTEXTS      65536
  18
  19 /* PMD_SHIFT determines the size of the area a second-level page table entry can map */
  20 #define SRMMU_REAL_PMD_SHIFT            18
  21 #define SRMMU_REAL_PMD_SIZE             (1UL << SRMMU_REAL_PMD_SHIFT)
  22 #define SRMMU_REAL_PMD_MASK             (~(SRMMU_REAL_PMD_SIZE-1))
  23 #define SRMMU_REAL_PMD_ALIGN(__addr)    (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
  24
  25 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  26 #define SRMMU_PGDIR_SHIFT       24
  27 #define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
  28 #define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
  29 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
  30
  31 #define SRMMU_REAL_PTRS_PER_PTE 64
  32 #define SRMMU_REAL_PTRS_PER_PMD 64
  33 #define SRMMU_PTRS_PER_PGD      256
  34
  35 #define SRMMU_REAL_PTE_TABLE_SIZE       (SRMMU_REAL_PTRS_PER_PTE*4)
  36 #define SRMMU_PMD_TABLE_SIZE            (SRMMU_REAL_PTRS_PER_PMD*4)
  37 #define SRMMU_PGD_TABLE_SIZE            (SRMMU_PTRS_PER_PGD*4)
  38
  39 /*
  40  * To support pagetables in highmem, Linux introduces APIs which
  41  * return struct page* and generally manipulate page tables when
  42  * they are not mapped into kernel space. Our hardware page tables
  43  * are smaller than pages. We lump hardware tabes into big, page sized
  44  * software tables.
  45  *
  46  * PMD_SHIFT determines the size of the area a second-level page table entry
  47  * can map, and our pmd_t is 16 times larger than normal.  The values which
  48  * were once defined here are now generic for 4c and srmmu, so they're
  49  * found in pgtable.h.
  50  */
  51 #define SRMMU_PTRS_PER_PMD      4
  52
  53 /* Definition of the values in the ET field of PTD's and PTE's */
  54 #define SRMMU_ET_MASK         0x3
  55 #define SRMMU_ET_INVALID      0x0
  56 #define SRMMU_ET_PTD          0x1
  57 #define SRMMU_ET_PTE          0x2
  58 #define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
  59
  60 /* Physical page extraction from PTP's and PTE's. */
  61 #define SRMMU_CTX_PMASK    0xfffffff0
  62 #define SRMMU_PTD_PMASK    0xfffffff0
  63 #define SRMMU_PTE_PMASK    0xffffff00
  64
  65 /* The pte non-page bits.  Some notes:
  66  * 1) cache, dirty, valid, and ref are frobbable
  67  *    for both supervisor and user pages.
  68  * 2) exec and write will only give the desired effect
  69  *    on user pages
  70  * 3) use priv and priv_readonly for changing the
  71  *    characteristics of supervisor ptes
  72  */
  73 #define SRMMU_CACHE        0x80
  74 #define SRMMU_DIRTY        0x40
  75 #define SRMMU_REF          0x20
  76 #define SRMMU_NOREAD       0x10
  77 #define SRMMU_EXEC         0x08
  78 #define SRMMU_WRITE        0x04
  79 #define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
  80 #define SRMMU_PRIV         0x1c
  81 #define SRMMU_PRIV_RDONLY  0x18
  82
  83 #define SRMMU_FILE         0x40 /* Implemented in software */
  84
  85 #define SRMMU_PTE_FILE_SHIFT     8      /* == 32-PTE_FILE_MAX_BITS */
  86
  87 #define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
  88
  89 /* SRMMU swap entry encoding
  90  *
  91  * We use 5 bits for the type and 19 for the offset.  This gives us
  92  * 32 swapfiles of 4GB each.  Encoding looks like:
  93  *
  94  * oooooooooooooooooootttttRRRRRRRR
  95  * fedcba9876543210fedcba9876543210
  96  *
  97  * The bottom 8 bits are reserved for protection and status bits, especially
  98  * FILE and PRESENT.
  99  */
 100 #define SRMMU_SWP_TYPE_MASK     0x1f
 101 #define SRMMU_SWP_TYPE_SHIFT    SRMMU_PTE_FILE_SHIFT
 102 #define SRMMU_SWP_OFF_MASK      0x7ffff
 103 #define SRMMU_SWP_OFF_SHIFT     (SRMMU_PTE_FILE_SHIFT + 5)
 104
 105 #define SRMMU_PAGE_NONE    __pgprot(SRMMU_CACHE | \
 106                                     SRMMU_PRIV | SRMMU_REF)
 107 #define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 108                                     SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
 109 #define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 110                                     SRMMU_EXEC | SRMMU_REF)
 111 #define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
 112                                     SRMMU_EXEC | SRMMU_REF)
 113 #define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
 114                                     SRMMU_DIRTY | SRMMU_REF)
 115
 116 /* SRMMU Register addresses in ASI 0x4.  These are valid for all
 117  * current SRMMU implementations that exist.
 118  */
 119 #define SRMMU_CTRL_REG           0x00000000
 120 #define SRMMU_CTXTBL_PTR         0x00000100
 121 #define SRMMU_CTX_REG            0x00000200
 122 #define SRMMU_FAULT_STATUS       0x00000300
 123 #define SRMMU_FAULT_ADDR         0x00000400
 124
 125 #define WINDOW_FLUSH(tmp1, tmp2)                                        \
 126         mov     0, tmp1;                                                \
 127 98:     ld      [%g6 + TI_UWINMASK], tmp2;                              \
 128         orcc    %g0, tmp2, %g0;                                         \
 129         add     tmp1, 1, tmp1;                                          \
 130         bne     98b;                                                    \
 131          save   %sp, -64, %sp;                                          \
 132 99:     subcc   tmp1, 1, tmp1;                                          \
 133         bne     99b;                                                    \
 134          restore %g0, %g0, %g0;
 135
 136 #ifndef __ASSEMBLY__
 137
 138 /* This makes sense. Honest it does - Anton */
 139 extern void *srmmu_nocache_pool;
 140 #define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
 141 #define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
 142 #define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
 143
 144 /* Accessing the MMU control register. */
 145 static inline unsigned int srmmu_get_mmureg(void)
 146 {
 147         unsigned int retval;
 148         __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
 149                              "=r" (retval) :
 150                              "i" (ASI_M_MMUREGS));
 151         return retval;
 152 }
 153
 154 static inline void srmmu_set_mmureg(unsigned long regval)
 155 {
 156         __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
 157                              "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
 158
 159 }
 160
 161 static inline void srmmu_set_ctable_ptr(unsigned long paddr)
 162 {
 163         paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
 164         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
 165                              "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
 166                              "i" (ASI_M_MMUREGS) :
 167                              "memory");
 168 }
 169
 170 static inline unsigned long srmmu_get_ctable_ptr(void)
 171 {
 172         unsigned int retval;
 173
 174         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 175                              "=r" (retval) :
 176                              "r" (SRMMU_CTXTBL_PTR),
 177                              "i" (ASI_M_MMUREGS));
 178         return (retval & SRMMU_CTX_PMASK) << 4;
 179 }
 180
 181 static inline void srmmu_set_context(int context)
 182 {
 183         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
 184                              "r" (context), "r" (SRMMU_CTX_REG),
 185                              "i" (ASI_M_MMUREGS) : "memory");
 186 }
 187
 188 static inline int srmmu_get_context(void)
 189 {
 190         register int retval;
 191         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 192                              "=r" (retval) :
 193                              "r" (SRMMU_CTX_REG),
 194                              "i" (ASI_M_MMUREGS));
 195         return retval;
 196 }
 197
 198 static inline unsigned int srmmu_get_fstatus(void)
 199 {
 200         unsigned int retval;
 201
 202         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 203                              "=r" (retval) :
 204                              "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
 205         return retval;
 206 }
 207
 208 static inline unsigned int srmmu_get_faddr(void)
 209 {
 210         unsigned int retval;
 211
 212         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 213                              "=r" (retval) :
 214                              "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
 215         return retval;
 216 }
 217
 218 /* This is guaranteed on all SRMMU's. */
 219 static inline void srmmu_flush_whole_tlb(void)
 220 {
 221         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 222                              "r" (0x400),        /* Flush entire TLB!! */
 223                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 224
 225 }
 226
 227 /* These flush types are not available on all chips... */
 228 static inline void srmmu_flush_tlb_ctx(void)
 229 {
 230         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 231                              "r" (0x300),        /* Flush TLB ctx.. */
 232                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 233
 234 }
 235
 236 static inline void srmmu_flush_tlb_region(unsigned long addr)
 237 {
 238         addr &= SRMMU_PGDIR_MASK;
 239         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 240                              "r" (addr | 0x200), /* Flush TLB region.. */
 241                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 242
 243 }
 244
 245
 246 static inline void srmmu_flush_tlb_segment(unsigned long addr)
 247 {
 248         addr &= SRMMU_REAL_PMD_MASK;
 249         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 250                              "r" (addr | 0x100), /* Flush TLB segment.. */
 251                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 252
 253 }
 254
 255 static inline void srmmu_flush_tlb_page(unsigned long page)
 256 {
 257         page &= PAGE_MASK;
 258         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 259                              "r" (page),        /* Flush TLB page.. */
 260                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 261
 262 }
 263
 264 #ifndef CONFIG_SPARC_LEON
 265 static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
 266 {
 267         unsigned long retval;
 268
 269         vaddr &= PAGE_MASK;
 270         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 271                              "=r" (retval) :
 272                              "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
 273
 274         return retval;
 275 }
 276 #else
 277 #define srmmu_hwprobe(addr) (srmmu_swprobe(addr, 0) & SRMMU_PTE_PMASK)
 278 #endif
 279
 280 static inline int
 281 srmmu_get_pte (unsigned long addr)
 282 {
 283         register unsigned long entry;
 284
 285         __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
 286                                 "=r" (entry):
 287                                 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
 288         return entry;
 289 }
 290
 291 extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
 292 extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
 293
 294 #endif /* !(__ASSEMBLY__) */
 295
 296 #endif /* !(_SPARC_PGTSRMMU_H) */