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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / powerpc / kvm / book3s_paired_singles.c
blobc972b15eae2597c6e62122bb7b1afa502ab73e33
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright Novell Inc 2010
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20 #include <asm/kvm.h>
21 #include <asm/kvm_ppc.h>
22 #include <asm/disassemble.h>
23 #include <asm/kvm_book3s.h>
24 #include <asm/kvm_fpu.h>
25 #include <asm/reg.h>
26 #include <asm/cacheflush.h>
27 #include <linux/vmalloc.h>
28
29 /* #define DEBUG */
30
31 #ifdef DEBUG
32 #define dprintk printk
33 #else
34 #define dprintk(...) do { } while(0);
35 #endif
36
37 #define OP_LFS 48
38 #define OP_LFSU 49
39 #define OP_LFD 50
40 #define OP_LFDU 51
41 #define OP_STFS 52
42 #define OP_STFSU 53
43 #define OP_STFD 54
44 #define OP_STFDU 55
45 #define OP_PSQ_L 56
46 #define OP_PSQ_LU 57
47 #define OP_PSQ_ST 60
48 #define OP_PSQ_STU 61
49
50 #define OP_31_LFSX 535
51 #define OP_31_LFSUX 567
52 #define OP_31_LFDX 599
53 #define OP_31_LFDUX 631
54 #define OP_31_STFSX 663
55 #define OP_31_STFSUX 695
56 #define OP_31_STFX 727
57 #define OP_31_STFUX 759
58 #define OP_31_LWIZX 887
59 #define OP_31_STFIWX 983
60
61 #define OP_59_FADDS 21
62 #define OP_59_FSUBS 20
63 #define OP_59_FSQRTS 22
64 #define OP_59_FDIVS 18
65 #define OP_59_FRES 24
66 #define OP_59_FMULS 25
67 #define OP_59_FRSQRTES 26
68 #define OP_59_FMSUBS 28
69 #define OP_59_FMADDS 29
70 #define OP_59_FNMSUBS 30
71 #define OP_59_FNMADDS 31
72
73 #define OP_63_FCMPU 0
74 #define OP_63_FCPSGN 8
75 #define OP_63_FRSP 12
76 #define OP_63_FCTIW 14
77 #define OP_63_FCTIWZ 15
78 #define OP_63_FDIV 18
79 #define OP_63_FADD 21
80 #define OP_63_FSQRT 22
81 #define OP_63_FSEL 23
82 #define OP_63_FRE 24
83 #define OP_63_FMUL 25
84 #define OP_63_FRSQRTE 26
85 #define OP_63_FMSUB 28
86 #define OP_63_FMADD 29
87 #define OP_63_FNMSUB 30
88 #define OP_63_FNMADD 31
89 #define OP_63_FCMPO 32
90 #define OP_63_MTFSB1 38
91 #define OP_63_FSUB 20
92 #define OP_63_FNEG 40
93 #define OP_63_MCRFS 64
94 #define OP_63_MTFSB0 70
95 #define OP_63_FMR 72
96 #define OP_63_MTFSFI 134
97 #define OP_63_FABS 264
98 #define OP_63_MFFS 583
99 #define OP_63_MTFSF 711
100
101 #define OP_4X_PS_CMPU0 0
102 #define OP_4X_PSQ_LX 6
103 #define OP_4XW_PSQ_STX 7
104 #define OP_4A_PS_SUM0 10
105 #define OP_4A_PS_SUM1 11
106 #define OP_4A_PS_MULS0 12
107 #define OP_4A_PS_MULS1 13
108 #define OP_4A_PS_MADDS0 14
109 #define OP_4A_PS_MADDS1 15
110 #define OP_4A_PS_DIV 18
111 #define OP_4A_PS_SUB 20
112 #define OP_4A_PS_ADD 21
113 #define OP_4A_PS_SEL 23
114 #define OP_4A_PS_RES 24
115 #define OP_4A_PS_MUL 25
116 #define OP_4A_PS_RSQRTE 26
117 #define OP_4A_PS_MSUB 28
118 #define OP_4A_PS_MADD 29
119 #define OP_4A_PS_NMSUB 30
120 #define OP_4A_PS_NMADD 31
121 #define OP_4X_PS_CMPO0 32
122 #define OP_4X_PSQ_LUX 38
123 #define OP_4XW_PSQ_STUX 39
124 #define OP_4X_PS_NEG 40
125 #define OP_4X_PS_CMPU1 64
126 #define OP_4X_PS_MR 72
127 #define OP_4X_PS_CMPO1 96
128 #define OP_4X_PS_NABS 136
129 #define OP_4X_PS_ABS 264
130 #define OP_4X_PS_MERGE00 528
131 #define OP_4X_PS_MERGE01 560
132 #define OP_4X_PS_MERGE10 592
133 #define OP_4X_PS_MERGE11 624
134
135 #define SCALAR_NONE 0
136 #define SCALAR_HIGH (1 << 0)
137 #define SCALAR_LOW (1 << 1)
138 #define SCALAR_NO_PS0 (1 << 2)
139 #define SCALAR_NO_PS1 (1 << 3)
140
141 #define GQR_ST_TYPE_MASK 0x00000007
142 #define GQR_ST_TYPE_SHIFT 0
143 #define GQR_ST_SCALE_MASK 0x00003f00
144 #define GQR_ST_SCALE_SHIFT 8
145 #define GQR_LD_TYPE_MASK 0x00070000
146 #define GQR_LD_TYPE_SHIFT 16
147 #define GQR_LD_SCALE_MASK 0x3f000000
148 #define GQR_LD_SCALE_SHIFT 24
149
150 #define GQR_QUANTIZE_FLOAT 0
151 #define GQR_QUANTIZE_U8 4
152 #define GQR_QUANTIZE_U16 5
153 #define GQR_QUANTIZE_S8 6
154 #define GQR_QUANTIZE_S16 7
155
156 #define FPU_LS_SINGLE 0
157 #define FPU_LS_DOUBLE 1
158 #define FPU_LS_SINGLE_LOW 2
159
160 static inline void kvmppc_sync_qpr(struct kvm_vcpu *vcpu, int rt)
161 {
162 kvm_cvt_df(&vcpu->arch.fpr[rt], &vcpu->arch.qpr[rt], &vcpu->arch.fpscr);
163 }
164
165 static void kvmppc_inject_pf(struct kvm_vcpu *vcpu, ulong eaddr, bool is_store)
166 {
167 u64 dsisr;
168
169 vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 33, 36, 0);
170 vcpu->arch.msr = kvmppc_set_field(vcpu->arch.msr, 42, 47, 0);
171 vcpu->arch.dear = eaddr;
172 /* Page Fault */
173 dsisr = kvmppc_set_field(0, 33, 33, 1);
174 if (is_store)
175 to_book3s(vcpu)->dsisr = kvmppc_set_field(dsisr, 38, 38, 1);
176 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE);
177 }
178
179 static int kvmppc_emulate_fpr_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
180 int rs, ulong addr, int ls_type)
181 {
182 int emulated = EMULATE_FAIL;
183 int r;
184 char tmp[8];
185 int len = sizeof(u32);
186
187 if (ls_type == FPU_LS_DOUBLE)
188 len = sizeof(u64);
189
190 /* read from memory */
191 r = kvmppc_ld(vcpu, &addr, len, tmp, true);
192 vcpu->arch.paddr_accessed = addr;
193
194 if (r < 0) {
195 kvmppc_inject_pf(vcpu, addr, false);
196 goto done_load;
197 } else if (r == EMULATE_DO_MMIO) {
198 emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, len, 1);
199 goto done_load;
200 }
201
202 emulated = EMULATE_DONE;
203
204 /* put in registers */
205 switch (ls_type) {
206 case FPU_LS_SINGLE:
207 kvm_cvt_fd((u32*)tmp, &vcpu->arch.fpr[rs], &vcpu->arch.fpscr);
208 vcpu->arch.qpr[rs] = *((u32*)tmp);
209 break;
210 case FPU_LS_DOUBLE:
211 vcpu->arch.fpr[rs] = *((u64*)tmp);
212 break;
213 }
214
215 dprintk(KERN_INFO "KVM: FPR_LD [0x%llx] at 0x%lx (%d)\n", *(u64*)tmp,
216 addr, len);
217
218 done_load:
219 return emulated;
220 }
221
222 static int kvmppc_emulate_fpr_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
223 int rs, ulong addr, int ls_type)
224 {
225 int emulated = EMULATE_FAIL;
226 int r;
227 char tmp[8];
228 u64 val;
229 int len;
230
231 switch (ls_type) {
232 case FPU_LS_SINGLE:
233 kvm_cvt_df(&vcpu->arch.fpr[rs], (u32*)tmp, &vcpu->arch.fpscr);
234 val = *((u32*)tmp);
235 len = sizeof(u32);
236 break;
237 case FPU_LS_SINGLE_LOW:
238 *((u32*)tmp) = vcpu->arch.fpr[rs];
239 val = vcpu->arch.fpr[rs] & 0xffffffff;
240 len = sizeof(u32);
241 break;
242 case FPU_LS_DOUBLE:
243 *((u64*)tmp) = vcpu->arch.fpr[rs];
244 val = vcpu->arch.fpr[rs];
245 len = sizeof(u64);
246 break;
247 default:
248 val = 0;
249 len = 0;
250 }
251
252 r = kvmppc_st(vcpu, &addr, len, tmp, true);
253 vcpu->arch.paddr_accessed = addr;
254 if (r < 0) {
255 kvmppc_inject_pf(vcpu, addr, true);
256 } else if (r == EMULATE_DO_MMIO) {
257 emulated = kvmppc_handle_store(run, vcpu, val, len, 1);
258 } else {
259 emulated = EMULATE_DONE;
260 }
261
262 dprintk(KERN_INFO "KVM: FPR_ST [0x%llx] at 0x%lx (%d)\n",
263 val, addr, len);
264
265 return emulated;
266 }
267
268 static int kvmppc_emulate_psq_load(struct kvm_run *run, struct kvm_vcpu *vcpu,
269 int rs, ulong addr, bool w, int i)
270 {
271 int emulated = EMULATE_FAIL;
272 int r;
273 float one = 1.0;
274 u32 tmp[2];
275
276 /* read from memory */
277 if (w) {
278 r = kvmppc_ld(vcpu, &addr, sizeof(u32), tmp, true);
279 memcpy(&tmp[1], &one, sizeof(u32));
280 } else {
281 r = kvmppc_ld(vcpu, &addr, sizeof(u32) * 2, tmp, true);
282 }
283 vcpu->arch.paddr_accessed = addr;
284 if (r < 0) {
285 kvmppc_inject_pf(vcpu, addr, false);
286 goto done_load;
287 } else if ((r == EMULATE_DO_MMIO) && w) {
288 emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FPR | rs, 4, 1);
289 vcpu->arch.qpr[rs] = tmp[1];
290 goto done_load;
291 } else if (r == EMULATE_DO_MMIO) {
292 emulated = kvmppc_handle_load(run, vcpu, KVM_REG_FQPR | rs, 8, 1);
293 goto done_load;
294 }
295
296 emulated = EMULATE_DONE;
297
298 /* put in registers */
299 kvm_cvt_fd(&tmp[0], &vcpu->arch.fpr[rs], &vcpu->arch.fpscr);
300 vcpu->arch.qpr[rs] = tmp[1];
301
302 dprintk(KERN_INFO "KVM: PSQ_LD [0x%x, 0x%x] at 0x%lx (%d)\n", tmp[0],
303 tmp[1], addr, w ? 4 : 8);
304
305 done_load:
306 return emulated;
307 }
308
309 static int kvmppc_emulate_psq_store(struct kvm_run *run, struct kvm_vcpu *vcpu,
310 int rs, ulong addr, bool w, int i)
311 {
312 int emulated = EMULATE_FAIL;
313 int r;
314 u32 tmp[2];
315 int len = w ? sizeof(u32) : sizeof(u64);
316
317 kvm_cvt_df(&vcpu->arch.fpr[rs], &tmp[0], &vcpu->arch.fpscr);
318 tmp[1] = vcpu->arch.qpr[rs];
319
320 r = kvmppc_st(vcpu, &addr, len, tmp, true);
321 vcpu->arch.paddr_accessed = addr;
322 if (r < 0) {
323 kvmppc_inject_pf(vcpu, addr, true);
324 } else if ((r == EMULATE_DO_MMIO) && w) {
325 emulated = kvmppc_handle_store(run, vcpu, tmp[0], 4, 1);
326 } else if (r == EMULATE_DO_MMIO) {
327 u64 val = ((u64)tmp[0] << 32) | tmp[1];
328 emulated = kvmppc_handle_store(run, vcpu, val, 8, 1);
329 } else {
330 emulated = EMULATE_DONE;
331 }
332
333 dprintk(KERN_INFO "KVM: PSQ_ST [0x%x, 0x%x] at 0x%lx (%d)\n",
334 tmp[0], tmp[1], addr, len);
335
336 return emulated;
337 }
338
339 /*
340 * Cuts out inst bits with ordering according to spec.
341 * That means the leftmost bit is zero. All given bits are included.
342 */
343 static inline u32 inst_get_field(u32 inst, int msb, int lsb)
344 {
345 return kvmppc_get_field(inst, msb + 32, lsb + 32);
346 }
347
348 /*
349 * Replaces inst bits with ordering according to spec.
350 */
351 static inline u32 inst_set_field(u32 inst, int msb, int lsb, int value)
352 {
353 return kvmppc_set_field(inst, msb + 32, lsb + 32, value);
354 }
355
356 bool kvmppc_inst_is_paired_single(struct kvm_vcpu *vcpu, u32 inst)
357 {
358 if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE))
359 return false;
360
361 switch (get_op(inst)) {
362 case OP_PSQ_L:
363 case OP_PSQ_LU:
364 case OP_PSQ_ST:
365 case OP_PSQ_STU:
366 case OP_LFS:
367 case OP_LFSU:
368 case OP_LFD:
369 case OP_LFDU:
370 case OP_STFS:
371 case OP_STFSU:
372 case OP_STFD:
373 case OP_STFDU:
374 return true;
375 case 4:
376 /* X form */
377 switch (inst_get_field(inst, 21, 30)) {
378 case OP_4X_PS_CMPU0:
379 case OP_4X_PSQ_LX:
380 case OP_4X_PS_CMPO0:
381 case OP_4X_PSQ_LUX:
382 case OP_4X_PS_NEG:
383 case OP_4X_PS_CMPU1:
384 case OP_4X_PS_MR:
385 case OP_4X_PS_CMPO1:
386 case OP_4X_PS_NABS:
387 case OP_4X_PS_ABS:
388 case OP_4X_PS_MERGE00:
389 case OP_4X_PS_MERGE01:
390 case OP_4X_PS_MERGE10:
391 case OP_4X_PS_MERGE11:
392 return true;
393 }
394 /* XW form */
395 switch (inst_get_field(inst, 25, 30)) {
396 case OP_4XW_PSQ_STX:
397 case OP_4XW_PSQ_STUX:
398 return true;
399 }
400 /* A form */
401 switch (inst_get_field(inst, 26, 30)) {
402 case OP_4A_PS_SUM1:
403 case OP_4A_PS_SUM0:
404 case OP_4A_PS_MULS0:
405 case OP_4A_PS_MULS1:
406 case OP_4A_PS_MADDS0:
407 case OP_4A_PS_MADDS1:
408 case OP_4A_PS_DIV:
409 case OP_4A_PS_SUB:
410 case OP_4A_PS_ADD:
411 case OP_4A_PS_SEL:
412 case OP_4A_PS_RES:
413 case OP_4A_PS_MUL:
414 case OP_4A_PS_RSQRTE:
415 case OP_4A_PS_MSUB:
416 case OP_4A_PS_MADD:
417 case OP_4A_PS_NMSUB:
418 case OP_4A_PS_NMADD:
419 return true;
420 }
421 break;
422 case 59:
423 switch (inst_get_field(inst, 21, 30)) {
424 case OP_59_FADDS:
425 case OP_59_FSUBS:
426 case OP_59_FDIVS:
427 case OP_59_FRES:
428 case OP_59_FRSQRTES:
429 return true;
430 }
431 switch (inst_get_field(inst, 26, 30)) {
432 case OP_59_FMULS:
433 case OP_59_FMSUBS:
434 case OP_59_FMADDS:
435 case OP_59_FNMSUBS:
436 case OP_59_FNMADDS:
437 return true;
438 }
439 break;
440 case 63:
441 switch (inst_get_field(inst, 21, 30)) {
442 case OP_63_MTFSB0:
443 case OP_63_MTFSB1:
444 case OP_63_MTFSF:
445 case OP_63_MTFSFI:
446 case OP_63_MCRFS:
447 case OP_63_MFFS:
448 case OP_63_FCMPU:
449 case OP_63_FCMPO:
450 case OP_63_FNEG:
451 case OP_63_FMR:
452 case OP_63_FABS:
453 case OP_63_FRSP:
454 case OP_63_FDIV:
455 case OP_63_FADD:
456 case OP_63_FSUB:
457 case OP_63_FCTIW:
458 case OP_63_FCTIWZ:
459 case OP_63_FRSQRTE:
460 case OP_63_FCPSGN:
461 return true;
462 }
463 switch (inst_get_field(inst, 26, 30)) {
464 case OP_63_FMUL:
465 case OP_63_FSEL:
466 case OP_63_FMSUB:
467 case OP_63_FMADD:
468 case OP_63_FNMSUB:
469 case OP_63_FNMADD:
470 return true;
471 }
472 break;
473 case 31:
474 switch (inst_get_field(inst, 21, 30)) {
475 case OP_31_LFSX:
476 case OP_31_LFSUX:
477 case OP_31_LFDX:
478 case OP_31_LFDUX:
479 case OP_31_STFSX:
480 case OP_31_STFSUX:
481 case OP_31_STFX:
482 case OP_31_STFUX:
483 case OP_31_STFIWX:
484 return true;
485 }
486 break;
487 }
488
489 return false;
490 }
491
492 static int get_d_signext(u32 inst)
493 {
494 int d = inst & 0x8ff;
495
496 if (d & 0x800)
497 return -(d & 0x7ff);
498
499 return (d & 0x7ff);
500 }
501
502 static int kvmppc_ps_three_in(struct kvm_vcpu *vcpu, bool rc,
503 int reg_out, int reg_in1, int reg_in2,
504 int reg_in3, int scalar,
505 void (*func)(u64 *fpscr,
506 u32 *dst, u32 *src1,
507 u32 *src2, u32 *src3))
508 {
509 u32 *qpr = vcpu->arch.qpr;
510 u64 *fpr = vcpu->arch.fpr;
511 u32 ps0_out;
512 u32 ps0_in1, ps0_in2, ps0_in3;
513 u32 ps1_in1, ps1_in2, ps1_in3;
514
515 /* RC */
516 WARN_ON(rc);
517
518 /* PS0 */
519 kvm_cvt_df(&fpr[reg_in1], &ps0_in1, &vcpu->arch.fpscr);
520 kvm_cvt_df(&fpr[reg_in2], &ps0_in2, &vcpu->arch.fpscr);
521 kvm_cvt_df(&fpr[reg_in3], &ps0_in3, &vcpu->arch.fpscr);
522
523 if (scalar & SCALAR_LOW)
524 ps0_in2 = qpr[reg_in2];
525
526 func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2, &ps0_in3);
527
528 dprintk(KERN_INFO "PS3 ps0 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
529 ps0_in1, ps0_in2, ps0_in3, ps0_out);
530
531 if (!(scalar & SCALAR_NO_PS0))
532 kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
533
534 /* PS1 */
535 ps1_in1 = qpr[reg_in1];
536 ps1_in2 = qpr[reg_in2];
537 ps1_in3 = qpr[reg_in3];
538
539 if (scalar & SCALAR_HIGH)
540 ps1_in2 = ps0_in2;
541
542 if (!(scalar & SCALAR_NO_PS1))
543 func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in1, &ps1_in2, &ps1_in3);
544
545 dprintk(KERN_INFO "PS3 ps1 -> f(0x%x, 0x%x, 0x%x) = 0x%x\n",
546 ps1_in1, ps1_in2, ps1_in3, qpr[reg_out]);
547
548 return EMULATE_DONE;
549 }
550
551 static int kvmppc_ps_two_in(struct kvm_vcpu *vcpu, bool rc,
552 int reg_out, int reg_in1, int reg_in2,
553 int scalar,
554 void (*func)(u64 *fpscr,
555 u32 *dst, u32 *src1,
556 u32 *src2))
557 {
558 u32 *qpr = vcpu->arch.qpr;
559 u64 *fpr = vcpu->arch.fpr;
560 u32 ps0_out;
561 u32 ps0_in1, ps0_in2;
562 u32 ps1_out;
563 u32 ps1_in1, ps1_in2;
564
565 /* RC */
566 WARN_ON(rc);
567
568 /* PS0 */
569 kvm_cvt_df(&fpr[reg_in1], &ps0_in1, &vcpu->arch.fpscr);
570
571 if (scalar & SCALAR_LOW)
572 ps0_in2 = qpr[reg_in2];
573 else
574 kvm_cvt_df(&fpr[reg_in2], &ps0_in2, &vcpu->arch.fpscr);
575
576 func(&vcpu->arch.fpscr, &ps0_out, &ps0_in1, &ps0_in2);
577
578 if (!(scalar & SCALAR_NO_PS0)) {
579 dprintk(KERN_INFO "PS2 ps0 -> f(0x%x, 0x%x) = 0x%x\n",
580 ps0_in1, ps0_in2, ps0_out);
581
582 kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
583 }
584
585 /* PS1 */
586 ps1_in1 = qpr[reg_in1];
587 ps1_in2 = qpr[reg_in2];
588
589 if (scalar & SCALAR_HIGH)
590 ps1_in2 = ps0_in2;
591
592 func(&vcpu->arch.fpscr, &ps1_out, &ps1_in1, &ps1_in2);
593
594 if (!(scalar & SCALAR_NO_PS1)) {
595 qpr[reg_out] = ps1_out;
596
597 dprintk(KERN_INFO "PS2 ps1 -> f(0x%x, 0x%x) = 0x%x\n",
598 ps1_in1, ps1_in2, qpr[reg_out]);
599 }
600
601 return EMULATE_DONE;
602 }
603
604 static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
605 int reg_out, int reg_in,
606 void (*func)(u64 *t,
607 u32 *dst, u32 *src1))
608 {
609 u32 *qpr = vcpu->arch.qpr;
610 u64 *fpr = vcpu->arch.fpr;
611 u32 ps0_out, ps0_in;
612 u32 ps1_in;
613
614 /* RC */
615 WARN_ON(rc);
616
617 /* PS0 */
618 kvm_cvt_df(&fpr[reg_in], &ps0_in, &vcpu->arch.fpscr);
619 func(&vcpu->arch.fpscr, &ps0_out, &ps0_in);
620
621 dprintk(KERN_INFO "PS1 ps0 -> f(0x%x) = 0x%x\n",
622 ps0_in, ps0_out);
623
624 kvm_cvt_fd(&ps0_out, &fpr[reg_out], &vcpu->arch.fpscr);
625
626 /* PS1 */
627 ps1_in = qpr[reg_in];
628 func(&vcpu->arch.fpscr, &qpr[reg_out], &ps1_in);
629
630 dprintk(KERN_INFO "PS1 ps1 -> f(0x%x) = 0x%x\n",
631 ps1_in, qpr[reg_out]);
632
633 return EMULATE_DONE;
634 }
635
636 int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu)
637 {
638 u32 inst = kvmppc_get_last_inst(vcpu);
639 enum emulation_result emulated = EMULATE_DONE;
640
641 int ax_rd = inst_get_field(inst, 6, 10);
642 int ax_ra = inst_get_field(inst, 11, 15);
643 int ax_rb = inst_get_field(inst, 16, 20);
644 int ax_rc = inst_get_field(inst, 21, 25);
645 short full_d = inst_get_field(inst, 16, 31);
646
647 u64 *fpr_d = &vcpu->arch.fpr[ax_rd];
648 u64 *fpr_a = &vcpu->arch.fpr[ax_ra];
649 u64 *fpr_b = &vcpu->arch.fpr[ax_rb];
650 u64 *fpr_c = &vcpu->arch.fpr[ax_rc];
651
652 bool rcomp = (inst & 1) ? true : false;
653 u32 cr = kvmppc_get_cr(vcpu);
654 #ifdef DEBUG
655 int i;
656 #endif
657
658 if (!kvmppc_inst_is_paired_single(vcpu, inst))
659 return EMULATE_FAIL;
660
661 if (!(vcpu->arch.msr & MSR_FP)) {
662 kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL);
663 return EMULATE_AGAIN;
664 }
665
666 kvmppc_giveup_ext(vcpu, MSR_FP);
667 preempt_disable();
668 enable_kernel_fp();
669 /* Do we need to clear FE0 / FE1 here? Don't think so. */
670
671 #ifdef DEBUG
672 for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
673 u32 f;
674 kvm_cvt_df(&vcpu->arch.fpr[i], &f, &vcpu->arch.fpscr);
675 dprintk(KERN_INFO "FPR[%d] = 0x%x / 0x%llx QPR[%d] = 0x%x\n",
676 i, f, vcpu->arch.fpr[i], i, vcpu->arch.qpr[i]);
677 }
678 #endif
679
680 switch (get_op(inst)) {
681 case OP_PSQ_L:
682 {
683 ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
684 bool w = inst_get_field(inst, 16, 16) ? true : false;
685 int i = inst_get_field(inst, 17, 19);
686
687 addr += get_d_signext(inst);
688 emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
689 break;
690 }
691 case OP_PSQ_LU:
692 {
693 ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
694 bool w = inst_get_field(inst, 16, 16) ? true : false;
695 int i = inst_get_field(inst, 17, 19);
696
697 addr += get_d_signext(inst);
698 emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
699
700 if (emulated == EMULATE_DONE)
701 kvmppc_set_gpr(vcpu, ax_ra, addr);
702 break;
703 }
704 case OP_PSQ_ST:
705 {
706 ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
707 bool w = inst_get_field(inst, 16, 16) ? true : false;
708 int i = inst_get_field(inst, 17, 19);
709
710 addr += get_d_signext(inst);
711 emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
712 break;
713 }
714 case OP_PSQ_STU:
715 {
716 ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
717 bool w = inst_get_field(inst, 16, 16) ? true : false;
718 int i = inst_get_field(inst, 17, 19);
719
720 addr += get_d_signext(inst);
721 emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
722
723 if (emulated == EMULATE_DONE)
724 kvmppc_set_gpr(vcpu, ax_ra, addr);
725 break;
726 }
727 case 4:
728 /* X form */
729 switch (inst_get_field(inst, 21, 30)) {
730 case OP_4X_PS_CMPU0:
731 emulated = EMULATE_FAIL;
732 break;
733 case OP_4X_PSQ_LX:
734 {
735 ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
736 bool w = inst_get_field(inst, 21, 21) ? true : false;
737 int i = inst_get_field(inst, 22, 24);
738
739 addr += kvmppc_get_gpr(vcpu, ax_rb);
740 emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
741 break;
742 }
743 case OP_4X_PS_CMPO0:
744 emulated = EMULATE_FAIL;
745 break;
746 case OP_4X_PSQ_LUX:
747 {
748 ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
749 bool w = inst_get_field(inst, 21, 21) ? true : false;
750 int i = inst_get_field(inst, 22, 24);
751
752 addr += kvmppc_get_gpr(vcpu, ax_rb);
753 emulated = kvmppc_emulate_psq_load(run, vcpu, ax_rd, addr, w, i);
754
755 if (emulated == EMULATE_DONE)
756 kvmppc_set_gpr(vcpu, ax_ra, addr);
757 break;
758 }
759 case OP_4X_PS_NEG:
760 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
761 vcpu->arch.fpr[ax_rd] ^= 0x8000000000000000ULL;
762 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
763 vcpu->arch.qpr[ax_rd] ^= 0x80000000;
764 break;
765 case OP_4X_PS_CMPU1:
766 emulated = EMULATE_FAIL;
767 break;
768 case OP_4X_PS_MR:
769 WARN_ON(rcomp);
770 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
771 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
772 break;
773 case OP_4X_PS_CMPO1:
774 emulated = EMULATE_FAIL;
775 break;
776 case OP_4X_PS_NABS:
777 WARN_ON(rcomp);
778 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
779 vcpu->arch.fpr[ax_rd] |= 0x8000000000000000ULL;
780 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
781 vcpu->arch.qpr[ax_rd] |= 0x80000000;
782 break;
783 case OP_4X_PS_ABS:
784 WARN_ON(rcomp);
785 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rb];
786 vcpu->arch.fpr[ax_rd] &= ~0x8000000000000000ULL;
787 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
788 vcpu->arch.qpr[ax_rd] &= ~0x80000000;
789 break;
790 case OP_4X_PS_MERGE00:
791 WARN_ON(rcomp);
792 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
793 /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
794 kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
795 &vcpu->arch.qpr[ax_rd],
796 &vcpu->arch.fpscr);
797 break;
798 case OP_4X_PS_MERGE01:
799 WARN_ON(rcomp);
800 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_ra];
801 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
802 break;
803 case OP_4X_PS_MERGE10:
804 WARN_ON(rcomp);
805 /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
806 kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
807 &vcpu->arch.fpr[ax_rd],
808 &vcpu->arch.fpscr);
809 /* vcpu->arch.qpr[ax_rd] = vcpu->arch.fpr[ax_rb]; */
810 kvm_cvt_df(&vcpu->arch.fpr[ax_rb],
811 &vcpu->arch.qpr[ax_rd],
812 &vcpu->arch.fpscr);
813 break;
814 case OP_4X_PS_MERGE11:
815 WARN_ON(rcomp);
816 /* vcpu->arch.fpr[ax_rd] = vcpu->arch.qpr[ax_ra]; */
817 kvm_cvt_fd(&vcpu->arch.qpr[ax_ra],
818 &vcpu->arch.fpr[ax_rd],
819 &vcpu->arch.fpscr);
820 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rb];
821 break;
822 }
823 /* XW form */
824 switch (inst_get_field(inst, 25, 30)) {
825 case OP_4XW_PSQ_STX:
826 {
827 ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
828 bool w = inst_get_field(inst, 21, 21) ? true : false;
829 int i = inst_get_field(inst, 22, 24);
830
831 addr += kvmppc_get_gpr(vcpu, ax_rb);
832 emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
833 break;
834 }
835 case OP_4XW_PSQ_STUX:
836 {
837 ulong addr = kvmppc_get_gpr(vcpu, ax_ra);
838 bool w = inst_get_field(inst, 21, 21) ? true : false;
839 int i = inst_get_field(inst, 22, 24);
840
841 addr += kvmppc_get_gpr(vcpu, ax_rb);
842 emulated = kvmppc_emulate_psq_store(run, vcpu, ax_rd, addr, w, i);
843
844 if (emulated == EMULATE_DONE)
845 kvmppc_set_gpr(vcpu, ax_ra, addr);
846 break;
847 }
848 }
849 /* A form */
850 switch (inst_get_field(inst, 26, 30)) {
851 case OP_4A_PS_SUM1:
852 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
853 ax_rb, ax_ra, SCALAR_NO_PS0 | SCALAR_HIGH, fps_fadds);
854 vcpu->arch.fpr[ax_rd] = vcpu->arch.fpr[ax_rc];
855 break;
856 case OP_4A_PS_SUM0:
857 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
858 ax_ra, ax_rb, SCALAR_NO_PS1 | SCALAR_LOW, fps_fadds);
859 vcpu->arch.qpr[ax_rd] = vcpu->arch.qpr[ax_rc];
860 break;
861 case OP_4A_PS_MULS0:
862 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
863 ax_ra, ax_rc, SCALAR_HIGH, fps_fmuls);
864 break;
865 case OP_4A_PS_MULS1:
866 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
867 ax_ra, ax_rc, SCALAR_LOW, fps_fmuls);
868 break;
869 case OP_4A_PS_MADDS0:
870 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
871 ax_ra, ax_rc, ax_rb, SCALAR_HIGH, fps_fmadds);
872 break;
873 case OP_4A_PS_MADDS1:
874 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
875 ax_ra, ax_rc, ax_rb, SCALAR_LOW, fps_fmadds);
876 break;
877 case OP_4A_PS_DIV:
878 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
879 ax_ra, ax_rb, SCALAR_NONE, fps_fdivs);
880 break;
881 case OP_4A_PS_SUB:
882 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
883 ax_ra, ax_rb, SCALAR_NONE, fps_fsubs);
884 break;
885 case OP_4A_PS_ADD:
886 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
887 ax_ra, ax_rb, SCALAR_NONE, fps_fadds);
888 break;
889 case OP_4A_PS_SEL:
890 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
891 ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fsel);
892 break;
893 case OP_4A_PS_RES:
894 emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
895 ax_rb, fps_fres);
896 break;
897 case OP_4A_PS_MUL:
898 emulated = kvmppc_ps_two_in(vcpu, rcomp, ax_rd,
899 ax_ra, ax_rc, SCALAR_NONE, fps_fmuls);
900 break;
901 case OP_4A_PS_RSQRTE:
902 emulated = kvmppc_ps_one_in(vcpu, rcomp, ax_rd,
903 ax_rb, fps_frsqrte);
904 break;
905 case OP_4A_PS_MSUB:
906 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
907 ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmsubs);
908 break;
909 case OP_4A_PS_MADD:
910 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
911 ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fmadds);
912 break;
913 case OP_4A_PS_NMSUB:
914 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
915 ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmsubs);
916 break;
917 case OP_4A_PS_NMADD:
918 emulated = kvmppc_ps_three_in(vcpu, rcomp, ax_rd,
919 ax_ra, ax_rc, ax_rb, SCALAR_NONE, fps_fnmadds);
920 break;
921 }
922 break;
923
924 /* Real FPU operations */
925
926 case OP_LFS:
927 {
928 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
929
930 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
931 FPU_LS_SINGLE);
932 break;
933 }
934 case OP_LFSU:
935 {
936 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
937
938 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
939 FPU_LS_SINGLE);
940
941 if (emulated == EMULATE_DONE)
942 kvmppc_set_gpr(vcpu, ax_ra, addr);
943 break;
944 }
945 case OP_LFD:
946 {
947 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
948
949 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
950 FPU_LS_DOUBLE);
951 break;
952 }
953 case OP_LFDU:
954 {
955 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
956
957 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd, addr,
958 FPU_LS_DOUBLE);
959
960 if (emulated == EMULATE_DONE)
961 kvmppc_set_gpr(vcpu, ax_ra, addr);
962 break;
963 }
964 case OP_STFS:
965 {
966 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
967
968 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
969 FPU_LS_SINGLE);
970 break;
971 }
972 case OP_STFSU:
973 {
974 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
975
976 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
977 FPU_LS_SINGLE);
978
979 if (emulated == EMULATE_DONE)
980 kvmppc_set_gpr(vcpu, ax_ra, addr);
981 break;
982 }
983 case OP_STFD:
984 {
985 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) + full_d;
986
987 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
988 FPU_LS_DOUBLE);
989 break;
990 }
991 case OP_STFDU:
992 {
993 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) + full_d;
994
995 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd, addr,
996 FPU_LS_DOUBLE);
997
998 if (emulated == EMULATE_DONE)
999 kvmppc_set_gpr(vcpu, ax_ra, addr);
1000 break;
1001 }
1002 case 31:
1003 switch (inst_get_field(inst, 21, 30)) {
1004 case OP_31_LFSX:
1005 {
1006 ulong addr = ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0;
1007
1008 addr += kvmppc_get_gpr(vcpu, ax_rb);
1009 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
1010 addr, FPU_LS_SINGLE);
1011 break;
1012 }
1013 case OP_31_LFSUX:
1014 {
1015 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
1016 kvmppc_get_gpr(vcpu, ax_rb);
1017
1018 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
1019 addr, FPU_LS_SINGLE);
1020
1021 if (emulated == EMULATE_DONE)
1022 kvmppc_set_gpr(vcpu, ax_ra, addr);
1023 break;
1024 }
1025 case OP_31_LFDX:
1026 {
1027 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
1028 kvmppc_get_gpr(vcpu, ax_rb);
1029
1030 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
1031 addr, FPU_LS_DOUBLE);
1032 break;
1033 }
1034 case OP_31_LFDUX:
1035 {
1036 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
1037 kvmppc_get_gpr(vcpu, ax_rb);
1038
1039 emulated = kvmppc_emulate_fpr_load(run, vcpu, ax_rd,
1040 addr, FPU_LS_DOUBLE);
1041
1042 if (emulated == EMULATE_DONE)
1043 kvmppc_set_gpr(vcpu, ax_ra, addr);
1044 break;
1045 }
1046 case OP_31_STFSX:
1047 {
1048 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
1049 kvmppc_get_gpr(vcpu, ax_rb);
1050
1051 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
1052 addr, FPU_LS_SINGLE);
1053 break;
1054 }
1055 case OP_31_STFSUX:
1056 {
1057 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
1058 kvmppc_get_gpr(vcpu, ax_rb);
1059
1060 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
1061 addr, FPU_LS_SINGLE);
1062
1063 if (emulated == EMULATE_DONE)
1064 kvmppc_set_gpr(vcpu, ax_ra, addr);
1065 break;
1066 }
1067 case OP_31_STFX:
1068 {
1069 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
1070 kvmppc_get_gpr(vcpu, ax_rb);
1071
1072 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
1073 addr, FPU_LS_DOUBLE);
1074 break;
1075 }
1076 case OP_31_STFUX:
1077 {
1078 ulong addr = kvmppc_get_gpr(vcpu, ax_ra) +
1079 kvmppc_get_gpr(vcpu, ax_rb);
1080
1081 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
1082 addr, FPU_LS_DOUBLE);
1083
1084 if (emulated == EMULATE_DONE)
1085 kvmppc_set_gpr(vcpu, ax_ra, addr);
1086 break;
1087 }
1088 case OP_31_STFIWX:
1089 {
1090 ulong addr = (ax_ra ? kvmppc_get_gpr(vcpu, ax_ra) : 0) +
1091 kvmppc_get_gpr(vcpu, ax_rb);
1092
1093 emulated = kvmppc_emulate_fpr_store(run, vcpu, ax_rd,
1094 addr,
1095 FPU_LS_SINGLE_LOW);
1096 break;
1097 }
1098 break;
1099 }
1100 break;
1101 case 59:
1102 switch (inst_get_field(inst, 21, 30)) {
1103 case OP_59_FADDS:
1104 fpd_fadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1105 kvmppc_sync_qpr(vcpu, ax_rd);
1106 break;
1107 case OP_59_FSUBS:
1108 fpd_fsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1109 kvmppc_sync_qpr(vcpu, ax_rd);
1110 break;
1111 case OP_59_FDIVS:
1112 fpd_fdivs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1113 kvmppc_sync_qpr(vcpu, ax_rd);
1114 break;
1115 case OP_59_FRES:
1116 fpd_fres(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1117 kvmppc_sync_qpr(vcpu, ax_rd);
1118 break;
1119 case OP_59_FRSQRTES:
1120 fpd_frsqrtes(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1121 kvmppc_sync_qpr(vcpu, ax_rd);
1122 break;
1123 }
1124 switch (inst_get_field(inst, 26, 30)) {
1125 case OP_59_FMULS:
1126 fpd_fmuls(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
1127 kvmppc_sync_qpr(vcpu, ax_rd);
1128 break;
1129 case OP_59_FMSUBS:
1130 fpd_fmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1131 kvmppc_sync_qpr(vcpu, ax_rd);
1132 break;
1133 case OP_59_FMADDS:
1134 fpd_fmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1135 kvmppc_sync_qpr(vcpu, ax_rd);
1136 break;
1137 case OP_59_FNMSUBS:
1138 fpd_fnmsubs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1139 kvmppc_sync_qpr(vcpu, ax_rd);
1140 break;
1141 case OP_59_FNMADDS:
1142 fpd_fnmadds(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1143 kvmppc_sync_qpr(vcpu, ax_rd);
1144 break;
1145 }
1146 break;
1147 case 63:
1148 switch (inst_get_field(inst, 21, 30)) {
1149 case OP_63_MTFSB0:
1150 case OP_63_MTFSB1:
1151 case OP_63_MCRFS:
1152 case OP_63_MTFSFI:
1153 break;
1154 case OP_63_MFFS:
1155 *fpr_d = vcpu->arch.fpscr;
1156 break;
1157 case OP_63_MTFSF:
1158 vcpu->arch.fpscr = *fpr_b;
1159 break;
1160 case OP_63_FCMPU:
1161 {
1162 u32 tmp_cr;
1163 u32 cr0_mask = 0xf0000000;
1164 u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
1165
1166 fpd_fcmpu(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
1167 cr &= ~(cr0_mask >> cr_shift);
1168 cr |= (cr & cr0_mask) >> cr_shift;
1169 break;
1170 }
1171 case OP_63_FCMPO:
1172 {
1173 u32 tmp_cr;
1174 u32 cr0_mask = 0xf0000000;
1175 u32 cr_shift = inst_get_field(inst, 6, 8) * 4;
1176
1177 fpd_fcmpo(&vcpu->arch.fpscr, &tmp_cr, fpr_a, fpr_b);
1178 cr &= ~(cr0_mask >> cr_shift);
1179 cr |= (cr & cr0_mask) >> cr_shift;
1180 break;
1181 }
1182 case OP_63_FNEG:
1183 fpd_fneg(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1184 break;
1185 case OP_63_FMR:
1186 *fpr_d = *fpr_b;
1187 break;
1188 case OP_63_FABS:
1189 fpd_fabs(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1190 break;
1191 case OP_63_FCPSGN:
1192 fpd_fcpsgn(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1193 break;
1194 case OP_63_FDIV:
1195 fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1196 break;
1197 case OP_63_FADD:
1198 fpd_fadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1199 break;
1200 case OP_63_FSUB:
1201 fpd_fsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_b);
1202 break;
1203 case OP_63_FCTIW:
1204 fpd_fctiw(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1205 break;
1206 case OP_63_FCTIWZ:
1207 fpd_fctiwz(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1208 break;
1209 case OP_63_FRSP:
1210 fpd_frsp(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1211 kvmppc_sync_qpr(vcpu, ax_rd);
1212 break;
1213 case OP_63_FRSQRTE:
1214 {
1215 double one = 1.0f;
1216
1217 /* fD = sqrt(fB) */
1218 fpd_fsqrt(&vcpu->arch.fpscr, &cr, fpr_d, fpr_b);
1219 /* fD = 1.0f / fD */
1220 fpd_fdiv(&vcpu->arch.fpscr, &cr, fpr_d, (u64*)&one, fpr_d);
1221 break;
1222 }
1223 }
1224 switch (inst_get_field(inst, 26, 30)) {
1225 case OP_63_FMUL:
1226 fpd_fmul(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c);
1227 break;
1228 case OP_63_FSEL:
1229 fpd_fsel(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1230 break;
1231 case OP_63_FMSUB:
1232 fpd_fmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1233 break;
1234 case OP_63_FMADD:
1235 fpd_fmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1236 break;
1237 case OP_63_FNMSUB:
1238 fpd_fnmsub(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1239 break;
1240 case OP_63_FNMADD:
1241 fpd_fnmadd(&vcpu->arch.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b);
1242 break;
1243 }
1244 break;
1245 }
1246
1247 #ifdef DEBUG
1248 for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++) {
1249 u32 f;
1250 kvm_cvt_df(&vcpu->arch.fpr[i], &f, &vcpu->arch.fpscr);
1251 dprintk(KERN_INFO "FPR[%d] = 0x%x\n", i, f);
1252 }
1253 #endif
1254
1255 if (rcomp)
1256 kvmppc_set_cr(vcpu, cr);
1257
1258 preempt_enable();
1259
1260 return emulated;
1261 }
Tomato firmware and modifications.