[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / powerpc / kernel / exceptions-64e.S
| blob | 2d52cf191be9ae8192fe9433afb13204ae163081 |
1 /*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
12 #include <linux/threads.h>
13 #include <asm/reg.h>
14 #include <asm/page.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/exception-64e.h>
21 #include <asm/bug.h>
22 #include <asm/irqflags.h>
23 #include <asm/ptrace.h>
24 #include <asm/ppc-opcode.h>
25 #include <asm/mmu.h>
27 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
29 /* Exception prolog code for all exceptions */
30 #define EXCEPTION_PROLOG(n, type, addition) \
31 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
32 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
33 std r10,PACA_EX##type+EX_R10(r13); \
34 std r11,PACA_EX##type+EX_R11(r13); \
35 mfcr r10; /* save CR */ \
36 addition; /* additional code for that exc. */ \
37 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
38 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
39 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
40 type##_SET_KSTACK; /* get special stack if necessary */\
41 andi. r10,r11,MSR_PR; /* save stack pointer */ \
42 beq 1f; /* branch around if supervisor */ \
43 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
44 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
45 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
46 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
48 /* Exception type-specific macros */
49 #define GEN_SET_KSTACK \
50 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
51 #define SPRN_GEN_SRR0 SPRN_SRR0
52 #define SPRN_GEN_SRR1 SPRN_SRR1
54 #define CRIT_SET_KSTACK \
55 ld r1,PACA_CRIT_STACK(r13); \
56 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
57 #define SPRN_CRIT_SRR0 SPRN_CSRR0
58 #define SPRN_CRIT_SRR1 SPRN_CSRR1
60 #define DBG_SET_KSTACK \
61 ld r1,PACA_DBG_STACK(r13); \
62 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
63 #define SPRN_DBG_SRR0 SPRN_DSRR0
64 #define SPRN_DBG_SRR1 SPRN_DSRR1
66 #define MC_SET_KSTACK \
67 ld r1,PACA_MC_STACK(r13); \
68 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
69 #define SPRN_MC_SRR0 SPRN_MCSRR0
70 #define SPRN_MC_SRR1 SPRN_MCSRR1
72 #define NORMAL_EXCEPTION_PROLOG(n, addition) \
73 EXCEPTION_PROLOG(n, GEN, addition##_GEN)
75 #define CRIT_EXCEPTION_PROLOG(n, addition) \
76 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
78 #define DBG_EXCEPTION_PROLOG(n, addition) \
79 EXCEPTION_PROLOG(n, DBG, addition##_DBG)
81 #define MC_EXCEPTION_PROLOG(n, addition) \
82 EXCEPTION_PROLOG(n, MC, addition##_MC)
85 /* Variants of the "addition" argument for the prolog
86 */
87 #define PROLOG_ADDITION_NONE_GEN
88 #define PROLOG_ADDITION_NONE_CRIT
89 #define PROLOG_ADDITION_NONE_DBG
90 #define PROLOG_ADDITION_NONE_MC
92 #define PROLOG_ADDITION_MASKABLE_GEN \
93 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
94 cmpwi cr0,r11,0; /* yes -> go out of line */ \
95 beq masked_interrupt_book3e;
97 #define PROLOG_ADDITION_2REGS_GEN \
98 std r14,PACA_EXGEN+EX_R14(r13); \
99 std r15,PACA_EXGEN+EX_R15(r13)
101 #define PROLOG_ADDITION_1REG_GEN \
102 std r14,PACA_EXGEN+EX_R14(r13);
104 #define PROLOG_ADDITION_2REGS_CRIT \
105 std r14,PACA_EXCRIT+EX_R14(r13); \
106 std r15,PACA_EXCRIT+EX_R15(r13)
108 #define PROLOG_ADDITION_2REGS_DBG \
109 std r14,PACA_EXDBG+EX_R14(r13); \
110 std r15,PACA_EXDBG+EX_R15(r13)
112 #define PROLOG_ADDITION_2REGS_MC \
113 std r14,PACA_EXMC+EX_R14(r13); \
114 std r15,PACA_EXMC+EX_R15(r13)
116 #define EXCEPTION_COMMON(n, excf, ints) \
117 std r0,GPR0(r1); /* save r0 in stackframe */ \
118 std r2,GPR2(r1); /* save r2 in stackframe */ \
119 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
120 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
121 std r9,GPR9(r1); /* save r9 in stackframe */ \
122 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
123 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
124 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
125 ld r3,excf+EX_R10(r13); /* get back r10 */ \
126 ld r4,excf+EX_R11(r13); /* get back r11 */ \
127 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
128 std r12,GPR12(r1); /* save r12 in stackframe */ \
129 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
130 mflr r6; /* save LR in stackframe */ \
131 mfctr r7; /* save CTR in stackframe */ \
132 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
133 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
134 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
135 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
136 ld r12,exception_marker@toc(r2); \
137 li r0,0; \
138 std r3,GPR10(r1); /* save r10 to stackframe */ \
139 std r4,GPR11(r1); /* save r11 to stackframe */ \
140 std r5,GPR13(r1); /* save it to stackframe */ \
141 std r6,_LINK(r1); \
142 std r7,_CTR(r1); \
143 std r8,_XER(r1); \
144 li r3,(n)+1; /* indicate partial regs in trap */ \
145 std r9,0(r1); /* store stack frame back link */ \
146 std r10,_CCR(r1); /* store orig CR in stackframe */ \
147 std r9,GPR1(r1); /* store stack frame back link */ \
148 std r11,SOFTE(r1); /* and save it to stackframe */ \
149 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
150 std r3,_TRAP(r1); /* set trap number */ \
151 std r0,RESULT(r1); /* clear regs->result */ \
152 ints;
154 /* Variants for the "ints" argument */
155 #define INTS_KEEP
156 #define INTS_DISABLE_SOFT \
157 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
158 TRACE_DISABLE_INTS;
159 #define INTS_DISABLE_HARD \
160 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
161 #define INTS_DISABLE_ALL \
162 INTS_DISABLE_SOFT \
163 INTS_DISABLE_HARD
165 #define INTS_RESTORE_HARD \
166 ld r11,_MSR(r1); \
167 wrtee r11;
169 #define BAD_STACK_TRAMPOLINE(n) \
170 exc_##n##_bad_stack: \
171 li r1,(n); /* get exception number */ \
172 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
173 b bad_stack_book3e; /* bad stack error */
175 /* WARNING: If you change the layout of this stub, make sure you chcek
176 * the debug exception handler which handles single stepping
177 * into exceptions from userspace, and the MM code in
178 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
179 * and would need to be updated if that branch is moved
180 */
181 #define EXCEPTION_STUB(loc, label) \
182 . = interrupt_base_book3e + loc; \
183 nop; /* To make debug interrupts happy */ \
184 b exc_##label##_book3e;
186 #define ACK_NONE(r)
187 #define ACK_DEC(r) \
188 lis r,TSR_DIS@h; \
189 mtspr SPRN_TSR,r
190 #define ACK_FIT(r) \
191 lis r,TSR_FIS@h; \
192 mtspr SPRN_TSR,r
194 /* Used by asynchronous interrupt that may happen in the idle loop.
195 *
196 * This check if the thread was in the idle loop, and if yes, returns
197 * to the caller rather than the PC. This is to avoid a race if
198 * interrupts happen before the wait instruction.
199 */
200 #define CHECK_NAPPING() \
201 clrrdi r11,r1,THREAD_SHIFT; \
202 ld r10,TI_LOCAL_FLAGS(r11); \
203 andi. r9,r10,_TLF_NAPPING; \
204 beq+ 1f; \
205 ld r8,_LINK(r1); \
206 rlwinm r7,r10,0,~_TLF_NAPPING; \
207 std r8,_NIP(r1); \
208 std r7,TI_LOCAL_FLAGS(r11); \
209 1:
212 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
213 START_EXCEPTION(label); \
214 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
215 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
216 ack(r8); \
217 CHECK_NAPPING(); \
218 addi r3,r1,STACK_FRAME_OVERHEAD; \
219 bl hdlr; \
220 b .ret_from_except_lite;
222 /* This value is used to mark exception frames on the stack. */
223 .section ".toc","aw"
224 exception_marker:
225 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
228 /*
229 * And here we have the exception vectors !
230 */
232 .text
233 .balign 0x1000
234 .globl interrupt_base_book3e
235 interrupt_base_book3e: /* fake trap */
236 /* Note: If real debug exceptions are supported by the HW, the vector
237 * below will have to be patched up to point to an appropriate handler
238 */
239 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
240 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
241 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
242 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
243 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
244 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
245 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
246 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
247 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
248 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
249 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
250 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
251 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
252 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
253 EXCEPTION_STUB(0x1c0, data_tlb_miss)
254 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
255 EXCEPTION_STUB(0x280, doorbell)
256 EXCEPTION_STUB(0x2a0, doorbell_crit)
258 .globl interrupt_end_book3e
259 interrupt_end_book3e:
261 /* Critical Input Interrupt */
262 START_EXCEPTION(critical_input);
263 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
264 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
265 // bl special_reg_save_crit
266 // CHECK_NAPPING();
267 // addi r3,r1,STACK_FRAME_OVERHEAD
268 // bl .critical_exception
269 // b ret_from_crit_except
270 b .
272 /* Machine Check Interrupt */
273 START_EXCEPTION(machine_check);
274 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
275 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
276 // bl special_reg_save_mc
277 // addi r3,r1,STACK_FRAME_OVERHEAD
278 // CHECK_NAPPING();
279 // bl .machine_check_exception
280 // b ret_from_mc_except
281 b .
283 /* Data Storage Interrupt */
284 START_EXCEPTION(data_storage)
285 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
286 mfspr r14,SPRN_DEAR
287 mfspr r15,SPRN_ESR
288 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
289 b storage_fault_common
291 /* Instruction Storage Interrupt */
292 START_EXCEPTION(instruction_storage);
293 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
294 li r15,0
295 mr r14,r10
296 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
297 b storage_fault_common
299 /* External Input Interrupt */
300 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
302 /* Alignment */
303 START_EXCEPTION(alignment);
304 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
305 mfspr r14,SPRN_DEAR
306 mfspr r15,SPRN_ESR
307 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
308 b alignment_more /* no room, go out of line */
310 /* Program Interrupt */
311 START_EXCEPTION(program);
312 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
313 mfspr r14,SPRN_ESR
314 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
315 std r14,_DSISR(r1)
316 addi r3,r1,STACK_FRAME_OVERHEAD
317 ld r14,PACA_EXGEN+EX_R14(r13)
318 bl .save_nvgprs
319 INTS_RESTORE_HARD
320 bl .program_check_exception
321 b .ret_from_except
323 /* Floating Point Unavailable Interrupt */
324 START_EXCEPTION(fp_unavailable);
325 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
326 /* we can probably do a shorter exception entry for that one... */
327 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
328 bne 1f /* if from user, just load it up */
329 bl .save_nvgprs
330 addi r3,r1,STACK_FRAME_OVERHEAD
331 INTS_RESTORE_HARD
332 bl .kernel_fp_unavailable_exception
333 BUG_OPCODE
334 1: ld r12,_MSR(r1)
335 bl .load_up_fpu
336 b fast_exception_return
338 /* Decrementer Interrupt */
339 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
341 /* Fixed Interval Timer Interrupt */
342 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
344 /* Watchdog Timer Interrupt */
345 START_EXCEPTION(watchdog);
346 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
347 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
348 // bl special_reg_save_crit
349 // CHECK_NAPPING();
350 // addi r3,r1,STACK_FRAME_OVERHEAD
351 // bl .unknown_exception
352 // b ret_from_crit_except
353 b .
355 /* System Call Interrupt */
356 START_EXCEPTION(system_call)
357 mr r9,r13 /* keep a copy of userland r13 */
358 mfspr r11,SPRN_SRR0 /* get return address */
359 mfspr r12,SPRN_SRR1 /* get previous MSR */
360 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
361 b system_call_common
363 /* Auxillary Processor Unavailable Interrupt */
364 START_EXCEPTION(ap_unavailable);
365 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
366 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
367 addi r3,r1,STACK_FRAME_OVERHEAD
368 bl .save_nvgprs
369 INTS_RESTORE_HARD
370 bl .unknown_exception
371 b .ret_from_except
373 /* Debug exception as a critical interrupt*/
374 START_EXCEPTION(debug_crit);
375 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
377 /*
378 * If there is a single step or branch-taken exception in an
379 * exception entry sequence, it was probably meant to apply to
380 * the code where the exception occurred (since exception entry
381 * doesn't turn off DE automatically). We simulate the effect
382 * of turning off DE on entry to an exception handler by turning
383 * off DE in the CSRR1 value and clearing the debug status.
384 */
386 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
387 andis. r15,r14,DBSR_IC@h
388 beq+ 1f
390 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
391 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
392 cmpld cr0,r10,r14
393 cmpld cr1,r10,r15
394 blt+ cr0,1f
395 bge+ cr1,1f
397 /* here it looks like we got an inappropriate debug exception. */
398 lis r14,DBSR_IC@h /* clear the IC event */
399 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
400 mtspr SPRN_DBSR,r14
401 mtspr SPRN_CSRR1,r11
402 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
403 ld r1,PACA_EXCRIT+EX_R1(r13)
404 ld r14,PACA_EXCRIT+EX_R14(r13)
405 ld r15,PACA_EXCRIT+EX_R15(r13)
406 mtcr r10
407 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
408 ld r11,PACA_EXCRIT+EX_R11(r13)
409 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
410 rfci
412 /* Normal debug exception */
413 1: andi. r14,r11,MSR_PR; /* check for userspace again */
414 beq kernel_dbg_exc; /* if from kernel mode */
416 /* Now we mash up things to make it look like we are coming on a
417 * normal exception
418 */
419 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
420 mtspr SPRN_SPRG_GEN_SCRATCH,r15
421 mfspr r14,SPRN_DBSR
422 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
423 std r14,_DSISR(r1)
424 addi r3,r1,STACK_FRAME_OVERHEAD
425 mr r4,r14
426 ld r14,PACA_EXCRIT+EX_R14(r13)
427 ld r15,PACA_EXCRIT+EX_R15(r13)
428 bl .save_nvgprs
429 bl .DebugException
430 b .ret_from_except
432 kernel_dbg_exc:
433 b . /* NYI */
435 /* Doorbell interrupt */
436 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
438 /* Doorbell critical Interrupt */
439 START_EXCEPTION(doorbell_crit);
440 CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
441 // EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
442 // bl special_reg_save_crit
443 // CHECK_NAPPING();
444 // addi r3,r1,STACK_FRAME_OVERHEAD
445 // bl .doorbell_critical_exception
446 // b ret_from_crit_except
447 b .
450 /*
451 * An interrupt came in while soft-disabled; clear EE in SRR1,
452 * clear paca->hard_enabled and return.
453 */
454 masked_interrupt_book3e:
455 mtcr r10
456 stb r11,PACAHARDIRQEN(r13)
457 mfspr r10,SPRN_SRR1
458 rldicl r11,r10,48,1 /* clear MSR_EE */
459 rotldi r10,r11,16
460 mtspr SPRN_SRR1,r10
461 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
462 ld r11,PACA_EXGEN+EX_R11(r13);
463 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
464 rfi
465 b .
467 /*
468 * This is called from 0x300 and 0x400 handlers after the prologs with
469 * r14 and r15 containing the fault address and error code, with the
470 * original values stashed away in the PACA
471 */
472 storage_fault_common:
473 std r14,_DAR(r1)
474 std r15,_DSISR(r1)
475 addi r3,r1,STACK_FRAME_OVERHEAD
476 mr r4,r14
477 mr r5,r15
478 ld r14,PACA_EXGEN+EX_R14(r13)
479 ld r15,PACA_EXGEN+EX_R15(r13)
480 INTS_RESTORE_HARD
481 bl .do_page_fault
482 cmpdi r3,0
483 bne- 1f
484 b .ret_from_except_lite
485 1: bl .save_nvgprs
486 mr r5,r3
487 addi r3,r1,STACK_FRAME_OVERHEAD
488 ld r4,_DAR(r1)
489 bl .bad_page_fault
490 b .ret_from_except
492 /*
493 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
494 * continues here.
495 */
496 alignment_more:
497 std r14,_DAR(r1)
498 std r15,_DSISR(r1)
499 addi r3,r1,STACK_FRAME_OVERHEAD
500 ld r14,PACA_EXGEN+EX_R14(r13)
501 ld r15,PACA_EXGEN+EX_R15(r13)
502 bl .save_nvgprs
503 INTS_RESTORE_HARD
504 bl .alignment_exception
505 b .ret_from_except
507 /*
508 * We branch here from entry_64.S for the last stage of the exception
509 * return code path. MSR:EE is expected to be off at that point
510 */
511 _GLOBAL(exception_return_book3e)
512 b 1f
514 /* This is the return from load_up_fpu fast path which could do with
515 * less GPR restores in fact, but for now we have a single return path
516 */
517 .globl fast_exception_return
518 fast_exception_return:
519 wrteei 0
520 1: mr r0,r13
521 ld r10,_MSR(r1)
522 REST_4GPRS(2, r1)
523 andi. r6,r10,MSR_PR
524 REST_2GPRS(6, r1)
525 beq 1f
526 ACCOUNT_CPU_USER_EXIT(r10, r11)
527 ld r0,GPR13(r1)
529 1: stdcx. r0,0,r1 /* to clear the reservation */
531 ld r8,_CCR(r1)
532 ld r9,_LINK(r1)
533 ld r10,_CTR(r1)
534 ld r11,_XER(r1)
535 mtcr r8
536 mtlr r9
537 mtctr r10
538 mtxer r11
539 REST_2GPRS(8, r1)
540 ld r10,GPR10(r1)
541 ld r11,GPR11(r1)
542 ld r12,GPR12(r1)
543 mtspr SPRN_SPRG_GEN_SCRATCH,r0
545 std r10,PACA_EXGEN+EX_R10(r13);
546 std r11,PACA_EXGEN+EX_R11(r13);
547 ld r10,_NIP(r1)
548 ld r11,_MSR(r1)
549 ld r0,GPR0(r1)
550 ld r1,GPR1(r1)
551 mtspr SPRN_SRR0,r10
552 mtspr SPRN_SRR1,r11
553 ld r10,PACA_EXGEN+EX_R10(r13)
554 ld r11,PACA_EXGEN+EX_R11(r13)
555 mfspr r13,SPRN_SPRG_GEN_SCRATCH
556 rfi
558 /*
559 * Trampolines used when spotting a bad kernel stack pointer in
560 * the exception entry code.
561 *
562 * TODO: move some bits like SRR0 read to trampoline, pass PACA
563 * index around, etc... to handle crit & mcheck
564 */
565 BAD_STACK_TRAMPOLINE(0x000)
566 BAD_STACK_TRAMPOLINE(0x100)
567 BAD_STACK_TRAMPOLINE(0x200)
568 BAD_STACK_TRAMPOLINE(0x300)
569 BAD_STACK_TRAMPOLINE(0x400)
570 BAD_STACK_TRAMPOLINE(0x500)
571 BAD_STACK_TRAMPOLINE(0x600)
572 BAD_STACK_TRAMPOLINE(0x700)
573 BAD_STACK_TRAMPOLINE(0x800)
574 BAD_STACK_TRAMPOLINE(0x900)
575 BAD_STACK_TRAMPOLINE(0x980)
576 BAD_STACK_TRAMPOLINE(0x9f0)
577 BAD_STACK_TRAMPOLINE(0xa00)
578 BAD_STACK_TRAMPOLINE(0xb00)
579 BAD_STACK_TRAMPOLINE(0xc00)
580 BAD_STACK_TRAMPOLINE(0xd00)
581 BAD_STACK_TRAMPOLINE(0xe00)
582 BAD_STACK_TRAMPOLINE(0xf00)
583 BAD_STACK_TRAMPOLINE(0xf20)
584 BAD_STACK_TRAMPOLINE(0x2070)
585 BAD_STACK_TRAMPOLINE(0x2080)
587 .globl bad_stack_book3e
588 bad_stack_book3e:
589 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
590 ld r1,PACAEMERGSP(r13)
591 subi r1,r1,64+INT_FRAME_SIZE
592 std r10,_NIP(r1)
593 std r11,_MSR(r1)
594 ld r10,PACA_EXGEN+EX_R1(r13)
595 lwz r11,PACA_EXGEN+EX_CR(r13)
596 std r10,GPR1(r1)
597 std r11,_CCR(r1)
598 mfspr r10,SPRN_DEAR
599 mfspr r11,SPRN_ESR
600 std r10,_DAR(r1)
601 std r11,_DSISR(r1)
602 std r0,GPR0(r1); /* save r0 in stackframe */ \
603 std r2,GPR2(r1); /* save r2 in stackframe */ \
604 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
605 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
606 std r9,GPR9(r1); /* save r9 in stackframe */ \
607 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
608 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
609 mfspr r5,SPRN_SPRG_GEN_SCRATCH; \
610 std r3,GPR10(r1); /* save r10 to stackframe */ \
611 std r4,GPR11(r1); /* save r11 to stackframe */ \
612 std r12,GPR12(r1); /* save r12 in stackframe */ \
613 std r5,GPR13(r1); /* save it to stackframe */ \
614 mflr r10
615 mfctr r11
616 mfxer r12
617 std r10,_LINK(r1)
618 std r11,_CTR(r1)
619 std r12,_XER(r1)
620 SAVE_10GPRS(14,r1)
621 SAVE_8GPRS(24,r1)
622 lhz r12,PACA_TRAP_SAVE(r13)
623 std r12,_TRAP(r1)
624 addi r11,r1,INT_FRAME_SIZE
625 std r11,0(r1)
626 li r12,0
627 std r12,0(r11)
628 ld r2,PACATOC(r13)
629 1: addi r3,r1,STACK_FRAME_OVERHEAD
630 bl .kernel_bad_stack
631 b 1b
633 /*
634 * Setup the initial TLB for a core. This current implementation
635 * assume that whatever we are running off will not conflict with
636 * the new mapping at PAGE_OFFSET.
637 */
638 _GLOBAL(initial_tlb_book3e)
640 /* Look for the first TLB with IPROT set */
641 mfspr r4,SPRN_TLB0CFG
642 andi. r3,r4,TLBnCFG_IPROT
643 lis r3,MAS0_TLBSEL(0)@h
644 bne found_iprot
646 mfspr r4,SPRN_TLB1CFG
647 andi. r3,r4,TLBnCFG_IPROT
648 lis r3,MAS0_TLBSEL(1)@h
649 bne found_iprot
651 mfspr r4,SPRN_TLB2CFG
652 andi. r3,r4,TLBnCFG_IPROT
653 lis r3,MAS0_TLBSEL(2)@h
654 bne found_iprot
656 lis r3,MAS0_TLBSEL(3)@h
657 mfspr r4,SPRN_TLB3CFG
658 /* fall through */
660 found_iprot:
661 andi. r5,r4,TLBnCFG_HES
662 bne have_hes
664 mflr r8 /* save LR */
665 /* 1. Find the index of the entry we're executing in
666 *
667 * r3 = MAS0_TLBSEL (for the iprot array)
668 * r4 = SPRN_TLBnCFG
669 */
670 bl invstr /* Find our address */
671 invstr: mflr r6 /* Make it accessible */
672 mfmsr r7
673 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
674 mfspr r7,SPRN_PID
675 slwi r7,r7,16
676 or r7,r7,r5
677 mtspr SPRN_MAS6,r7
678 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
680 mfspr r3,SPRN_MAS0
681 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
683 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
684 oris r7,r7,MAS1_IPROT@h
685 mtspr SPRN_MAS1,r7
686 tlbwe
688 /* 2. Invalidate all entries except the entry we're executing in
689 *
690 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
691 * r4 = SPRN_TLBnCFG
692 * r5 = ESEL of entry we are running in
693 */
694 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
695 li r6,0 /* Set Entry counter to 0 */
696 1: mr r7,r3 /* Set MAS0(TLBSEL) */
697 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
698 mtspr SPRN_MAS0,r7
699 tlbre
700 mfspr r7,SPRN_MAS1
701 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
702 cmpw r5,r6
703 beq skpinv /* Dont update the current execution TLB */
704 mtspr SPRN_MAS1,r7
705 tlbwe
706 isync
707 skpinv: addi r6,r6,1 /* Increment */
708 cmpw r6,r4 /* Are we done? */
709 bne 1b /* If not, repeat */
711 /* Invalidate all TLBs */
712 PPC_TLBILX_ALL(0,0)
713 sync
714 isync
716 /* 3. Setup a temp mapping and jump to it
717 *
718 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
719 * r5 = ESEL of entry we are running in
720 */
721 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
722 addi r7,r7,0x1
723 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
724 mtspr SPRN_MAS0,r4
725 tlbre
727 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
728 mtspr SPRN_MAS0,r4
730 mfspr r7,SPRN_MAS1
731 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
732 mtspr SPRN_MAS1,r6
734 tlbwe
736 mfmsr r6
737 xori r6,r6,MSR_IS
738 mtspr SPRN_SRR1,r6
739 bl 1f /* Find our address */
740 1: mflr r6
741 addi r6,r6,(2f - 1b)
742 mtspr SPRN_SRR0,r6
743 rfi
744 2:
746 /* 4. Clear out PIDs & Search info
747 *
748 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
749 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
750 * r5 = MAS3
751 */
752 li r6,0
753 mtspr SPRN_MAS6,r6
754 mtspr SPRN_PID,r6
756 /* 5. Invalidate mapping we started in
757 *
758 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
759 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
760 * r5 = MAS3
761 */
762 mtspr SPRN_MAS0,r3
763 tlbre
764 mfspr r6,SPRN_MAS1
765 rlwinm r6,r6,0,2,0 /* clear IPROT */
766 mtspr SPRN_MAS1,r6
767 tlbwe
769 /* Invalidate TLB1 */
770 PPC_TLBILX_ALL(0,0)
771 sync
772 isync
774 /* The mapping only needs to be cache-coherent on SMP */
775 #ifdef CONFIG_SMP
776 #define M_IF_SMP MAS2_M
777 #else
778 #define M_IF_SMP 0
779 #endif
781 /* 6. Setup KERNELBASE mapping in TLB[0]
782 *
783 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
784 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
785 * r5 = MAS3
786 */
787 rlwinm r3,r3,0,16,3 /* clear ESEL */
788 mtspr SPRN_MAS0,r3
789 lis r6,(MAS1_VALID|MAS1_IPROT)@h
790 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
791 mtspr SPRN_MAS1,r6
793 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
794 mtspr SPRN_MAS2,r6
796 rlwinm r5,r5,0,0,25
797 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
798 mtspr SPRN_MAS3,r5
799 li r5,-1
800 rlwinm r5,r5,0,0,25
802 tlbwe
804 /* 7. Jump to KERNELBASE mapping
805 *
806 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
807 */
808 /* Now we branch the new virtual address mapped by this entry */
809 LOAD_REG_IMMEDIATE(r6,2f)
810 lis r7,MSR_KERNEL@h
811 ori r7,r7,MSR_KERNEL@l
812 mtspr SPRN_SRR0,r6
813 mtspr SPRN_SRR1,r7
814 rfi /* start execution out of TLB1[0] entry */
815 2:
817 /* 8. Clear out the temp mapping
818 *
819 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
820 */
821 mtspr SPRN_MAS0,r4
822 tlbre
823 mfspr r5,SPRN_MAS1
824 rlwinm r5,r5,0,2,0 /* clear IPROT */
825 mtspr SPRN_MAS1,r5
826 tlbwe
828 /* Invalidate TLB1 */
829 PPC_TLBILX_ALL(0,0)
830 sync
831 isync
833 /* We translate LR and return */
834 tovirt(r8,r8)
835 mtlr r8
836 blr
838 have_hes:
839 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
840 * kernel linear mapping. We also set MAS8 once for all here though
841 * that will have to be made dependent on whether we are running under
842 * a hypervisor I suppose.
843 */
844 ori r3,r3,MAS0_HES | MAS0_WQ_ALLWAYS
845 mtspr SPRN_MAS0,r3
846 lis r3,(MAS1_VALID | MAS1_IPROT)@h
847 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
848 mtspr SPRN_MAS1,r3
849 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
850 mtspr SPRN_MAS2,r3
851 li r3,MAS3_SR | MAS3_SW | MAS3_SX
852 mtspr SPRN_MAS7_MAS3,r3
853 li r3,0
854 mtspr SPRN_MAS8,r3
856 /* Write the TLB entry */
857 tlbwe
859 /* Now we branch the new virtual address mapped by this entry */
860 LOAD_REG_IMMEDIATE(r3,1f)
861 mtctr r3
862 bctr
864 1:
865 PPC_TLBILX(0,0,0)
866 sync
867 isync
869 /* We translate LR and return */
870 mflr r3
871 tovirt(r3,r3)
872 mtlr r3
873 blr
875 /*
876 * Main entry (boot CPU, thread 0)
877 *
878 * We enter here from head_64.S, possibly after the prom_init trampoline
879 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
880 * mode. Anything else is as it was left by the bootloader
881 *
882 * Initial requirements of this port:
883 *
884 * - Kernel loaded at 0 physical
885 * - A good lump of memory mapped 0:0 by UTLB entry 0
886 * - MSR:IS & MSR:DS set to 0
887 *
888 * Note that some of the above requirements will be relaxed in the future
889 * as the kernel becomes smarter at dealing with different initial conditions
890 * but for now you have to be careful
891 */
892 _GLOBAL(start_initialization_book3e)
893 mflr r28
895 /* First, we need to setup some initial TLBs to map the kernel
896 * text, data and bss at PAGE_OFFSET. We don't have a real mode
897 * and always use AS 0, so we just set it up to match our link
898 * address and never use 0 based addresses.
899 */
900 bl .initial_tlb_book3e
902 /* Init global core bits */
903 bl .init_core_book3e
905 /* Init per-thread bits */
906 bl .init_thread_book3e
908 /* Return to common init code */
909 tovirt(r28,r28)
910 mtlr r28
911 blr
914 /*
915 * Secondary core/processor entry
916 *
917 * This is entered for thread 0 of a secondary core, all other threads
918 * are expected to be stopped. It's similar to start_initialization_book3e
919 * except that it's generally entered from the holding loop in head_64.S
920 * after CPUs have been gathered by Open Firmware.
921 *
922 * We assume we are in 32 bits mode running with whatever TLB entry was
923 * set for us by the firmware or POR engine.
924 */
925 _GLOBAL(book3e_secondary_core_init_tlb_set)
926 li r4,1
927 b .generic_secondary_smp_init
929 _GLOBAL(book3e_secondary_core_init)
930 mflr r28
932 /* Do we need to setup initial TLB entry ? */
933 cmplwi r4,0
934 bne 2f
936 /* Setup TLB for this core */
937 bl .initial_tlb_book3e
939 /* We can return from the above running at a different
940 * address, so recalculate r2 (TOC)
941 */
942 bl .relative_toc
944 /* Init global core bits */
945 2: bl .init_core_book3e
947 /* Init per-thread bits */
948 3: bl .init_thread_book3e
950 /* Return to common init code at proper virtual address.
951 *
952 * Due to various previous assumptions, we know we entered this
953 * function at either the final PAGE_OFFSET mapping or using a
954 * 1:1 mapping at 0, so we don't bother doing a complicated check
955 * here, we just ensure the return address has the right top bits.
956 *
957 * Note that if we ever want to be smarter about where we can be
958 * started from, we have to be careful that by the time we reach
959 * the code below we may already be running at a different location
960 * than the one we were called from since initial_tlb_book3e can
961 * have moved us already.
962 */
963 cmpdi cr0,r28,0
964 blt 1f
965 lis r3,PAGE_OFFSET@highest
966 sldi r3,r3,32
967 or r28,r28,r3
968 1: mtlr r28
969 blr
971 _GLOBAL(book3e_secondary_thread_init)
972 mflr r28
973 b 3b
975 _STATIC(init_core_book3e)
976 /* Establish the interrupt vector base */
977 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
978 mtspr SPRN_IVPR,r3
979 sync
980 blr
982 _STATIC(init_thread_book3e)
983 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
984 mtspr SPRN_EPCR,r3
986 /* Make sure interrupts are off */
987 wrteei 0
989 /* disable all timers and clear out status */
990 li r3,0
991 mtspr SPRN_TCR,r3
992 mfspr r3,SPRN_TSR
993 mtspr SPRN_TSR,r3
995 blr
997 _GLOBAL(__setup_base_ivors)
998 SET_IVOR(0, 0x020) /* Critical Input */
999 SET_IVOR(1, 0x000) /* Machine Check */
1000 SET_IVOR(2, 0x060) /* Data Storage */
1001 SET_IVOR(3, 0x080) /* Instruction Storage */
1002 SET_IVOR(4, 0x0a0) /* External Input */
1003 SET_IVOR(5, 0x0c0) /* Alignment */
1004 SET_IVOR(6, 0x0e0) /* Program */
1005 SET_IVOR(7, 0x100) /* FP Unavailable */
1006 SET_IVOR(8, 0x120) /* System Call */
1007 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1008 SET_IVOR(10, 0x160) /* Decrementer */
1009 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1010 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1011 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1012 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1013 SET_IVOR(15, 0x040) /* Debug */
1015 sync
1017 blr