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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / mips / include / asm / gic.h
blob242b2ed891b499d754a062e6398b2aebb067a7f0
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
7 *
8 * GIC Register Definitions
9 *
10 */
11 #ifndef _ASM_GICREGS_H
12 #define _ASM_GICREGS_H
13
14 #undef GICISBYTELITTLEENDIAN
15
16 extern unsigned long _gic_base;
17
18 /* Constants */
19 #define GIC_POL_POS 1
20 #define GIC_POL_NEG 0
21 #define GIC_TRIG_EDGE 1
22 #define GIC_TRIG_LEVEL 0
23
24 #define GIC_NUM_INTRS (24 + NR_CPUS * 2)
25
26 #define MSK(n) ((1 << (n)) - 1)
27 #define REG32(addr) (*(volatile unsigned int *) (addr))
28 #define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
29 #define REGP(base, phys) REG32((unsigned long)(base) + (phys))
30
31 /* Accessors */
32 #define GIC_REG(segment, offset) \
33 REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
34 #define GIC_REG_ADDR(segment, offset) \
35 REG32(_gic_base + segment##_##SECTION_OFS + offset)
36
37 #define GIC_ABS_REG(segment, offset) \
38 (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
39 #define GIC_REG_ABS_ADDR(segment, offset) \
40 (_gic_base + segment##_##SECTION_OFS + offset)
41
42 #ifdef GICISBYTELITTLEENDIAN
43 #define GICREAD(reg, data) (data) = (reg), (data) = le32_to_cpu(data)
44 #define GICWRITE(reg, data) (reg) = cpu_to_le32(data)
45 #define GICBIS(reg, bits) \
46 ({unsigned int data; \
47 GICREAD(reg, data); \
48 data |= bits; \
49 GICWRITE(reg, data); \
50 })
51
52 #else
53 #define GICREAD(reg, data) (data) = (reg)
54 #define GICWRITE(reg, data) (reg) = (data)
55 #define GICBIS(reg, bits) (reg) |= (bits)
56 #endif
57
58
59 /* GIC Address Space */
60 #define SHARED_SECTION_OFS 0x0000
61 #define SHARED_SECTION_SIZE 0x8000
62 #define VPE_LOCAL_SECTION_OFS 0x8000
63 #define VPE_LOCAL_SECTION_SIZE 0x4000
64 #define VPE_OTHER_SECTION_OFS 0xc000
65 #define VPE_OTHER_SECTION_SIZE 0x4000
66 #define USM_VISIBLE_SECTION_OFS 0x10000
67 #define USM_VISIBLE_SECTION_SIZE 0x10000
68
69 /* Register Map for Shared Section */
70
71 #define GIC_SH_CONFIG_OFS 0x0000
72
73 /* Shared Global Counter */
74 #define GIC_SH_COUNTER_31_00_OFS 0x0010
75 #define GIC_SH_COUNTER_63_32_OFS 0x0014
76 #define GIC_SH_REVISIONID_OFS 0x0020
77
78 /* Interrupt Polarity */
79 #define GIC_SH_POL_31_0_OFS 0x0100
80 #define GIC_SH_POL_63_32_OFS 0x0104
81 #define GIC_SH_POL_95_64_OFS 0x0108
82 #define GIC_SH_POL_127_96_OFS 0x010c
83 #define GIC_SH_POL_159_128_OFS 0x0110
84 #define GIC_SH_POL_191_160_OFS 0x0114
85 #define GIC_SH_POL_223_192_OFS 0x0118
86 #define GIC_SH_POL_255_224_OFS 0x011c
87
88 /* Edge/Level Triggering */
89 #define GIC_SH_TRIG_31_0_OFS 0x0180
90 #define GIC_SH_TRIG_63_32_OFS 0x0184
91 #define GIC_SH_TRIG_95_64_OFS 0x0188
92 #define GIC_SH_TRIG_127_96_OFS 0x018c
93 #define GIC_SH_TRIG_159_128_OFS 0x0190
94 #define GIC_SH_TRIG_191_160_OFS 0x0194
95 #define GIC_SH_TRIG_223_192_OFS 0x0198
96 #define GIC_SH_TRIG_255_224_OFS 0x019c
97
98 /* Dual Edge Triggering */
99 #define GIC_SH_DUAL_31_0_OFS 0x0200
100 #define GIC_SH_DUAL_63_32_OFS 0x0204
101 #define GIC_SH_DUAL_95_64_OFS 0x0208
102 #define GIC_SH_DUAL_127_96_OFS 0x020c
103 #define GIC_SH_DUAL_159_128_OFS 0x0210
104 #define GIC_SH_DUAL_191_160_OFS 0x0214
105 #define GIC_SH_DUAL_223_192_OFS 0x0218
106 #define GIC_SH_DUAL_255_224_OFS 0x021c
107
108 /* Set/Clear corresponding bit in Edge Detect Register */
109 #define GIC_SH_WEDGE_OFS 0x0280
110
111 /* Reset Mask - Disables Interrupt */
112 #define GIC_SH_RMASK_31_0_OFS 0x0300
113 #define GIC_SH_RMASK_63_32_OFS 0x0304
114 #define GIC_SH_RMASK_95_64_OFS 0x0308
115 #define GIC_SH_RMASK_127_96_OFS 0x030c
116 #define GIC_SH_RMASK_159_128_OFS 0x0310
117 #define GIC_SH_RMASK_191_160_OFS 0x0314
118 #define GIC_SH_RMASK_223_192_OFS 0x0318
119 #define GIC_SH_RMASK_255_224_OFS 0x031c
120
121 /* Set Mask (WO) - Enables Interrupt */
122 #define GIC_SH_SMASK_31_0_OFS 0x0380
123 #define GIC_SH_SMASK_63_32_OFS 0x0384
124 #define GIC_SH_SMASK_95_64_OFS 0x0388
125 #define GIC_SH_SMASK_127_96_OFS 0x038c
126 #define GIC_SH_SMASK_159_128_OFS 0x0390
127 #define GIC_SH_SMASK_191_160_OFS 0x0394
128 #define GIC_SH_SMASK_223_192_OFS 0x0398
129 #define GIC_SH_SMASK_255_224_OFS 0x039c
130
131 /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
132 #define GIC_SH_MASK_31_0_OFS 0x0400
133 #define GIC_SH_MASK_63_32_OFS 0x0404
134 #define GIC_SH_MASK_95_64_OFS 0x0408
135 #define GIC_SH_MASK_127_96_OFS 0x040c
136 #define GIC_SH_MASK_159_128_OFS 0x0410
137 #define GIC_SH_MASK_191_160_OFS 0x0414
138 #define GIC_SH_MASK_223_192_OFS 0x0418
139 #define GIC_SH_MASK_255_224_OFS 0x041c
140
141 /* Pending Global Interrupts (RO) */
142 #define GIC_SH_PEND_31_0_OFS 0x0480
143 #define GIC_SH_PEND_63_32_OFS 0x0484
144 #define GIC_SH_PEND_95_64_OFS 0x0488
145 #define GIC_SH_PEND_127_96_OFS 0x048c
146 #define GIC_SH_PEND_159_128_OFS 0x0490
147 #define GIC_SH_PEND_191_160_OFS 0x0494
148 #define GIC_SH_PEND_223_192_OFS 0x0498
149 #define GIC_SH_PEND_255_224_OFS 0x049c
150
151 #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
152
153 /* Maps Interrupt X to a Pin */
154 #define GIC_SH_MAP_TO_PIN(intr) \
155 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
156
157 #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
158
159 /* Maps Interrupt X to a VPE */
160 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
161 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
162 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
163
164 /* Convert an interrupt number to a byte offset/bit for multi-word registers */
165 #define GIC_INTR_OFS(intr) (((intr) / 32)*4)
166 #define GIC_INTR_BIT(intr) ((intr) % 32)
167
168 /* Polarity : Reset Value is always 0 */
169 #define GIC_SH_SET_POLARITY_OFS 0x0100
170 #define GIC_SET_POLARITY(intr, pol) \
171 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
172 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
173
174 /* Triggering : Reset Value is always 0 */
175 #define GIC_SH_SET_TRIGGER_OFS 0x0180
176 #define GIC_SET_TRIGGER(intr, trig) \
177 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
178 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
179
180 /* Mask manipulation */
181 #define GIC_SH_SMASK_OFS 0x0380
182 #define GIC_SET_INTR_MASK(intr) \
183 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
184 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
185 #define GIC_SH_RMASK_OFS 0x0300
186 #define GIC_CLR_INTR_MASK(intr) \
187 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
188 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
189
190 /* Register Map for Local Section */
191 #define GIC_VPE_CTL_OFS 0x0000
192 #define GIC_VPE_PEND_OFS 0x0004
193 #define GIC_VPE_MASK_OFS 0x0008
194 #define GIC_VPE_RMASK_OFS 0x000c
195 #define GIC_VPE_SMASK_OFS 0x0010
196 #define GIC_VPE_WD_MAP_OFS 0x0040
197 #define GIC_VPE_COMPARE_MAP_OFS 0x0044
198 #define GIC_VPE_TIMER_MAP_OFS 0x0048
199 #define GIC_VPE_PERFCTR_MAP_OFS 0x0050
200 #define GIC_VPE_SWINT0_MAP_OFS 0x0054
201 #define GIC_VPE_SWINT1_MAP_OFS 0x0058
202 #define GIC_VPE_OTHER_ADDR_OFS 0x0080
203 #define GIC_VPE_WD_CONFIG0_OFS 0x0090
204 #define GIC_VPE_WD_COUNT0_OFS 0x0094
205 #define GIC_VPE_WD_INITIAL0_OFS 0x0098
206 #define GIC_VPE_COMPARE_LO_OFS 0x00a0
207 #define GIC_VPE_COMPARE_HI 0x00a4
208
209 #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
210 #define GIC_VPE_EIC_SS(intr) \
211 (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
212
213 #define GIC_VPE_EIC_VEC_BASE 0x0800
214 #define GIC_VPE_EIC_VEC(intr) \
215 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
216
217 #define GIC_VPE_TENABLE_NMI_OFS 0x1000
218 #define GIC_VPE_TENABLE_YQ_OFS 0x1004
219 #define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
220 #define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
221
222 /* User Mode Visible Section Register Map */
223 #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
224 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
225
226 /* Masks */
227 #define GIC_SH_CONFIG_COUNTSTOP_SHF 28
228 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
229
230 #define GIC_SH_CONFIG_COUNTBITS_SHF 24
231 #define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
232
233 #define GIC_SH_CONFIG_NUMINTRS_SHF 16
234 #define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
235
236 #define GIC_SH_CONFIG_NUMVPES_SHF 0
237 #define GIC_SH_CONFIG_NUMVPES_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
238
239 #define GIC_SH_WEDGE_SET(intr) (intr | (0x1 << 31))
240 #define GIC_SH_WEDGE_CLR(intr) (intr & ~(0x1 << 31))
241
242 #define GIC_MAP_TO_PIN_SHF 31
243 #define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF)
244 #define GIC_MAP_TO_NMI_SHF 30
245 #define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF)
246 #define GIC_MAP_TO_YQ_SHF 29
247 #define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF)
248 #define GIC_MAP_SHF 0
249 #define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
250
251 /* GIC_VPE_CTL Masks */
252 #define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
253 #define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
254 #define GIC_VPE_CTL_TIMER_RTBL_SHF 1
255 #define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
256 #define GIC_VPE_CTL_EIC_MODE_SHF 0
257 #define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
258
259 /* GIC_VPE_PEND Masks */
260 #define GIC_VPE_PEND_WD_SHF 0
261 #define GIC_VPE_PEND_WD_MSK (MSK(1) << GIC_VPE_PEND_WD_SHF)
262 #define GIC_VPE_PEND_CMP_SHF 1
263 #define GIC_VPE_PEND_CMP_MSK (MSK(1) << GIC_VPE_PEND_CMP_SHF)
264 #define GIC_VPE_PEND_TIMER_SHF 2
265 #define GIC_VPE_PEND_TIMER_MSK (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
266 #define GIC_VPE_PEND_PERFCOUNT_SHF 3
267 #define GIC_VPE_PEND_PERFCOUNT_MSK (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
268 #define GIC_VPE_PEND_SWINT0_SHF 4
269 #define GIC_VPE_PEND_SWINT0_MSK (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
270 #define GIC_VPE_PEND_SWINT1_SHF 5
271 #define GIC_VPE_PEND_SWINT1_MSK (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
272
273 /* GIC_VPE_RMASK Masks */
274 #define GIC_VPE_RMASK_WD_SHF 0
275 #define GIC_VPE_RMASK_WD_MSK (MSK(1) << GIC_VPE_RMASK_WD_SHF)
276 #define GIC_VPE_RMASK_CMP_SHF 1
277 #define GIC_VPE_RMASK_CMP_MSK (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
278 #define GIC_VPE_RMASK_TIMER_SHF 2
279 #define GIC_VPE_RMASK_TIMER_MSK (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
280 #define GIC_VPE_RMASK_PERFCNT_SHF 3
281 #define GIC_VPE_RMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
282 #define GIC_VPE_RMASK_SWINT0_SHF 4
283 #define GIC_VPE_RMASK_SWINT0_MSK (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
284 #define GIC_VPE_RMASK_SWINT1_SHF 5
285 #define GIC_VPE_RMASK_SWINT1_MSK (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
286
287 /* GIC_VPE_SMASK Masks */
288 #define GIC_VPE_SMASK_WD_SHF 0
289 #define GIC_VPE_SMASK_WD_MSK (MSK(1) << GIC_VPE_SMASK_WD_SHF)
290 #define GIC_VPE_SMASK_CMP_SHF 1
291 #define GIC_VPE_SMASK_CMP_MSK (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
292 #define GIC_VPE_SMASK_TIMER_SHF 2
293 #define GIC_VPE_SMASK_TIMER_MSK (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
294 #define GIC_VPE_SMASK_PERFCNT_SHF 3
295 #define GIC_VPE_SMASK_PERFCNT_MSK (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
296 #define GIC_VPE_SMASK_SWINT0_SHF 4
297 #define GIC_VPE_SMASK_SWINT0_MSK (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
298 #define GIC_VPE_SMASK_SWINT1_SHF 5
299 #define GIC_VPE_SMASK_SWINT1_MSK (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
300
301 /*
302 * Set the Mapping of Interrupt X to a VPE.
303 */
304 #define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
305 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
306 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
307
308 struct gic_pcpu_mask {
309 DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
310 };
311
312 struct gic_pending_regs {
313 DECLARE_BITMAP(pending, GIC_NUM_INTRS);
314 };
315
316 struct gic_intrmask_regs {
317 DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
318 };
319
320 /*
321 * Interrupt Meta-data specification. The ipiflag helps
322 * in building ipi_map.
323 */
324 struct gic_intr_map {
325 unsigned int cpunum; /* Directed to this CPU */
326 #define GIC_UNUSED 0xdead /* Dummy data */
327 unsigned int pin; /* Directed to this Pin */
328 unsigned int polarity; /* Polarity : +/- */
329 unsigned int trigtype; /* Trigger : Edge/Levl */
330 unsigned int flags; /* Misc flags */
331 #define GIC_FLAG_IPI 0x01
332 #define GIC_FLAG_TRANSPARENT 0x02
333 };
334
335 /*
336 * This is only used in EIC mode. This helps to figure out which
337 * shared interrupts we need to process when we get a vector interrupt.
338 */
339 #define GIC_MAX_SHARED_INTR 0x5
340 struct gic_shared_intr_map {
341 unsigned int num_shared_intr;
342 unsigned int intr_list[GIC_MAX_SHARED_INTR];
343 unsigned int local_intr_mask;
344 };
345
346 extern void gic_init(unsigned long gic_base_addr,
347 unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
348 unsigned int intrmap_size, unsigned int irqbase);
349
350 extern void gic_clocksource_init(void);
351 extern unsigned int gic_get_int(void);
352 extern void gic_send_ipi(unsigned int intr);
353 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
354 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
355 extern void gic_bind_eic_interrupt(int irq, int set);
356 extern unsigned int gic_get_timer_pending(void);
357
358
359 #endif /* _ASM_GICREGS_H */
Tomato firmware and modifications.