release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/ar7/irq.c

   1 /*
   2  * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
   3  * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/irq_cpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/mach-ar7/ar7.h>
  26
  27 #define EXCEPT_OFFSET   0x80
  28 #define PACE_OFFSET     0xA0
  29 #define CHNLS_OFFSET    0x200
  30
  31 #define REG_OFFSET(irq, reg)    ((irq) / 32 * 0x4 + reg * 0x10)
  32 #define SEC_REG_OFFSET(reg)     (EXCEPT_OFFSET + reg * 0x8)
  33 #define SEC_SR_OFFSET           (SEC_REG_OFFSET(0))     /* 0x80 */
  34 #define CR_OFFSET(irq)          (REG_OFFSET(irq, 1))    /* 0x10 */
  35 #define SEC_CR_OFFSET           (SEC_REG_OFFSET(1))     /* 0x88 */
  36 #define ESR_OFFSET(irq)         (REG_OFFSET(irq, 2))    /* 0x20 */
  37 #define SEC_ESR_OFFSET          (SEC_REG_OFFSET(2))     /* 0x90 */
  38 #define ECR_OFFSET(irq)         (REG_OFFSET(irq, 3))    /* 0x30 */
  39 #define SEC_ECR_OFFSET          (SEC_REG_OFFSET(3))     /* 0x98 */
  40 #define PIR_OFFSET              (0x40)
  41 #define MSR_OFFSET              (0x44)
  42 #define PM_OFFSET(irq)          (REG_OFFSET(irq, 5))    /* 0x50 */
  43 #define TM_OFFSET(irq)          (REG_OFFSET(irq, 6))    /* 0x60 */
  44
  45 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
  46
  47 #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
  48
  49 static int ar7_irq_base;
  50
  51 static void ar7_unmask_irq(unsigned int irq)
  52 {
  53         writel(1 << ((irq - ar7_irq_base) % 32),
  54                REG(ESR_OFFSET(irq - ar7_irq_base)));
  55 }
  56
  57 static void ar7_mask_irq(unsigned int irq)
  58 {
  59         writel(1 << ((irq - ar7_irq_base) % 32),
  60                REG(ECR_OFFSET(irq - ar7_irq_base)));
  61 }
  62
  63 static void ar7_ack_irq(unsigned int irq)
  64 {
  65         writel(1 << ((irq - ar7_irq_base) % 32),
  66                REG(CR_OFFSET(irq - ar7_irq_base)));
  67 }
  68
  69 static void ar7_unmask_sec_irq(unsigned int irq)
  70 {
  71         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
  72 }
  73
  74 static void ar7_mask_sec_irq(unsigned int irq)
  75 {
  76         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
  77 }
  78
  79 static void ar7_ack_sec_irq(unsigned int irq)
  80 {
  81         writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
  82 }
  83
  84 static struct irq_chip ar7_irq_type = {
  85         .name = "AR7",
  86         .unmask = ar7_unmask_irq,
  87         .mask = ar7_mask_irq,
  88         .ack = ar7_ack_irq
  89 };
  90
  91 static struct irq_chip ar7_sec_irq_type = {
  92         .name = "AR7",
  93         .unmask = ar7_unmask_sec_irq,
  94         .mask = ar7_mask_sec_irq,
  95         .ack = ar7_ack_sec_irq,
  96 };
  97
  98 static struct irqaction ar7_cascade_action = {
  99         .handler = no_action,
 100         .name = "AR7 cascade interrupt"
 101 };
 102
 103 static void __init ar7_irq_init(int base)
 104 {
 105         int i;
 106         /*
 107          * Disable interrupts and clear pending
 108          */
 109         writel(0xffffffff, REG(ECR_OFFSET(0)));
 110         writel(0xff, REG(ECR_OFFSET(32)));
 111         writel(0xffffffff, REG(SEC_ECR_OFFSET));
 112         writel(0xffffffff, REG(CR_OFFSET(0)));
 113         writel(0xff, REG(CR_OFFSET(32)));
 114         writel(0xffffffff, REG(SEC_CR_OFFSET));
 115
 116         ar7_irq_base = base;
 117
 118         for (i = 0; i < 40; i++) {
 119                 writel(i, REG(CHNL_OFFSET(i)));
 120                 /* Primary IRQ's */
 121                 set_irq_chip_and_handler(base + i, &ar7_irq_type,
 122                                          handle_level_irq);
 123                 /* Secondary IRQ's */
 124                 if (i < 32)
 125                         set_irq_chip_and_handler(base + i + 40,
 126                                                  &ar7_sec_irq_type,
 127                                                  handle_level_irq);
 128         }
 129
 130         setup_irq(2, &ar7_cascade_action);
 131         setup_irq(ar7_irq_base, &ar7_cascade_action);
 132         set_c0_status(IE_IRQ0);
 133 }
 134
 135 void __init arch_init_irq(void)
 136 {
 137         mips_cpu_irq_init();
 138         ar7_irq_init(8);
 139 }
 140
 141 static void ar7_cascade(void)
 142 {
 143         u32 status;
 144         int i, irq;
 145
 146         /* Primary IRQ's */
 147         irq = readl(REG(PIR_OFFSET)) & 0x3f;
 148         if (irq) {
 149                 do_IRQ(ar7_irq_base + irq);
 150                 return;
 151         }
 152
 153         /* Secondary IRQ's are cascaded through primary '0' */
 154         writel(1, REG(CR_OFFSET(irq)));
 155         status = readl(REG(SEC_SR_OFFSET));
 156         for (i = 0; i < 32; i++) {
 157                 if (status & 1) {
 158                         do_IRQ(ar7_irq_base + i + 40);
 159                         return;
 160                 }
 161                 status >>= 1;
 162         }
 163
 164         spurious_interrupt();
 165 }
 166
 167 asmlinkage void plat_irq_dispatch(void)
 168 {
 169         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 170         if (pending & STATUSF_IP7)              /* cpu timer */
 171                 do_IRQ(7);
 172         else if (pending & STATUSF_IP2)         /* int0 hardware line */
 173                 ar7_cascade();
 174         else
 175                 spurious_interrupt();
 176 }