release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/alchemy/devboards/pb1500/board_setup.c

   1 /*
   2  * Copyright 2000, 2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  11  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  13  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  14  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  16  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  18  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20  *
  21  *  You should have received a copy of the  GNU General Public License along
  22  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  23  *  675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/gpio.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30
  31 #include <asm/mach-au1x00/au1000.h>
  32 #include <asm/mach-db1x00/bcsr.h>
  33
  34 #include <prom.h>
  35
  36
  37 char irq_tab_alchemy[][5] __initdata = {
  38         [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff },   /* IDSEL 12 - HPT370        */
  39         [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD },   /* IDSEL 13 - PCI slot */
  40 };
  41
  42
  43 const char *get_system_type(void)
  44 {
  45         return "Alchemy Pb1500";
  46 }
  47
  48 void __init board_setup(void)
  49 {
  50         u32 pin_func;
  51         u32 sys_freqctrl, sys_clksrc;
  52
  53         bcsr_init(DB1000_BCSR_PHYS_ADDR,
  54                   DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
  55
  56         sys_clksrc = sys_freqctrl = pin_func = 0;
  57         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  58         au_writel(8, SYS_AUXPLL);
  59         au_writel(0, SYS_PINSTATERD);
  60         udelay(100);
  61
  62         /* GPIO201 is input for PCMCIA card detect */
  63         /* GPIO203 is input for PCMCIA interrupt request */
  64         alchemy_gpio_direction_input(201);
  65         alchemy_gpio_direction_input(203);
  66
  67 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  68
  69         /* Zero and disable FREQ2 */
  70         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  71         sys_freqctrl &= ~0xFFF00000;
  72         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  73
  74         /* zero and disable USBH/USBD clocks */
  75         sys_clksrc = au_readl(SYS_CLKSRC);
  76         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  77                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  78         au_writel(sys_clksrc, SYS_CLKSRC);
  79
  80         sys_freqctrl = au_readl(SYS_FREQCTRL0);
  81         sys_freqctrl &= ~0xFFF00000;
  82
  83         sys_clksrc = au_readl(SYS_CLKSRC);
  84         sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  85                         SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  86
  87         /* FREQ2 = aux/2 = 48 MHz */
  88         sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
  89         au_writel(sys_freqctrl, SYS_FREQCTRL0);
  90
  91         /*
  92          * Route 48MHz FREQ2 into USB Host and/or Device
  93          */
  94         sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  95         au_writel(sys_clksrc, SYS_CLKSRC);
  96
  97         pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
  98         /* 2nd USB port is USB host */
  99         pin_func |= SYS_PF_USB;
 100         au_writel(pin_func, SYS_PINFUNC);
 101 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 102
 103 #ifdef CONFIG_PCI
 104         /* Setup PCI bus controller */
 105         au_writel(0, Au1500_PCI_CMEM);
 106         au_writel(0x00003fff, Au1500_CFG_BASE);
 107 #if defined(__MIPSEB__)
 108         au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
 109 #else
 110         au_writel(0xf, Au1500_PCI_CFG);
 111 #endif
 112         au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
 113         au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
 114         au_writel(0x02a00356, Au1500_PCI_STATCMD);
 115         au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
 116         au_writel(0x00000008, Au1500_PCI_MBAR);
 117         au_sync();
 118 #endif
 119
 120         /* Enable sys bus clock divider when IDLE state or no bus activity. */
 121         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
 122
 123         /* Enable the RTC if not already enabled */
 124         if (!(au_readl(0xac000028) & 0x20)) {
 125                 printk(KERN_INFO "enabling clock ...\n");
 126                 au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
 127         }
 128         /* Put the clock in BCD mode */
 129         if (au_readl(0xac00002c) & 0x4) { /* reg B */
 130                 au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
 131                 au_sync();
 132         }
 133 }
 134
 135 static int __init pb1500_init_irq(void)
 136 {
 137         set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
 138         set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
 139         set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
 140         set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
 141         set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
 142         set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
 143         set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
 144         set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 145
 146         return 0;
 147 }
 148 arch_initcall(pb1500_init_irq);