1 #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
2 #define _ASM_MICROBLAZE_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 /* Force re-assigning all resources (ignore firmware
20 PCI_REASSIGN_ALL_RSRC
= 0x00000001,
22 /* Re-assign all bus numbers */
23 PCI_REASSIGN_ALL_BUS
= 0x00000002,
25 /* Do not try to assign, just use existing setup */
26 PCI_PROBE_ONLY
= 0x00000004,
28 /* Don't bother with ISA alignment unless the bridge has
29 * ISA forwarding enabled
31 PCI_CAN_SKIP_ISA_ALIGN
= 0x00000008,
33 /* Enable domain numbers in /proc */
34 PCI_ENABLE_PROC_DOMAINS
= 0x00000010,
35 /* ... except for domain 0 */
36 PCI_COMPAT_DOMAIN_0
= 0x00000020,
40 * Structure of a PCI controller (host bridge)
42 struct pci_controller
{
45 struct device_node
*dn
;
46 struct list_head list_node
;
47 struct device
*parent
;
54 void __iomem
*io_base_virt
;
55 resource_size_t io_base_phys
;
57 resource_size_t pci_io_size
;
59 /* Some machines (PReP) have a non 1:1 mapping of
60 * the PCI memory space in the CPU bus space
62 resource_size_t pci_mem_offset
;
64 /* Some machines have a special region to forward the ISA
65 * "memory" cycles such as VGA memory regions. Left to 0
68 resource_size_t isa_mem_phys
;
69 resource_size_t isa_mem_size
;
72 unsigned int __iomem
*cfg_addr
;
73 void __iomem
*cfg_data
;
76 * Used for variants of PCI indirect handling and possible quirks:
77 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
78 * EXT_REG - provides access to PCI-e extended registers
79 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
80 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
81 * to determine which bus number to match on when generating type0
83 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
84 * hanging if we don't have link and try to do config cycles to
85 * anything but the PHB. Only allow talking to the PHB if this is
87 * BIG_ENDIAN - cfg_addr is a big endian register
88 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
89 * on the PLB4. Effectively disable MRM commands by setting this.
91 #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
92 #define INDIRECT_TYPE_EXT_REG 0x00000002
93 #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
94 #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
95 #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
96 #define INDIRECT_TYPE_BROKEN_MRM 0x00000020
99 /* Currently, we limit ourselves to 1 IO range and 3 mem
100 * ranges since the common pci_bus structure can't handle more
102 struct resource io_resource
;
103 struct resource mem_resources
[3];
104 int global_number
; /* PCI domain number */
107 static inline struct pci_controller
*pci_bus_to_host(const struct pci_bus
*bus
)
112 static inline int isa_vaddr_is_ioport(void __iomem
*address
)
114 /* No specific ISA handling on ppc32 at this stage, it
115 * all goes through PCI
120 /* These are used for config access before all the PCI probing
122 extern int early_read_config_byte(struct pci_controller
*hose
, int bus
,
123 int dev_fn
, int where
, u8
*val
);
124 extern int early_read_config_word(struct pci_controller
*hose
, int bus
,
125 int dev_fn
, int where
, u16
*val
);
126 extern int early_read_config_dword(struct pci_controller
*hose
, int bus
,
127 int dev_fn
, int where
, u32
*val
);
128 extern int early_write_config_byte(struct pci_controller
*hose
, int bus
,
129 int dev_fn
, int where
, u8 val
);
130 extern int early_write_config_word(struct pci_controller
*hose
, int bus
,
131 int dev_fn
, int where
, u16 val
);
132 extern int early_write_config_dword(struct pci_controller
*hose
, int bus
,
133 int dev_fn
, int where
, u32 val
);
135 extern int early_find_capability(struct pci_controller
*hose
, int bus
,
136 int dev_fn
, int cap
);
138 extern void setup_indirect_pci(struct pci_controller
*hose
,
139 resource_size_t cfg_addr
,
140 resource_size_t cfg_data
, u32 flags
);
142 /* Get the PCI host controller for an OF device */
143 extern struct pci_controller
*pci_find_hose_for_OF_device(
144 struct device_node
*node
);
146 /* Fill up host controller resources from the OF node */
147 extern void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
148 struct device_node
*dev
, int primary
);
150 /* Allocate & free a PCI host bridge structure */
151 extern struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
);
152 extern void pcibios_free_controller(struct pci_controller
*phb
);
153 extern void pcibios_setup_phb_resources(struct pci_controller
*hose
);
156 extern unsigned int pci_flags
;
158 static inline void pci_set_flags(int flags
)
163 static inline void pci_add_flags(int flags
)
168 static inline int pci_has_flag(int flag
)
170 return pci_flags
& flag
;
173 extern struct list_head hose_list
;
175 extern int pcibios_vaddr_is_ioport(void __iomem
*address
);
177 static inline int pcibios_vaddr_is_ioport(void __iomem
*address
)
182 static inline void pci_set_flags(int flags
) { }
183 static inline void pci_add_flags(int flags
) { }
184 static inline int pci_has_flag(int flag
)
188 #endif /* CONFIG_PCI */
190 #endif /* __KERNEL__ */
191 #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */